JPRS ID: 10318 TRANSLATION UNIFIED SYSTEM HARDWARE AND SOFTWARE (YES-11) BY V.V. PRZHIYALKOVSKIY AND YU.S. LOMOV

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JPRS L/1~318
11 February 1982
Transiatior~
UNIFIED COMPUTER S~ISTEM HARDWARE AND SOFTWARE CYES-II)
By
- V.V. Przhiyalkovskiy and Yu..S. Lomov
- Fg~$ FOREIGN BROADCAST INFORMATION SERVICE
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JPRS L/10318
11 February 1982
UNIFIEU COMPUTER SYSTEM HARDWARE AND SOFTWARE (YES-II)
Moscow TEKHNICHESKIYE T PROGRANII~lNYYE SREDSTVA YEDINOY SISTEMY EVM
(YES EVN1-2) in Russian 1980 (signed to press 1 Aug 80) pp 1-232
[Book "Unified Computer System Hardware and Software (YeS-II)" by
Viktor Vladimirovich Przhiyalkovskiy and Yuriy Sergeyevich Lrnnov,
Izdatel'stvo "Statistika", 20,000 copies, 232 pages]
CONTENTS
Annotation 1
- Forew~rd 1,
- - - _
Cl~apter 1. Uniried Computer System Architectural Development 3
l.l. Unified System of Electronic Ccmputers 3
1.2. Basic Directions in Development of Principles of Operation of the
- Unified Computer System 5
1.3. Basic Properties of the Architecture of the Unified Computer System 8
1.4. Structure of YeS EVM-2 Models 10
Chapter 2. Raising the Efficiency of Computations 15
2.1. Main Concepts of Processor Structure 16
2.2. System Control Facilities 26
2.3. Dynamic Translation of Addresses 33
2.4. Microprogram Control 36
2.~. Principles of Organization of Array Processor 40
Chapter 3. Organization of Data Storage 47
3.1. DPVelopment of Main Storage Units 48
3.2. Organization of Main Storage SO
_ 3.3. Raising Reliability of Data Storage 5$
Chapter 4. Development of Input/Output System (2
4.1. Organization and Logic Structure of Input/Output Channels 62
_ 4.2. Development of Principles of Input%~utput Ope~-~tions 65
4.3. Operation of Input/Output System 7,5
4.4. External Storage Units 78
4.5. Input/Output and Data Preparation Units 8,5
Chapter S. Means of Organization of ~s,uputer Syatems 90
5.1. Multiprocessor Systems 90.
5.2. Multimachine Systems 9~
~ 5.3. Data Teleprocessing Hardware ?03
, - a- j T-- USSR ~ N FOUO]
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- Chapter 6. Development of Facilities for Monitoring and Diagnosing ]:15
6.1. Means of Checking for Machine Errors ~'S
6.2. Processing of Machine Checking Signals 117
6.3. Microdiagnostic Procedures ~23
6.4. DIAGNOSE Instruction ~ 1'?L'
6.5. Software Facilities for Checking and Diagnosing 12~
b.6. Computer Maintenance ~130
Chapter 7. Software 131
7.1. Development of YeS OS Operating 8ystem 131
7.2. General Structure and Functions of YeS OS 133
7.3. Virtual Storage Support I43
7.4. Virtual Storage Mode SVS 147
7.5. Basic Telecommunication Access Method [BTAM] 150
7.6. General Telecommunication Access Method ~1
7.7. Remote Job Entry [RJE] Mode 153
7.8. Time Sharing System [TSS] 154
7.9. Virtiual Storage Access Method [VS~.M] 156
- 7.10. Means of Building Multimachine Complexes 156
- 7.11. Dqnamic Debugging Monitor 158
7.12. General-Purpose Trace Facility ~9
7.13. YeS OS Recovery Facilities 160
7.14. YeS DOS-3 Aperating System 163
7.15. Application Program Packages 169
- Chapter 8. Functional ~t?aracteristics of Models of YeS EVM-2 174
8.1. YeS-1015 Computer 174
8.2. YeS-1025 Computer 175
8.3. YeS-1035 Computer l~$
- 8.4. YeS-1045 Computer 1F1
8.~: YeS-1055 Computer 184
8.~. YeS-1060 Computer 187
8.7. YeS-1065 Computer 191
Conclusion . 193
Bibliography 194
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Y
IJ
a
[Text] Annotation
This book deals with the questi.ons of development of the archiCecture, internal
structure and principles of operation of the family of software-compatible computers
- in the Unified System (Ye~ EVM). The main problems of development of functional
properties, technical characteristics and software fcr the Unified Systezn are
rc~flected.
This book is inte~~ded for specialis*_s using Unified Computer Systeln hardware and
software, for computer c~nter ~~rkers, students in WZ's and people interested in
the problems of development computers.
~ Foreword
I Equipping the national economy with computers is now a ma~or factor determining the
rate of development of science, growth in industrial production and enhancement of
~ managerial efficiency. Much attention was paid in the decisione of the 24th and 25th
; CPSU congresses to the development of computers and introduction of them in the
various spheres of the national economy.
A decisive role in the development of computers continues to be played by general-
purpose computers used to solve scientific and technical problems and to solve prob-
lems within information and lo~ic systems and automated control systems at varioua
levels. The emergence at the end of the sixtiea of minicomputers and in recent years
- even micr~computers has not only n~t reduced the field of application of general-
purpose computers, but rather, conversely, has expanded it through the emergence of
combine~ systems in which information undergoes initial processing on micro and mini-
compi:~ers and is then sent for centralized processing and storage to a central
co*.~puter.
In 1969, an intergoverr.mental agreement was concluded between the countries in the
socialist commur_ity and the Intergovernmental Commiesion on Cooperation in Computer
1'
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Technology was formed. Because of this agreement, the rate of development, produc-
tion and introduction of modern computer hardware into the national economy of the
countries in the soc.ialist co~unity has increased considerably. Within a relative-
ly short period, the Unified System of Computers was developed in the community
countries. The system includes several computers with various throughruts that
have full program and information compatibility, an extensive set of p~ripheral~
and common technological design principles of construction.
The results of cooperation on the program for the first phase of the Unified System
(YeS EVM-1) were presented at the international exhibition "YeS EVM--73" held in`
Moscow. By that time, development had been completed on six computers with through-
put ranging from 5000 to 500,000 operations/second, about 100 types of peripherals
and four operating systems supporting efficient operation of the hardware.
In 1979, the second international exhibition, "YeS EVM and SM EVM--79," was held
successfully. Presented at it were the results of cooperation among the countri~es
in the socialist community on the program for the second phase of the Unified Sys-
tem (YeS EVM-2). YeS EVM-1 was replaced by the new, more modern YeS EVM-2 system
that consists of seven computers with throughput ranging from 20,000 to 5 million
operations/sec~nd.
The YeS EVM-2, production of which began several years ago, is an essential evolu-
tion of the YeS EVM-1 in many directions. The most essential features of the n~w
system are:
the increase in throughput in the YeS EVM-2 computers, achieved in the majority of
cases without increasing cost;
the increase in precision of computations (appearance of operations on operands
having quadruple length);
the introduction of special control operations to expand computer oAerating modes,
in particular to facilitate operation within multi~achine and multiprocessor com-
plexes;
further improvement of the input/output system, appearance of new peripherals with
higher throughput, increase in channel throughput, and the capability of
simultaneous operation of several high-speed storage units;
the emergence of supplementary hardware to raise the efficiency of software system
operation in the modes of multi.programming, ~ime sharing, teleprocessing, multi,-
machine and multiprocessor operation;
the introduction of hordware and software to support organization of the virtual
storage mode;
improvement of the monitoring system, introduction of facilities for correcting sin-
gle and detecting double errors. Introduction and development of facilities for
diagnosing malfunctions and recovery of system after failure;
further development of ineans of microprogram control, introduction of reloadable
� storage of microprograms; and
, development of the software system to support the new computer operating modes and
new hardware.
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, It should be noted that the series of YeS EVM-2 machines provides for s~ftware ,
compatibility between the models of this series and with the YeS EVM-1 mach~nes. In
r~dd[.tion, the YcS CVM-2 system, ,~ust ~s th~- YeS EVM-1, maintains full compatibility
at the user Frogram lev~l with widespread foreign computer systems, i.e., joins in
fact the world sta.idard, formed in the last 10-15 years, of external structure of
general-purpose computers.
This book covers a broad range of questions of architecture, internal structure and
organization of computer systems, as well as questions of software for the YeS EVM-2
machines. It is the first publication to elucidate comprehensively the principles
of operation of the new system. ~
Academician V. S. Sem~nikhin.
Chapter 1. Unified System Architectural Development
1.1. Unified System of Electronic Computers ,
The family of program-compatible third-generation computers, called the Unified
System of Electronic ComputerG "'eS EVM), includes a series of models with a speed
ranging from several thou,sands to several millions of instructions ger sECOnd. All
models in the Unified System are united by common principles of operation, uniformi-
ty of control procedures and a uniform method of organization of links between the
_ individual system modules. Thanks to the large nomenclature of peripherals and the
standard method f.or cor.^.ecting them, computers systems with various configurations
can be set up. The software and hardware ensure efficient operation of the Unified
System of Computers in various modes for solving a wide range of scientific, techni-
cal, economic, managerial and other problems and offer the capabiZity of using these
computers both in computer centers of varying function and in various types of auto-
mated systems f.or data management and processing.
Two phases of work on the Unified System program have now been completed: the first
phase, YeS E`1M-1, and the second, YeS EVM-2.
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The main goal in de.veloping the first phase was to develop a family of third-
generation computers meeting the nodern requirements imposed on the architecturEa,
software, design and technology. In addition, as a result of the rapidly develop-
ing field of computer applications, the need arose for computer hardware with high
operating qualities and intended for mass production.
This goal could not have been met without the solution to the problems of further
evolution of the theory of organization of structures and computational processes
of camputErs, and the development of related fields of science and technology that
support creation of the new element base with integrated circuits, new materials
and equipment. In the process, methods of automating the design and production of
computers were extensively developed and implemented.
1 The structure and principles of operation of phase-one computers are defined by the
followine basic concepts:
computer software compatibility;
standard set of instructions, forms and formats for data representation;
standard set of operating units;
standard procedures for the input/output c~ntrol system [IOCS];
extensive nomenclature of peripherals connectable through a standard input/output
interface; and
unity of design principles that support a high degree of unification.
The YeS EVM-1 includes several dozens of types of peripherals, four operating sys-
tems and seven computer models: YeS-1010 (VNR [Hungarian People's Republic]), _
YeS-1020 (USSR), YeS-1021 (ChSSR [Czechoslovak Socialist Republic]), YeS-1030
(USSR), YeS-1032 (PNR [Polish People's Republic]), YeS-1040 (GDR) and the Ye3-1050
(USSR) . ~
In subsequeat years, new models were developed: YeS-1012 (VNR), YeS-1022 (USSR),
YeS-1033 (USSR) and the YeS-1052 (USSR) which are modifications of the YeS-1010,
YeS-1020, YeS-1030 and the YeS-1050 computers developed earlier.
The main technical characteristics of the YeS EVM-1 were widely published earlier.
Thus, 11 models of the family of the Unified System have been developed and are in
operation within the YeS EVM-1.
In the YeS EVM-2, which is a further evolution of the YeS EVM-1, all the merits of
the preceding system have been kept, and in addition, new functional capabilities
have been added. The latest achievements in the microelectronic component base
were made use of in developing it. The improved technical and economic character-
istics of the YeS EVM-2, which put it on a qualitatively higher level of develop-
ment and meet the enhanced user requirements, were obtained as a result of:
raising the throughput of the central processing units and the overall efficiency
of the system while at the same time observing the requirements of economy and
adaptabilj.ty to manufacture;
expanding hardware and software functional capabilitieE;;
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_ developing the input/output system;
increasing the capacity of main storage and improving the organization of data
storage;
- raising system reliability, developing efficient checking and diagnosing facilities;
further developing the software system;
providing the capability of setting up multiprocessor and multimachine computer
systems; and
developing a new complex of peripherals.
, ~he YeS EVM-2 now includes a large nomenclature of hardware and software for the
Unified System which supports operation of seven models: YeS-1015 (VNR), YeS-1025
(ChSSR), YeS-1035 (USSR), YeS-1045 (USSR), YeS-1055 (GDR), YeS-1060 (USSR) and the
YeS-1065 (USSR).
1.2. Basic Directions in Development of Principles of Operation of the Unified
Computer System
- Combining the efforts of a lar.ge number of teams of developers, including those
from the different countries, to implement the Unified Computer System is possible
given the common logic structure of the entire system that defines the set of
interrelated requirements and links between the hardware and software components,
i.e., with the common principles of system operation.
The Y~S EVM-2 operating principles were developed thanks to including in the logic

J structure:
an expande3 instruction set;
expanded control facilities in tl~e processor;
~ indirect addressing of data in the channels;
the block-multiplex mode of channel operation;
new facilities for multiprocessor operation;
facilities for raising precision of floating-point operations;
an expanded sqstem of interrupts;
new facilities for time readout;
facilities for recording program events;
facilities to support ~n~nitor programs; and
facilities for raising the efficiency of checking and diagnosing.
Instruction System. In contrast to the YeS EVM-1 (computing functions of which are
implemented by the universal instruction set), the YeS EVM-2 has a more developed
instruction set. The additional instructions are intended to provide for new func-
tions of the pracessor and channels, provide multiproeessor faciiities and facili-
ties for time readout, and to expand the cupabilities of scientific and technical
computer applications. The instruction set used to execute system control func-
tions has also been increased considerably.
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Control Modes in the Processor. There are two modes of operation of the processor
in the YeS EVM-2: basic control mode and extended control mode.
The basic control mode provides for functioning of the computer in accordance with
- the YeS EVM-1 operating principles. The exte.nded control mode is intended to make
use of the new YeS EVM-2 functions and facilities. To this end, control registers
that can be addressed by a pragram have been incorporated in the processor struc-
ture. Stored in the control registers are information on system status and infor-
mation needed when implementing YeS EVM-2 capabilities.
Dynamic Address Translation. Computer system efficiency is largely determined by
the method of organizing storage of data, addressing system adopted and structure
of distribution of information flows. In the YeS EVM-2, these questions have been
reso.lved by intro3ucing the facilities of dynamic address translation and indirect
addressing of data, which with the corresponding support of ~he operating system
and in the aggregate with it allow making use of a 16-megabyte extent of ~irtual
storage.
The concept "virtual" has become widsspread in recent years and literally means
"apparent." It is used in terms such as "virtual storage," "virtual machines," etc.
In this case it means that the complete illusion of using a several-fold greater
size of main storage is created for a programmer working with the physically limited
size of main storage, or the illusion is created that each user has been allocated
his own installation with all resources when several users are workiug simultaneous-
_ ly with one computer. This illusion is achieved through special organization of
~ontrol of the corresponding processES. This is the purely external aspect of the
virtual concept. The internal significance is that virtual organization allows
making more efficient use of system reources, for instance in the ex3mples cited,
through reducing the limitations on the size of main storage or, respectively,
?_imitations on the joint use of the equipment.
The introduction of dynamic address translation facilities reduces the limitations
associated with the necessity of assigning fixed areas of real main sCorage for
programs. Dynamic address translation facilities allow placing programs or parts
of them in external storage units (i.e., outside main storage) with subsequent in-
troduction of them into the free space of main storage upon request under control
- of the processor. These relocations, as well as relocations of information from
main storage to external are performed automatically by the system without program-
mer intervention. This allows making efficient use of computer resources, includ-
ing main storage resources, in the process of computations.
Thus, dyn~mic address translatior. facilities offer the user working storage, the
size of which exceeds the size of storage physically connected to the computer.
Indirect Addressing of Data. While dynamic address translation allows translation
of addresses of instructions and data formed in the processor, the mechanism of in-
direct addressing of data serves the same purpose during input/c+utput [IO] opera-
tions in a channel. Indirect addressing facilities optimize execution of IO opera-
tions, allowing otie channel command to control transmission of data located in non-
_ contiguous areas of real main storage.
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Dynamic address translation in the processor and indirect addressing of data in a
channel are used together to organize the virtual storage mode.
Block Multiplex M~de of Channel Operation. In the block multiplex mode, blocks of
data from various IO devices are multiplexed, and in the process, each data block is
transmitted in the burst mode. Implementation of block multiplexing raises consider-
ably the efficiency of channel operatien through parallel operation of several high-
speed external IO devices.
Facilities for Multiprocessor Operation. Multiprocessor operation presumes organi-
zation of access of two (multi in the ge~?eral case) processors to a storage area
. defined as common in a system configuration. There may also be storage areas belong-
ing to the individual processors in the system. In addition to programs and the
resident part of the operating system, the common extent of main storage holds infor-
mation on the status of the processor and operations neceasary for control of it.
This information is stored in the starting area of storage with the addresses 0-4096,
which is called the permanently allocated (fixed) area.
Multiprocessor facilities are intended for operation of several processors ~rith a
common extent of main storage. These facilities provide for partitioning of main
storage, address prefixing, interprocessor signaling and synchronization of
astronomical time clocks.
Facilities for Raising Precision of Operations with Floating Point. For flo~ting-
point addition, subtraction and multiplication operations, facilities have been pro-
vided in the YeS EVM-2 that enable working with a mantissa consisting of 28 hexi-
decimal numbers. In addition, necessary operations are performed to rourid off the
result and convert numbers from the long to the short format and vice versa.
The introduction of these facilities stems from the fact that ~ith increased computer
- throughput, it nas become possibl~ to solve complex and laborious scientific and
technical problems with high precision. These problems, as a rule, are characterized
by a large number of computational iterations, as a result of which a considerable
, increase in rounding errors could be expected with ordinary precision of computations.
The system of interrupt;s makes it possible to expeditiously react ~nd change the
status of the computc~r under certain conditions that arise in the system or outside
it. These conditions include rec~uirements on the part of cantrol facilities and
external units, incorrect results of execution of operations, improper addressing
as well as results of operation of apparatus monitoring circuits.
The interrupt system has been enhanced by the introduction of program debugging
facilities, improvement of the apparatus for error detection and correction, and ex-
pansion of the functional properties of the processor and capabilities of multi-
processor organization.
- Time Readout Facilities. In the YeS EVM-1, the sole hardu~are for time readout was
the interval timer. The increase in processor throughput required development of
new facilities whose resolution would be commensurate with the instruction processing
rate. In addition, software facilities for time readout using just the interval
timer are rather inconvenient, require large storage size and take up considerable
processor time for their operation.
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In addition to the interval timer, a time-of-day [TOD] clock and a CPU timer have
- been incorporated in the YeS EVM-2. They have been impler.i~nted in the form of
hardware-controlled 52-bit counters with a resolution of 1 microsecond. Their
values are set by the instructions SET CLOCK and SET CPU TIMER.
The CPU timer does not change when the processor is in the stopped state. Once
set, the TOD clock runs even when the CPU is in the wait or stopped state. The
clock measur~:s elapsed time. It c~n be used to determine the date and time of day.
A CPU timer interruption occurs each time a negative quantity is in the timer. To
interrupt the CPU at a given time indicated by the TOD clock, t~ere is a comparator
in the CPU in which a specified value is set by the instructi~n SET COMPARATOR.
New instructions have been introduced to store readouts from the clock, CPU timer
and comparator in storage: STORE CLOCK, STORE CPU TIMER and STORE CLOCK COMPARATOR.
Program Event Recording. Facilities for program event recording and providing mon-
itor programs give the user the capability of debugging new programs at the same
time other problems are being solved.
' These facilities interrupt processor operation and write to a defined storage area
information needed by a user when the following events occur in a program:
successful completion of a transfer instruction;
change in contents of speci~ied general-purpose registers;
_ instruction is fetched from specified area of main storage; or
change in contents of specified area dn main storage.
Operation of the facilities fc;- program event recording reduces processor speed;
therefore, to maintain the rate of execution of ;~rograms not needed for these
facilities, masking of them has baen provided for.
Provision of Monitor Programs. Facilities for support of m~nitor programs permit
organizing transier of control to a program that effects specific control functions
- (the monitor). This occurs when the instruction CALL MONITOR is encounterPd in a
program being executed and transfer of control is permitted (not masked).
Checking and Diagnostics. Capabilities f~r raising the efficiency of checking and
diagnostics in the YeS EVM-2 are provided by various software and hardware facili-
ties for detecting, localizing and correc~ing errors, as well as facilities to
restore th~e computing process when malfunctions occur.
1.3. Basic Properties of Unified Computer System Architecture
In making an overall evaluation of all the changes in the logic structure of the
YeS EVM-2, it can be noted that they are aimed at evolvin~ the main features of
. the Unified System Architecture: efficiency, general-purposeness, compatibility
and reliability.
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Efficiency. The nec~ models of the second phase of the Unified Computer System,
from an architectural point of view representing one computer, cover a broad range
of throughput that increases from the bottom to the top of the line. In addition,
the computational capacity of each model can be enhanced by uniting two processors
by means of multiprocessor facilities. As a rulP, within the bounds of one system,
the throughput of each ~:tccessive model is higher than a dual processor system.
built on the basis of the precPding model.
YeS EVM-2 models have better technical and economic characteristics than YeS EVM-1
- models. In particular, the throughput/cost ratio has been increased two to three-
fold; the absolute value of throughput for processors in the top models also has.
- been increased: from 0.7 (YeS-1052) to 5 million instructions/sec~nd (YeS-1065);
and size of main storage has been increased. Storage size ranges from 1 to S mega-
bytes as a function of model throughput; IO system throughput has been raised both
through the capability of connecting a larger number of channels and the increase
in their throughput to 3 megabytes/second.
In addition, along with the operating systems developed for phase-one models, soft-
ware is used in phase-two models that takes the new functions and capabilities into
account.
All this taken together gives a wide choice of hardware and software while ensuring
efficiency in solving specific user problems.
General-purposeness. General-purposeness means the capability of solving a wide
range of problems in differer~t classes with appr.oximately the same efficiency. In
second-phase models, this capability is supported primarily by the e:cpansion of the
general-purpose instruction set, which consists of the standard set and instruc-
tions for economic and scientific applications.
The standard set includes instructions for fixed-point arithmetic, control, exchange,
I0, logic operations and storage protection instructions. The instruction set for
economic applications~contains the standard instruction set plus instructions that
allow operation of facilities for processing decimal data with variable wordlength.
Instructions for scientific applications include floating-point operations in
addition to t-he standa.rd set.
Versatility in using Unified System Computers is also achieved by the modular hard-
ware principle that allows connecting periptiE:rals for various functions and develop-
ing a sof tware system that includes modes for multiprogramming, time sharing,
interaction and tele~rocessing.
Thus, the appropriate components can be selected to build a specif lc computer com-
plex most suited to a given application considering the requirements for through-
put, functional capabilities and set of peripherals.
Compatibility. Second-phase architecture ensures software compatibility both be-
tween second-phase models and with phase-one models. The different second-phase
models are compatible downwards' and upwar.ds. This provides for convenience in
maintenance, use of unified operating systems and application program packages
developed earlier, and simplicity in training and mastering the new models.
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However, the principle of compatibility does have limitations: programs must use
i3entical hardware and must not depend on the dur~tion of execution of instructions
by a processor and on functions peculiar to a given model (model-dependent). In
- addition, a program must not use areas assigned or that could be assigned for
special hardware functions.
Phase two is compatible with phase one from "bottom up." To execute programs on
phase-two models, that we.re written for phase-one models, not only the above cited
limitations have to be taken into account, but also those associated with the
features of the new system, which consist in:
proper. use of the bits in the program status word that determine the codes for out-
put flf results;
proper use of permanently allocated storage areas in the YeS EVM-2; and
taking into account the new capabilities of the IO channel for pre-fetching of in-
formation and the new capabilities for retry � of instructions and specifics
of the new instructions.
Reliability of the YeS EVM-2 models is ensured both by the technology of manufac-
- ture and by the use of special hardware and software facilities (more flexible
system for processing machine errors, circuits for correction of main storage
errors, mechanism for re~try ~of instructions in the processor and channels, and
the system for microdiagnostic procedurea).
In addition, the capabilities for preventing erroneous writes have been increased
- in the YeS EVM-2 through dynamic address translation which permita isolating one
program from the other during joint use of the same resourcea.
= 1:4. Structure of YeS EVM-2 Models
The base structure of the YeS EVM-2 models (fig. 1.) is described by the presence
of the obligatory (standard) functional devices of the five levels: the central
- processing unit (processor), main storage, channels, peripheral control units and
the peripheral equipment. The internal organization of each of these devices may
vary in the different models, but in doing so, the common principles of operation
. that ensure compatibility and the unified methods of system control are maintained.
Peripherals are connected through control units to channels by a standard IO inter-
face. Properly, this interface can be conaidered the sixth obligatory level of the
system. The channels have a link with the central processor since the latter
coordinates and controls the entire system as a whole, and a direct link to main
storage, thanks to which independent operation of the channels and the processor
is achieved. The system permits connection of different typea of channels:
byte-multiplexer, aelector and block-multiplexer.
The structure of the YeS EVM-2 permits the capability of connecting additional
- (nonstandard) functional units (for example, array proceasor, channel-to-channel
adapter, logic repeater)and various units that support communication between two
processors at the level of external storage units or a common area of main storage.
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The central processor is the nucleus of the system. Its functions include execu-
tion of arithmetic and logic operations, organization of main atorage accesa,
fetching and decoding of instructions, initiation of operation of executive units
and IO procedures, procesaing of interrupts and others. In accordance with theae
functions, the processor includes a central control unit, an~. arithmetic and lOgi~
unit and a storage control unit.
The internal organization of the processor structure (by which is meant the inter-
action of the functional assemblies and units tor organization of the computation-
al process) may vary from model to model, but in all models the procesaor performa
the same logic functions, i.e. the result of execution of an instruction will be
identical irrespective of the model.
As a function of requirementa for throughput and economy, the internal.structure
permits parallel or serial processing of information, a different width of data
streams, varying number of levele of overlap of instructions, and various
algorithms for execution of operations. ~
At the same time, unity of principles of operation is achieved by etandard facili-
ties: program status word register, general registers, regiaters with floating-
point and control registera which form the internal storage for the procesaor.
SEored in these registers are control information, information on aystem atatus,
addressea and operands. In addition, adherence to the principles of operation is
achieved by unity of formats and forms of representation of inatructions and data.
The program statua word (SSP) [PSW], which is stored in a 64-bit register, is in-
tended for instruction sequence control. The PSW contains the addreas of the cur-
rent instruction and information on the status of equipment needed by the pro~ram
being executed at the given time. The set of this information variea as a function
of the control mode.
Sixteen 32-bit general-purpose registers are used as index regietera in operations
for addressing and as data and result registers for logic and fixed-point opera-
tions. ' �
- The general-purpose registers are addressed from 0 to 15 by uaing a four-bit code
placed directly in the instruction. For work with 64-bit numbers, adjacent regis-
ters may'be used in pairs--an even and an odd register.
There are four 64-bit floati~g-point registers intended for atoring operands dur-
ing floating-point operations. The Eirst two and last two registers may be com- .
bined when the expanded data format (128-bit) is used.
Sixteen 32-bit control registers (RU) are ilsed in th~ processor for performing the
new YeS EVM-2 functions. They are ad~ressed by using a four-bit code in the in-
structions LOAD CONTROL and ST~RE CONTROL; [t is poasible to access a
group of control registers.
Operating principles are adhered to al8o by the unity of formats and forms of data
representation.
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~oR oFFic~nL usF oNt,v
, ,
( 1 ~ Oneporu~NnA nayA~e ,
naayecrop ' ( 3 ~ Konnna Aaoab-JsiQod7
yc~poucrpo yn/rodnedurr noMx~ero~~+)
6c~i�~v~/neru~- �
qpu~neruvecNO-nnruvecw ne,vcNa~i NaNnn
u~
S~awa � ~~,~,;~,e~ ~`6 ) � (13 ) �
n~e~ow�~ r~,y�~c m,ePoy~~ .
- yc~pnuc~eb r Q,uwcuan nom~HU ~t cnnodoro- CeneK~op~~eiu
n udneNUA ~n~NMi .u~ !/!N!N//p!% u~ev aonA- (14 ) KaNan
~ P i~q~ad dnr~~r~ruAu'~ ioti\
( 7 ) ~I/VNYMtl Ml ( 9 /
(15 ) Q^o^'~i~~nerun
9npo n~ ezuc~pe~ ezucrpa nnn peKC~i~~u wa~~o~ ,
rquepezr: a~ryetoNO Sa~vyHi aa-
~pA~ /!61 JIAOYlNU~(/6f n~~0u (~J
;
(10) (11) (12) .
~ ~ ~ (16 ('~7 .
` R �4~0
" . . _ ' _ ' V i ~q
ao~ ~
- - ~ a a
~ ~ ~ ~ ~ ~
Fig. 1. YeS~EVM-2 Base Structure
Key:
1. Main Storage 9. Floating-point operations .
2. Processor 10. 16 control registera
~ 3. IO channels 11. 16 general-purpose registera
4. Storage control unit 12. 4 floating-point regiaters
5. Central control unit 13. byte-multiplexer channel
6. Arithmetir, ~nd Logic unit 14. selector channel
7. Fixed-point operations 15. block-multiplexer channel
8. Operations with variable-length 16. peripheral control units
fields and decimal numbers 17. IO interface
All instructions (fig. 2) have a length of two, four or aix bytes and one of six
formats: RR, RX, RS, SI, S or SS. The instruction format reflecta the location
of the operand taking part in the operation.
In the RR inatruction format, both. operands are placed in the general registers or
the floating-point registers, depending on the type of operation. When an RX for-
mat inatruction is executed, one operand ia selected from the general regiaters or
floating-point registers, and the aecond one from main storage. For thia format,
the address of the second operand (memory address) is formed by using an index.
The RS instruction format differs from the RX only in that indexation of the ad-
dress of the second operand is not required for it. For the Sl~format instruction,
. the first operand is selected from main storage and the second directly from the
instruction. In executing SS format inatruc~fons, both operands.�are selected from
main storage. For S format instructions, the first operand is specified in impli-
cit form, and the second is placed in main atorage.
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a
Execution of inatructions in the proces-
sor begins with fetching of the instruc-
ricn whose address is placed in the pro- ~1~

- gram status word register. Then this RR xnn e, N~
address is incremented by the number of o e~z~s
bytes in the instruction, forming the ~1~
address of the next instruction. ex Kon e, xt e2 D= .
0 B 1? ~6 20 31
The address by which the data is ~1~
accessed in main storage is contained in As Kon e, e, a2 ~Z
the register indicated by the field R..of o ' e ~z r6 ~a sr
the instruction, or is formed from the
base, index and displacement, defined by st Kon rt e, n,
the fields B, X and D of the instruction u e ~s zo 3t
(index 1 or 2 defines the number of the
operand s xnn e? n?
o ~ 1 ~ ~s ro 3~
The base is placed in general-purpose
registers and is a 24-bit number, by the ss xnn ~ ~ a, y, eZ Dz
use of which main storage can be ad- o e n~s zo 3z ti0 47
dressed. The base address is used for
addressing an area of a program or data
- files and can also be used as an index.
Fig. 2. Instruction Formate
The index is also placed in general-
purpose registers and is used only Key:
in RX format instructions for 1. KOP (operation code]
addressing an individual element in a
file by the use of a 24-bit number.
The displacement is a 12-bit number, specified directly in the instruction, that
addres~es individual sections of a file with a size of 4096 bytes.
In forming the address, the base, index and displacement are added together as
positive binary numbers and overflow is ignored.
In SS and S format instructions, length of operands in bytes ia specified by
field L.
Aevelopment of the YeS EVM-2 processor structure is aimed at increasing the effi-
ciency of the computational process. In this plan, besides the new functions de-
termined by the principles of operation, the most important are the further de-
velopment and introduction of microprogram control, and the introduction of buffer
main storage that supports fetching of data at a rate corresponding to the
processor cycle oE operation.
Main storage is intended for storing data files and must ensure fast access with
direct addressing to information for the processor and channels. The largest main
storage size is 16,277,216 bytes and is defined by a 24-bit address that always
points to the extreme left byte in fetching some block of information. In the
process, the length of the mem~ry block addressed is determined by two methods:
explicitly and implicitly. In the first case, the address ia accompanied by a
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length code that indicates the number of bytes addressed. In the second, the length
of the data field is defined by the instruction code. This is the case for fixed-
length information since it can equal only 1, 2, 4 or 8 bytes.
To properly define the start of blocks of fixed-length information, the specific
integral boundary rule has been established for placement of data in main storage.
In accordance with this rule, fixed-length data are placed in storage beginning at
the integral boundary for a given block of storage. The boundary for aome block of
information is called integral if its address is a multiple of the number of by�es
in the block. Thus, the binary code of the addresa for reference to main storage
for a halfword, word or doubleword of information must have one, two or three low-
� order bits, respectively, equal to zero. For the majority of unprivileged instruc-
tions in YeS EVM-2 processors, the restriction on placement of operands at the in-
tegral boundary has been removed. In certain cases, this makes it possible to re-
duce the size of inemory taken up by data, however, in doing so, processor speed may
be considerably reduced, especially for high-throughput computers. Therefore,
placing operands at an arbitrary byte boundary is recommended only in exceptional
ca~ses .
The reduction in speed is associated with the fact that for fetching an operand lo-
cated ata-nonintegral boundary, there may be required, firgt, two references to
main storage instead of one, and second, alignment of the ooerand prior to its pro-
~cessing in the arithmetic unit. Placin~z an aperand at a noninte,gral boundary for
write instructions also requires two accesses to storage.
Development of the principles of virtual storage which expand the capabilities of a
computer system led to the formation of concepts of logical, real and virtual ad-
dresses.
Logical addresses are thase us~d by a program that are translated into real by the
address translation facilities.
The different levels of storage linked together by information transmfssion channels
form the aggregate of computer storage units called virtual storage. The highest
level of atorage, main storage or part of it, is called real storage. Addresses
used to access real or virtual storage are called real or virtual, respectively.
Depending on size, main storage may be implemented both in the form of an individual
unit and integrated in the processor. In both casea, access is provided to the
processor and channels by priority, and channels have the highest priority.
The IO channels organize and service the process of data exchange between peripher-
als and main storage, freeing the central processor from these functions. Data is
exchanged with peripherals in two modes: burst and multiplexer.
In accordance with operating modes, two types of channels are used in the YeS EVM-1:
the selector which services one unit at a given time until completion of the data
transmission in the burst mode, and the multiplexer that operates in both the burst
and multiplexer modes, permitting simultaneous execution of several IO operations
for data transmission in small portions (bytes, for in~tance) at time intervals
less than 100 microseconds.
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Used in the YeS EVM-2 is a new type of channel, a block-multiplexer which makes it
posaible to combine the operations for making the peripherals ready for data trane-
miasion with IO operationa.
The channel functional capabilitiea were also developed further: facilitiea Wer~
introduced for indirect addresaing during IO operations, supporting facilities of
dynamic addresa translation of the processor in the organization of virtual etor-
age, and tacilitiea for repetition of instructions in a channel and the two-byte
interface. The aggregate of theae facilities has made it poasible to increase IO
efficiency to a considerable extent.
From the point of view of epecific implementation, channele can be made both in
the form of individual independent unita and with partial uae of proceeeor equip-
ment. In any case, uniformity of IO procedurea defined by the YeS EVM-2 princi-
ples of operation ia maintained.
The broad nomenclature of peripherals for the Unified Computer Syetem includee
devices with various principlea of operations, functional purpobe and rate capa-
bilitips: perforated card and tape units, tape and diak atorage units, plotters
and CRT units, etc.
- The technical characteristics of facilities already in existencQ have been im-
proved and new ones developed in the YeS EVM-2 peripherale. New disk atorage
units with large capacity and tape ~torage units with a high density of recorded
information have been developed. The peripheral nomenclature has been aupple-
mented with displays and systems based on them.
Control units are intende-~ ta control the peripherals. Physically, they can be
placed in the peripherals then.a�'vPs, in the processor or channels, or made as
individual units, but i.n any case, realization of all capabilities aupporting
operation of chr~nnels with the peripherals is maintained.
J
The control units are connected to a channel through the IO interface which
1 makes the control signals device-independent.
The YeS EVM-2 control units have been improved in accordance with the evolution of
the IO peripherals and channels.
Chapter 2. Raising Efficiency of Computations
Enhancement of computational efficiency in the YeS EVM-2 is primarily linked to
the developn~Pnt of the structural organization and to the expansion of the func-
tional capabilities of the central processing unit, the processor, and is achieved
through:
improvement in the throughput/cost ratio as the basic parameter of the genez'al-
purpose computer;
increase in the absolute value of throughput for models of each class;
development of structures with fundamentally new qualitiea: virtual organization,
automation of program debugging, event recording and others;
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~ availability of advanced facilities for building multiprocessor and multimachine
systems, and special-purpose systems;
improvement of operating characteristics--reliability and validity of computations,
reduction of hardware maintenance time and others.
Discussed in this chapter are the basic structural concepts and hardware featurea
of the processor by which the new capabilities for data processinL in the YeS EVM-2
- are realized.
2.1. Main Concepts of Processor Structure
The criterion of efficiency of processor computations for all models in the Unified
Computer System is the throughput/cost ratio, i.e. achieving a given throughput
with the least outlays for equipment. However, this problem is solved differently
for different models. While a given throughput is achieved for low and medium
speed machines by relatively uncomplicated structural methods and, in connection
with this, the determining factor ia reducing equipment cost by using a cheaper,
elemPnt-design and technological ba.se, for high-throughput machines that, as a
rule, use the latest achievements in microelectronica and technology, special com-
plexity is presented by the organization of the computer structure and optimiza-
tion of the computing pracess to obtain a given rate of calculatione. From this
point of view, processor structure efficiency is largely determined by:
_ width of the paths for processing and tranafer of data;
number of.levels of instruction procesaing overlap;
structure and algorithme for operation of the executive units;
organization of execution of instructions for transfer of control;
organization of CPU internal storage; and
degree of joint use of equipment by the CPU a?d channels.
' In addition, improvement in the organization of CPU internal atructure in all YeS
EVM-2 models is related to the development of the principles of microprogram con-
trol and realfzation of the capabilities of connecting apecial-purpose unita
optimized for execution of a particular claea of problema.
Width of Patha for Data Proceasing and TYansfer. In the Unified System of Compu-
ters, the methods selected for addressing main storage and the byte for.�m of data
representation make it possible to use a different width of paths for data proces-
sing and transfer in different models as a function of economic expediency and the
capability of achieving given parameters on throughput.
The width of the path for processing operands differa as applied to the CPU, i.e.
the width of the arithmetic unit, and the width of the path for data exchange be-
tween the CPU and main storage (instructions and operands)
The width of the path for data exchange affects both the rate of processing and
the size of the CPU equipment. This atems primarily from the fact that the width
_ of the path for data exchange largely determines the organization and effective
time of main storage operation.
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As a rule, main storage is divided into independent logical blocks that makes pos-
sible access to some blocks before eompletion of an operation uegun in other
blocks. Used in the process is the principle of interlesving of addresses or the
so-called interleaving of main storage, which consists in the fact that the addres-
ses of related addressed storage cells are located in variout~ logicel blocks.
Usually, a two-, four- or eight-fold interleaving of gtorage is used, i.e. there
are two, four or eight independent blocks of storage in the system. The width of
the path for data exchange with one logical block is Cwo, four or eight bytes.
With interleaving of storage, each logical block has its own independent main
paths for data exchange.
The width of the path for data exchange in the majority of caszs cl~~arly defines
- the width of the path for processing of operands in the arithmetic and logic units.
By the width of the arithmetic unit is meant the width of the adder and the main
registers for the operands. And when there are several aclders in the CPU, as for
example in high-throughput CPU's, the width is determ~ned by the adder in which
operations on operands with fixed-point are executed.
Since arithmetic unit equipment makes up from 40 to 70 percent of the total CPU
equipment, the selection of the width for data processing has a considerable
effect on the total equipment. At the same time, it i~~ obvious that when the
widtti of the processing path is reduced, the time for execution of operations will
be increased for operands whose size exceeds the processing path width. Taking
this into account, two, four and eight bytes are usually selected for the exchange
and processing path width for low, medium and high-throughput machines, respective-
ly.
Number of Levels of Inetruction Processing Overlap. To increase the rate of in-
struction processing in the CPU's, the concurrent processing method is used: the
whole processing process is subdivided into stages and execution of the different
stages of several serial instructions coincides in one CPU operation cycle. To
achieve concurrent processing of instructions in a CPU, functional and independent
blocks are separated out; each of them executes only one of the instruction pro-
- cessing stages. For example, for the case of three-level concurrency, the proces-
sing process is subdivided into three stages: the stage of preparing the instruc-
_ tion for execution, i.e. fetching the instruction from main storage and generating
the addresaes of the operands, the operand fetching stage, and the stage of direct
execution of the operation in the arithmetic unit. Subdividing into stages is
usually based on equal time intervals for execution of thP individual stages, since
only in this case is maximum efficiency achieved for making use of the individual
functional blocks of the CPU that afford concurrent proceasing, i.e. there is no
idle time in waiting for the completion of operation of preceding or subsequent
blocks.
For three-1eve1 concurrency in a CPU, it is necessary to assign a block for �etch-
ing instructions and generating addresses, a block for fetching operands and an
executive block or arithmetic unit.
In addition, characteristic of YeS EVM-2 CPU's are stages for prefetching of in-
structions and operands and buffering them for subsequent proceasing, and overlap
of execution of the various operations in the executive units of the arithmetic
and logic unit, which increases even more the number of processing stages and
overlap levels.
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Although the efficiency of the method of overlapped processing of instructions,
from the point of view of increasing CPU throughput, is a function ~f the number of
overla~ levels, this dependency is not proportional. The full use of efficiency of
' the overlap method is rather rarely achieved in solving problems, since any suc-
cessful branch instruction in t?ie program or use by a following instruction of re-
~ sults obtxined c~uring execution of a preceding instruction causes stoppages of
instruction processing.
In fact, tim~ T for processing S instructions with K levels of overlap can be
c
represented by the following expression:
, 7'~-7'(K~-S
~ K
where T is the time for execution of one instruction wi�thout overlap.
It is easy to see that when one instruction is executed (S=1), T~=T, and with a
full CPU load over a long time (S-~~), the rate of instruction proceasing tends
to the value equal to T/K. Thus, the overlap method does not reduce the execution
time for one inatruction; it does make it posaible to increase device throughput.
Therefore, if dependent instructions (instructions, upon sequential entry of which
to input of the unit, processing of the next instruction can be started only after
completion of execution of the preceding one) are encountered among the instruc-
tions S, CPU throughput is reduced to ttie value defined by the order of dependency
~ of the overlap levels compared to the case when there is no dependency of instruc-
tions. Levels of processin~ of instructic~ns with numbers m and n(m ~ n) are de-
pendent, if to start proces3ing of the current instruction at level m, it is
necessary and sufficient that procesaing of the preceding instruction at level n
be completed. The value N=n-m is called the order of dependency of the overls~
levels. It can be shown that in thia case, the CPU instruc:tion processing rate is
defined by the expression
(K~-r-S- ~l
- T`- T l K~ , 1'
where K=K/N. Physically, this means that in the case of dependency of instruc-
tions, lit is as if the number of overlap levels is reduced and, conaequently, the
CPU throughput is reduced. Thus, if execution of an instruction at the firat level
cannot be started until the instruction at the last level has been executed (for
example, the result of the preceding instruction changes the content of the follow-
ing instruction), the order of dependence of the leve b of overlap N equals K,
which is equfvalent to operating without overlap (K1=1).
The relationship between instruction execution ovsrlap efficiency and instruction
interrelationships presented above is considered in the moat general form. In
fact, this relationahip is far more complex and, in addition, inatruction execut-
_ ion overlap efficiency is affected by a large number of other factors. It should
also be taken into consideration that overlap of procesaing increases the size of
equipment and complicates the con~trol circuit.
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All these circumstances have to be taken into account in selecting the number of
levels of instruction processing overlap in each specific case to achieve given
parameters and first of all the throughput/cost ratio. Experience in developing
~ the Unified System computers and studies made indicate that overlap processing ie
technically and economically expedient for a class of machines in which up to fiv~
instructions are executed simult~neously. Therefore, the CPU's in the different
models of the YeS EVM-2 generally use two- and five-level overlapping as a function
of throughput. At the same time, sequential processing of instructions is provided
for in the smaller models, and in those machines where overlapping is used, modes
of operating without overlap have been provided for to facilitate search for and
localizatian af malfunctions in diagnostic procedures.
Struciure and Algorithma for Executive Unit Operation. These units include the
traditional CPU arithmetic and logic units [ALU] and specialized hardware (for
example, a high-speed multiplier) that was developed in the YeS EVM-2. Executed
in these units are all the arithmeti.c and logic operations in the universal in-
struction set in the YeS EVM-2, which includes operations on numbers with fixed-
point and with fioating-point with conventional and extended precieion, logical
operations and decimal arithmetic operations. Operations are executed with
fixed and variable length fields.
Further raising ot the efficiency of executive units in the YeS EVM-2 comparee~ to
the YeS EVM-1 is determined by the:
expansion of functional capabilities;
improvement of etructural organization; and
use of more efficient algorithms. '
The functional capabilities of YeS EVM-2 CPU executive units have been expanded by
the introduction of facilities for executing extended-precision floating-point
operations. In this case, CPU efficiency is increased in solving acientific and
technical problems and primarily those that have a large number of computational
iterations. Using conventional-precision floating-point operationa in aolving
these problems in some cases does not provide the necessary precision of the result
because of rounding errors. The introduction of facilitiea that permit operating
with a mantissa consisting of 28 hexidecimal numbers reducea the criticality of
this factor. Seven extended-precision floating-point arithmetic inatructions have
been introduced in the YeS EVM-2: ADD NORMALIZED, LOAD ROUNDED (extended to long),
LOAD ROUNDED (long to short), MULTIPLY (extended), MULTIPLY (long to e:~tended--RR
instruction format), MULTIPLY (long to extended--RX instruction format) and
SUBTRACT NORMALIZED.
Executive unit structure in the various YeS EVM-2 moclels determines the following
trend :
minimal size of equipment through universal arithmetic units with a small width of
operating units ~8-16 bits) for the small models;
use of additional equipment which speeds up execution of individual operations with
an increase in the width of the operating assemblies to 32 bits for models in the
- medium class;
achievement of maximum speed in the large models through specialization in opera-
tions of arithmetic units of large width (h4 bits); and
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= use of microprogram control to the full extent of operationa for small and mQdium-
size models, and �or large models to the extent in which achievement of the given
throughput is possible.
With the introduction into the CPU of buffer storage that supporte fetching data
at the rate equal to the CPU operating r_ycle, the time for execution of operations
in the operating units of the executive units has become decisive in determining
the computer speed. CPU computation rate depends to the highest extent on execu-
tion of addition/subtraction and multiplication/division operations with fixed and
floating point. Based on this, the structure of the operating units must in the
firat place be oriented to rapid execution of these operations. ~
An efficient and widely employed method for structural organization uf executive
units that results in increased throughput is the use of the principle of local
paralleliam which consists in parallel processing in time of the algorithm for
execution of an individual operation by splitting it into a series of independent
sections. Such parallel processing is possible when the result of operation of
- one section of the algorithm dces not depend on the result of operation of another.
Thus, in executing a floating-point operation, operations on exponents are execu-
ted at the:same time as operations on the mantiasas.
Concrete realization of this principle requires incorporating several proceseing
functional assemblies that operate concurrently in time: mantissa adder, exponent
adder, operating shifter and analysis circuits. The principle of local parallelism
leads to increased speed not only through parallel processing of the operands pro-
per but also through parallel analysis of the operands and execution of the
functions of checking and control.
Used in the large YeS EVM-2 models also is the well known method of increasing
speed: the method of conveyor processing. To implement conveyor processing, the
entire processing apparatus is subdivided into eteps, operating sequentially one
after the other, that perform elementary operations. The sequence of elementary
operations being performed while passing through all the steps determines the
execution of the full operation. The high speed of the conveyor method of proces-
- sing stems from the short fixed time for execution of an elementary operation and
the concurrency of operation of all steps. Intermediate results of processing in
these steps are stored in registers which makea it possible to avoid the effect of
asynchronization. Selection of the number of atepe and clock time for their opera-
tion is determined by the capability of achieving a given throu$hput taking into
account limitations on equipment size and the convenience of obtaining the required
clock frequency from the basic frequency for synchronization, and is also based on
the functional composition and physics:. properties of the element system selected.
Speed of executive units can be increased also through their specialization.
Specialization, i.e. orientatf.on of unit functions to execution of one type of
operation, allows optimal achievement (for a specific unit) of maximum posaible
speed with existing technology, although it should be noted (as a disadvantage)
that a considerable amount of equipment is required to implement the whole set of
operations. Therefore, a basic problem is the optimal selection of the number and
types of units. Since specialized units are used for the highest throughput models
where it is necessary to obtain the maximum possible speed while disregarding out-
lays for equipment, in selecting types of units, i.e. their organization, the
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orientation is on speeding up execution of operations which are processed in more
than one machine cycle in the universal units. These operations include primarily
multiplication, division and addition with floating-point. Based on this, the fol-
lowing types of executive specialized units are used in the CPU for the large YeS
EVM-2 model: unit for �ixed-point operations, unit ior floating-point operatione,
unit for multiplication and division, and a unit for decimal arithmetic.
A further development of thia method for increasing the speed of executive units is
the organization of parallel operation of the operating units. However, for high
- efficiency of parallel operation, epecial software is required that allowa dis-
tributing instruction streams with regard to specialization of the unita.
The problem of optimal correlation between speed and economy for medium-size cpm-
puters, as a rule, ia solved by apeeding up only certain operations. "Accelerators"
are used for these purposes, i.e. supplementary equipment opPrating at an increased
clock frequency and oriented to speeding up a certain section of the algorithm for
execution of certain operations.
Thus, used is the YeS-1045 computer is an accelerator for executing a number of
operationa based on the tabular method of obtai:ling a result. The acclerator is
implemented with high-speed microcircuits of p�rogrammable read-only memory (PPZU)
[PROM] with a 256 X/~ organization. A table is atored in the PROM, and the appro-
priate result is generared at the PROM output as a function of the input signal.
In other words, the various Boolean functions of the input aet are output as a
function of the prog,ram embedded in the PROM. Also undergoing acceleration are
operations that have a substantial effect on throughput (multiplication, tranefer,
packing) and operations that, on the one hand, are conveniently implemented by
using the tabular method, and on the other, do not require additional outlays for
equipment. The accelerator is controlled by a special accelerator control memory
with a size of 512 48-bit words, the cycle of which is half the cycle of the CPU
control memory. Use of the accelerator has made it posaible to increase the
throughput of the CPU in the YeS-1045 computer by 15 percent on the average with
a 6 percent increase in equipment.
Executive unit throughput is largely dete;rmined by the efficiency of the algorithms
for execution of multiclock operations (addition, mu;.tiplication, division with
floating-point, translation of codes, and a number of operations for processing
variable-length fields). In this case, by effxcient algorithms are meant algo-
rithms that make optimal use of the structure of the executive units. It is
obvious that these algorithms will vary for each computer class in the Unified
Sys tem .
Organization of Execution of Instructions for Transfer of Control. Used.in rating
internal CPU speed are so-cal.led mixtures of instructions that take into account
execution time and r~currence (weight) of individual instructions in programs for
the most typical classes of problems. Statistics show that CPU computation rate
is most affected by only about 10 types of instructions which require raising the
execution rate. These instructions include (in addition to those discussed in the
preceding section) transfer of control instructions too which affect not only the
rate, but to a considerable extent also the CPU structure.
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tn t}ie Ur~if ieci System of Computera, [wo methods of raising the executien rate of
transfer of. control instructiona are widespread. The first is based on a statis-
~ tical account of the probability of successful execution of an instruction for
conditional transfer of control, and the second, on a statistical accoun~ of the
most probable length of program cycles realized by using instructions for con-
ditional transfer of control.
Implementatian of the first method requires rapid prefe:ching of instructions from
main storage, overlap processing and incorporation of additional buffers with a
size of 8-16 bytes into the CPU structure. Qne buffer is used to store the basic
sequence of instructions in executing the program. When a transfer of control in-
struction is encountered, an estimate of the most probable outcome is made and
fetching is organized for the instructions of that branch of the program that will
- most probably be executed after completion of the branch instruction. These in-
- structions are placed in the second buffer and processing of them is started even
before the transfer of control instruction is executed. When the estimate is cor-
rect, the high rate of instruction processing is maint.ained; in the opposite case,
fetct~ing of the other branch is not r.equired since it is stored in the first buffer
and can be processed right after completion of execution of the tranafer of control
instruction.
In the fastest computers, the CPU structure has a third bsffer for [areselected in-
structions. It is used to store instructions selected as a result of processing of
the next transfer of control instruction in the most probable branch of the progratri
before completion of execution of the preceding one.
Implementation of the second method for speeding up execution of conditional trans
fer of control instructions is organized by a buffer for processed instructions,
in which usually from 64 to 128 doublewords of instructions are kept, i.e. in exe-
cuting the basic sequence of instructions in a program, the processed instructions
- are not erased, but stored in a the special buffer. In this case, a special algo-
rithm has to be provided to replace processed instructions of old information in
the buffer by new. The main idea of the second method is this: Since conditional
transfer of control instructions are usually placed at the end of a cyclic section
of a progiam when programs are written, in the majority of cases, this conditional
transfer will point to a section of the program already selected. This is preciae-
ly the section of the program with high probability that is atored in the bufEer
of processed instructions, which makes it possible to reduce the time for preparing
instructions of the new branch for execution.
Shown in fig. 3 are the structural schemes for paths of instructions in speeding up
execution of transfer of control instructions by the method of estimating the pro-
bability of a transfer (a) and the method of probable length of a cycle (bi.
Both of these methods require additional equipment outlays for implementation and
result 'n considerable complication of the control algorithms in the CPU; however,
they are used in~the large YeS EVM-2 models because they produce a considerable
increase in the CPU speed, while reducing execution time by a factor of two to
three for transfer of control instructions.
Qrganization of CPU Internal Storage. CPU internal storage consiste of a large
number of resiters and buffer storage for temporary storing of intermediate results
obtained during execution of operations, storage of data files during exchange,
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i~~~~~o~c t i on s
_ a t. ,
p~~v~~ ~p~a- bu f f er a f or ,
~ ~ . ~16QCN 6/A'
MOMOH~ Preselected
iRstruction.s
p �~~""p re ister for instruction
o erand address oB~u6ore~~otMad ~
ko..nNde~
�generation Cxe~io y~psrupo- being procesaed
~aNUr+ p~pccU
C 1 r C U 1 L onPpnNdo Ovepeae
ur.nonnneMe~,queue Of instructions
i � NpMONB
- address Aave~ to be executed..
, O~iepunda~
NcnonMU~tneNe~u
operands 6ioK � executive unit
KoMO~~ae~ n s tr uc t i ons
b h w n ~n~ae~o~,~~e- buffer for preeel~cted
~ ~e~hpnNUeix u
. , eb~~~~~,~NN.~x and executed
' NonnN
- instructions
Oe?ucrp
operand address o6i~a6~~e~e~e~~o,:register for inatruction
CKtNa qin nu o- ~'~~uNae~ be in roceased ~
generation eaNUA q~�Q , 8 P
- C 1 T C ll l t onepando
Ovep~ae queue of instruc tions .
ucnonNAe.ve~~
. . KOI/ON(J to be executed
address A'~P_`~
~ Onepandei
o p e r and s Ncnondu ~eneHeiu
6~oK executive ut~it
~
Fig. 3. Scheme for execution af transfer of control instructions by the method of
estimating transfer pr.obability (a) and the method of estimating loop
length (b)
storage of control attributes and information on computer status during program
execution and information that controls the sequence of instruction execution.
CPU computational efficiency is largely determined by the structure and speed of
internal storage, since certain of its components directly determine or affect to
a considerable extent the CPU operating cycle.
A major c}~aracteristic of a CPU and computer is the CPU and IO channel data ex-
change rate with main storage. As noted earlier, aelection of the optimal exchange
path width and use of interleaved memory make it posaible to increase the data ex-
- change rate; however, a substantial factor in increasing this rate ie the reductior..
of fetch time and ~ycle time of main storage. CPU buffer storage and channel buf-
fer storage are used in YeS EVM-2 CPU's to reduce the effective cycle of main
storage.
Main buffer storage is an intermediate block of storage (between the basic main
storage and the CPU) that operates with the CPU cycle and provides for storing
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instruction and operand files most frequently used by the processor. Buffer stor-
age usually holds from 8 to 64 bytes, which permits a reduction in main storage ac-
cess time. Buffer storage is filled as data is fetched from main storage during
program execution. Since programs have a limited amount of instructions and ope-
rands and usually operate in the cyclic mode for processing a data file, af ter exe-
cution of the first cycle, about 90-95 percent of needed information will be in
. buffer storage. Consequently, during subsequent operation of the program, instruc-
tions and operands will be fetched not from main, but from buffer storage. In this
case, the effective main atorage cycle will be close to the buffer storage cycle.
Algorithms for replacing information in buffer storage provide for holding the most
frequently used data files. Exchange between main and buffer storage occurs in
blocks containing from 16 to 64 bytes, which permits making effective use of
interleaved main storage.
Processor buffer storage may be used for operation of IO channels, but this leads
to the emergence of conflict situations during a simultaneous call from the chan-
nels and the processor and, consequently, to a reduction in the efficiency of the
operation of tiuffer storage. Therefore, to raiae the rate of data exchange be-
tween channels and main storage, used more often is special buffer storage for
channels, which is broken down into groups of registers allocated for each IO chan-
nel. As a rule, four to eight double words of information each are stored in these
registers. With this organizati~n of exchange, the capability emerges of making
efficient use of interleaved storage and reducing data exchange time, because the
channel effects its exchange not with main storage, but with the buffer storage for
_ the channel. Information is exchanged.between main storage and channel buffer
storage also in blocks of four to eight double words each.
The introduction of buffer storage units, in addition to redticing the effective
- cycle of main storage, also leads to a reduction in the number of conflicts during
a simultaneous call for storage from channels and the processor. Both the former
and the latter are especially important for high-throughput computers, which has
dictated the use of buffer memories in the YeS EVM-2 medium and large models. Use
of these memories in small models is inexpedient because of the relatively high
cost of the additional equipment needed to implement them and the considerable com-
plication of the organization of the processor control structure.
The method of storing intermediate resulta of computationa also largely determines
processor structure. in essence, in the Unified System of Computers, this method
is determined by the instruction set, form of data repreaentation and addressing
structure. In the general case, there are three ways of organizing storage of
intermediate results obtained during performance of calctilations.
The first is based on sending any results to main storage immediately af ter com-
pletion of the calculations without intermediate storage in the processor. This is
one of the most uneconomical methods since repeated access to main storage is
required in the process of executing one instruction.
The second method calls for using an intermediate register through which the re-
sults are transferred to main storage. Here the number af transfers is reduced,
since the information in the register can be used during execution of the opera-
tions. But in this case too, rather frequent access to main storage is required
tu free the register.
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The third method uses several registers that form a small amount of storage, and
the reaults of the various groups of operations are k~pt in their own registera.
In this case, the number of registers or storage size is selected in auch a way
that as a rule, only final reaults are stored in main atorage.
In essence, all three methods are used in Unified System processors, but the third
_ one is the main one. For this purpose, the processor structure has 16 general-
purpose registers and four registers for storing resulta of floating-point opera-
tions (see chapter 1). The general-purpose registers atore resulta of fixed-point
operationa and are also used as index registers in modifying an address and execu-
ting instructions associated with addressing, which elii:~inatea the need for addi-
tional registers for these purposea. Beaides this, a program status word (PSW]
register and a group of control regiaters are used to store control features and
information on the current status of the system during program exeCUtion.
- Direct writing of results to main storage is provided for only for "starage-to-
storage" instruction formst, during execution of which variable-length operands
are processed. This is because storage of intermediate results would require a
buffer too large in size and in addition, these instructions are not decisive for
computer speed.
For writing information to main storage in large models, in addition to the methods
discussed, individual registers are used that are intended for coordinating opera-
tion of the CPU and main storage with store instructiona.
~
The microprogram method of control is used to one or another extent in all YeS
EVM-2 models. Organization of the control storage for microprograma is a major
feature determining the efficiency of CPU operation. In each specific case, it is
selected on the basis of the computer purpose, throughput and structure. From a
physical point of view, control storage for microprograms comes in two varieties:
read-only storage [ROS] and writeable control storage [WCS]. ROS is used only for
reading of information and, as a rule, is faster and simpler for control than WCS.
At the same time, WCS offers additional capabilities for raising CPU efficiency
through continuous improvement of algorithma for executing operations.
Joint Use of Equipment by CPU and Channels. To reduce the total amount of equip-
ment in some models in the Unified System, the principle of so-called integrated
channels has been implemented. It is based on the fact that procesaing of instruc-
tions in the CPU during program execution and proces5ing of IO operations in a
channel are largely similar and require the same type of both executive and control
assemblies and units. Based on this and on the fact that information exchange be-
tween a channel and an external device takes conaiderably more time than that for
data exchange between a channel and main storage, it is possible to use a part of
the CPU equipment to perform channel functions. This permite a substantial reduc-
tion in channel equipment and designing it into the CPU. The common equipment is
used primarily by the CPU. After completion by a channel of an exchange of a
routine portion of data with an external device, CPU operation is halted tempor-
arily and the necessary operations for a channel exchange with main storage are
perf~rmed.
_ In each specific case, depending on the organization of the computational process,
the channels can use various equipment of the CPU, but, as a rule, this equipment
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includes the control storage for the microprograms and the storage control unit
(exchange path). Microprogram control provides for data exchange between the
channels and main storage and organization of processing of control information,
and the microprogram storage unit is used by the channels and.CPU on a time-sharing
principle. In addition, in many cases, the CPU ALU is designated for processittg
control information for a channel. Joint use of equipment is provided for by using
- hardware-controlled priority circuits that permit transfer of control to a specific
unit only at certain points of the microprogram sequence of the CPU and channels.
Since channel operation can be interrupted upon CPU request, each channel must be
provided with its own address register for storing the current addreas when control
storage is transferred to the CPU. After transfer of microprogram control to a
channel, it will continue its operation at the address stored in the register.
In the general case, from the viewpoint of equipment used, channel functions are
divided as follows: data is exchanged with IO peripherals under contr~~l of channel
hardware in parallel with CPU operation; data exchange between channels and main
storage, as well as processing of control information is performed by CPU facili-
ties under control of microprograms and in this case the CPU is not performing its
own operations.
The principle of integrated channels is used only in the amall and sometimes in
medium-size YeS EVM-2 models, since use of this principle in large models is not
warranted because of limitations that it imposes on CPU speed. ,
2.2. System Control Facilities
CPU system control facilities provide for the set of necessary actions for monitor-
ing system states, specifying modes of operation, protecting programs from destruc-
tion, expeditious linking of hardware facilities together and synchronization of
their operation in time, ext~rnal intervention, etc. Some of these facilities are
well known from their use in YeS EVM-1 (facilities of direct control, external in-
terrupts, storage protection and initial program loading). A number of new facili-
ties have been introduced in the YeS EVM-2 that raise control capabilities to an
even greater extent:
facilities of extended control and control registers;
facilities for expansion of the system of interrupts;
facilitiea for program event recording;
faci~ities providing for monitor programs; and
facilities for time readout.
Extended Control Mode. The PSW defines the status of the computer and controls
operation of hardware and software.
In the YeS EVM-2, there are two control modea that determine the function of the
PSW fields and bits and use of permanently assigned locations in main storage.
Operation of computer hardware while maintaining full program compatibility with
the YeS EVM-1 is defined as the basic control mode (BC mode).
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Operation of the new hardware and software under which additional functiona are
performed and greater capabilities emerge ia defined as the extended control mode
(EC mode).
The modes are specified by the value in PSW bit 12: 0 for the BC mode or 1 for the
EC mode.
In the EC mode, the location of certain control fielda in the PSW is changed, aome
PSW fields have been removed and.additional ones introduced. In particular, the
interruption code and the instruction-length code have been assigned permanent
main storage locationa, masks for interruptions have been expanded and placed in
the control registera, and additional control fields have been introducad in the
PSW: the program event recording mask and the translation mode.
Table 1 shows the allocation of PSW fiel.ds that fully determine the state of the
computer hardware at a given time.
For the EC mode, PSW bit 1 has been allocated for the program event recording maek,
and bit 5 definea the translation mode. Unused PSW bits in the.EC mode must
contain zeros.
Table 1. Allocation of PSW Bits PSW Bits
- Function of PSW Fields BC EC
Channel masks 0-5 0-5 *
IO mask 6 6
External interrupt mask ~ ~
Protection key 8-11 8-11
Control 'mode 12 12
Machine-check mask ].3 13
- Wait state 14 14
Problem state 15 15
Interruption code 16-31
Instruction-length code 32-33
Condition code 34-35 18-19
Program mask 36-39 20-23
Instruction addreas 40-63 40-63
*
Channel masks are stored in control regieter 2.
Interruption and instruction-length cc~des are stored in permanently assigned
locations in main storage.
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Control Regiatera. Sixteen 32-bit control registere have been provided for stor-
ing additional control information that expands PSW information in the CPU.
Control information is loaded into the registers and their contents stored in main
storage by execution of the instructions LOAD CONTROL and STORE CONTROL.
Control registers support CPU operation in the EC mode, hold the expanded maska for
external interruptions and IO channel interruptions, control information for the
facilities of virtual organization of the system and other new facilities in the
Unified System.
Control register 0 includes the fielde.for ccntrol of the block multiplex mode for
the IO channels (bit 0) and control of suppression of set system mask [SSM] (bit 1).
Facilities for organization of multiprocessor systems use the clock synchronization
control field--bit 2 of control register 0, and masks for malfunction alert, emer-
gency signal, external call and clock synchronization check--bita 2, 16-19 of con-
trol register 0. Dynamic addresG tranaslation facilities use a control field for
_ page and segment size control--bits 8, 9 and 11 of control regiater 0, as well as
fields for segment tahle length and segment table addrese--bits 0-7 and 8-25 of
control register 1.
Channel masks which determine the CPU accessibility for IO interruptions in the BC
mode are stored directly in the PSW (bits 0-5). In the EC mode, these masks are
located in control register 2(bits 0-31). Control register 8 containa the moni-
tor masks in bits 16-31.
Program~event recording facilities contain individual event masks in bits 0-3 and
~ 16-31 of control register 9; the starting and ending addresses of the main storage
area monitored by the recording are stored in bits 8-31 of control registers 10
and.ll.
ri~chine error. r,r^~^_ee'_.^.b facilities ar.d recev�ry faci li ties uee ~~-.trol Y'e~i ~arPT'R
14 and 15 for their purposes.
~ Unused bits of control registers and unused registers must contain zeros.
Interrupt System. As a function of the interrupt source and cause, there are six
classes of interrupts: supervisor call, program, external, I0, restart and
machine check.
lluring execution of the SUPERVISOR CALL instruction, an interrupt aignal is gene-
rated whose main purpose is the switching of the CPU from the problem to the super-
visor state. Program interrupts occur when an instruction is executed incorrectly,
and when operands and computer devices are used incorrectly. External interrupts
provide for CPU response to signals from time readout facilities, interrupt aignals
from the operator's console and signals from six external sources. Requeste for
an IO interrupt come from a channel after completion of an IO operation in'a chan-
nel or external device control unit, as well as after CPU intervention when certain
situations occur in the IO syetem. The restart interruption is initiated by
activating the restart key on the system console.
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A machine check interruption results from a system malfunction and ia calssified
as either hard or soft. A h3rd interrupt is caused by a nonrecoverable machine
error. A soft interrupt is caused by a recoverable error.
Each class of interrupts has been allocated two fixed locationa in main storage.
Stored in the first location is the current PSW transferred from the PSW register
at the instant of interruption. The double word stored in the first location is
called the old PSW. It is stored again in the PSW regiater after execution of the
interrupt subroutine. Stored in the second location is the new PSW that af ter
storage of the current status in the first location is transferred to the PSW re-
gister for initialization of the inte~-rupt subroutine. Bits 16-31 of the old PSW
contain an interruption code that apecifiea the cause or source of the interruption.
With the emergence of the new hardware facilities (dynamic address translation,
program event recording, monitor, multiprocessor systems and new time readout), it
was necessary to introduce new types of interruptsto support the interaction of
this hardware with the software system. This in turn required the development of
control of interrupts through inclusion of masks for the new hardware facilities
in the control registers.
Expansion conc2rned the class of program interrupts and the claes of external in-
terrupts. Program interrupts were introduced in operation of dynamic address
translation facilities associated with use of a segment (interrupt code 10) and a
page (interrupt code 11), as well as with specification during translation (code
12). Interrupts supporting operation of the monitor and program event recording
also pertain to the program class and have codes 40 and 80, respectively.
- Signals of external interrupts were introduced that are associated with operation
of a multiprocessor system (malfunction alert, emergency signal and external call:
interrupt codes 1200, 1201 and 1202, respectively), as well as with operation of
the new time readout facilities (time-of-day clock synchronization check, clock
_ comparator and CPU timer: codes 1003, 1004 and 1005).
In addition to expansion of the interrupt system, with the introduction of the
new hardware facilities the need arose too for storing additional information dur-
ing the interruption. This in turn required new fielde in permanently allocated
main storage that were intropduced as well for machine check handling facilities
and recovery facilities.
Table 2 gives the location of the new fields in ~ermanently allocated storage.
Monitoring Facilities. Monitor facilities were introduced for basically two rea-
sons. First, raising the capabilities of the multiprogramming and time sharing '
modes required development of facilities that would allow selective storage of
information at a certain time during program execution. Second, there was a re-
quirement for statistics that permit monitoring the course of execution of pro-
grams and analyzing the efficiency of CPU operation. Theae facilities can be used
to track which programs were executed and at what times, and also how often they
were used.
Access to the monitor program that.implements execution of the necessary functions
is effected by using interrupts. For these purposes, the special instruction
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Table 2. Assigned Ma.in Storage "Locations
Address
~ hexa-
- decimal decimal Function of field
0 0 restart new PSW
8 8 restart old PSW
18 24 old PSW for external interrupts
20 32 old PSW for supervisor call interrupts
28 40 old PSW for program interrupts
30 48 old PSW for machine check interrupts
38 56 old PSW for IO interrupts
40 64 channel status word
48 72 channel addreas word
50 80 interval timer
58 88 new PSW for external interrupts
60 96 new PSW for supervbaor call interrupts
68 104 new PSW for program interrupts
70 112 new PSW for machine check interrupts
78 120 new PSW for IO interrupts
84 132 processor address during external interrupt in EC mode
86 134 external interruption code in EC mode
~ 88 136 instruction-length code and aupervisor call interrupt code
in EC mode
8C 140 instruction-length code and program interrupt code in EC mode
90 144 translation exception address during program interrupt in EC
mode
'94 148 monitor class number during program~interruption due to a
monitor event
96 150 program event recording code during program event interrupt
98 152 address of instruction that caused interrupt for program event
9C 156 monitor code during monitor event interrupt
A8 168 channle ID during execution of STORE CHANNEL ID inatruction
AC 172 IO extended logout addreas
BO 176 limited channel logout information
B8 184 IO addreas during an IO interruption in the EC mode
D8 216 machine check interruption code and expanded information on
the machine check interruption
MONITOR CALL has been introduced that is placed at certain pointa within the pro-
gram being executed. As soon as program processing reaches thia point, the MONITOR
CALL instruction is fetched and a program interrupt occura that ia aerviced by the
monitor subroutine.
The MONITOR CALL instruction has the SI format, i.e. the operand is placed directly
in field I2 (bits 8-15). In this case, bits 12-15 specify one of the 16 posaible
monitor classes, and bits 16-31 (fields B1 and D1) the monitor code. In essence,
the monitior~code performs the role of an interrupt code identifying the function
that must be performed. Within the bounda of each monitoring class, 24-bit addres-
sing can be used that is defined by the monitor code.
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Depending on circumstances, performance of a particular function defined by the
monitor class may be suppressed. For this in bits 16-31 of control register 8 are
stored masks corresponding in ascending order of the numbers to all 16 monitoring
classes. For *_hose monitor classes with a mask bit equal to one, att interrupt is
permitted. If the mask bit is zero, no interrupt is initiated.
During an interrupt, the interrupt code (monitor call) is placed in the old PSW,
and the monitor class and code are placed in permanently allocated main storage
~ at addresses 148 and 157-159, and in the process, zeros are placed in the bytes
with addresses 149 and 156.
Program Event Recording Facilities. Computer program debugging is a laborious,
but necessary operation that cannot be solved by another method. Therefore, the
availability in the CPU of special facilities that facilitate the process of pro-
_ gram debugging and reduce machine time in the process is a mandatory part of
modern computers. In the YeS EVM-?_, these facilities include program event record-
ing facilities. Program events to be processed are recorded by uaing the mecha-
nism of program interrupts. The interrupt code identifies the program events that
cause the interruption.
Program event recording facilities operate only in the EC mode and control infor-
mation for this is stored in control registers 9-11. Bita 0-3 of control register
9 contain the ~e~ent masks and bits 16-31 contain the genEral register masks.
Event masks specify which events are monitored and the bits are assigned as
followe: 0 successful branch;
1 instruction fetch;
2 storage alteration; and
3 general register alteraticn.
General register masks specify which general registers are monitored for altera-
tion of their contents. For this, each of the 16 mask bits in ascending order
corresponds to a general register number.
The starting address of the monitored main-storage area ia stored in bits 8-31 of
control register 10. The ending address of the monitored main-storage area is
stored in bits 8-31 of control register 11. The starting and ending addreaoes
specify a atorage area for two events 1n a program: instruction fetching and
starage alteration. When the starting address ia equal to the ending addresa,
only the location designated by that address is monitored. When the starting ad-
dress is larger than the ending address, the monitored storage area consists o~
two zones. One zone covers the area from th~ starting address to the largest ad-
dress in the system, and the other, from location 0 to the starting address. Thus,
the maximum possible amount of main storage, defined by a 24-bit address, may be
allocated for recording of these events.
During an interrupt caused by program event recording, additional information on
the cause of the interrupt is placed in the permanently allocated storage area
(locations 150-155). The specific event code that caused the interrupt is placed
. in bits 0-3 of location 150. !'he values of these bits correspond exactly to the
values of the event mask bits in bits 0-3 of control regiater 9. The addresses of
instructions that caused a given event in a program are stored in bits 8-31 of
locations 153-155. Zeros are placed in all other bits of locationa 150-155.
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Time readout facilities include the time-of-day clock, CPU timer, clock comparator
and the interval timer.
The time-of-day clock continuously measures elapsed time and is a 52-bit binary
counter, in which information is represented in the form of an unsigned fixed-point
number. The clock is incremented by adding a one in bit position 51 every micro-
second following the rules for unsigned fixed-point arithmetic. A carry into bit
position 0 is ignored, and counting continues from zero on.
The time-of-day clock operates in all CPU states: wait/running, problem/supervisor
and stopped/operating. Its operation is not affected by any operations for CPU and
system reset. Time-of-day [TOD] clock operation can be stopped only by a clock
malfunction, by disconnection of power to the CPU or clock itself and when it is in
the STOPPED state.
The STOPPED state of the TOD clock is set each time before its contents has to be
altered by the SET CLOCK instruction, by which the current number stored in the
counter is replaced by the operand specified by the instruction. Transition from
the STOPPED state to a new state and vice versa is defined by bit 2. of control re-
gister 0. When this bit is one, the TOD clock remaina in the STOPPED state. A new
clock value is set by the SET CLOCK instruction only whPn this bit is zero.
The TOD clock value can be stored in main storage by the instruction STORE CLOCK.
When this instruction, as well as the instruction SET CLOCK, is executed, facili-
ties have been provided to ensure synchronization of clocks when there is more
than one in a multiprocessor system organization.
When it is necessary to cause an external interrupt at a certain TOD clock value,
the clock comparator is used for these purposes. The value specified in a program
is stored in the comparator by the instruction SET CLOCK COMPARATOR; this value is
continuously compared to the TOD clock value. An interrupt signal is generated at
the moment these values coincide. Comparator contents are stored in atorage by
the instruction STORE CLOCK COMPARATOR.
The CPU timer provides a means for measuring elapsed CPU time and for caueing an
interruption when a prespecified amount of time has elapsed. Juat as the TOD clock,
_ the CPU timer is a binary counter with the same format, except that a one is not
added, but subtracted from the Slst bit. In the procesa, bit 0 in the timer coun-
ter is used as the sign of a fixed-point number. A request for a CPi]-timer inter-
ruption exists whenever the value in the CPU timer is negative ~bit 0 is one).
When both the CPU timer and TOD clock are running, the stepping rates are synchro-
nized such that both are stepped at ttie same rate. In contrast to the TOD clock,
the CPU timer does not change its state when the CPU is in the STOPPED state.
The timer reading can be stored in storage by using the instruction STORE CPU
TIMER. The instruction SET CPU TIMER is used to change the value of the timer.
The interval timer, in association with a program, can serve both as a real-time
clock and as an interval timer. It is in location 80 of main stnrage. The 32-bit
number is treated as a signed fixed-point number. An interrupt occurs when this
number becomes negative (bit 0 is one). Interval timer contents are reduced by
one in bit position 23 at 300 cyclea per second between the Qxecution af instruc-
tions.
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2.3. Dynamic Address Translation
The multiprogram mode has become the main mode of computer operation. Efficient
use of this mode presupposes the availability of a large amount of main storage as
well as hardware and sottware facilities for dynamic storage allocation in the pro-
cess of program processing.
The largest main storage size for the Unified System of Electronic Computers is
limited to the address capacity adopted and may be 16M bytes. However, development
of main storage of this size with the required time parameters preaents coneider-
able technical difficulty. In addition, the size of system, standard and control
programs far exceeds the size of real main storage. Based on this, only active
sections of system programs are in main storage, which restricts the capability of
processing them efficiently. The availability of a large amount of external stor-
age and programming in symbolic addresses with use of the virtual principle makes
- it possible to get around this limitation. The programmer appears to have the
maximum permissible amount of main storage and in the process, storage is reallo-
cated for programs dynamically withQut programmer participation.
In the YeS EVM-1, used for dynamic storage allocation was the method of base re-
gisters, in which a real address of main storage was formed as the sum of a sym-
bolic address and the base. Base addresses for the various system prograrr~~ are
stored in register local storage of the CPU. .
Dynamic storage allocation using base registers does not have eufficient flexi-
bility since the system program has to be brought into main storage completely,
even if this is not necessary. In addition, any input of a new program requires
- phyaical reallocation of storage size, which is ~time-consuming.
The dynamic storage allocation method with page and segment organization is used
in the YeS EVM-2. This method assumes subdividing the entire extent of virtual
storage into blocks called segments and pages. Symbolic (logical) addresses are
translated into real ones by special translation tables. Dynamic address trans-
lation is possible only when operating in the EC mode.
Logical Address Structure. Segments and pages are used as movable blocks of data
in the dynamic address translation mode. A segment may be 64K or 1M byte; a page.
_ may be 2K or 4K bytes. Sizes of a segment and a page are controlled by the values
of bits 11,12 and 8,9 respectively of control register 0. Data in each block are
- addressed by sequential logical addresses. A logical addresa consiata of a page
index (number) field, a segment index (number) field and a byte index field (dis-
placement within a page). Fig. 4 shows the formats of the logical addresa for
the different segment and page sizes.
To translate the logical into real addresses, translation tables are used for seg-
ments and pages. These tables reside in main storage and determine the current
allocation of storage actually installed. The addreRs and length of the segment
table are defined by the appropriate bits of control register 1. The entry
fetched from the segment table�designates the length, avallability and origin of
the corresponding page table. The entry fetched from the page table indiaates the
availability of the page and contains the high-order bits of the real address. A
zero value in the availability bits coritained in the entries of the segment and
page tables indicates the given en try is available for use.
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;Inpn6nnrouIui~ (2 ) /?~~�'~~'+PCkuu ndprr,
cHenleNUe ~'~�O1'~n f cHea{er~uc~6)
NOHCp NUM[p ~N tp(/ N(~~Ip,p NO~ICp
ter~reNro trpoNU4u crpaNU (1 ~ ~ IPNrO TpQi~uqsi ~~u8S5c) 6au~v ' ,
4J ~
q ~ e n re ~y zo ~
~4~ CtZNeNr-64 K6auT, CTPONll4d-4 K6dur ,
CneuteNUe ~
, ~~Po ~N~~uus~ QNy~pJ
~q ~~S ClPOMUI{~t3 m +
~ n ~ e rs ~s zo 2, ar ~
_ ~ 5~ CeaneMr- 64 X6arir, trpaHUya~ ? K6uur ( 7) ~
!o nu~Sh
ceeHeHrnll
NoMep NoNep CMeweNUe ~a6nu~!a
ce~le~N~o eTpZ 1~k~~ ~rpu ue~ ~ c~puHU~~ ,
J l
' 0 7 B !I J2 19 ?0 J?
~6 ~ Cez~~eN?- J ~+6aur, C/poMw(0- y A60tir
i
Caeu~eNUe ~ ~
Honep NoMep
- cezNeM~o c~poNUuei e"y'pu ' ~
(1) ('L ) ~,~oH~,uC3 - ' ~
~n ` p~
0 7 B 11 1? ?0 ?1 9J ~
(9)
~ CetneNr-1 H6n~ir, c~paHU~{q-2 B6aur q cmpinra Neie prr.ucr~ei unu '
' ' ~cnnNn~nrennne~d 6y~ep
nepeoBpecoyuu (1~ PenneNat7 o peC
Fig. 4. Formats of the logical addreas Fig. 5. Diagram of dynamic address
translation procesa
Key : Key :
1. segment index 1. control regiater 1
2. page index 2. logical address
3. byte index 3. segment index
4. for 64K-byte segments and 4. page index
4K-byte pages 5. byte index
5. for 64K-byte segments and 6. diaplacement
2K-byte pages 7. segment table
6. for 1M-byte segments and 8. page table ~
4K-byte pages 9. tranelation-lookaside buffer
7. for 1M-byte segments and 10. real addreas
2K-byte pages
Translation. The translation process (fig. 5) ia as follows: The segment-�index
portion cf :.i?e logical address is used to select an entry from the segir~ent table,
the starting address and length of which are specified by the contents of cotttrol
_ register l. This entry designatea the page table to be uaed. Zhe page-index por-
tion of the logical address is used to select an entry from the page table. This
entry contains the high-order bits of the real address. The byte-index field of
the logical address is used for the low-order bit poaitiona of the real address.
A translation buffer is uaed to apeed up the translation process. Capacity and ~
sizes of the tranalation buffer are mo~iel-dependent parametera. The traneletion
- buffer includes the high-order portion of the logical addreases and theix
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corresponding real addresses, by which the CPU accesses main storage. Thus, con-
sidering that the CPU accesses main storage usualty by sequential addresses and
with a high probability within the bounds of one page, table entries are fetched
from main storage only once. The information obtained in the first reference sub-
sequently remains in the buffer, and all subsequent references to storage that
use translation table entries from the same area of storage are performed by using
the buffer. Buffer size ranges from 8 words for the YeS-1035 to 128 words for the
YeS-1060 model.
There are certain conditions under which information may be placed in the buffer
and used for dynamic address translation. The concepts of a valid, attached and
active entry are introduced. An entry is valid when the segment or page valid bit
- in this entry is zero. A segment table entry is attached when the dynamic address
translation mode is specified, the entry is within the segment table designated by
control register 1, and it is designated by a logical address with regard to seg-
ment size. A page-table entry is attached when it is within the page table desig-
nated by the page table address and page table length in an attached and valid seg-
ment table entry. An entry is active when it may remain recorded in the transla-
tion buffer. An entry may be placed in the buffer when it is valid and attached.
Information on the state of translation table entries and their use is given in
table 3.
Table 3. Use of Translation Tables
State of table entry: Can copy Can table Can table Can buffer
of entry entry be entry be copy be
be in fetched for used for fetched for
active attached valid buffer? translation? translation? translation?
yes yes yes yes yes yes yes
yes ~yes no yes yes no yes
yes no yes yes no no no
yes no no yes no no no
no yes no no yes no no
no no yes no no no no
no no no no no no no
For efficient processing of the algorithm for page replacement in main storage,
- two types of recording are used: recording of references to a main storage block
location during storing or fetching of data, and recording of changes which re-
flects information on which pages ir~ main storage had data stored in them.
In the dynamic address translation mode, the storage protection key code is exten-
ded with two additional bits. The reference bit is set to one each time a loca-
tion in the corresponding storage block is referred to either for storing or fetch-
ing of information. The change bit is set to one each time information is stored
in the corresponding storage block.
Reference and change recording takes place for both CrJ and IO channel accesses
for 2048-byte blocks and does not depend onpa~e size invoked.
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2.4. Microprogram Control
Selection of the CPU controt method is governed by th~ CPU operating cycle, com-
plexity of processing and control algorithms, and control method efficiency.
Until recently, the microprogram method of contro~ was not widespread in high-
throughput machines. This was because this method had a number of shortcomings,
the most important of which were reduction in machine throughput and the high cost
- of microprogram development. Therefore, as a rule, the hardware method of control
that permitted achieving a given level of speed was used in high-speed machines,
including the large models of the YeS EVM-1.
The situation has changed sharply in recent yeara. Microprogram control began to
be used extensively in designing high-throughput computers. This interest in
microprogramming was caused by the development of the technology of the micro-
Erlement base, the expansion of the computer instruction set and the considerably
greater capabilities offered by this method compared to the hardware.
' The emergence of large-scale integrated semiconductor circuits with a low level of
delay made it possible to develop control storage, the parameters of which made it
possible to substantially reduce the effect of microprogramming on computer
throughput.
A study of CPU control methods revealed the dependence of their efficiency on the
size of the instruction set used in operations. An evaluation of the composition
of the instructions in the YeS EVM shows that the microprogram method is more
efficient. It is evident that CPU effectiveness will grow with extensions of the
- composition of instructions and functions of the CPU. However, in building con-
trol circuits for the individual units in the CPU, a large rQle begins to be
played by the factor of speed of the cor.trol circuit and complexity of algorithms.
Indeed, performed for high-throughput computers in one CPU cycle simultaneously
are resolving the priority of the many requests from CPU units and channels,
checking the key for storage protection and accessing independent blocks of main
- storage, translating logical addresses, fetching from buffer storage and other
operations.
Complex algorithms, on the one hand, can be more economically implemented with
microprogram control, but on the other hand, these algorithms have a large number
of branching cunditions, which complicates the microinstruction addressing scheme
and in t.he final analysis both the cycle itself and the number of cycles in the
algorithm are increased. In this case, a comnromise is required, which leads to
a mixed hardware-microprogram method of control.
It is most efficient to use microprogram control in CPU executive units, in which
Ere implemented miilticycle algorithms having a large number of linear sections
and a limited number of branching conditions. Based on this, small models have
primari.ly microprogram contro: in all CPU units, while CPU's in the large models
use it mainly in the executive units.
The advantages of the microprogram method of control compared to the hardware
from the point of view of raising CPU efficiency and or~anization of maintenance
- are expressed in the following:
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with microprogram implementation, the structure of the control circuit is more
regular, hardware facilities are used more economically, and the le~el of unifica-
tion of individual assemblies is raised, which leads to simplification and reduc-
tion in cost of equipmen t;
microprogram control permits developing a system of microdiagnostic tests to
automatically search for malfunctions; and
the control algorithms are documented more simply and clearly., which supporte sim-

~ plicity in training service personnel and facility in CPU operation.
The structure of the microprogram control unit (MPU) is governed by three factors:
the principle of construction of control storage, the structure of the microinstruc-
tion and the method of generating the address of the following microinstruction.
Control storage for a microprogram control unit comes in two types: read-only and
writable. Read-only storage is implemented on the basis of modules or integrated
circuits of semiconductor programmable storage (IS PPZU). Special programming de-
vices are used to program the storage when the CPU is manufactured. The informa-
tion in the programmable read-only memory is preserved under all conditions of CPU
- operation, even when power is disconnected.
Writable storage is implemented on the basis of integrated circuits of high-speed
storage (OZU). The user loads inforrt~stion into this storage unit from external
media each time power is switched on t.~ the CPU. In the YeS EVM, cassette recorders
are used to hold f iles of microprograms. Microprograms are replaced or changed by
replacing the cassettes which are prepare.~ at the computer ~rsanufacturing plant.
All YeS EVM-2 mudels are oriented to using writable storage of microprograms, since
it has invaluable advantages in optimizing algorithms for operations and developing
a dynamic system of microprogramming.
Microprogramming with the use of writable storage of microprograms has important
advantages in debugging prototypes and makes possible raising the efficiency of
machines in series production and operating at a using installation thanks to the
introduction of new software that n~akes use of the extended set of instructions and
new CPU functions. The latter is very important in selecting the method for imple-
mentation of the control circuits. This is in connection with the observed trend of
reducing time spent on the work of the operating system by "integrating" some fre-
quently used subroutines and operating system modules into the hardware. Such in-
tegration can be performed only when the CPU functional capabilities are extended,
_ i.e. when the control circuit algorithms are updated, which is easily done by
changing the contents of control storage.
The main character~.stics of control storage are fetch time, word width and number
of words. Memories with a capacity to 4K words, width to 144 bits and fetch time
to 60 ns are used in the Unified System of Electronic Computers.
- The width of a word of control storage is governed by the type of coding of the
sets of microoperat~ons and by the method of generating the address of the next
microinstruction.
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Functional as well as instruction-oriented coding is used in coding the micro- ,
operations. Functional or field coding presupposes the presence in the operation
part of individual fields that contain sets of compatible microorders that control
the various functional parts of the processor that permit parallel operation of
them. Usually in the composition of the fields there is a field that includes the
immediate operand or instruction that can be used for aetting certain registers.
Fig. 6 shows an example of such a microinstruction. Control signals are generated
by decoding of the fields. Field.size is from 1 to 4-5 bits which permits coding
from 1 to 32 microorders.
~r~n~ ~ ~r~~~ . . . ~jrona~ ant
n ao ~ n n >
Knn nr'~ ~ nBp 7
' D 4 0 J!I J
(4 nu~ ~~u (4) n~~, 4)
Fig. 6. Microinstruction with Fig. 7. Microinstruction with
functional coding instruction-oriented coding
- Key: Key:
1. RA field that controls 1. KOP operation code
.reception into register A 2. Adr 1-- addreas 1
2. RB field that controls 3. Adr 2-- address 2
reception into register B
3. SM adder function control
field
4. DSh decoder
With instruction-oriented coding, the microinstruction, just as a nominal instruc-
tion, contains the operation code field, fields in which addresses of registers or
processor functional assemblies are specified, and fields containing additional
control information (fig. 7).
A comparison of these two methods shows that outlays for equipment and time for
generating control signals with instruction-oriented coding are greater than that
with functional coding, although the width of the microinstruction is amaller.
Instruction-oriented microprogramming lends itself more easily to automation of de-
- sign of~microprograms. With this method, the microprogram can be written by a pro-
grammer who has a formal description of the microinstructions. Although functional
coding is considerably more complex and requires detailed knowledge of all proces-
sor assemblies for writing the microprograms, in this case, more efficient micro-
programs are obtained in terms of time of execution and number of microinstructions.
Functional coding is intended primarily for the large models in the Unified System.
Tt~vo methods of addressing, natural and compulsory, are used to generate the address
of the next microinstruction.
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addrees (1)
' an~c~ an
~1? ) ) ~ ~~Gft ~ A~~ 2 )
- ~ . UuKn ~~jgv---
~ (1) (2) l3)(1) (2) (3) (1) (2) (3) ~~bbb~J~~1,~,R
nnr~n~s
~ mq Bb~~/JIU_
~~_~b16. ~W~ ma i d6l6. , AW , stora e
r
1-
(4) (49 ~
Rbin. ' 861If. ~
- UUNn ~ L(UK/1
cycle cycle , ~
Ivurpo~roMnwAo
microinstruction
~ Fig. 8. Time chart of operation of Fig. 9. Diagram of microprogram
control storage control of proceasor
- Key: Key:
- 1. FA microinstruction address 1. FA - microi.nstruction addreas
generation generation
2. VYB - fetch from control 2. DSh - decoding of microordera
. storage
3. DSh - decoding of microorders
4. VYP - execution of operations
The compulsory addressing method presupposea that each microinetruction contains
the base address of the next microinstruction to be executed and the fields~that
define the conditions that.affect a change of the base address. Thus, all condi-
tions for microprogram transfer are specified in the microinstruction.
The natural addressing method ~resupposes that after execution of the microinstruc-
tion with addFes4 A, the microinstruction with address A+ 1 will be executed,
which eliminates the need for microinstruction addressing~fields within the micro-
instruction. But used in the process in the microprogram in addition to operation
microinstructions are tho~e of the control type that contain only fields for effect-
ing microprogram transfer. This causes complication of the microinstruction decod-
ing circuit and extension of the microprogram, although the length of a microin-
struction is shortened. Since this method of microprogramming is similar to de-
signing ordinary programs, natural addressing is often used with instruction-
oriented coding.
- Various methods are employed to raise the speed of operation of a microprogram con-
trol unit. The unit operating cycle consists of four phases: microinstruction
address generation (FA), fetch from control storage (VYB), decoding of microorders
(DSh~ and execution of operations (VYP) (fig. 8). Uaually, the operation execution
phase coincides with the address generation, fetch and decoding phases.
Thus, with proper selection of relations of times of oper~tion of executive units
and microprogram control, the processor cycle can be shortened.and is governed
usually by the operation of the control circuits. The cycle can be ehortened fur-
ther by reducing address generation time or eliminati:ig it from the operating cycle.
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For example, if the branching in the microprogram can be in no more than four direc-
tions, then a method is used in which the four words are fetched at once from con-
trol storage, starting at the word specified by the base address, and the final
fetch of one of the four words is effected according to the transfer condit~ons
generated simultaneously with the fetch of the microinstruction (f ig. 9).
The time for the microorder d ecoding phase can be reduced by using for critical
purposes control fields with direct coding, when each bit of a field is directly a
control signal. .
2.5. Principles of Organization of Array Processor
An array processor (MP) is a supplemental, specialized porocessor connected to a
main computer instead of one of the IO channels or directly as an operating resource.
Standard YeS OS channel progr ams are used in the first case to organize communica-
tion with an array processor; the second case requires a apecial supplement to the
Ye S EVM sof tware .
The main operations executab 1 e in an array proceasor include correlation,�convolu-
tion, vector, scalar and matr ix multiplication, tranelatioz of fixed-point to
floating-point format and the functions of indexing, counting, fetching and storing
of input and output data. Operations are performed in the arithmetic unit of the
array processor. T~ao buffer s with a capacity of 32 words each are used to match
the rates of operation of computer main storage and the arithmetic unit in the
array processor duriiig itera t ive operationa. These buffere are used to hold both
input data and the result. The basic arithmetic function executable in the array
processor is the function UX+Y with data having the short floating-point format.
Fixed-point numbers the leng th of a halfword may also be used as input data in the
_ array processor; prior to pr ocessing, they are translated to floating-point format
in the arithmetic unit.
As mentioned earlier, the arr ay procesaor is considered as one of the selector chan-
nels, connectable to the main processor and main storage in the computer. Such
organization permits simultaneous data processing in the main and array processors.
Four IO instructions, SIO, T IO, HIO and TCH, can initialize operation of the array
processor. Each instruction contains a channel addreas and an external device
address for identification c~f the array processor. In the process, the channel
- address (bits 16-23 of the instruction) must contain the code 3 and the external
device address (bits 24-31) i s arbitrary. The external device address code O1 (hex-
adecimal) is intended for in i tializing special diagnostic operations. Upon comple-
tion of execution of an IO instruction, one of four values of a condition code (OQ,
O1, 10, 11) is issued to the processor. The array processor priority for access to
_ main storage is higher than that of the processor and lower than that of a channel.
Table 4 gives the condition c ode valuea and etate of the array proceseor in the
various modes when ~IO rnstructions are executed.
Just as the IO channels, the array processorfetchea from main storage the channel
address word (ASK), then the channel command word (USiC) and generates the channel
status word. Control informa tion for data (USO--operand control word) is fetched
for executing matrix operatio~~s in the array processor. Operand control word for-

- mat is silown in f i~. 10.
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Table 4. Condition codea and array procesaor states
Kowei~nM Instructions i
array
procasso sio Tio ~nc~ rci+
COfTpAlltlC _
. Mil '
state ,~~n~.. ~1~ (1) K~~t ~ (1) ~,2,?
~co cT ncecT� ncAcr-
enc YCJIO� pIIC Ycan� ni~e Y~'~n� euc ycno�
enn eua ena nna
/
I Icr~3 ) I ItT~4 ) 3~nu- ~ I le�r
~~miifi~iK OQ 1~cii �r- , Illl Mim~- 01 nciicr- 00 .
available Nnnttit- nuil niic nnii ,
~m~aa-
; 11ocTynnoe w~s~ ~ .
- , ~,~~~r~- .
~ ~u~~~
, ~
' ~ o~S~~~- oi
. ,
~ ~ K~ , ,
. ~rino~ni- '
. ti~inia .
i
% executin (4) ~(4) ~7) 4
; f3~tn~nnemie ~cr 10 llrr 10 ( cTa- 10 I eT IQ
1 oncpeqtm ~lciict- nciicr- non JtciicT-
ni~ii nNii n~iii
: o.n~ration
d scon- ' I Ic4~~ ) , I IcT4 ~ I IcT ~ ,
~rK~!~ven neiicT- II neticr- II neilcr- It ~eficr- , II '
_ n~tii nHi1 ~n~ti BHII
IlEC ted
1
Key :
T. operation 4. no operationa
~ 2. condition code 5. ~tore
3. no errors; initialization of 6. store error
operation 7. halt
( ~hupn+aT fi~fira ~ Anp~~~ ncpnoro ~ne~+cnrn ~
format of, b.ytg___... address of .first. elem nt~
(1 7 A ' ;41
I I lnncicc index I count - Cvcr ' I
;~2 � 47 4ti . f3
Fig. 10. Format of operand control word
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Specification of bits 0-7 of the byte format field is shown in table 5.
Table 5
Uaed for control word
State of operand
Bits Function 0 1 Y X U
0 data format floating-point fixed-point + + +
1 used only for data in + +
fixed-point data complement code
2 data quantity + + +
3 operation algebraic absolute + + +
addition subtraction
4 stack control without stack with stack + - -
5 not used
- 6 not used
7 not used
Bits 8-31 contain the address of the first element in the matrix. This addresa
must correspond to the data type, i.e. integral boundaries of storage data (word or
halfword).
Bits 32-47 include a halfword with fixed point and are used as the index for addres-
sing the current byte in main storage. Both poeitive and negative index values are
possible. Bits 48-63 contain the quantity defining the number of operands in the
matrix, considered as a 16-bit poaitive number.
Zhree types of operations may be executed in the array processor: vector, scalar
and matrix. Examples of executable operations are given below.
Vector move operation with tranalation into floating-point format (VMC). This
operation may be shown by the following expression:
~ Yi ~ Xi for i= 1, 2, n, where n= min (CTY, CTX) and Yi = 0 for i=
n+ 1, CTY, if CTY ~ CTX; here and from now on the symbol E- denotea
putting one variable into the place of another; CTY, CTX and CTU is the value of
the count field in the operand control worda for Y, X and U; reapectively;
min (a, b) and max (a, b) is the minimum and maximum values of quantities a and
b; nd
~Y~ is the supplementary operand. .
l
Thus, vector operand X is put into the place of vector operand Y in main storage.
If the dimension of vector X is less than the dimenaion of vector Y, then the com-
ponents of vector Y, for which i~ n, are replaced by zeros.
_ In the process of executing the operation, operand X ia translated into floating-
- point format.
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Vector moye operation with translation into fixed-point format (VFX). Thia
operation is described by the expression:
S,=X, �X,-Xl
~ S~=X,� X~-f-S~
Yc ~ S~ I~' U?Xa f or i- 1, n, whe~e
~ n - min (CTY, CTU)
and ?'1 ~ for i(n 1) to C"I'Y, if . C1`Y ~ CTU
In the process of executing the operation, floating-point numbers are tranelated
into fixed-point format. For this, bits 8-22 of the floating-poirit nwnber are put
into bits 1-15 of the fixed-point field, and the zero bit ia reserved for. the eign
if bit 8 equals 1, otherwise bita 9-23 are put into bits 0-15 if bit 8 of the
original number equals 0. The factore X1, X2 and X3 are used to extend the pre-
cision during translation of the formata.
Element-by-element multiplication of vectora (VEM). Thia operation may be
described by the expression:
- Y~'- Yi Ur ~~t for ~ � 1~ 2~ . n,
where n= min (CTY, CTX, CTU) ~ ~ ~
and Ytas the 4tnucleus" is
equipment that permits execution of the algorithm shown in fig. 40, i.e. statements
marked with an asterisk). This program, using the DIAGNOSE instruction, effects
step-by-step "photography" of the sequence of test instructions ("instruction 1,"
"instr.uction 2," "instruction i") and comparison of the frames obtained with the
ceference information derived earlier on a computer in good working order.
6.5. Software Checking and Diagnostic Facilities
Software checking and diagnostic facilities are divided into off-line and on-line.
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CVI/Ylfl~~, _
NvNnNdn /~NNlHIIf.INA'R ~pM~p~j
cverv w roMrat-N
- ~ /~NAfNpCIMNA UNdpONU- .
C4C7VUK 10K10~~ N JOQUfI
~ T � (1)
NoNOydp` Tecro X~l I N_;
~.7 / I
~ ~ XDHpHBn 1 M_2
N- S T
1
I j H-~
NOMONBd stcro K�T ~ j N-S �
J ~ ~ ~YoHONao 2 I
r ~ ~
Pezuc?/~otWn u "
n ~pNdpNU~ ~IO KONONaO 7tt~a N�1 1 j/ / I CVlf4UN T~NrOQ~N-1
~ NONIUHNOII (3, I Q 1~ T
oruu6Ke � I ~ n nvepiMNU~ ~
(4 ) "OOw~~ (3 )xoHaHaQ ~ I z
. , I~ ~}o �
p ^Cr M-1-0!
~tpenuce o~nocro peautr- , * CpoeNeNUe Kodpa N. A
c aionoNOM �
por~u~ No e~y 5 yea
" /~rnexoa No cnni rou~y
~,b �NOap e �
C4rTVUN TONIO~.N-l ~
6 voeNO ~ Ao
?
Ner
N-1-o~ Q�ye8 NoNeu M no
QMf~OVO MO /1C4pTI
N~? Js//N10IId M~fOOeN/,N(IA (6 ~
no � ~
Fig. 39. Flowchart of routine for Fig. 40. Flowchart of diagnoatic
obtaining reference resulte routine
Key: ~ Key:
1. atep counter ' 1. synchronization steps
2. DIAGNOSE instruction 2. DIAGNOSE inetruction
step counter - N etep counter - N
3. test instruction (K+1, K+2, K=i) 3. Inatruction (1, 2, i)
4. logging and machine-check 4. logging and machine-check
interruption : interruption
5. copy logging area to external 5. compare frame N to etandard
storage unit 6. print~out resulte of no match
6. atep counter = N-1 7. atep counter = N- 1
8. go to next series of "framea"
.
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On-line routines operate under control of operating systems in parallel with running
of user jobs in the multiprogram mode. The peripheral to be tested is ewitched to
the off-line mode for user jobs and teh job ie atarted for execution of particular
teat sectiona of the given device. On-line teste allow performing preventive main-
tenance and repair of computers without reducing conaiderably computer throughput
as a whole. Thie pertains primarily to computera with a large set of peripherals
among which these is redundancy. Using on-line teats, it is also convenient to
perform preventive main~enance of peripherals operating occasionally in the system
(plotters, optical readers and others). The main aim of on-line testa is to sub-
stantially. reduce the time for preventive maintenance of computere and thereby
raise the factor of technical use of the equiprnent.
- aff-line test routines in both the YeS EVM-1 and EVM-2 are part of the set of YeS
TEST-MONITOR (TMYeS) programs. The set includea the TMYeS teat control program,
utilities for generating and maintaining media of the set (tapes, disks, cards) and
a set of test-sections of all devices, including central.
The control routine interprets a simple and convenient job language, enables stan-
dard output of inessages to the operator and has a set of utility subroutines facili-
tating programming of test-sectiona. The control routine ie compiled so that only
40 of the simplest instructions (of 183) are used which require minimum serviceable
hardware "nucleus" of the CPU and the input path.
To ensure serviceability of the control routine, the CPU and minimum path of input
from magnetic tape are checked with the so-called base test. The lattet checks
the above mentioned 40 instructions and path of input from magnetic tape only in
the read mode.
In the base test, messages are not printed out. Incorrect execution of test samples
is indicated by looping of an unconditional branch instruction to itself or by a
halt upon error signals from the check circuits. Then maintenance personnel per-
form analysis by the display on the engineer console and when necessary the micro-
test system is used (see section 6.3).
The set of off-line routines loadable directly from the medium of an external stor-
age unit amy include any sort of ineasuring routine for one-time use, for example,
routines to determine throughput of the CPU and channels, checking the accuracy of
timers, checking disk rotation rate and the like.
Development of the complex automatic teating syatem (SKAT) for the YeS EVM-2 is
planned as a prospect for development of test software. A characteriatice feature
of SKAT is the parallel testing of peripherals by the method of elimination: the
devices are serially connected for parallel operation. If n devices are already
operating and an error appears in the system when the n+l-th device ie started, by
a halt and start retry among the n+l devices SKAT defines the minimum configuration
in which the error rc~mains. In the minimum configuration, it is easier to localize
the source of the error. As a rule, these are complex interface errora occurring
in parallel operation of the devices. During operation of SKAT, the CPU handles
background test jobs. By operating modes, SKAT approximates the work of operating
systems and at the same time has testing facilities ("elimination," tracing of
events prior Co the error, program halts upon specified conditions and othery).
Use of SKAT, an off-line system, permits checking computers with a large set of IO
peripherals within 5-10 minutes.
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A aecond promising direction in development of main~tenance test software is the
trend to having one (and not two) set of test-sections for a peripheral both in the
off-line and in the on-line testing systems. This will lead to introduction of new
control routines in the TEST-MONITOR and operating syatems.
The third direction involves increasing the diagneotic .propertiea of sof twar e testa.
This will require incorporating additional hardware diagnostic modes in the device.
6.6. Computer Maintenance
In maintaining computers during preventive maintenance and prescribed operationa
and when malfunctions occur, all hardware-software facilities for checking and
diagnostics typical for the YeS EVM-2 are used:
hardware checking and improvement of the machine-check handling eyatem;
hardware retry of inetructions upon failure;
~ system of microdiagnostics;
DIAGNOSE instruction;
sof tware testing;
hardware facilitiea for recovery of channela and IO units; and
- software facilities for recovery of operating syatems.
Daily prescribed operations include checking the computer with the base test and a
limited set of the test-sections of the TMYeS. The configuration sufficient for
starting YeS OS and the initial batch of user joba is checked. A complete check of
the configuration needed for the current day is performed with on-line tests undez
control of YeS OS.
A malfunction may be detected either during performance of the prescribed opera-
tions or in the working mode. When a peripheral fails, the malfunction may be lo-
cated by using the on-line tests. For this, the peripheral is awitched to the off-
line mode, tested by off-line facilities through the unit conaole and again con-
nected to the system for checking. If there is no capability of repairing the
peripheral by uaing the on-line tests, repair is either put off till the next
scheduled prescribed operationa (if posaible) or a aearch for the malfunction is
made with the TMYeS test-aections, as a result of~which running user jobs on the
computer is terminated.
Failures of the central part (CPU, mFin storage, channels), as a rule, lead to com-
puter failure. It is possible to continue operating in some cases when one can get
by with reduced size of storage or without some number of channels. When the CPU
fails, the base test and the set of TMYe S test-aections are executed to f ind the
location of the malfunction.
When maintenance personnel have some preliminary information on the malfunction,
the single-purpose set of test-aections is executed in specific order. The test
aections enable localization down to a block, instruction and mode. Then the micro-
test system ia used selectively. And in the most necessary case, a awitch is made
to manual diagnostics using either microteats, the base test or test-sectiona
(tracing, step-by-step mode, time logical analyzera and the like).
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Information from operating system recovery facilities is used by the engineer for
forecasting the source of failures and further planning of the next scheduled
operational checks.
Chapter 7. Software
Sof tware, which largely determines the capability of hardware, hol.ds a major place
in the development of computer technology. The role of software in extending the
sphere of application and efficiency of the uae of computers is decisive. This is
due to the relation of cost of development of hardware and sof tware ateadily and
continually changing in favor of the latter.
A considerable stock of user software has now been accumulated and continues to
increase rapidly; this must be taken into account not only in the development of
new computer systems, but also in choosing the directions of development of software.
Therefore, in developing the YeS EVM-2, considerable attention was F:aid to
improving Unified System sof tware.
The Unified System software system consists of operating syetems, application pro-
grar.i packagaes (PPP) and maintenance programe.
The main function of operating systems is to increase the efficiency of use of the
resources of a computer installation and to raise the convenience of operator-compu-
ter interaction. Extensively used in the Unified System are the YeS OS and YeS DOS
operating systems that are discussed in detail in this chapter.
The makeup and function of PPP are also considered in this chapter; they extend the
capabilities of operating systems and are oriented to solving apecific user
problems.
Maintenance routinea are intended for determining the technical condition of compu-
ters both in the mode of preventive maintenance and while jobs are being executed
(see chapter 6).
7.1. Evolution of the YeS OS Operating Syetem
YeS OS is designed for use in medium and large Unified Syatem models. Its evolution
in developing the YeS EVM-2 was determined by:
expanding the sphere of services offerred the computer uaer;
raising the efficiency of software proper; and
raising the efficiency and reliability of uae of hardware capabilities.
Within the YeS EVM-2, expanding the sphere of servicea is expressed in the follow-
ing:
development of multiprogramming;
expanding the makeup of basic data atruc turea and standardized methods of operating
with theae structures;
development of teleprocessing support;
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improvement in the facilities far program debugging and those for checking the
operation of a ~computer system..
Fundamentally important to the YeS EVM-2 is the incorporation of virtual main ator-
age, one of the main resourcee in a computer syatem. In the YeS EVM-2, up to 16M
bytes of virtual storage are made available to all joh steps to be executed and are
allocated among them dynamically. The use of virtual storage for mutual protection
of jobs from each other as well as protection of the operating ayatem control pro-
gram from the jobs has made it possible to increase the number of aimultaneously
executable jobs and thereby raise the degree of multiprogrammability.
The development of multiprogramming in conjunction with the improvement in telepro-
cessing facilities and methods has allowed creating the time-sharing mode that
enables shared access to the computing resources of the Unified System of Computers.
The user is also offerred the capability of remote job entry baoed on the developed
capabilities of teleprocessing.
From a sof tware point of view, the transition from the YeS EVM-1 to the EVM-2 was
effected by an evolutionary development of the YeS OS and DOS operating syatems as
well as by accumulating a stock of application programs. ~
YeS OS wae developed in the following directions:
A new version of the control program was introduced: SVS (virtual storage mode~,
available with MFT and MVT versions from the YeS EVM-].;
A new common telecommunications access method, QTt~, is used in all versions of the
YeS OS control program;
The time-sharing mode (SRV) and interactive remote job entry (DUVZ) ia supported in
all versions of the ccntrol program;
YeS EVM-2 disk storage facilities with 100M and 200M bytes with aector aearch are
used in all versions of the control program;
In the SVS version, the user is offerred a new type of data organization on direct
access devicea and the corresponding accesa method, the VSAM virtual accese method;
A new component, the dynamic debugging monitor (DDM), has been developed and in-
cluded in OS to enable debugging of uaer programa and extend the operating eyetenn
capabilities; and
A new component, the generalized trace facility (UST), has been developed and in-
cluded in OS to trace the operation of individual programs and obtain atatistics.
To make use of the advantages of the new functional capabilities of the YeS EVM to
the full extent, measures to raiae reliability and immunity to failurea were also
taken at the software level. In the YeS OS, exiating software facilities for re-
covery and logging of malfunctions were improved and new facilities included, and
the capabilities of dynamic reconfiguration of peripherals and selecting alterna-
tive paths for peripheral accesa were extended. Programs for handling specific
errors of YeS EVM-2 peripherals were developed and included in the corresponding
components of OS.
The inclusion in OS of facilities for building multimachine configurationa also
helps solve the problem of reliabil,ity and meet growing requirements for throughput
of computer systems.
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7.2. General Structure and Functions of YeS OS
Closely associated with the development of information processing har3ware is the
development of operating systems oriented to specific structures and functional
capabilities of CPU's and allowing efficient resolution of the problems facing the
user.
The YeS OS operating system is an integral part of the computer system and is a
software extension of Unified System computer hardware. It is based on the modular
principle that allows selecting facilities for a specific computer system in
accordance with user requirements. The process of adjusting an operating system
to a specific application is called generation.
Functions of the YeS OS Operating System. In working with YeS OS, the user formu-
lates his jobs in one of the high-level programming languages: PL/1, FORTRAN,
COBOL, ALGOL or RPG or in the Assembler machine-oriented language. He then send~
his work to the computer center in the form of a job consistir~g of a aequence of
individual. operations associated with the execution of the YeS OS defined programs.
'I'he operating system executes the job in three stages:
preparation for job processing;
execution of the individual steps of job processing; and
output of results.
Based on the job, the operating system forms a sequence of tasks making up the
individual units of operations for the YeS OS. The operating system optimizes uae
of the resources in the computer installation by overlapping in time processing of
several tasks belonging to various jobs. The operating system itself functions on
_ the basis of tasks that are system tasks. The used principle of overlapping of
execution of several different operations making up the basis for the mode of pro-
cessing of several jobs is one of the versiona of the multiprogramming mode of
operation.
Needed to execute user jobs are certain hardware reaources (such as main atorage,
IO devices and others) and logical resources stored in the form of programs or
files. YeS OS special components coordinate the uae of all resourcee in the compu-
ter system, allocating them among the different ,jobs in accordance with requests
and priority (job control). Requests f.or computer syetem resources are a job com-
ponent and are formulated in job control language.
The resources needed are allocated after a job is fetched from the job queue. The
job is entered into main storage and put on the list of active jobs. Execution of
- the basic tasks located in main storage at the same time is controlled by special
operating system programs (task management).
Results of the operation that emerge in executing jobs in the form of data are in-
tended for slowly operating devices (printer, puncher, microfilm output) and may be
preliminarily accumulated in storage with direct acceas. The accumulated informa-
tion is output to the required devices after the job ia completed under control of
system output programs.
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YeS OS Structure. The YeS OS operating system consists of a control program and a
- aet of proceasing programs (fig. 41). The control program, intended to control the
CPU for data processing in a computer system, consists of the following components:
- job management;
task management;
data management; and
diagnostic facilities.
' OnepayuoHNaa ~tu~reHa Ot EC
ynpadnAa~kW~pczpaMrre~ 06paoaraBarou~{ porpa~yMO/
naotpaM
~i~4 ) 'pQMt,~prooa(5 ) ~porpcr+Me~6 )
. / I
i
(,7~ (,8 ) ~9 ) ( ~0 11 (12 13 14 (15 (16 17 18 19 20
a k e;? a
c ~ ~ a i2 �.o ~ a~, ~ j ~ i ~ ^ C : C
a 'v ~n ~ po~2 Q o o L
1'O ~~D O 2 L j ~d ~ : n4i,'~ S~i C Q O C y
~tn a~ ~r~ r`'~ 4~ " C~ Q c a ~
Fig. 41. YeS OS Operating System Structure
Key:
1. YeS OS operatiag system 11. linkage editor
2. control programs 12. loader
3. processing programs 13. utilitiea
4. service programs 14. sort/merge program
5. tranal~tors 15. Assembler
6. problem programs 16. PL/1
7. job management 17. FORTRAN
8. task management 18. COBOL
9. data management 19. ALGOL
10. recovery facilities 20. RPG
Processing programs are the translators and service programa supplied by the soft-
ware developer as well as the programs written by computer uaers.
There are several different configurations of the control program that can be
formed at generation time:
the MFT mode-=control program with a fixed number of tasks; �
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the MVT mode--control program with a variable number of tasks; and
the SVS mode--system with virtual storage.
Under MFT, several jobs can be executed simultaneously. Except for the area for the
nucleus of the operating system, all main storage is divided into fixed partitions~
The number of partitions, equal to the number of simultaneously executable jobs, and
the sizes of the par titions are defined at system generation time. The computer
operator has tne capability of reducing the number of partitions and changing their
size.
Under MVT, the number of simultaneously executable jobs may vary dynamically. A
storage partition is allocated for each job atep and its eize may also vary from
job to job.
' The maximum number of partitions used for job processing under MFT and MVT ia 15 and
all partitions have different values of protection keys.
- In contrast to MVT and MFT, the number of partitions is not restricted under SVS,
because not only pr.otection keys but also the atructure of dynamic addressing are
used for protection of main storage. The number of partitions in which jobs are
executed depends on the number of operating initiators. Other iimitations on the
number of simultaneously executable jobs under SVS are diacussed in section 7.3.
The principles of f unctioning under SVS are considered in detail in section 7.3.
Operating System Modes of Operation. The mode of operation governa the basic organ-
ization of the process of processing by compuetr. The YeS OS may be used in two
modes: batch and shared use.
Operating in the batch mode ensures continuous and efficient use of a computer.
However, the time between receipt of the user job and return of the resulta to him
- may be substantial.
The user operating in the ahared-use mode is linked directly to the computer and
controls the processing from a terminal, which subatantially reducea the time for
obtaining results f rom execution of jobs. YeS OS offere the following �acilities
for operating in the shared-use mod e:
conversntional remote job entry (DUVZ); and
time sharing system (SRV).
Job Management. Job management facilities effect input of user jobs into the system
and perform all ac tions associated with allocation of resources, execution of jobs
and output of results to IO devices. In accordance with functions performed, the
software for job management is divided into the job scheduler, that receives and
proceases jobs prepared by the user in the job control language, and the master
scheduler, the facility for interaction between the computer operator and YeS OS.
Jobs coming in for processing from remote terminals are controlled not by the job
scheduler, but by the correspodning programs that are part of the shared-use
facilities.
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. A programmer uses the job control language (JCL) to plan the processing of the job
and request the resources needed for this. The language includes the JOB statement,
the EXEC statement for a job step and the DD data definition statement. The JOB
statement assigns the job name, class and priority. The job name is used to identi-
fy the job in operator communication with the operating system. The job class af -
fects the process of forming the input queue, and the priority determines the order
of job entry from the queue of the given clase for processing. Also indicated in
the job statement are the size of the storage area needed to execute the job and~ a~
number of other parameters specifying modes for job execution. The EXEC statement
is used to indicate the program or procedure to be executed. A procedure consists
of previously prepared job control statements that can be modified when referenced.
Each job may contain several EXEC statements. For each data set to be procesaed or
formed during execution of a job step, a DD statemer.t must be provided to code the
data set description, type and number of IO devices requested.
In the operating system, jobs are processed in several stages. In the firat atage,
the read-interpret program, a component of the job acheduler, reads the stream of
jobs from the input device and forms the input queue in accordance with the job
class and priority. If there is input data in the input stream among the JCL state-
ments, it is placed for storage on external storage with direct access. Input of
jobs into the system can be effected simul~aneously by several input atreams from
different IO devices. .1obs in which JCL errors are detected are excluded from
further processing.
Another componentof the job scheduler, the initiator, aelects jobs from the input
queue in accordance with class and priority, allocates the resources needed and
sends them for processing, effecting subsequently the planning of each successive
- job step. Parallel execution of several operations results from the start of
several initiators, each of which serves the jobs of well defined~classes. Results
of tr~e operation of each job are sent to defined output classes. For each output
class, the statement assigns a system output program and the corresponding external
- device. Operation of the system input and output programs and job processing are
effected in parallel, which results in a high degree of automation of the procesa
of job processing and high throughput of the operating aystem.
In job processing using the job entry subeystem (KROS), raising the rate of job pro-
_ cessing is provided for by preliminary reading of the input atream and placing it
in direct access storage. The statements are interpreted when the jobs are selected
for processing. As a result, the job input unit operates at the maximum rate (fig.
42). After allocation of the needed resourcea, the problem program is laoded and
receives control. Qutput data sets are stored on direct access storage. KROS
ensures output of output files and system messages to the appropriate output device.
The user can control output by using DD statement parameters or through computer
operator commands. -
In loading the operating system and in the process of its operation, the computer
operator communicates with the operating system. The operating system requests
data on operator actions and decisions pertaining to removal and mounting of data
media and reports the statt?s of IO devices. In turn, the operator has the capabili-
ty of controlling system operation, requesting information on its atatus, and
- changing parameters of the system and individual jobs to raise syatem operation
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z attHa repnp e~m~r~~
P ynpuD~aMU~eci
tUCTPNHOtO ~ 5~ MN 0 UIl NOQUU
eeoaa ~ ~PMOUIIR ~ m~
n~oa aoamionM
~ 1~ . ~ G~ BNy,~
UH JO~NU~~ ~ L~
~ AlndH~[ (1UHNN~
06po6arxu
- nnozpaMMa QM~oBNUe BGNNd~ maroR
cuc~enaazo ' ao~7nNUd
NNQoBo
(3) (4)
Fig. 42. Structure of the KROS job entry subaystem
Key:
1. system input program 5. job control information
~ 2. interpretation of control 6. job control internal data
information 7. input data
3. system output program 8. output data
4. job step processing
efficiency. Using the appropriate commands, the operator starts system input and
output programs, monitor programs and the shared-use mode.
The master scheduler communicates with the operator for the syatem. In generating
an operating system, both a single-conaole and a multiconsole mode for its opera-
tion may be selected. In the latter case, the capability is available for using
up to 32 devices operating as consoles. In doing so, one device must be selected as
the basic console since certain commands can be aent only through this device.
Task Management. YeS OS ensures efff.ci~n4.passage~of user taska thanke to opera-
tion in the multiprogramming mode. Operating~syatem multiprogramming facilities
that allow simultaneous handling of several taska on data procesaing permit these
tasks to rnake joint use of syetem computer reaourcea. Stepa belonging to the same
job are executed in strict sequence. Overlapping of execution is possible only for
steps of different jobs. However, within a step, several tasks or subtaske may be
formed that will be executed at the same time with each other and with other taska.
Processing efficiency is raised subatantially through uee of programs used in para-
llel that can serve several different taska at the same time, which saves main
storage (it is sufficient to have one copy v� the progrem in storage) and reduces
program loading time.
The supervisor is the main task control program. Frequently used programs of the
YeS OS supervisor are part of the nucleus kept permanently in main atorage. The
other programs are loaded to main storage as needed. The main function of the
supervisor consists in servicing other operating aystem programs as well as compu-
ter user programs. The supervisor prevents an uncalled-for effect of programs on
each other and on the operation of a control program, making use of storage protec-
tion facilities and effecting complete control over IO operationa.
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In operating in the multiprogramming mode implemented in a aingle-CPU computer
installation, a maximum of one task can be processed by the CPu at any given time.
This task is called the active task. The active task is selected from those ready
based on priority in accordance with the dispatcher algorithm. When an active task
can not make use of the CPU, for example while awaiting the reault of an IO opera-
tion, or wY~en a higher priority task becomes ready, a new task ia selected and made
acti~~e. '
~ The task c~~ntrol program receives control of the CPU af ter interruptions. The
cause of i~terruptions may be the emergence of an event that a task is waiting for.
In processing interruptions, information ne '.ed to restart operation of the inter-
rupted program is stored. Further processing essentially depends on the cause of
the interruption. For example, in the virtual storage mode, in event of an inter-
ruption due to the absence of a needed page in main storage, the mechanism for re-
trieving and loading the required page to main storage begins operating. An inter-
ru~~ion may occur as a result of a special request for supervisor facilitiea from
another operating system program or a computer user program.
Data Management. YeS OS atandard data management programs support user program in
data processing. Considering that the entire operating system is kept in data aeta
on volumes of external storage, data management facilities, in organizing exchange
of information betweeen external and main atorage, play a key role in the organiza-
tion of control and processing procesaes in a computer system. Data management im-
plements control of I~0 operations, initial processing of data, overlap of IO opera-
tiona with processing and protection of data sets from unauthorized acceas. The
operating system has a catalog used by data management facilities to identify and
find any data set. An increase in the number of programs and data during syatem
operation leads to an increase in the size of the syatem catalog.
A data set is a collection of logically associated records with a specific struc-
ture. The operating system offers the user the capability of ueing fixed, variable
and undefined-length records (fig. 43). A record ie conaidered the amallest logi-
cal unit of information tranaferred between a program and data management facilitiea.
To raise the efficiency of information tranafer and make fuller use of the surface
of the magnetic media, several logical recorda are combined into a block that is
written/read to/from the medium in one reference to IO facilitiea. Blocking and
unblocking are performed by data management routines. The blocking method depends
- on the r.ype of data used. In using fixed-length records, the block size, as a rule,
is a multiple of the record size; in the case of variable-length recorda, an addi-
tional field desczibing the total block length is included in the block. The length
of a variable-length record is contained in the initial bytes of each record.
Data set characteristics are usually stored on external storage with the data set
itself and reflect data set organization, location and size.
The operating system provides an extensive set of IO routines (accesa method rou-
tines) that free the programmer from writing routines to acess data sets. These
routines automatically perform such functions as overlap of data processing with
IO operations, and preparation and checking of labels for volumes and data sets.
Instead of using YeS OS data management routinea, a programmer has the capability
of writing his own channel routines and IO are management routinea. A programmer
may request data by a similar method irrespective of the features of a apecific IO
device.
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~1 ~ ,7a~ucu muHr,upaem~Nmi r7n~iNn?
Key : f 9 1 ~~oKu
1. fixed-length records ,
2. blocks %
3. records (3) nnucu (4) c6noxupr,drn,er
4 . blocked (5 ) P/art6nayHe~e npa,ve~ryrxu ~
; 5. interblock gaps % i ~
6. unblocked
7. variable-length records (6) Nec6~nKUpo~nHe~
` ( ] ~ 3anueu nepeieNNau anu~~ni
8. block length
9. data record
L
10. data
~ NMQrOpHOI{fIOH1f0 ~ .
11. record length (g ~AnuNO n eBno~reHUe 9 ~ C~/10HUn0OONN~L} ~
hnolro
12. undefined-length records ~(nu~ra- ~ no""",e (10)
~ l l~tnucu _ _r
~r___~ � ~
_ ~
; ~z
~ ~
nnNa ~ ~ 6 ~ Nec6nnkripoAnue~
( $ nnxn
C /;ONHA/C ~ 1 O
~nuNa
( ,
~ 12 ~ 3anuCU NeonpeBe~eNHD~i 8nu~ie~
/faNNnle ~ ,(1pH/!WQ p!/Nbl , Aal/1INe
r~,{~~ ~1~~ ~1~~ ~10~
Fig. 43. Fixed, variable and undefined-
length records
The YeS OS permits the following types of data set organization: aequential, direct,
library, indexed sequential and telecommunications. Let us note also the organiza-
tions associated with creating microfilms and the generalized form af organization
of files on direct access devicea that ia characterietic for devices with a capacity
of 100M and 200M bytes.
Sequential organization of data sets is characterietic for the majority of exiating
devices and is oriented to sequential processing of records without skipping.
In indexed sequential data sets, records are ordered by the value of a key that pre-
cedes each record. Records in thie data set may be processed both sequentially and
randomly. In the latter case, the key c~f the required record has to be specified.
Similar capabilities are offerred by the direct organization of data sets that per-
mits an arbitrary value of the record key.
A data set with partitioned organization consists of a collection of sequentially
organized partitions. A directory is located at the beginning of the data set. A
record in the directory is selected by keys, and within the bounds of a partition,
sequentially. This form of organization is used to store program libraries and
groups of logically interrelated sequential filea of data.
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Data sets with partitioned, direct and indexed sequential organization may exist
only on direct access devices.
Messages sent over communication channels and kept in an IO buffer are no different
from ordinary data obtained from local devices, and the telecortununications organiza-
tion is provided for message queues.
Data management facilities provide for two data acceas methods: the method of
access with queues that automates execution of IO operation to the maximum, and the
basic method that permits a programmer to directly participate in managing IO opera-
tions. The queued access method effects automatic synchronization of processing
programs and execution of IO operations.
An access method may be defined as the aggregate of the data set organization and
the access method used used to process the data set. Basic access methods are in-
tended for all types of data set organization, but queued access methods are used
only for sequential, indexed sequential and telecommunications data sets. The list
of access methods supported by YeS OS in all modea of the control program is given
in table 29.
Table 29
Data set Access Method
organization
(accesses) Basic Queued
sequential BSAM sequential method QSAM sequential
indexed BISAM indexed sequential QISAM indexed aequential
sequential
partitioned BPAM for data sets organized by
partitions
direct BDAM direct access
graphic accesa method (G1~)
remote method of access for remote extended method of access for
- processing of processing of data (BTMD) remote procesaing of data
data [BTAM] with program control of
messagea (OTNID) [TCAM]
It ie important to note that the graphic acceas method (Gt~) [GAM] is organized in
a way that a request for transfer of data may originate not only from a program,
but also from a display operator. The capability of identification of inessages
_ sent in random sequence between ter.minals and main storage is provided in the GAM
in data teleproceasing.
BTAM and TCAM differ in the number of services offerred the uaer. BTAM, the simpler
and more economical method, is a ser~es of macro instruction.s for organizing IO and
translating messages. Using these macros, the problem program participates directly
in controlling the teleprocessing hardware. TCAM presumes use of a special measage
control program oriented to a specific configuration of a teleprocessing network.
As a result, the problem program becomes independent of the specifics of the tele-
processing network.
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BTAM and Z'CAM are considered in more detail in sections 7.5 and 7.6.
VSAM has been developed for virtual storage aystems (see section 7.9).
Recovery Facilities. Sof tware recover~ facilities are part of the OS control pro-
gram and process interruptions from the machine check circuits.
Recovery facilities enable acquisition of information on system errora and the
time of their appearance, recovery of the serviceability of a ta.sk or the system
after an error occurs or emergency termination of processing if system recovery is
unsuccessful.
Recovery facilities are discussed in more detail in aection 7.13.
Programming Languages. The YeS OS user is offerred various programming languages
to compile programs: In addition to the Assembler machine-oriented language, he
may use the problem-oriented languages of PL/1, FORTRAN, COBOL, ALGOL and RPG.
Problem-oriented languages are closer to conversational language and mathematical
notation than to machine instructions. Using problem-oriented languages to write
an algorithm makes it independent of the computer inatruction list. The program is
written in brief form and outlays for developing it are far less than when pro-
gramming in Assembler.
Problem-oriented languages have certain Limitationa with respect to external de-
vices used and functions of the operating system, but at the same tine do not re-
_ quire precise knowledge of the operating system and specifics of specific devices
on the par t of the programmer .
_ Programs written by the user are teh source data for the corresponding translators
- that translate the source data into machine codes.
The Assembler machine-oriented language is maximally adapted to computer features.
Programming outlays are rather high compared to using the problem-oriented langu-
ages. Assembler is divided into the basic language and a macro language.
Mnemonics are used to code machine instructions.
PL/1 is a multipurpose languag~ suitable for both commercial and scientific and
technical problems. The broad range of application of this language is charac-
- terized by the wealth oE different typea of data. PL/1 offers the user a large set
of standard functions. There are several different versions of the compiler for
this language. The standard compiler translates source sta~ements into machine
code and produces a listing of the translation and messages on errors detected.
The optimizing compiler generates object code that results in reducing the time f~r
program execution and substantially reducing storage taken up.
The debugging version of the PL/1 compiler is intended for operation in the inter-
active mode with the capability of checking individually input statements of the
source language. The optimizing and debugging versions of the PL/1 compilers may
be eff_iciently used in the time sharing mode.
FORTRAN is a problem-oriented language for representation of formulas and calcula-
tions in science and engineering. It has a aimple atrueture and is easy to learn.
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Computational op~rationa are in the form of expressions in which arithmetic and
logic operations as well as operations with binary strings and compare operationa
may be performed.
When the source text is compiled, a listing is produced of the tranalation and
messages on syntactic errors detected.
There are different versions of the compilers. The ST (standard) FORTRAN compiler
has additional debugging facilities. The OP (optimizing) FORTRAN compiler is used
to generate optimized machine code.
The SS interactive version of the FORTRAN compiler ia intended for use in the time-
- sharing mode, in which the new expanded versiona of the standard and optimizing
compilers, FORTRAN SE and FORTRAN OE, may also be uaed.
RPG is a problem-oriented language developed for solving aimple commercial probleme
which requires processing of extensive data seta uaing eimple operationa and output
of them on a printer. Only alphanumeric strings and decimal numbers with fixed
point are used as data. The RPG compiler printa out the translation, detects syn-
tactic errors and corrects some of them. The new expanded version of the RPG-2 com-
piler has autoreport facilities.
ALGOL is one of the early problem-oriented languagea. Programa written in this
language have a blcok organization. The compiler aupports all capabilities provided
in ALGOL-60.
COBOL is a problem-oriented programming language oriented to commercial applicationa.
Programs in this language process numeric and alphanumeric data.
COBOL compiler capabilities under YeS OS are the same as those under YeS DOS. The
only difference is in system-oriented elements.
The new expanded veraion of the COBOL compiler includes additional facilitiea
enabling ita efficient uae in the time-sharing mode. There are English and Ruasian
language versions of the COBOL compilera.
Service Programs. These YeS OS programs include the linkage editor, the loader,
the sort/merge program and YeS OS utilities.
The linkage editor and loader combine load modules of separately compiled parts
(object modules) and other load modules. The input data for theae components con-
sist of object and load modules and control instructions. In the linkage process,
links are formed between the different parts of the load module in a way as if all
parts of the program had been translated together. The linkage editor and loader
form a load module in relocatable formIn the loading process, the module is
adjusted for a specific location in main atorage.
The load module may have an overlay structure (structure with planned overlap), for
which it is divided into individual segments loadable into main storage in accor-
dance with a scheme epecified by the user. Thia allows saving on main storage
needed for execution of the module. In operating with a virtual atorage system,
the overlay structure loses ita value.
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The sort/merge program sorts or merges fixed or variable-length records in ascend-
ing or descending order. This program may be used with Assembler, COBOL and PL/1.
YeS OS utility programs include standalone service programs, sy stem service pro-
grams, data set service programs and system programmer service programs.
7.3. Virtual Storage Support
The operating system supporting virtual storage fn the YeS EVM-2 is an evolution of
those versions of YeS OS used with YeS EVM-1 models. Based on a number of hardware
and software facilities, the user is offerred virtual storage with a capacity of
16M bytes, which substantially exceeds the size of computer rea 1 main atorage. Let
us note a number of advantages stemming from the use of virtual storage.
1. Using virtual storage, the user has little need for the ovexlay structure and
subdividing tasks into a sequence of smaller tasks. Programs are automatically
overlapped based on the page swap mechanism.
2. Real storage size ceasea to be a critical factor in locating components of the
operating system and user taska, since they are Located in vir tual storage. In ex-
tending the real storage of a computer installation, operating efficiency automati-
cally increases based on the concept of paging.
3. Real storage fragmentation is reduced. Uaing the page organization for storage
- management eliminates fragments of real storage between and within partitions.
Fragments may exist only in virtual atorage. In real atorage, fragmentation is
substantially reduced.
4. The rather efficient apparatus of dynamic management of a basic resource of a
computer installation, real storage, is realized. If a task is not very.active,
because of paging it will use an iqaignificant amount of real s torage.
5. The degree of multiprogramming rises significantly, since the most active pages
of a substantially greater number of tasks than in a conventional syatem may be
present in the same real storage.
6. The system has a greater area for resident functione that may be used eimul-
taneously by many taske. :'trtual etorage can hold a great number of aupervieor
programe and acceas method programs. When they are not being u sed, they do not
take up real storage.
The virtual storage system is supported by the control program SVS which implements
multiprogramming with a variable number of taeka that use virtual atorage at the
same time.
Virtual Storage. The main aspects of the f unction and use of v irtual storage may
be described by using the concept of addresa space. There is addreae apace for a
program, understood as the tange cf variation of addresses of i ta instructions and
data, and address space of real storage with reflects the capac ity of computer main
storage. There is also the address apace of a computer installation that describes
the maximum possibel size of real storage that can be connected to the computer in-
stallation. A computer system with a 24-bit addresa may have an address space of
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16M bytes. This concept of addreas space that may be many times larger than real
storage is called virtual storage.
The traditional principles of multiprogramming that became widespread in the compu-
ter systems on the base of the YeS EVM-1 were based on the total aize of address
spaces of programs being processed at the eame time not exceeding the address space
of real storage. The placement of programs in real starage in these systems was
based on the concept of static relocation that consisted in translating program ad-
dresses at loading time in accordance with its location in real storage. Increasing
the degree of multiprogramming was curbed by teh sizes of real etorage and the pre-
sence of unused fragments between the partitiona occupied by tasks.
The use of virtual storage is based on using the strategy of dynamic relocation im-
plemented by the facilities of dy.namic address translation (DPA) [DAT] and on using
- the segment-page organization of~'the address space and external page storage.
Dynamic translation of virtual addresses into real ie based on the segment-page or-
ganization of virtual storage. A virtual addreas has the structure (S, P, i) (see
fig. 4), where S is the segment index, P is the page index and i points to the
specific address (displacement) within a page. In the YeS EVM-2, 4 or 8 bite are
allocated for coding the segment index; therefore, there may be either 16 1M-byte
segments or 256 64K-byte segments in virtual atorage. For coding the diaplacement
of i, 11 or 12 bits may be allocated, and page eize is 2K or 4K, respectively.
One-megabyte segments may contain, as a function of the structure of the virtual ad-
dress, 512 or 256 pages, while 64K-byte segments may have 16 or 32 pagea. Transla-
tion tables, a segment table and several page tables, are used in the operation of
the hardware facilities for DAT. A segment table consists of elements that, as
shown in fig. 44, define the availability of segments and the length and addresses
of the corresponding page tables. Page tables consist of elementa that indicate the
availability of a page in real storage and the high-order bits of ita real address.
There is an entry in the page table for each page of virtual atorage. The etructure
of a page table entry is shown in fig. 45.
qnuNO dpec ~oJnuiSbr ~or.ryn- ~~opmur pa~paa~~ Antryn-
7a6nUye~ ~~noNUy Nnetb OBptCO NDGtb ~
c~v(~`~ 2) ( 3) c: aHf/qdf ~
Fig. 44. Structure of segment table entry Fig. 45. Structure of page table entry
Key: Key:
1. page table length 1. high-order bita of page address
2. page table address 2. availability
3. availability
The beginning address of the segment table is stored in control regieter 1. Segment
and page tables must be fixed in real etorage.
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HONQQ NOM!~I
CQ2MCNI0 CI/1~Nf/f(H CN~WCNUC Key �
eaoa~~aarG ~2 3 4 �1. virtual address
- - 2. segment index
- ~ 3. page index
, 4. diaplacement
5. segment and page index
~ No~~p a,~pa Aacec 6. reference bit
tezneHrc u 0 pa- 6noka�
- crpoNUU~~ ryeMUn cipoNUUe 7, page block address
' ~ ~
'NoMI.~ 11oH(!~ ~NUC
Q.'?IMNTO CIf1fINf/l~Fl
'(2) (3) ~ _ (4)
I ~
' I
Fig. 46. Asaociative Registers
Program interruptions with codes X'10', X'll' or X'12' may occur in the proceas of
dynamic address translation that indicate that reference was made to an unavatlable
segment of virtual storage or an unavailable page or an invalid address wae detected
for the segment or page table.
Special hardware facilities have been provided to increase the tranalation rate.
Asaociative registere~are used in small models, and a rapid tranelation buffer in
the large ones. A system of eight asaociative registera ie ahown in fig. 46. In
referencing storage, the par.t of the virtual addrese containing the page and segment
index is compared with the first part of the registers. The registera hold informa-
- tion on the eight last used pages, identified by their aegment and page indexes.
If there is a match in one of the registers, the real address is generated based on
the displacement and the contents of the right portion of the register. If there is
no match, the tablea are used for translation. The information obtained on the lo-
cation of pages in real storage~and the correapodning segment and page indexes are
stored in one of the registers in accordance with the replacement algorithm.
External Page Storage. Since virtual storage is many times larger than real stor-
age, the latter holds only the most active pages. Pages to be used are kept in
external storage in the system data set, SYSI.PAGE, that ie called the page data
set.
In the process of translating virtual addresses, when the system detects that the
required page is not in real storage, a copy of this page is moved into real storage.
The location of pages in external storage are reflected in a special table, called
the external page table.
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Paging organization is a function of the operai:ing ayetem component called the page
supervisor. ,
Page Supervisor. From the viewpoint of paging organization, real atorage is divided
- into fixed and page~replaceable (dynamic) areas. The special table reflects the
list of real storage pages available for exchange and their status.
The page supervisor performs the following basic functions:
management of the segment table, page tables and real page tables;
start of operations associated with page swapping;
processing of interruptions associated with the absence of needed pages in real
storage;
management of page replacement in real etorage; and
management of the intensivenesa of page exchange.
The al.gorithm for replacement of pagea in real storage ie the basis for page
exchaiige.
T~ao replacement algorithms affording common interface with YeS OS components have
been implemented in the page superv~isor. The YeS OS uaer-programmer has the capa-
bility of including the required algorithm in the apecific version of YeS OS when
it is generated.
Translation of Channel Programs. In contrast to the CPU, YeS EVM IO channels can
not translate virtual addresses into real onea. Therefore, virtual addreases used ~
in channel programs have to be translated into real onea by sof tware. Channel pro-
grams with virtual addresaea are translated into logically equivalent programs with
real addresses. Because of this, access methdo rpograms that exist in previous
YeS OS editions may be used with virtual storage with no change. The channel pro-
gram is translated right before the sta~t of the IO operations. Cre,ated in the
system queue area is the logically equivalent duplicate of the channel program, but
now with real addresses, which is used in starting the IO operationa. In such
tranalation, it may happen that all addresses required are in non-adjacent real
pages. In the YeS EVM IO channels, there is the hardware facility of indirect ad-
dressing that allows sending data to nonadjacent pages of real storage.
During execution of the IO operation, all needed pages need not undergo page ex-
change. Before starting the IO operation, theae pages are fixed in real storage,
and unfixed after successful completion of it.
Jobs in which dynamic modification of channel programs is effected during execution
of IO operations are executed in a special mode, when the the virtual addresses of
the instructions and data match their real addresses. In thia case, channel program
translation is not required.
Channel program translation facilities are part of the IO supervisor. Channel pro-
gram translation does not require fixations on the part of the programmer and is an
internal function ~f the operating system.
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7.4. Virtual Storage Mode SVS
The mode of multiprogramming with a variable number of tasks, that make joint use
of virtual storage (SVS), is oriented to YeS EVM-2 hardware facilities and is a
prectical implementation of the concept of virtual atorage in the YeS EVM. It wae
developed on the basis of the MVT mode and affords multiprogram execution on a com-
puer of programs, the total size of which substantially exceeda the capacity of
real storage.
~1 ~dupTyonn~~an nnHnr~
~2 ~ MRX n8pec Key :
- 1. virtual atorage
~3 ~ 3or7oHUe 1 2. MAX addrese
4 3. job (1, 2, N)
- ~ 3o~loNUe 2 r, 4. dynamic area
~ 3 ~ Iro~aene~
, ; A ~o n~~~~a 5. job partitiona in batch
; ~ ~`;NO~ procesaing
i o : o6ppt~rnRt
a 6. system queue area
`T ' 7. general area
(3 ) 3aaoN~e N 8. master acheduler
~ 9. nucleus
' (10 (6 ~dnncn cucieHUe~x 10. fixed area
o~e~.aeo 11. addresa 0
4
_ ? . ~ 7Q1Sft~0A 06RdC76
b ~ )
V
j C f/70~HA1(% nnoNUpoBu{uM
ub ,
k0
~ ( 9 ) Aapo
i
R~pec o~ 11)
Fig. 47. Structure of virtual storage in SVS mode
Virtual storage is used jointly as one address space by both the control program
and all computer users in accordance with the princip~les of allocation of storage
in the MVT mode. Virtual storage is divided into two areas: the f ixed (containing
the nucleus of the control program, the system queue area, the general area, and
the master scheduler partition) and the dynamic, in which partitions are organized
for execution of jobs (fig. 47). The maximum size of the dynamic area is
V = 16M bytes - ~fix .
' where Vfix is the size of the fixed area.
The virtual storage size provided with a specific loading of YeS OS is governed by
the size of the page data set used, since the more space for page storage, the
greater the size of virtual storage.
Job execution in the dynamic area is affected by page size: program interruptions
occur when pages are not in real storage and~ there are delaye in program execution
due to page transfers. This effeet can be avoided, if deaired, by fixing in real
storage both fndividual apges and entire partitions. Therefore, under SVS, there
- are two types of partitions: with virtual ddresses (V=V) and those in which virtual
addresses equal the real (~1=R).
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Virtual storage for V=V partitions is allocated by segments. The size of a V=V par-
tition is $et to a multiple of segment size, even when less storage is requested in
a job for the execution of which a partition is created. The same protection key,
equal to one, is set for all these partitions, because storage protection is orga-
nized not only by using protection and storage keys as in the MVT mode, but also by
using the translation tables. According to the principles of operation of the YeS
EVM-2, in the segment table used in dynamic address translation, in the entry for
each segment there is a bit for the "availability-unavailability" of access to this
_ segment. Any reference to the segment (either a write or read) for which this bit
is set as "unavailable" causes a program interruption, perceived by YeS OS as an
- interruption due to a storage protection exception.
In a transfer of control to a task being executed with a nonzero protection key,
availability in the segment table is indicated only for partition segments and seg-
ments occupied by YeS OS. In a transfer of control to a task being executed with a
zero protection key, i.e. having the right of accesa to any partition, availability
for all segments is indicated in the segment table.
To reduce the time required to readjust segment tables when tasks are switched, two
segment tables are created that differ only in the availability bit setting: a user
table, in which availability is indicated for partition segments and those taken up
by the computer YeS OS, and a system table in which availability is indicated for
all segments. Because of this, readjustment of segment tables is required only
when tasks are switched that are being executed in different partitions. In trans-
ferring control between system programs of the us~r, readjustment of tables is not
required; loading the address of the corresponding table into the control register
suffices.
_ In transferring control to tasks being executed with a zero protection key, the
address of the system segment table is loaded for translation; in transferring con-
trol to tasks being executed with a nonzero protection key, the user table is used.
For V=R partitions, virtual storage is allocated by pages. The allocated pages are
fixed in real storage, and the page and segment tables are adjusteii so that the
- virtual addresses equal the real in dynamic address translation. The size of this
partition may be less than the segment size and a multiple to the page size. For
storage protection in this case segment tables are not used: varioua protection
keys not equal to 0 or 1 are set for the partitiona. Consequently, there may be
no more than 14 V=R partitions. They are created in the real storage area directly
following the nucleus of the control program. The size of this area is set during
generation of the specific version of YeS EVM OS. During loading of it, the com-
puter operator has the capability of changing the size of the area for creating
V=R partitions.
In the partitions of both types, local system queue areas (LSQA) are created in
which control blocks related only to the given partition are placed (under MVT,
they are placed in the SQA [system queue area]). This substantially localizes re-
ferences of tasks to pages of virtual storage, for example in processing storage
control block queues, and reduces the number of references to pages not present.
One segment of virtual storage is allocated for the LSQA. It is allocated by the
control program automatically, above the size of. virtual storage specified in the
job for the execution of which the partition is created.
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This organization of partitions and storage p.r.otection under SVS simplifies the re-
striction on the number of partitions under MVT: The number of partitions created
is limited not by the number of protection keys, but by the size of virtual storage
provided. Page exchange for the fixed and dynamic parts is organized as f.ollows:
in the fixed part, pages containing the nucleus and SQA storage sectors, allocated
by the virtual storage control program, are fixed in real storage and not subject
to page exchange; pages containing the general area and the master acheduler parti-
tion are subject to page exchange;
in the dynamic part, pages containing V= R partitiona and LSQA storage sectors, al-
located by the virtual storage control program, are fixed in real storage and not
subject to page exchange; pages containing V=V pa~rtitions are subject to page ex-
change.
For the page data set, it is necessary to allocate a eize that enables holding the
pages of the fixed part subject to page exchange and the needed numher of parti-
tions from the dynamic part. The size of pages in the fixed part subject to page
exchange varies with the different YeS OS versions and averagea about 3M bytes.
The size and location of the page data set are set only when YeS OS ia loaded.
Paging means that a page is kept in real storage only when it is referenced; it ia
withdrawn to the page data set by the paging algorithm as soon as the need ariaes
_ for placing another page in real stor age. Placing a virtual page in real atorage
or removing it may also be performed upon program requests.
- Program requests f or placing, fixing, unfixing and removing pages change the normal
conditions for tunctioning of the paging algorithm, since they reduce the size of
real storage accesible for organization of the page exchange. Therefore, the num-
_ ber of simultaneously fixed pages is a parameter that depends on the amount of real
storage, the intensity of requests for replacement of pages and on the intensity
of servicing them.
SVS components subject to page exchange make up a large part of the syetem and use
external page storage in the process of operation. However, unallocated segments
of the dynamic area of partitions does not use external storage. Similarly, a11
pages not used in the segments do not require external page storage. Unallocated
segments and pages unused within segments are "potential" address space.
The distribution of pages in the page data set is reflected in the external page
table.
If an interrupt occurs due to unavailability of a page in the procesa of program
operation, the system makes use of the external page table to determine the loca-
tion of the needed page.
A page selected for replacement is moved to the page data set only if it ie altered.
Pages are stored in an order that ensures a balanced load on the devices holding
the page data set and minimum movement of each device's reading mechanism. The
- control blocks describing the location of the external pages are used to determine
the position of the reading mechanism and the free space closest to it to which
the page is moved from real storage. This achieves minimum movement of the reading
- mechaniam which reduces the time fqr page exchange.
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To prevent unproductive, extremely intenae exchange of pages that is possible when
the number of problems executed at the same time increases, management of page ex-
change intensity has been implemented. The criterion for management is the page
exchange intensity, i.e. the number of pages transferred between real storage and
- the page set within a unit of time. When paging increases to the value
' Imo: fApt -I-nt~r
where Iopt is the optimal intensity and 0 lI ia the permiasible increment of inten-
sity, execution of one or more low-priority tasks is halted. When intensity de-
clines to the value ~ �
f min = ~ar~ - ~~j,
where ~ 21 is the permisaible intensity decrement, execution of some halted tasks
is resumed. The optimal intensity of paging Io t, the permisaible interval of
P .
_ change in paging intensity /1~/=e,~+ez~, and the time interval uaed in measuring the
intensity are the ma;or parameters affecting the throughput of computer systems and
depend on its structure, i.e. on the number of IO channels, types of IO devices
intended for placement of the page set.
The main difference in the process of loading programs under SVS from that under
NNT is that the programs are loaded not into real, but into virtual storage. Before
loading, the program is in the system or personal library. The loading program
reads the program to be Loaded and translates the addresaea of the program being
loaded in accordance with the location of the partition in virtual storage. In
doing so, the program being loaded sutoamtically assumea the segment-page format
and is withdrawn to external page storage in the paging proceae.
After completion of the program loading, control apsses according to the virtual
address to the entry point of the loaded program. The required page will be placed
in real storage and the loaded program starts its execution.
7.5. Basic Telecommunications Accese Method
The basic telecommunications accese method (BTMD) [BTAM] ie uaed for creating pro-
grams that implement exchange of data between a computer and remote terminals by
using communication channels. BTAM affors use of only half-duplex channels.
Communication is established through switched or unewitched communication channels.
This access method provides the programmer with facilitiea for creating a subscriber
list that contains the information needed to eatablish communication with a remote
station. BTAM effects addressing and interrogation of terminals, sending and re-
ceiving of inessages, insertion of changes to the the subscriber list, buffering
and code translation.
In developing programs by using BTAM, execution of the following procedures that
enable proper functioning of the teleprocessing hardware must be provided for:
definition of the teleprocessing system;
- use of the code Lranslation table;
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opening and cloeing of data sets; and
management of the data transmission channel.
TFie teleprocessing system is defined by creating descriptions of channel groups,
data transmission multiplexer parameters and terminal parameters.
- The main aim of uniting channels into groups is the capability of making use of the
common resources of the access method for all channels in the group. Therefore,
channels with similar characteristics are united into a group.
Using the Code Translation Table. The YeS EVM internal code is the DKOI [decimal
information interchange code], while the teleprocessing equipment sende information
in other codes. The macro definitions of BTAM contain code translation tablea; in-
dication of the name of the needed table in the macro instructions ASMTRTAB and
TRNSLATE by the programmer suffices. The programmer may also specify his own
tranalation table if required for specific applicationa.
Opening and Closing of Data Sets. The procedures for opening data sets of communi-
cation channels are performed by using the macro instruction OPEN. As a result,
BTAM programs are loaded into main storage and auxiliary tables are generated. If
it turna out that some channels were not opened due to their unavailability for
transmission, one can later open a single channel by using the maco instruction
LOPEN. After completion of data transr~ission, data sets are closed by using the
- macro ins*_ruction CLOSE.
Data transmission channel management consists in establishing communication between
the computer and the remote station and adhering to the algorithm for transmission
of inessages over the communications channel. This management is effected by using
the acc~ss method programs taking into account the specifics of the operation of
the MPD--F,PD-AP [data transmission multiplexer--data transmission equipment-terminal]
link. In the process of receiving and transmitting information, a block by block
check is made by using the check sum. When information is received with an incor-
rect check sum, the block in error is retransmitted.
The etandard READ and WRITE macro inatructione are uaed for message Cransmisaion.
To eatablish communication with a remote station and aend the first block of data,
these maco inatructions are used in the modes of intial read and initial write.
There is the capabiltty of tranemitting data in the transparent mode, when any bi-
nary code combination can be tranamitted as data, even if it matches the control
symbol code.
7.6. General Telecommunications Accesa Method
Compared to BTAM, the general telecorranunic~tions access method (OTMD) [TCAM] is at
a higher logical level. Using TCAM frees the applications programmer from having
to take into account in programming the featurea of the algorithma for data trans-
mission through the communication channel, to program terminal polling and sampling
and code translation, and to define the network configuration. All this is per-
formed in a separate task by using the message control program (PUS) [MCP].
The MCP is generated for a specific teleproceseing system by using macro instruc-
tions and TCAM program modules; it operates in the partition with the highest
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priority. The MCP has several sectiona:
activati,on and completion of the teleprocessing eystem operation;
definition of data sets needed for MCP operation;
definition of the teleprocessing network configuration; and
message handlers.
The first sectiop of the MCP must be the section for activation and completion of
the teleprocessing system operation. The firet macro in the section is INTRO,
which defines the basic parameters of the MCP. OPEN opens the MCP data sets.
READY transfers control to the MCP dispatcher which plans all MCP operations; if
there are none, it is placed in the wait state. After completion of the MCP opera-
tion, control is passed to the macro CLOSE, following the macro.READY, which close
the MCP data sets; then, control is returned to the operating system by using the
RETURN macro.
The data set definition section contains macros:
for the groupe of communication channels, for a data aet, for the measage queue,
for the MCP system log, for check-point data sets, as well as PCB macroa for
- user application programs.
The section for defining the teleprocessing network configuration contains macros
that deecribe communication channels, terminals and application programa. In thie
section, polling lists are built and other parameters that define system configura-
tion are apecified.
- The section for message handlers contains macroa used to apecify unique handling of
- messages circulating in the system for each group of terminals or application pro-
~ grams. In particular, message handler macroa can be used to control putting mes-
sages into a queue in accordance with prioritiea, edit meseages, control routing by
sending messagea to the needed destination queue, tranalate messagea from the trans-
mission code to computer code and vice versa, etc.
The MCP keeps message queues on NI~ [magnetic disk storage] and in main storage; it
has facilities allowing the computer operator to control netwark operation by uaing
commands issued from the console. The facility for creatin~ checkpoints allows re-
sumption of MCP operation at the point previously planned af ter computer malfunc-
tione.
The MCP has facilities affording interface between the MCP and uaer application
programs.
User application programs operate usually in individual storage partitiona; they
interact with terminals through the MCP and by using the usual sequential access
methods in YeS OS. This allows writing application programs in high-level langu-
agea and debugging them in advance without using the data teleprocessing devices.
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7.7. Remote Job Entry htode
Conversational remote job entry [CRJE] facilities allow job entry from remote termi-
nal9~ connected to a central computer by communication chan~els, and from local dis-
plays. They offer the CRJE user, working at a terminal, the same capabilities the
ordinary YeS OS user has at a central computer installation. The CRJE ensures ef-
ficient use of central computer equipment through joint use of computer resources
by several users at the same time. There is also the capability of joint use of
information media by several users executing jobs similar in content.
~e CRJE system operates within a syatem task aimilar to system IO tasks. A termi-
nal keyboard and printer (or display) are available in the CRJE system for input of
source information and output of f inal results. Jobs aent by a user come into the
operating system for subsequent planning and execution. When a job input from a
terminal completes its operat.ion, aIl ita output is placed in a special class for
the CRJE system. Then the contents of thia class are sent to the appropriate user
terminal where the job was input. The CRJE syetem enables creation of new data
sets, every possible operation on them and modification of any accessible informa-
tion, including jobs immediately prior to their input into the system stream of jobs
at the central computer installation.
There are three modes of user operation in the CRJE system: command, edit and
input.
When a user terminal is connected to the system, operation occurs in the command
mode. The user switches to the edit or input mode by using the EDIT command. In
the edit mode, commands are entered that are used to perform different operations
on the data sets. Operation in this mode ia terminated by entering the END command.
The input mode is used to create a new data set or add records to an existing file.
In the edit mode, the terminal user may request syntactic checking of PL/1 or
FORTRAN statements, if the appropriate syntactic checking programs have been in-
cluded in the system. Checking is done on a aingle statement; therefore, errors
will not be detected when a check of the relations between statementa is needed to
find them. For statements entered in the input moae, there ia the capability of
automatic checking. Wi1en errors are found, an appropriate measage is sent to the
terminal uaer.
In the command mode, the CRJE system uaer h~s the capability of inputting jobs from
data sets located in the terminal user'9 library and checking the process of its
execution at the cPnCral computer installation by requesting information on job
status. The terminal user may cancel a job input by him at any time. By using com-
mands, the terminal user may obtain information on the status of data sets prior to
job execution. When job execution enda, the terminal user receives a message indi-
cating normal or abnormal end. This means that job output is available for the
. user. By special command, all the output from the given job, placed in the output
class for CRJE, is sent to the term~inal. If the terminal does not have special in-
terruption facilities, the user ma~ uae the capability of receiving the output in
groups containing a specific numb~~r of liries. Information output may be interrupted
after any group. If the terminal is equ{.~,ped with interruption facilities, the user
of CRJE may interrupt output. at any time. The data set in the output class for CRJE
is erased after it is completely output to the terminal. If output is interrupted
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during data set transmission, this set is not erased. When necessary, the user may
resume information transmission, as well as sent it to the printer at the central
inatallation.
7.8. Time Sharing System
The YeS EVM software includes the time sharing system (SRV) [TSS], implemented in
the form of an independent program functianing within YeS OS. TSS assumes shared,
conversational and simultaneous use of a computer system by several users. This
system offers users the most advanced form of multiprogramming and functions under
control of YeS OS/MVT versions.
TSS offers a terminal user a sufficiently universal method of control o� the comput-
ing procese, implemented in the form of a command language and suitable for many
practical applications. T~arminal software is based on YeS OS TCAMa Including TSS
in YeS OS has no effect on the amount and nature of functione offered computer
users during operation in other procesaing modes. The capability ia provided for
- combining TSS and batch processing modes.
In a functional sense, TSS capabilities are considerably broader than those offered
users by the CRJE system. The fundamental differences between CRJE and TSS are as
follows. TSS joba are not put into the usual job queue, but are executed directly
under user control. In contrast to CRJE, which operates at the system task level,
TSS affects the operation of the YeS OS control programs. The number of TSS users
whose jobs execute in parallel exceeds considerably the number of CRJE system users
because of the efficient use of external atorage used to hold programs when they
are withdrawn from main storage and awaiting their turn for execution.
A command language similar to that in CRJE is used in TSS. The syntax of problem-
oriented language statements ie checked during input. Error messages are output to
the terminal.
TSS Operating Algorithm. The set of jobs to be executed in TSS form a queue that
is placed in external storage. Jobs are successively entered from the queue (fig.
48) into real storage and processed within a epecific time slice Z, which depends
on queue service time T and the number of joba K.
- Z _ K
Selection of the tiem slice depends on a number of contradictory factors. The time
slice must be sufficient for the system to be able to perform a certain quantity of
useful work and at the same time enaure a sufficiently quick response to user re-
quests, equal to the queue servicing period. At the same time, a decrease in the
slice leade to a decrease in the frequency of replacement of jobs in real atorage
and increases system overhead for transferring them.
The selection of these parameters is affected by the number. of partitions in real
storage allocated for execution of jobs in the TSS mode, the specific composition
of the job mix and a number of other factors.
Jobs in real storage at the same time make uae of the resources of the computer in-
atallation during smaller time slicea just as is done in the usual batch processing
mode (fig. 49).
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Time Bn~!+p ~teal Storage
. connnva noNnre
~'ea ro6 KQnNr o6 K~nNro6� ~aH~ nA .lodnNUr f. nn ~7~ne~
' P ~a n! po~p~KU nu6o~xu QorKU na6o~wu ~nn
Part~t~o A e c D aoaoi~~re~il~ )
1 ~ Jo[ n~~ut F PrHruhA
Pp~aen ? 2 KDoHr A'DoNS !'OJar/~ f~qR
06~o6o~NU � o6po60rku ~ .7ndnNUt N npKt7IOt7
Job Queue in Partition 2 ' (3, o6~5)rxu
External Storage _ _ ,
Real Storage `~ea"��'
I'oJd~O 1 POJdt/12 MJa[/I J
~7~ ~7~ ~7~
.
~
~L----' Job B
~AJ j
�Job D' / Fig. 49. TSS job procesaing together
~ with batch processing jobs
Job C /
Key:
1. proceseing slice (A, B, C, D)
2. processing elice (E, F)
liprk~ o6cnyHCU6a~~un avrpeBi~ 3. j ob ( C, F, N)
queue servicing time 4. TSS job partitiona
. 5. batch processing partition
x~aHr xeoNr ti~evNr kerrnr 6. smaller slices
~ 06paBorxu a6podnrKU n6pu6nrKU n6po6n~Ku 7
~pl~Qllf/R JQdQHUA J0t70NU~ ,70(~OI~UR / . partition ~1 ~ 2 ~ 3 ~
A B r, j D 1
Oacn .~xeNei
serviced
- E'ig. 48. TSS job procesaing
Key:
l. job processing slice (A, B, C, D)
The TSS control task functions under OS/MVT and controls TSS job exchange between
external and main storage. When the operator issues the command TSS START, the TSS
module receives control and forms the storage sector needed for the task in which
buffer areas are built, partitiona for job execution are formed and a parti.tion con-
trol task ie built for each partition.
In the process of fi~nctioning, the TSS mode control task effects replacement of
jobs in real storage, while optimizing the use of resourcea of the computer instal-
lation. It builds channel programs for each request for job input or output. By
ueing the apparatus of program-controlled interruptions, high efficiency of the job
replacement process is achieved: the interrupt procesaing program completes the
next channel program after the current channel program. Considering the high inten-
sity of exchange, the process flows as one unending IO operation. Information on
the location and sizes of the programs being transferred is formed in partition con-
trol task tables. If the operator isaues the STOP command, each active user is in-
formed of the termination of the operating session; the atorage area occupied by TSS
is returned to the operating system and operation is terminated.
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Tt?e partition control task operates in each partition allocated for job execution
in the TSS mode. It switches to active status those jobs given a partition for
the current time period and monitors the conditions associated with the end of the
servicing time. In particular, if IO operatione are not complete at the end of a
processing slice, the job is retained in the partition until the end of these
operations.
LOGON-LOGOFF Handler. The functiona of this task are eimilar to the functions of
the initiator and read (interpretation) program that operate in the conventional
batch processing mode. The LOGON-LOGOFF handler ia loaded into a partition for
planning of the new job when the immediate user is connected to the TSS.
The terminal control program is a monitor and the apecific user operates under its
control. Ae a function of the request, it retrieves the module needed for proces-
sing and passes control to it. After completion ~f processing of the request, the
terminal is sent the message READY and the program is ready to receive the next
command.
The message control program (PUS) [MCP] is a TCAM component. It contains the des-
cription of the configuration of terminals connected to the system and the IO areas
_ for storing information transferred between main storage and the terminals; it
effects data exchange between the IO areas and buffer areas of TSS. The MCP func-
tions in YeS OS as an ordinary problem program in a real atorage partition. It
must have the highest priority among the problem tasks operating in the operating
system.
Command and User Program Handlers. At this level of control are effected checking
of the correctness of commands, correctness of operand coding, calls of modules
that implement the standard servicing algorithms, and programs prepared by the TSS
user.
7.9. Virtual Storage Acceas Method
The virtual storage accese method (VSAM) is based on the concept of virtual atorage
and is used in systems with virtual atorage; therefore, data sets with virtual or-
ganization are atored aa pages. This access method is most efficient when disk
storage with 100M and 200M-byte capacity is used.
This access method combinea all the functional capabilitiea of all the other accesa
methods used in the MVT and MFT operating systems, except operation with parti-
- tioned data sets. VSAM substantially reducea data access time, especially because
with the indexed etructure, the procese of adding new records is organized without
use of overflow areas. VSAM offers the capability of indexing data sets by several
keys at the same time, which is very important for ASU [automated control systems).
7.10. Facilities for Building Multimachine Complexes
Hardware facilities have been provided in the YeS EVM-2 to implement multimachine
systems consisting of several CPU's and the corresponding IO devices and channels.
Multimachine systems allow increasing the overall throughput of a computer inatal-
lation and have increased reliability when errors and malfunctions occur, since a
computer going down in a multimachine system leada only to a reduction in through-
_ put.
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Computer complexing facili[ies (direct control facilitiea, channel-to-channel adap-
ter, common extent of external storage) enable organization of communication and ex-
change of information between several computers in a multimachine computer system.
Direct control facilities are used for rapid exchange of control and synchronizing
information between two computers in a multimachine computer installation. A
channel-to-channel adapter (AKK) may be designated for exchange between several com~
puters in a system of both control information and data files at the rate of opera-
tion of IO channels. A common extent of external disk (NrN) or tape (NML) storage
units allows two computers to make use of common information files stored in this
extent.
Multimachine system software is implemented at two levels. On the first level,
facilities are provided to control information transfer between CPU's, effected by
problem progra.Ts. Data exchange through an AKK occurs similar to the operation with
other IO devicea with the use of the operating syetem access method. On the aecond
level, multimachine syetem control is implemented, which optimizes distribution of
the programs, subject to procesaing, between the varioue CPU's making up the complex.
Central control of the complex is performed by the hoat machine which organizes
distribution of operations.
A modified YeS OS control program, which monitore the entire system and controls
the common job file, is uaed to control the multimachine syatem.
Appropriate software is provided within the YeS OS for each level of organization
of the multimachine system.
Direct control soYtware facilities presuppoae data exchange between two computers
connected by direct control interfaces.
The DIRECTWR macro is provided for access to another CPU through the direct control
interface. Reception of informatian sent through the direct control interface by
using the DIRECTWR macro is effected by YeS OS. Depending on the operating mode
chosen, information feedback for monitoring may be initiated. Then control is
passed to a procedure for analysis of the information received, which is a program
interface between the programs for processing the received information.
In YeS OS, there are standard interface programs for direct control facilitiea and
an asynchronous exit to a program prepared by a user is provided.
In asynchronous operation of two compt~tere, a conflict situation may arise when re-
quests for information exchange over the direct control lines come into the two
computers at the same time. To overcome thie, in the syatem loading procees there
is an exit to the console for the purpose of specifying the priority when aimulta~i-
eous requests from two computera come in. Operator responses on the various com-
puters in the multimachine syatem muet be coordinated.
Program Control of Channel-to-Channel Adapter. In connection with the sequential
structure of data sets sent through an AKK, two acceas methods, QSAM and BSAM, have
been provided. Each provides its own set of macroa to deacribe a data set and re- ~
quest IO operations.
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Program checking of the correctnces ot' tran~miseion of information through a
channel-to-channel adapter is provided in the YeS OS. The program generating a
block of data muet include in it the check sum
modulo 232. A secondary check of the check sum and comparison of it with the origi-
nal sum are effected by the YeS OS programe. After reception and checking, the
information is sent to the user program.
Program Control of the Common Extent of External Disk and Tape Storage. The common
extent of.external storage may contain data sets with any data organization valid
in YeS OS and all valid access methods may be used for operation with them.
Appropriate macros have been provided to reserve the devices of any of the compu-
tere and to subsequently release them. After completion of a task, if the operating
system detects a resource not released by the task, the resource is automatically
released.
It should be stressed that the level of reservation for the cc+trnnon extent of exter-
nal tape storage differs considerably from that for disk because of the sequential
nature of magnetic tapes. Reserving a tape storage unit from the common storage
extent actually results in reservation c~f all the tape unita connected to the eame
control unit as the reserved unit. The specifica of operating with data aets on
tape also imposes a restriction on the place of issuance of the macros f or device
reserving and releasing. Reservation is required to create and modify data aets on
disk. It is not needed for reading data seta and in the intervals between data
modif ications .
When problem-oriented languages are used, the functiona of reaerving and releasing
peripheral.s may be performed by a special program written in Assembler.
The sof tware for the common extent of external storage is included in the YeS OS
when it is generated. There ls a restriction on syatem data sete, which cannot be
placed in the common extent of disk storage. In operation with the common extent
of external storage, special attention is paid to placement of a data set on certain
extents, since the stipulated arrangement may reault in conflict situations.
7.11. Dynamic Debugging Monitor
~he dynamic debugging monitor (DDM) is designed to debug both YeS OS programs and
user programe operating under operating syetem control. The DDM can be used to
perform:
halts of the syatem being monitored when specified program events occur, which in-
clude: transfer of control according to a epecified address, and occurrence of
program events recorded by using the hardware facilities of program event recording
(PER); and
recording of certain program events (various typea of interruptions, times of exe-
cution of privileged inatructione) pertaining to the operation of the system being
debugged.
After a halt of the system being debugged at the specified point, one can perform:
a change in the status of the system of the contents of the general, control and
floating-point registers, a specified area of main storage, and a PSW change.;
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a printout of the information reflecting tl~e status of ttie system being debugged at
the the halt point: printout of the general, control and floating-point registers,
the PSW, conetnts of certain areas of the operating system, etc.
The DDM is included in the system being debugged when the YeS OS is generat~d. DDM
is initiated during operation of the program to intiate the nucleus of the operating
- system.
By method of organization, DDM programs are divided into DDM supervisor programs,
which operate in the supervisor state and receive control as a result of the occur-
rence of an interruption, and DDM processes, which operate in the "task" state.
The system being debugged operates in the "task" mode; therefore, DDM programs re-
ceive control when interruptions occur during execution of privileged instructiona
in the system being debugged, having the capability of tracking the flow of control
in the system being debugged without interfering in its operation.
DDM interrupt handlers distinguieh interruptions pertaining to monitor operation
which are sent to DDM programs, and interruptions pertaining to operation of the
_ system being debugged which are sent for procesaing to the programe of the aystem
being debugged.
The control processors of the monitor receive control by means of the DDM dispatcher.
A program operating in the "task" mode is provided for each process. These programs
include a program to issue messages to the console, a program to control the pro-
cesses of the printout and change of data of DDM, and progarms to control the mode
of debugging, processing of printout inetructions and data change. .
7.12. Generalized Trace Facility
The generalized trace facility (UST) [GTF], pertaining to a class of monitor pro-
grams, is designed to acquire information on a specified class of events occurring
during the functioning of the computer under operating system control. The GTF is
included in any specific OS version when it is generated. It exists in the form of
modules of the control program nucleus and in system libraries. To use the GTF, a
- monitor program is generated which implements ita functions.
An event occurring in the computer functioning process is considered recognizable
if with each onset of this event, the monitor, in which the procesaing program for
this event is provided, receives control. After processing of the recognizable
event, the monitor returns control to the program, during operation of which this
event occurred.
The monitor places records on events recognized in the event trace and stores it on
an external storage unit. The event trace is a sequence of records on recognized
events, ordered by thz time of their onset and which reflects the history of func-
tioning of a progarm or the computer as a whole during some time interval.
Events recognized by the monitor form three groups: interruptions, privileged in-
structions and the GTRACE macro inatruction.
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Of the interrupt group, the following eventa are diatinguiehed:
external interruption;
supervisor-call interruption;
program interruption; and
IO interruption.
The group of privileged instructions includes the following events:
LPSW instruction;
SSM instruction;
SIO, TIO, HIO, TCM, WRP, ROD instructions; and
SSK, ISK instructions.
The GTRACE macro instruction is deaigned for inaerting into the event trace data
- especially provided for this purpoae.
The monitor ~an eb started only by computer operator command and functions as a
system task. Certain requirements on main storage and the IO eystem must be met .
for successful functioning of the GTF. To atore the evnt trace, the GTF monitor
may use a data set on either tape or disk. The computer must have a peripheral
for storing the event trace and ensure its serviceability.
An appropriate operator cammand is issued to terminate monitor operation and
cancel the GTF task. ~
7.13. YeS OS Recovery Fac:.lities
Yn t~; computer functioning process, various hardware malfunctions occur periodic-
ally which result in errors. The complexity of modern computera requires a rapid
response to an error; otherwise, delays it~ localizing errora and eliminating their
consequences will result in irregularities of the information in main storage and
extreme losses of time. t
To raise the efficiency of using modern computers, the operating eyetem includes
special programs to recover the serviceability of the YeS OS af ter errors occur in
the CPU, main atorage, IO channels and peripherals, and to record information on
the status of hardware and software at the time the error occurs.
These facilities include the following programs that have become traditional:
SERp, SERl for recording the status of tt~e hardware and the YeS OS;
CCH for handling IO channel errors;
ERP for handling peripheral errors;
OBP for recording the .status of peripherals;
EREP for editing and printing records on errors; and
the standalone program SEREP for editing and printing information on errors.
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With further development of the YeS OS recovery facilities based on generalization
of the experience of operating with the preceding versions of the YeS OS, the need
arose to create additional program components that substantially expand the capa-
bilities of the recovery facilities. The new components reduce many aituationa
th~ti result in overloading YeS OS and strive maximally to overcome the effect of
errors on system serviceability.
The additional recovery facilities include:
the POSK program which enables recovery of YeS OS aerviceability on the functional
and system levels;
the APR program for retry of IO operations over an alternate access path;
the DDR, dynamic device reconfiguration, program; and
the MIC [missing interruption checker] program for processing misaing IO inter-
_ ruptions.
Software recovery facilities are claesified as facilities for recovery after IO
or machine errors.
Facilities for recovery after IO errore are componenta of the IO supervisor or
~ operate under its control. Let us touch in more detail on an analysie of each of
the programs.
- The CCH program receives control when an error occurs in an IO channel. It analyzes
the error, generates information on the statua of the YeS OS and hardware when the
error was detected and informs the operator that the error occurred. If it is es-
tablished that the error ia transient, control ia passed to the ERP program for re-
try of the IO operation. In event of a permanent error, control is passed to the
APR program (if it has been included in the specific OS conf iguration during system
generation) to find an alternate path for access to the peripheral. But if CCH
determined the need to terminate YeS OS operation, it generatea a record on the
- error and passes control to the SER1 or POSK programs for recording these data in
the system log SYSI.LOGREC and switches the CPU to the wait state. When termina-
tion of YeS OS operation is not required, control ie pasaed to the OBR program for
recording information on the error in SYSI.LOGREC and sending a warning message to
the computer operator.
The APR program finds an alternative path for access to the peripheral specified in
the IO operation, but only when the channel error occurs on the main path. When
an alternate path through another channel is available, APR passes control to the
ERP program for retry of the IO operation. Wh~n an alternate path is not found,
cantrol is passed to the SERO, ~iERl and POSK programs for recording the status of
the YeS OS and hardware in the ~lata set SYSI.LOGREC. APR givea the operator the
capability of adding or removin;; one of the patha for accesa to the p~ripheral.
- The ERP program, a mandatory component of YeS OS, is a set of standard procedures
for processing peripheral errors. There is an individual procedure for each
peripheral. The ERP program analyzes the error. If the error is permanent, retry
of the operation is not possible. The computer operator issues the appropriate
message and control is passed to the OBR program. In the other cases, ERP attempts
a retry of the IO operation. T:~e number of retries depende on the peripheral type.
If the error is not corrected after the specifiec~ number of retries, it is
classified as permanent.
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The OBR program, a component of the IO supervisor, gathers statistics on the status
of the YeS OS and the peripherals in which the error occurred. The information is
logged in the system log SYSI.LOGREC. OBR also monitors how full the SYSI.LOGREC
data set is and informs the aystem operator about this.
The DDR program reconfigures devices. After a permanent error ie detec ted, the IO
supervisor paeses control to the DDR program which determines the possibility of
moving the IO operation to another IO device. If thia ia possible, the DDR performs
the appropriate rearrangement of the syatems tgbles, issuea inetructions to the
operator for moving the volume needed and returns control to the ERP progrem for a
retry of the IO operation. DDR offers the capability of reconfiguring devices of
the same type, including card devices, disk and tape atorage units and printers.
The MIC program monitora completion of IO operations. It identifiea aituations
associated with losaes of IO interruptiona that are a reeult of both hardware mal-
functiona and errors in YeS OS operation. If an expected interruption has not
occurred within a apecified time, MIC messages the computer operator, loga the in-
formation on the error that occurred in the ayatem log and eimulatea the missing
interruption, completing the request for I0.
_ Facilitiea for recovery after machine checka conaist of the SERO, SER1 and POSK ~
programe that log the etatus of the hardware and YeS OS, depending on the type of
- computer used. The programs receive control when machine checks occur through a~
new PSW for interruptions from the check circuite and in the case of IO errore,
from the CCH program. The SERO, SER1 and POSK programa are mutually exclusive.
SERO determinea the type of error detected, generatea a record o� the error, com-
pletes execution of all IO operatione, records the information on the error in the
system log SYSI.LOGREC, sende the computer operator a.measage on !:he error,, recom-
mending reloading of YeS OS, and puts the CPU in the wai,t etate.~ If a second
machine check occure during operation of the SERO program, SERO loga special infor-
mation in the SYSI.LOGREC data eet and puta the CPU in the wait state.
In addition to the functione implemented by the SERO program, the SER1 program
analyzes the nature of the error based on information supplied by hardware facili-
ties, checke the nucleus area for parity errore, and attempte to recover aystem
serviceability, af ter abending the task affected by the error. If SER1 has estab-
liehed the fact of dietortion of the control programs or hae not detected a
damaged task, the computer operator ie sent a meeeage on the error with the recom-
mendation of reloading YeS OS, and the CPU ie switched to the wait state.
The POSK program begins operation with analysis of the interrupt code that contains
information on the nature of the machine check detected. If the error wae overcome
by hardware facilities, POSK loge the appropriate information in the system log
and performs no recovery operationa. But if the interruption code is for an unsuc-
ceeaful hardware recovery, POSK tries maximally to keep YeS OS in a aerviceable
atate. An attempt is made at functioncil recovery, ae a result of which the da-
maged taek remaine fully serviceable. If functional recovery ie not posaible, re-
covery is rr,ade at the syetem level, which consists in abending the damaged task.
When the control program ie damaged, recovery is conaider~d impoesible and the com-
puter operatar ie ieaued a meseage with the recommendation to reload Ye S OS.
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7.14. YeS DOS-3 Operating System
The YeS DOS-3 m~.iltiprogram operating systen~ is intended f or organization of effi-
cient functioning of small and medium YeS EVM-2 computers with virtual storage. It
supports batch job processing, data teleprocessing facilitiea and data base manage-
ment facilities. The concept of the DOS-3 control program differs considerably
from that of previous versions of the DOS. This new concept has the following main
advantages:
more flexible allocation of system resources;
more efficient IO control system in a virtual environment;
program independence of type and model of peripheral; and
simplified systems maintenance.
The DOS-3 modular structure permits expansion and improvement of software, which
allows relying on its viability over the entire period of operation of the YeS
EVM-2 in traditional and new applications. DOS-3 is based on using the concept of
virtual storage, d~~namic allocation of resources and centralization of all major
system functions.
YeS DOS-3 Composition. The first phase of the YeS DOS-3 includea the following
program components:
control program: supervisor, job management, initial loading, program for
_ peripheral concurrency;
logical IO control system;
system utility routines: editor, librarian, special routines, sorting routines,
, debu~ging facilities, device test routine;
Assembler translator;
translators for programming languages: FORTRAN, PL/1, COBOL, RPG-2 with auto-
report; and
BTAM.
Development plans call for the following program components in the second phase of
the YeS DOS-3:
expanaion of the control program: support of secondary consoles, catalog of files,
expansion of remote job entry;
system utility routines: facilities for checking system generation, facilities
for managing etatietics;
translators for programming languages: optimi.zing PL/1, PL/C, PASCAL, SIMSCRIPT,
- SYSTRAN; and
the DL/1 system.
C~mpatibility with YeS DOS-2. YeS DOS-3 is compatible with YeS DOS-2 at the level
of .
+ high-level programming languages;
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Assembler language, if the program daes not refer to internal control units and
syatem tables (including DTF tables) by meana of non-syatem functi4ns; and
object modules, if the program does not refer to the system nucleus and the re-
- quirements for compatibility at the Assembler level are met.
Compatibility is not supported for programs dependent on specific characteristics
of computer models or devices.
To facilitate programming and increase compatibility, YeS DOS-3 has declarative
macro instructions that permit reference to control units and s-stem tables in
symbolic form.
System Resources. The main function of the operating aystem nucleus is control of
utilization of all system resourcea. DOS-3 offers the following resources:
area of virtual addresses;
area of real storage;
- area of storage on auxiliary storage direct-access devic~;s for syatem use;
IO peripherals;
data files on external storage units; and
operating eystem programs.
The best possible distribution depends on the nature of theae resourcea. Some of �
them, control program components for example, are used jointly by many users at the
same time. Similarly, libraries and data files may be used jointly (only as input
information).
Unsha~~d resourcea (for example, a atorage area, unit record peripherals, output
and update files) are allocated dynamically, but largely to the entire process of
operation to avoid system impasaes.
' Sequential and unit record peripherals are essentially not shared. DOS-3 supports
, definition of peripherals used jointly by aeveral users and indirect IO (SPOOLING).
The system work area is primarily implemented in an area of virtual addresses, and
in doing so, a permanently allocated work area on disks ia not required. Because
of this, the usual "critical" elements of a DOS eystem (SYSUT syatem utility filea
and SYSLNK files) are not needed; therefore, the multiprogram mode ia enabled for
~ even small hardware configurations.
Main Storage Management. The main aystem reaource is virtual atorage. All user
operations executed at the same time have their own virtual area not exceeding 16M
bytes. This virtual area is etatically divided into four parte:
area of identical addressea;
area of jointly used programs;
a jointly used virtual work area; and
a personal virtual area.
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~ The identical address area takes up the lower part of any virtual area, starting
with the zero address (real ro virtual). This area is always implemented in real
storage, not reflected c~a magnetic diaks and ie common for all virtual areas, but
the addresses of all objects are identical and real. This area contains the DOS-3
control program and control tables. The boundary of this area is set when the
system.is generated.
The area of jointly used programs is also common for all virtual areas. Stored on
magentic disks is a copy of the DOS-3 control pro~ram phasea in the form in which
these phases are stored in the abaolute module library. This area contains super-
visor transient programs, logical IO control system modules, logical IO control sys-
tem transient programs, the job management program, etc.
From the area of jointly used programs, parte of the DOS-3 are moved into real
storage by the paging mechanism. Since these system programa are reentrant, they
do not have to be copied into the page set. A copy of the jointly used virtual
work area is kept in the page data set. The upper boundary of the jointly used
virtual work area is set when the system is generated and defines the lower bound-
ary of L'he personal virtual area. This address is the address, starting from
which the user usually edits his programs. Each user job is given its own (perso-
nal) virtual area (i.e. appropriate page tables are built). At thsi same time (or
_ during editing) the SYSLNK area is built. After a program is loaded for execution,
a copy of it remains unaltered in the absolute module library; alterable copies of
a program and data are kept in the page data set and used in the paging between
real storage and the page set. The size of a personal virtual area may be dynamic-
ally extended to a maximum of 16M bytes.
Real storage or the area of real pages is divided into two parts: the area of
identical addresses and the area of replaceable pages. The contents of the area of
identical addresses is the permanent reaident part of the DOS-3 control program,
_ i.e. the real part of all virtual areas. The series of pages of the jointly used
and personal virtual storage is transferred to real pages when necessary. The con-
trol program periodically executes a review procedure to determine which pages are
no longer needed in real storage to keep the contents of changed pages in the page
set in the end.
The page set is nlaced on one or more disk volumes; a unique adjacent sector must
be allocated on each volume. The set forms the required storage area on disks to
keep the form of changed or constructed contents of any virtual atorage area. The
entire page set area is formatted in advance into 1K-byte blocka and a segment is
the unit of allocation. Dynamic allocation of segments is determined by uaing the
segment set scheme in ref~I etorage. The maximum eize of this set is a parameter
of DOS-3 system generation.
Job Input and Planning. Jobs are input into the system by means of the device(s)
assigned by the oper~tor as the syatem input device. When several syatem input de-
vices are available or if the system input device is a virtua.l device, the system
operates in the multiprogram mode. The system input unit may be a card input unit,
a tape or disk storage unit, a virtual system input unit that can be connected to
any unit record device, a floppy disk input unit or a telecommunications unit.
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The unit of agsignment and planning of reaources is the order, conaisting of one
or more jobs that can be processed sequentially and make uae of the same system
resource.s .
The first statement in any ordes [zakaz] muet be a*$$JOB atatement that can be con-
ventionally described as the creation and description of a partition. The *$$JOB
statement parameters are used by the system scheduler to determine whether all re-
sources requested are accessible and, consequently, whether the partition needed
can be creat.ed and started. The user first idnicates the required size of virtual
storage in kilobytes and the actual size of real storage (size of a working set of
pages). The required configuration of other resources (peripherals, disk and tape
volumes, files) is indicated by a reference to a certain phase of the description
of the partition in the absolute module library. Any number of different phases of
a deacription of a partition may be written and cataloged by using the system macro-
instructions. The partition description phase contains a list of standard assign-
ments, in which all devices (by means of the phyaical addrees (CUU) or device
class), tape and disk volumes needed fo~ execution of the entire order are indicated.
This information is used by thE systern to determ..ne the capabil~~~ of starting the
operation, reserving all required devicea and building the appropriate table of
logical devicea for the partition.
- The work scheduler builds a table of requests for operatian and puts it in the sys-
_ tem job queue. When all required resourcea are available, they are reaerved, par-
tition t.ables are built, and the first job in the order is started. Jointly used
IO devices are not reserved for exclusive use. It is recommended that IO devicea
be allocated by class or volume registration number to make full use of eystem
flexibility. Output and update files on disk are reserved when opened for individ-
ual use; input files may be shared.
Supervisor. DOS-3 consists of a relatively amall nucleus that includes the inter-
rupt handler, the queue handler, the SVS programs, programs for recovery of IO
errors on disk, a program to find a miasing page and other.s.
The nucleus stays permanently in t.he identical addreas area. In addition to the
nucleus, the supervisor includes a number of programs kept permanently in the area
for jointly used programs. The table of contents of all the programs in this area
is built by the editor and stored in the identical address area during initial load-
ing. The supervisor can control parallel procesaing of up to five independent
operations (job streams), each of whicli is ex2cuted in its own partition; up to 99
subtasks may be created and executed c~~r.currently in any partition.
Logical IOCS. Three basic aims were cana;.dered in developing the logical IO control
system [IOCS]:
maintain the continuity of the logical IOCS;
improve the efficiency of the system with regard to its functioning in the virtual
environment; and
increase the flexibility of the system.
The first aim was achieved by keeping all the data accesa methods that exiated in
- preceding versions of YeS DOS in the YeS DOS-3 logical IOCS. Syetem declarative and
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1~()N t)I~H'I('IA1. I~til~: ()NI.Y
executive macro instruclions re[r~in at the symbolic levc:l Che muin leaturey irum
preceding systems; in the process, howver, a number ~f file description parameters
are not considered. All system expanaion methods were designed to maintain soft-
ware compatibility. Organization of files of varioua formata was also retained.
The exception is organization of index sequential files which underwent some chang -
es because of implementation of more modern concepts of index aequential files.
The system offers programs to translate index sequential files from previous ver-
sions of YeS DOS into those for YeS DOS-3.
The necessity of achieving the second aim occurred because the DOS-3 logical IOCS
is intended for functioning in the virtual environment, while the hardware for IO
operations in a virtual environment is insufficiently developed. The main task in
- executing any IO operation is the fixing of all storage areas needed in execution
of the IO operation in real storage for the entire operation execution time. Work
areas such as those for the channel program, list of addresses for indirect addres -
sing in the channel, disk address for finding a specific block on disk and others
are reserved in one area during the data file opening procedure. The user should
not specify IO areas in his program. In this case, allocation of IO areas is per -
formed automatically during the opening procedure. Automatic allocation of work
areas di!rint; the opening procedure allow:: obtaining an adjacent area for all work
areas associated with the I~ operat:.ns; this saves on the number of apges needed
for fixing in real storage and permits one fixing during the opening procedure in -
stead of multiple fixing at the start of each IO operation.
Raising the flexibility of the logica? IOCS is achieved by the following methods:
change in the principle for connecting executive modules for I0. Executive IO
modules are connected during the dat~ file opening procedure; since they are reen -
trant, they may be used in several, tasks at the same time, which saves considerab 1 e
storage in the multiprogram mode of ope�ration;
offering the capability of dynamic allocation of IO areas during the file
opening procedure;
the capability of dynamic change of parameters; for example, right before the
start of a program, record size and record block size may be specified; and
the higher degree of independence of the peripheral makeup. In aseigning devices,
one may specify only the device type, and the operating system will allocate a
free device of the given type.
Libraries. There are fi~re types of libraries in YeS DOS-3: absolute module
(phase), object module, aource module, procedure and edited macro definition.
The absolute module library is intended for atoring programs (phases) ready for
execution. In addition to the usual phasea, this lit;rary contains partition de-
scription phases that are used during :;tart of p~artitiona an list the resources
needed for thP partition; it also contains the t3ble of contents of programs in
the virtual area of jointly used progarms.
The object module library is intended for atoring object modules tha~ result from
the programming language translators. Basically, this library is used to hold
standard programs stored in object module form convenient for connecting to other
programs.
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i~~~u c~~~rt~ ~i ~i ~~~r� t?Ni ~
'fhe source module librdry is intended for storing modules in the source programming
languages. A convenient apparatus ia provided to make changes in source modules
and connect other source modules as parts of a given source module.
The procedure library is designed to hold frequently used job sets. There is en
apparatus for adjusting procedures for specific applications (substitution of
assigned parameters).
A thorough syntactic check is made during cataloging of macro definitions. Thie
speeds up debugging and translating of macro definitiona from the usual format into
the edited, which speeds up considerably the procesa of generating macro expansions
from macro definitions. This information is contained in the edited macro
definition library.
All libraries are disk files. At the beginning of each library, there is a table
of contents of the library elements, which are eorted and blocked. To speed up
searching, each block of a table of contenta has a key. Library element text is
- stored in fixed-length blocks. A~1 libraries may be system or personal.
The general library maintenance routine performs on library elements functions such
as caCaloging, deleting, renaming, correcting, perforating and printing individual
elements or groups of library elements. The maint~nance routine used to copy and
reorganize lihraries transfers entire libraries, sublibraries and groups of library
elements from uisic to tape, i.e. it copies libraries, sublibraries or individual
elements from one or more libraries input to one output library. Ordering and
compression of text occurs during this transfer.
Spooling. The real capabilitiea of multiprogramming with a small amount of hard-
ware are limited by the number of unit record devicea, especially by the number of
- line printers. Therefore, spooling is included in the DOS-3 control program. At
system generation time, the user may specify any number of virtual unit record de-
vices, each fo which is associated with a real device. Virtual devices may be used
at the same time by several partitions.
If several additional virtual printers or ot.her devices have been defined, any
program in any partition may use all these devices at the same time. Data obtained
as a result may then b~ printed sequentially on one real~ printer.
For input, the situation is somewhat different. In this case, the oper.ator may
start the process of buffering of data on any number of.input units, including
telecommunication dev~ces. Direct input of other jobs into the system may occur at
the same time, if a real peripheral has been assigned to the corresponding logical
input unit.
Thus, one can combine as desired direct input and spooling, i.e. system IO of data
through SYSRDR, SYSIPT, SYSLST and SYSPCH from a terminal or output to it is
possible only in the spooling mode. In this case (indirect IO over teleprocessing
- lines), any program can read (write) its data from (and to) a terminal by using
the conventional macro instructions in the logical IOCS just as if it came from a
card reader or output to a printer, etc.
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Thcre ia a job control language and operator command language that allows setting
and changing priorities of individual operations and specifying the need for
keeping or processing data, deleting after processing or moving from the output
queue to some input queue. The majority of central operator control commands are
av~ilable to a remote operator.
Command statements can be used in the data input stream to include data coming from
other input unita in the atream. Thia ia especially useful in inputting data from
floppy disks or perforated tape units prepared without the appropriate control
cards. Data input from nonstandard units, from perforated tape input units for ex-
ample, can be translated into the standard DKOI [decimal information interchange
code] and then processed the usual way.
Spooling allows the operator to determine the actual status of IO queues, the
status of current operations, use of resources, etc. This enables collection of
basic accounting data, that is kept automatically in the form of a spearate data
queue and output as required. The system is built to enable simplicity and
efficiency in restarting after device errora occur.
7.15. Application Program Packagea
Along with the operating systems and maintenance programa discussed above, applica-
tion program packages (PPP) are an integral part of the YeS EVM software system.
A PPP is a functionally complete complex of program facilities oriented to solving
a specific logically complete class of problems.
The PPP developed within the YeS EVM differ in independence of the type of hardware
and pex�ipherals used, ease of adjustment, diversity of clasaes of problems solved
(application areas) and by the various algorithma for aolutions in each class.
They are oriented to operating under the control of the YeS DOS and YeS OS opera-
ting systems and in many cases are a further expansion of them. There are now over
a hundred packages embracing several millions of inatructions in the Unified System.
PPP are classified by application sphere and class of problem solved as folows:
general-purpose;
for solving engineering, scientific and technical problems;
for solving economic problems and those in ASU's; and ,
expanding the capabilities of themain operating systems.
General-purpose PPP include programs that implement mathematical methods (for ex-
- ample, methoda of queueing theory, probability theory, mathematical programming,
etc.) for solvin~ problema that pertain to many a~herea of application. As a rule,
- these programs form the baeis of the complex application problems of management and
planning, operations research, aimulation, etc., but may have an even greater value
of their own.
Individual packages, as w~~ll as methodologically oriented (numerical mathematics,
mathematical statistics, ~~tc.) PPP for engineering, scientific and technical calcu-
lations, are designed to solve problems of computing special functions, interpola-
tion, optimization, design, medical research and others. This class of PPP is
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charact~erized by a great diversity in probleme aolved and continual expansion of
them. Resting on program creation as the basis and making use of the high-level
programming languagea designed specif ically for scientific and technical applica-
tions, the user may develop packages oriented to solving his own problems.
The PPP for economic calculations and ASU are used to solve problems of production
management and planning, operatione and long-term planning, supply of materials and
equipment and othera. In connection with the wideapread incorporation of Unified
System computer facilities in various types of automated management systems, this
class of PPP is assuming major importance; new programs have to be written and
atandardized especially in view of their widespread application.
Efforts by developers of Unified System software who apecialize in the problems of
applications programming are mainly focused on creating PPP that extend the capa-
bilities of th~e main operating systems. Theae packagea are designed to aupport
cErtain modes of operation of computer systems, as well as the functioning of
specialized hardware.
Since this class of packages by its f unctional value is of special intereat to
YeS EVM users, given below in detail are the characteriatice of the programe that
expand the functions of operating eystems in the direction of supporting additional
modes of operation and managing complex data atructurea.
A major quality of modern computer systeme from the viewpoint of their use in
building ASU's and IPS [information retrieval syateme] is the availability within
the standard software of facilities for organizing and managing large data files
and facilities that afford shared access to these files in t~~ mode of aimultaneous
servicing of user queries coming from remote and local terminals. There are now
two PPP supporting these functions within the YeS EVM software system.
The "Oka" Data Base Management System (SUBD "Oka") [DBMS] is intended for building
large-scale informational, reference and management eystema with a large volume of
_ processed information and complex logical tiea between the data elements.
The system supports operation with data bases in the batch and teleprocessing
modes. All types of remote and l~cal YeS EVM terminals can operate in the system.
Data access is provided by application programming facilities in PL/1, COBOL and
Assembler through the BETA data language. The DBMS data bases are implemented by
hierarchical and inverted data structures.
The DBMS facilitiea support sequential and random acceas to the data basea and all
types of processing: aelection, insertion, replacement and deletion at the level
of LoRical units of data.
The system hae developed facilities for managing data bases that enable:
logging of all changes occurring in a data base and recording all messages;
data recovery that maintains the information stock of the system in the correct
status in event of equipment failures and malfunctions;
resource protection from unauthor:ized acsess;
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reorganization and loading of data basea; and
preparation of statistical reports.
In the teleprocessing mode, the "Oka" system performs all functions required for
managing the reception, transmission, switching and translation of inessages ex-
changed between the terminal network and a co~puter.
The "Kama" Data Base Teleprocessing Syst~em is intended for use as teh base software
in building:
a wide clase of conventional applications for teleprocessing syatems, including
message switching, reception of inquiries, data input in the interactive mode and
data acquisition; and
information reference systems for shared use operating online and characterized by
quick r.eeponse.
The "Kama" aystem supports procesaing forms euch as data input and accumulation on-
line, message transmission from one terminal to another, online start of applica-
tions programs from terminals. This system also aervices uaer queries at the same
time, coming from the terminal network. The number of simultaneously executable
programs is limited only by the size of main storage available.
User requests are realized by application programs written in PL/1, COBOL or Assem-
bler. Application programs are linked to a teleprocessing aystem by macro instruc-
tion facilities.
Data management in the data base teleprocessing system offers facilities for work-
ing with sequentially organized files and data basea built with YeS OS files with
index sequential or direct organization. Information capabilities of the data base
teleprocessing system enable management, selection, recording and updating of
information in data bases.
Information system developers are fully r~aponsible for the initial loading and
integrity of the data bases.
The KROS PPP is designed to expand the capabilities of the YeS OS. Operation of
the operating system together with the KROS PPP enables:
raising computer system throughput because of the change in the YeS OS job manage-
ment algorithm and the use of special acceas methods for operation with job input
streams and data output streams. How much throughput is increased depends on the
computer configuration and the nature of jobs executed; and
automating computer operator functions. The KROS PPP performs automatically some
of the actions usually performed by the computer operator.
For example, the KROS package plans and starts programs for system input, system
output and initiators. Computer operators are also given a number of additional
commands to manage job execution and peripheral operation:
dynamic ordering of task solving based on ai1 account of the use of the CPU and
peripherals; and
automatic inclusion in the job input stream of jobs formed by user programs.
.A
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Using the KROS package reduces the requirements for resources for a computer system.
In particular, less direct access storage needed for holding the input and output
data sets is required. Main storage size needed for KROS package operation is
generally less than that needed by standard YeS OS facilities performing similar
functions.
Since the KROS package supports remote job entry, the remote user can execute
jobs under the control of YeS QS and KROS.
Unified System computers with the standard instruction set and the AP-4 (YeS-8504)
terminals can be used as the remote stations.
Also note that using the KRdS PPP does not require any change to Ye S OS or user
programs.
The KROS PPP is independent of the YeS OS edition and can be used as the basi~s for
development of new facilities and capabilities that do not affect Ye S OS and user
programs.
The ROS PPP is intended for the functioning of a computer system tha t includes an
arbitrary number of Unified System computers, each of which operates under control
of the YeS OS.
. The ROS PPP operates in one computer in a multimachine system. This computer is
called the service computer and the others are called main computers. The service
and main computers are linked by a channel-to-channel adapter.
Using YeS OS together with the ROS package in a multimachin~e computer system raises
the throughput and reliability of the computer system compared to the computers
used separately; it also permits reducing the number of computer operators main-
taining the multimachine system. This advantage is achieved by dividxng the func-
tions for job execution between the service and main computers and making sue of
the additi.onal capabilities offereii by the ROS PPP.
Job execution functions are divided as follows. The service computer takes care of:
_ input and building a common job queue for the whole multimachine computer system;
planning of job execution on the main computers with regard to user requirements;
sending a job for execution to a selected main computer;
receiving data from a main computer, obtained as a result of job execution;
output of data received on a printer and perforation; and
automatic issuance of required operator commands to the main computer.
Since all auxiliary functions for job processing are taken care of by the service
computer, a main computer is concerned only with job execution. Also, instead of
the slow devices for job input, data output and the operator console, a main compu-
ter uses high-speed channel-to-channel adapters for data transmission. These con-
ditions for operation of a main computer within a multimachine compu ter system sig-
~ nificantly increase the efficiency of its operation compared to the usual operating
conditions.
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_ Additional capabilities of the ROS package include:
user job processing management by using ROS command statements together with YeS
OS JCL command statements. Use of ROS command statements is not mandatory;
capability of advance setting of data media needed for a job on a main comput~r
before the start of job execution;
processing of internal jobs, which allows a user program executed on a main compu-
ter to gen~rate new jobs and place them in the common ROS job queue;
management of dependent jobs, which allows a user to establish a relationahip be-
tween jobs in some group of jobs and execute these joba in a sequence described by
the user;
remote processing of jobs, i.e. the capability of remote job entry from terminals
and output of ,processing results to them;
additional service routines in the form of a standard set of service functions
operating under ROS control; and
the local execution mode, when one computer is used as the main and service
computer.
The real-time supervisor (SRV) is a PPP that together with the YeS OS enables
efficient use of all models in systems that control proceases or objects in real
time. The real-time supervisor offers facilities to extend the functional capa-
bilities of the operating system in the followin~ directiona:
use of nonstandard IO devices (real-time devices) and lines for external interrup-
tions (real-time lines) as sources of data to be processed in real time;
rapid system response in processing data coming into the computer from the real-
time devices and lines;
a strict tie-in between times of execution of functional programs in a system and
~ actual time transpiring; and
- a number of additional optional capabilities (operation with resident and nonresi-
dent data queues, logging of events in a system, operator aervice and others) that
may be used in process control systems.
To realize these capabilities, the real-time supervisor has its own facilities for
orgariizing the data processing procesa, in the background of which occurs the
operation of the operating system. As a result, the SRV offers an additional, with
respect to those available in the operating aystem, tnode for servicing programs,
called the rQal-time mode; programs using SRV capabilities are executed under
this mode.
Universality of SRV and the efficiency of the real-time mode aupported by it are
achieved because of the availability of the SRV generation facilities. The genera-
tion faci?ities allow obtaining specific versions of the SRV with regard to the
configuration of available hardware, the configuration of the operating system ver-
sion used and the features of the functional purpose of tne process control system.
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Chapter 8. Functional Characteristics of YeS EVM-2 Models
8.1. The YeS-1015 Computer
With a throughput of 19000-21000 instructions/second, the YeS-1015 computer is th~
smallest model in the YeS EVM-2 family. It is intended for use in batch processir~g
and the interactive mode in traditional data processing systems. This computer is
also used in rail transport management, enterprise management, in information sys-
tems for resource management, in power engineering, in executing commercial, bank-
ing and financial operations, in various data bank systems and in training.
In accordance with the YeS EVM-2 principles of operation, the YeS-1015 computer
is compatible with YeS EVM-1 models and realizes: ~
extended precision floating-point operations;
f acilities for organization of virtual storage with a 16M-byte capacity;
storage protection facilities;
extended facilities for processing of machine errors;
- monitor program svpport facilities;
program event recording facilities; and
microdiagnostic facilities.
A structural feature of the YeS-1015 is the connection to a comm~n bus of standa-
lone processors that operate concurrently and implement the principle of decen-
tralized data processing. Communication between the standalone processors that
make up the CPU is effected by using simple and easily interpreted standard mes-
sages. The CPU also includes the main storage unit; display console (operator con-
sole), and three types of standalone processors oriented to execution of different
functions: instruction processing (UEP), input/output (IOP) and service processor
(RAP).
The operator console consist~ of the YeS-7168 display with 16 lines of 56 charac-
ters per line and the YeS-7186 matrix printer with a printing rate of 180 charac-
ers per second [cps] with 132 characters per line.
The instruction processing processor:
fetches data from main storage;
decodes instructions;
- executes arithmetic and logic operations;
executes interruptions ;
unpacks IO instructions and starts the operation of the IO processor.
The internal storage of the instruction processor is made up of general, floating-
point and control registers. Processor cycle time is 550 ns.
Up to four IO processors that execute different functions may be used in the CPU.
The first processor controls the directly connected YeS-7184 printer and IO peri-
pherals through the multiplexer channel. The second processor controls the direct-
- ly connected Ye S-5061 disks, the maximum number of which is 8. The third processor
1 Here and from now on, computer throughput is indicated for statistical mixes
- for solving scientific and technical problems.
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is the selector channel; up to eight YeS-5017 units are connected to it through
a YeS-5517 control unit. And finally, the fourth processor for IO effects a
direct link to a data teleprocessing system.
Cycle time of the IO processor is the same as the instruction and service pro-
cessors, 555 ns.
The service processor checks the operation of all CPU functions and supports:
logging and analysis of errors, input of microprograms and computer-operator
communication.
Main storage with a maximum capacity of 256K bytes is built with integrated cir-
cuits. Cycle time is 1 microsecond, access width is 2 bytes. An autonomous unit,
the storage control unit (OTV), ia provided to organize access to main storage
within the CPU. ~
YeS-1015 compu*_er sof tware includes the YeS DOS-3 operating system that supports
the YeS EVM-2 capabilities and a set of maintenance routines (KPTO) that includes
not the traditional software, but a system of microdiagnostics that performs the
following functions:
correction of errors occurring during operation;
logging of malfunctions in automatic mode;
offline testing of the machine during preventive maintenance; and
localization of defective units and assemblies
The standard peripheral composition for the YeS-1015 and the other YeS EVM-2 models
is given in table 30.
8.2. T'he YeS-1025 Computer
With a throughput of 35000-50000 instructions/second, the YeS-1025 is the second
member of the family of program compatible YeS EVM-2 machines and belonga to the
class of small machines. It is oriented to solving a broad range of acientific and
technical, economic and special problems both in the standalone mode and in inf~r-
. mation processing systems, including real-time and shared use systems. The YeS-
1025 can also be used in large computer systems as a slave computer for preliminary
processing of information. The sphere of application of the YeS-1025 is governed
by the features of its structure:
higher technical and economic indicators and primarily of the throughput/cost raCio
than the YeS-1021 computer because of a more flexible and efficient internal
logical structure;
organization df vir~ual storage with a 16M-byte capacity;
connection of a broad complex of external devices;
direct connection of high-capacity external storage units; and
an easy and convenient method of connection t~ data teleprocessing systems and
to other computers.
The YeS-1025 computer processor is similar in structure to that of the YeS-1015.
It is designed in exactly the same way for decentralization of execution of func-
tions that permit processing of arithmetic and logic instructions concurrently with
IO of information from peripherals, with operationa from the operator console and
with diagnostic procedures. In accordance with this, the YeS-1025 processor is
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made up of six autonomous functionally complete modules connected to a common bus.
Communication between any two modules is effected by using special interface
adapters built into each of them. Since the modules use a cort~mon bus with time
sharing, the bus is physically divided in two to increase throughput. Also, one-
third of the bus is used for asynchronaus transmission of signals �r~m the service

;;ry module to the others and vice versa for convenience of diagnostics.
The YeS-2025 processor includes the following basic modules: oper a ting, Rervice,
control, main storage, disk and multiplexer.
Atiditional facilit3.es may be included in the proceasor as a function of the
application:
a second main storage module;
a tape module; and
a switching mo~uie.
Each of these modules uses micronrogram control and a set of internal registers to
enahle execution of the functions imposed on it.
The operating module realizes execution of the YeS EVM-2 universal instruction set,
including the standard set of operations, operations with decimal numbers, opera-
tions wi~h floating point, conventional and extended precision, operations for
translation of addresses and conditional exchange, and operations enabling opera-
tion with time facilities and storage protection keys.
As noted earlieL , a ma jor feature of the YeS EVM-2 models is the availability of a
developed diagnostic sys':em that enables detection and rapid localization (and in
some cases even correction of data) of faulta due to malfunctiona and failures
_ occurring during computer operations. In this respect, the YeS-1025 is no excep-
tion and makes use of both sof tware and special hardware for diagno s tics. The
software is intended mainly for diagnosing IO devices and disk and tape storage
uni.ts. The hardware includes a system of links that enable direct writing and
reading of information in each module or its major parts, and a spec ial service
module for initial recording of microprograms, control of procedures of micro-
si~nificance and processing of information on malfunctions. nrirdware facilities
for the YeS-1025 computer diagnostic syatem also include the operator coneole with
J the YeS-4063 alphanumeric 3isplay, the YeS-7934 serial printer and the YeS-5074 or
YeS-5075 flo~py disk storage unit. In the grocess of computer functioning, infor-
mation on malfunctions is accumulated on floppy disk and can be output on the dis-
play or printer f or expeditious analysis of the reasons for the f a ilures and mal-
functions. Also stored on floppy disks is information on the causes of the most
typical malfunctions that have ever occurred at a user site, which is essentially
a set of diagnostic tests that permit rapid and efficient diacovery and correction
of damage to computer functioning.
The control unit in the YeS--2025 processor is essentially a storage control unit
that performs all the encessary functions on organizing work with main storage and
oigsnizing access ra datr3.
The main storage module is built with inetgrated circuits with a capacity of 1024
bits per package. One module holds 128K bytes. Using an additional storage
, module permits obtaining the maximiim posaible main storage, 2561C bytes, for the
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YeS-1025 computer. Main storage read cycle is 500 ns; write cycle ia 750 ns, and
width is 72 bits.
The disk module is an adapter for dii~ct connection of up to four disk storage
units, just as the tape module iG used for direct connection of tape storage units.
The multiplexer module is designed to connect IO peripherals to a computer by means
of the standard IO interface. Throughput of the multiplexer module in the burst
mode is 29K bytes/second and in the multiplexer mode, 24K bytes/second. The numLer
of multiplexer subchannels is 32 with maximum throughput for a one-byte interface
of 29K bytes/second. Total throughput of the multiplexer module is 1.OM bytesJ
second.
A distinctive feature in the structure of the YeS-1025 computer processor is the
presence of a switching module that has 16 lines for connecting both terminal
equipment for a data teleprocessing system and small computers in the SM EVM series.
8.3. Tt~e YeS-1035 Computer
_ The YeS-1035 computer has a throughput rate of 140,000-160,000 instructiona~second
and is in the medium class. It is inter~ded for solving a broad range of scientific
and technical, econcmic and special problems in shared-use batch proceseing, tele-
processing and real-time systems as well as in areas that require a general-purpose
- computer with large computing capacity and a broad set of high-speed peripherals.
This model can be used in small and medium-size computer centers and s~t the lower
~ and mid levels ot automated management systems. It implements the universal seY. of
YeS EVM instructions and is program compatibl~ with other Unified System models.
Emulation facilities provide program compatibili_ty with the Minsk-32 computer.
By connecting the YeS-8371 communications processor to the computer, a general-
purpose computer complex can be created for shared use and teleprocessing of infor-
mation. By usin;; the special processor for array computations, a computer complex
can be obtained for scientific studies oriented to array processing of large data
files.
The processor (the YeS-2635 ) is the central unit in the YeS-1035 computer; it is
ineended for executing arithmetic and logic operatione, organizing reference to
main storage, organizing data exchnage betwe~n main storage and channels, control-
ling the sequence of instruction execution, actions during interruptions, operation
of time readout facilities , initial program loading and operation of IO devices~
The processor processes numbers written in binary code, fixed-length floating-point
numbers, variable-length decimal numbers, and fixed and variable-length logic
information.
This processor consists of the central processor (the YeS-2435) with a byte-multi-
plexer and two selector channels, the YeS-3235 main storage unit and the XeS-0835
power supply.
This processor also has additional facilities: a channe~to~channel adapter
enabling joint operation of two YeS-1035 computers and permitting transfer of
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data files from one computer to another through selector channels; two aelector
channels or an integrated file adapter.
Control of ALU operation is microprogrammed and width is two bytes. Control is
effec ted by using reloadable storage of microprograms made with IC's with a cycle
of 200 ns, width of 32 bits and capacity up to 64K bytes. Microprograms are laaded
into storage from the conaole magnetic tape storage unit. If necessary, the user
can replace the microprograms kept in atorage. Automatic localization and indica-
tion of computer malfunctions is performed by using a special set of diagnostic
microprograms. Checking computer serviceability by using the microdiagnostic sys-
tem takes no more than 15 minutes.
When a reference is made to main storage or to microprogram stcrage, a correcting
code is generated, stored and used to analyze the validity of the data transmission.
If a single error emerges, the information is corrected.
If a malfunction occurs in the procesaor, control is passed to the microprogram for
retry; it restores the situation that preceded the malfunction and passes control
to the sector of the microprogram where the malfunction occurred. If the retry is
successful, normal computer operation continues and the error ia recorded in
storage for analysis.
The instruction set includes arithmetic instructions to procese f_loating-point
128-bit operands.
There are two versions of main atorage for the YeS-1035 computer: the YeS-3235
ferrite core unit and the YeS-3238 integrated microcircuit unit. The YeS-3235 main
storage unit has variable capacity: 256, 512 and 1024K bytes. Storage cycl~~ time
is 2 microseconds, access width is 72 bits and ac~esa time is 800 ns. The YeS-3238
is built with 4K-bit integrated circuits and has a capacity of 2M bytes. Storage
cycle time is 850 ns and access time is 650 ns.
The YeS-1035 computer IO channels (selector and byte-multiplexer) make use of pro-
cessor equipment for their operation, i.e. th~y are integrated. The selector chen-
nel enables connecting high-speed peripherals (external storage devices) to the
processor. The computer has two selector channels; up to 256 devices may be con-
nected to each channel. The byte-multiplexer channel operates with low-speed IO
devices. Up to 184 devices can be connected to a multiplexer channel.
The selector channeis may be operated in the block-multiplexer mode which permits
connecting up to 512 devices to the aelector channels.
In a multiplexer channel, the number of subchannels (number of connectable device~)
is governed by control storage size allocated to store channel control word~, i.e.
from 64 to 128.
Execution of IO instructions and data transmission ia effected by multiplexer
channel microprograms.
Maximum throughput of the multipelxer channel is 30K bytes/second. �
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The mixed principle of control is used in the selector channels. IO instructions
are executed by selector channel microprograms, while data transmission between
main storage and channels is effected by hardware with partial use of CPU equip-
ment. Maximum rate of data transmission in the selector channel is 790K bytes/
second and total throughput of the channels is 1.2M bytes/second.
All basic conecpts of the YeS EVM-2 have been implemented in rhe YeS-1035 computer:
extended instruction set;
virtual storage;
l~lock-multiplexer mode of channel operation;
riultisystem facilities and time readout facilities;
program event recording;
~ provision of monitor programs;
extended precision floating point operations;
~ correcting codes for main storage; and
advanced microdiagnostic. procedures.
The YeS-1035 computer fe~~.ures Minsk-32 emulation facilitiea that permit use of the
large stock of application programs developed for that machine. These facilities
~ includ~:
facilities for emulating Minsk-32 programs;
facilities for translating programs in source languages; and
data transf er facilities.
Provision of Minsk-32 and YeS-1035 compatibility based on considerationa of econom-
ic effectiveness is implemented on two levels: program and program-microprogram
(emulation level).
_The expediency in using the program level of compatibility etema from the fact that
~ many Minsk-32 programs are written in the high-level programming languages and the
process of.their primary interpretation is not time criticul. Primary interpreta-
tion provides for the sequence af conversion, translation and execution.
The second compatibility level, emulation, is used for programs written in the
Minsk-32 machine language. Such programs make up a large part of the whole stock
of programs since they are most economical. Therefore, the emulation level is the
main and most efficient. Based on the great differences in data repreaentation and
formalization of computational processes and IO operations, in the second level of
compatibility, 68 percent of the inatruction set is covered by microprogram inter-
pretation and 32 percent by prog am. Program interpretation of Minsk-32 instruc-
tions is largely accounted for by interpretation of general extra codes for exchange
and extra codes for exchange with external devices. ?4icroprogram interpretation ia
propagated for both computational and IO operations.
IO emulation has been implemented for extern~l devices in the basic set for the
- Minsk-32 by using suitable analogs in the Ye5-1035 set of external devicea. In the
process, units designed to operate with the Minsk-32 or converted in advance for
use with the YeS-1035 may be used.
~ The YeS-1035 computer compatibility facilities provide emulation of the Minsk-32
computer with a 1.4-fold increase in throughput.
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8.4. The YeS-I045 Computer
The YeS-1045 is a general-purpose computer with medium throughput of 880,000 instruc-
tions/second; it is designed to solve a broad range of scientific and technical,
economic, informati~nal and special problems both in the standalone mode and in
information processing systems.
The universality of the YeS-1045 is provided by the balanced indicators of proces-
sor throughput, the universal instruction set, a unified method for connecting
various external devices and advanced software. The logical structure of this com-
puter meets the requirements imposed on the logical structure of the YeS EVM-2.
The YeS-1045 computer is program compatible with Ye:i EVM-1 models (in the basic
control mode) and with other YeS EVM-2 models from b~:low upwards.
The structure of the YeS-1G45 computer permits organizing a dual processor system
based on two computers and mutlimachine systems, ensuring in the proceea high
throughput, reliability and viability.
Dual processor systems are organized by creating a common extent of main (up to 8M
bytes) and extPrnal storage for both proceseors operating under the control of a
- single operating system.
Multimachine systems dre created by complexing at the level of channels by using
channel-to-channei adapters, direct control facilities and a common extent of exter-
nal storage; each computer operates under control of its own operating system.
In the YeS-1045 computer, the capability has been provided through a special inter-
face for connecting an array processor developed to substantially raise the effi-
ciency of solving problems on pattern recognition, processing of geophysical data,
etc.
A special access method under control of the OS 6.1 operating system allows the
user to solve problems with the use of high-level languages.
The array processor together with the power supply and engineer panel is placed
in a standard YeS EVM rack.
The YeS-1045 computer hardware has been developed on the modular principle, which
_ allows a user to design specialized compuer systems corresponding to the purpose
of the system befng created to the greates*_ extent without making any changes to
the stri~cture and design of the machine.
Standard YeS-1045 computer facilities included in any system configuration created
by a user include:
the processor;
facilities for processing i.n the basic and extended control modes;
the YeS EVM-1 universal instruction set and the majority of the new YeS EVM-2
instructions;
virtual storage;
instruction retry facilities;
monitor facilities;
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program event recording;
high-speed 8K-byte buffer storage;
byte-multiplexer channel; and
five block-multiplexer channels.
Optional YeS-1045 computer facilitiea include:
~ the array processor;
direct control facilities;
facilities for organizing a dual processor system;
extznsion of main storage to 4M bytes by adding new 1M-byte blocks;
two channel-to-channel adapters;
logic repeater; and
configuration panel.
New configurations of the YeS-1045 computer may be derived by adding specific
additional facilities to the basic machine compoeition or by connecting a broad ~
range of external storage units, IO devices or teleprocessing devices to the IO
_ channels through the standard interface.
The central part of the YeS-1045 computer ia placed in three standard YeS EVM
racks (processor and IO channels, main storage and computer power aupply). Also
placed in the power supply rack are the channel-to-channel adapters, logic
repeater and their power supply.
. When connecting main storage built with integrated circuita, the standard set for
the YeS-1045 is palced in two standard YeS EVM racks.
The CPU for the YeS-1045 computer includes the following units: microprogram con-
trol, instruction fetching and interruption servicing, arithmetic and logic,
" storage control, checking and diagnostics, and the control panel.
Machine control storage consists of two parts:
permanent, designed to store procesaor and IO channel control microprograms, and
loadable, for storing microprograms, console operation~, diagnostic microprograms
and the microprograms for array proceseor access to the YeS-1045 computer. The
microprograms are toaded from the console magnetic tape storage unit, the ML-45
cassette type.
A special high-speed unit, an accelerator, is included in the processor to speed
up execution of certain "long" arithmetic and logic operations. Executed in the
accelerator are ali multiplication operations, tranalations into tihe binary and
decimal systems for packing and unpacking, all primary shitt operations and some
_ move and store operations, 25 operationa in all.
The YeS-1045 computer processor has ,.he following technical parameters:
duration of machine step, na 120
. control principle hardware-microprogram
~.~ridth of arithmetic unit, bita 32
number of overlap levels 2
The processor include~ different types of integrated circuit atorage: control, buf-
fer, local protection key storage, etc. The YeS-3206 main atorage unit, designed
_ to receive, store and output information, is used as main storage in the YeS-1045.
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Ferrite cores are used to hold the information. The storage unit is built on the
principle of the 2.SD acceas. Structurally, the unit is made on the base of a
standard rack, in which are placed the control unit, storage modules (with 64K
bytes in each) and power supply system. There are f acilities for protecting main
storage for store and read.
The storage interface permits effecting a bua increment of capacity (up to 4M bytes)
of main storage by adding new OP [storage) modules.
'The technical characteristics of the main atorage unit made with ferrite cores are:
capacity, megabytes 1.0
cycle time, microseconds 1.25
access time, microseconds 0.65
width, bytes 8 .
ThP YeS-3267 main storage unit made with in.tegra�ed circuits has the following
technical parameters (4K bits to a package):
capacity, megabytes 1.0
cycle time, ns 850
access time, ns 650
width, bytes S
A rather advanced checking 1nd diagnostic system is provided in the YeS-1045 compu-
ter to support high operating reliability and repairability.
A lar~e share of the equipment (on the order of 95 percent) is hardwate checked by
self-checking circuits, which permits detecting malfunctions quite cloae to the
- time and place they appear.
The YeS-1045 computer recovery facilities provide the capability of continuing or
recov~ering the computing process when a random failure occurs. This is done either
by correction of single errors in main storage or by hardware-microprogram retry of
the 179 CPU instructions, in which the error occurred. Upon successful retry, nor-
mal operation continues, b~t the error is logged for subsequent analysis. Other-
wise, automatic retry of the situation that cauaed the malfunction is performed up
to eight times. An unsuccessful execution of all retry attempta causes storing of
the computer etatus and an interruption from the check circuits.
The high resolution of the diagnostics that enables localization of the malfunction
with an average precision of down to two-three TEZ~s [standard exchange cards] is
achieved because of the use of the microdiagnostic procedures with a capacity to
1M byte, the programs of which are stored on the ML-45 tape storage unit. This
provides the capability of checking the main assemblies of the central devicea
within 10-~2 minutes.
The diagnostic system also includes the autotester apparatus designed to check
TEZ~s and permitting localization of a malfunction within individual cards with a
precision down to one or more microcircuite. A raalfunctioning element on a card
is localized by using diagnostic tables and a special tester, and rapid recovery of
computer serviceability is enabled after a failure. Provided in the YeS-1045 com-
puter is the special unit for checking and diagnostics of the power supply (ASKD~)
that permits performing an auL~omatic change of voltages of power sources, as well
as automatic checking of the status of power sources, fane, thermosensors, etc.
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In the YeS-1045 computer, IO is performed through the byte-multiplexer and block-
- multiplexer channels. The combined hardware-micorprogram method is used to control
the IO channels. Data is exchanged through the IO interface under control of the
channel hardware facilities and is executed concurrently with processor operation.
Data exchange between the IO channels and main storage and processing of control
information are performed by processor f.cilities under microprogram control. The
IO channels share the apparatus of control storage with the CPU.
Up to two byte-multiplexer and five block-multiplexer channels may be connected to
the YeS-1045 computer. The byte-multiplexer channel can operate in the multiplexer
or burst modes at a data tranemission rate of 40K and 12K bytes/second, respective-
ly, and has up to 256 subchannels.
Throughput of the block-multiple:cer channels as a function of their number varies
from 0.5ri to 1.5M bytes/second, and total throughput of all IO channels is SM bytes
per second.
Up tc. 10 control units at a distance of 60 m may be physically connected to each
channel. The special unit, the logic repeater, ia included in the machine to in-
crease the number (to 19) of devices connectable to the byte-multiplexer channel.
8.5. The YeS-1055 Computer
~
The YeS-1055 general-purpose computer has a medium throughput of 450,000 instruc-
tions/second and is designed to solve a broad range of scientific and technical,
economic and special problems both in the standalone mode and in an information
processing system, including real-time and shared-uae systems.
The YeS-1055 computer has most of the properties of the YeS EVM-2 principles of
operation, tre main ones of which include:
the universal instruction set, except the four multiprocessing instructiona (SPX,
SIGP, STAP and STPX);
the basic and extended control modes;
organization of virtual storage by hardware fa~ilities in the processor and
channels in the aggregate with program support of the operating system;
the block-multiplexer mode of channel operatlon and the universal interface for
channel communication with peripheral control units;
calls of special-purpose interruptions during execution of programs through use of
the monitor facilities that permit acquisition, analys's and logging of information
on the status of program processing at the time of interruption;
logging of events in a program on branches, changeA in contents of general
registers and main storage;
correction of single errora by uaing correcting codes during reference to main
storage;
obtaining information on the time of processes and analysis of their status by
using the time-of-day clock, comparater and CPU timer;
analysis of the status of the internal logic circuits in the CPU and channels by
using microdiagnostic procedures;
instruction retry when an error occurs during inatruction execution;
extended precision floating point operations; and
operand placement on an arbitrary byte~boundary.
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The standard facilities in the logic structure of the YeS-1055 computer are: the
processor, control console, byte-multiplexer and block-multiplexer channels.
Optional facilities for the logic structure of the YeS-1055 computer are:
a second byte-multiplexer channel;
- two block-multiplexer channels;
array processor;
direct control facilities;
channel-to-channel adapter; and
facilities for multiprocessor operation.
The YeS-2b55 CPU has all the necessary function units for unpacking and executing
instructions and controlling the computing process; it also has all the facilities
for raising the efficiency of computations and extending system capabilitiea in
accordance with the YeS EVM principles of operation. It meets the requirementa
for interactive operation with a large number of subscribers and common use of
data files.
The principle of microprogram control is implemented in the processor. Control
storage has a capacity of 8K instructions with 64 bits each, cycle time of 380 ns
and access time of 140 ns. In the main, storage of microprograms is performed as
a storage unit with permanent information. Only part of the microprogram storage
is r.eloadable, the part used by the system for error correction.
The YeS-1055 computer CPU includes the processor proper, main storage and the IO
channels.
The YeS-3204 main storage unit is made of MOS IC's with a 1024 x 1 organization.
Used in the struc:ture of main storage is the method qf dividing the storage into
four independent logic modules, accesa to which si effected by overlap according to
the principle of address inetrleaving, which enabl~a the specified parameters of
model throughput. Main starage has two main versions: 1024K bytes and the maximum
of 2028K bytes. Storage cycle time is 1140 ns; access width is 8 bytes. Facilities
are provided to correct single and identify double errors in main storage, and to
protect storage for reading and atoring. Using the virtual principle allowa
increasing the efficiency of use of main storage.
The YeS-1055 computer IO system has byte- and block-multiplexer channels. The lat-
ter can also be used in the selector mode. Up to four block- and two byte-multi-
plexer IO channels can be connected. One byte- and two block-multiplexer channels
are used in the main design.
The byte-multiplexer channel can operate in the multiplexer and burst modes at a
data transmission rate of 40K and 1M bytes/second, respectively, and has up to 256
subchannels. The block-multiplexer channel has a data transmiasion rate of 1.SM or
3M bytes/second for the one-byte or two-b~te interfacea, respectively. The total
throughput of all IO channels is 4-5M bytes per second.
The channel equipment contains a special unit to check the operation of the IO
channels. This is a feature of the YeS-1055 computer. The channel check unit sim-
ulatea operation of peripheral equipment arid communication interfaces, which on the
one hand, f.acilitates debugging and checking of the IO channels, and on the other,
permits rapid and convenient localization of a malfunction that has occurred. -
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A supplementary unit for the YeS-2655 processor is the array module; it is not a
functionally independent device and can be used only in the YeS-1055 computer.
This is also a model feature. In contrast to the general method of connecting an
array processor as an IO channel (see chapter 1), the array module is connected
directly to the YeS-2655 processor as an executive resource. Structurally, it is
made so that it can be connected to a machine alXeady inatalled.
The array module is a specialized executive unit designed for rapid calculation of
floating point operations used in array computations and Fourier transforms. In
the process, because of parallel execution of different processes, a high rate of
computation ia achieved; depending on the size of fields, density of instruction
stream and algorithm used, it may be 10-50 fol.d greater than that achieved in
executing these operations in the arithmetic unit with floating point.
Connecting the array module directly to the procesaor opens the fundamental capa-
bility of organizing its operation concurrently with the operation of the executive
units in the pr~cessor. This raises considerably the computation rate in the pro-
cessor. However, specific realization of this operation involves modifying the
operating system and considerable difficulties in control of the computer processor.
Connecting the array procesaor through a atandard IO interface doea not provide to
the full extent overlap of its operation with the operation of the arithmetic unit
in the processor, but in return allows using standard control procedures. A quanti-
tative evaluation of the effectiveness of the first and second methods crf connection
has not yet been exhaustively studied; therefore, the operating experience of the
YeS-1055 computer wilZ be useful in solving this problem and aelecting the direction
of development of specialized ;~rocessors.
In the YeS-1055 computer, much attention has been paid to development of system con-
trol facilities and to the improvement of convenience in ~peration interaction with
the computer. The YeS-7069 operator display console, a structurally independent
unit, is used for these purposes. It is used both in controlling the syatem and in
servicing it. It contains all the necessary controls and facilities for maintenance
and display. The IO unit is a display with light pen and keyboard. The screen
displays 25 lines of 80 characters each. The keyboard is used to input the neces-
sary information and specify the control function; it has 26 alpha, 10 numeric and
27 special characters. One version of the keyboard also includes 20 Cyrillic char-
acters. A high rate of communication is achieved through connecting a aerial
printer to copy the information output to the display. The serial printer
operates at a rate of 45 cps.
The YeS-7069 op~rator console is connected to the processor by means of standard
and special interfaces. The standard IO interface allows connect:.ng the YeS-706y
unit to any YeS EVM-1 or EVM-2 model as an operator console. The special interface
is designed to be used only with the YeS-1055 computer for display out~ut and per-
forming diagnostic procedures. The CPU Allows connection of two YeS-7069 units.
The second unit is supplied at user option. The YeS-7069 operator console has high
esthetic and operating characteristics en~ur.ing high comfort in computer servicing.
A peripheral feature for the YeS-1055 computer is the use of the YeS-7602 micro-
fiche output unit. Output rate is 5 microfiche/minute, which is about 250,000
characters/minute. Lettering of each microfiche with visually readable microtype
is possible. The operating system supports operation of this unit.
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Another feature of the YeS-1055 computer is the availability of YeS DOS emulation
facilities. These facilities allow operation of YeS DOS under control of the YeS
OS control program. In other words, these facilities allow execution of programs,
written by the user for YeS DOS, under control of the YeS OS operating system.
8.6. The YeS-1060 Computer
The YeS-1060 general-purpose computer has a high throughput of 1 million instruc=
tions per second. The concepts incorporated in the design of the YeS-1060 assume
its use in major computer centers ar.id automated management systems for solving a
broad range of scientific and technical, plann-economic, informational and special
problems in the modes of local ane remote processing ~f information. Capabilities
of versatile application of this computer are provided by the universal instruction
set, large aize of main and external etorat~e, high-speed IO channels and broad set
of peripherals. The availability of these facilities as well as the advanced sys-
tem of i4lterruptions, facilities for time readout and main storage protection
allow efficient use of the YeS-1060 computer in the multiprogramming, time-sharing
and interactive modes.
The YeS-1060 computer has all the capabilities of the YeS EVM-1 and realizea all
the new concepts incorporated in the logic structure of the YeS EVM-2: -
extended instruction set;
extended control mode in the processor;
dynamic address translation in the processor;
indirect data addressing in c.he channels;
block-multiplexer mode of channel operation;
new multiprocessor facilities;
extended precision floating point operations;
extended interruption system;
new facilities for time readout;
provision of monitor programs;
program event recording; and
increase in efficiency of checking and diagnostic facilities.
The architectural and structural features of the YeS-1060 com~uter are aimed at
raising throughput, reliability and efficiency of use and cre3ting simplicity and
convenience in servicing.
The YeS-2060 processor provides for fetching of data from main storage, controlli~ng
the sequence of instruction execution, organizing interruptions, initiating opera-
tion of IO channels and implementing functions for checkinb and diagnostics. The
processor includea: central control unit, arithemtic and logic unit, storage con-
trol unit, chPCking and diagnostics unit and the control console.
The central control unit is designed to fetch, unpack and buffer instructions, con-
trol the operation of the arithmetic unit and execute system functions. This device
includes the units of instructions, data addresses, microprogram control, interrup-
tions, timers and external communications unit.
The arithmetic and logic unit is used to execute arithmetic and logic operations
and generate operand addresses. It includes: general and floating point registers
and a parallel adder. An optional unit is a fast multiplier.
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The storage control unit is designed for processor and IO channel communication
with main storage and includes main buffer storage, dynamic address translation
facilities, channel buffer unit and storage adapter.
The checking and diagnostics unit provides for control of the proceasor indication
system, control of hRrdware checking circuits and check interruptions, recoraing
processor status, hardware retry of instructions after detection of an error,
execution of the functior.s of the DIAGNOSE instruction, loading of microprograms
into control storage, execution of microdiagnostic tests for localization of mal-
functions and control of the synchr~nization system.
The control cansole is intended for manual control and display of computer statua
during maintenance and operation. '
High speed of the processor is achieved through organization of rapid access to
data, overlap of execution of operations and use of efficient computation algorithms.
The 81C-byte main buffer storage is built with fast int~.grated circuits. I.t is used
to match processor operation time with main storage time parameters. Data ia ex-
changed between main storage and the buffer in 32-byte blocka (pages). Four-way
interleaving of addresses is uaed to apeed up exchange. The buffer storage opera-
ting cycle, equal to the pr.ocessor operating cycle, eneurea rapid preparation of
instructions and operands. Using an efficient algorithm for replacement of infor-
mation in buffer storage combined with the use of a channel buffer permite
reducing conflicts in the processor.
Efficient algorithms are used in the arithmetic unit. This makes it possible to
combine a high rate of execution of operations with reasonable outlays for equip-
ment. Using a special u..~.t for fast multiplication has made it possible to raise
the speed of execution of multiply operations 2-2.5 fold.
Instruction processing in the processar has three atages:
instruction fetching from ~he buffer, unpacking and generating of the operand
addre~s;
refFrence to storage and fetching of data;
execution of the operation and storage of the result. ~
In accordance with this, several instructions, at different levels of processing,
are executed at the same time in the processor. Operation of the overlap levels
ie strictly synchronized in time, which simplifiea organzation of control. Con-
currently with processing of the inatructic~ns, the address of the next aector of
the program is generated and instructions are read fr~om atoraye to the buffer
register.
Besides the purely logic capabilities of the computer, the simplicity and conveni-
ence oF operation of the machine and rapid location of malfunction3 ane very impor-
tant. Juring structure development, the designer almost always solves a compromise
problem: achieving high throughput with reasonable computer complexity. In the
YeS-1060 carnputer, the solution to these problems is shaped by:
the introduction of microprogram contr~l. not only in the arithmetic unit, but also
in the central control unit; and
the introduction of an efficient checking and diagnostics system.
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Microprograms control instruction processing in the processor, execution of opera-
tions and interruption processing. The writable control storage is built with
integrated circuits and consists of two units: basic and control, which are
accessed by independent addresses. The main unit of microprogram storage holds
4096 words of 144 bits each; the control unit holds 512 words of 24 bits each.
The microprograms stored in the control unit determine the sequence of processing
stages and processor steps in instruction execution and also the degree of overlap
of the processing stages. They also interrupt the sequence of the computing pro-
cess when conflict situations, outside intervention or interrupt requests occur.
The microprograms in the basic unit of control storage determine the specific ac- ~
tiona needed in the process of preparing instructi.ons and executing operations and
interruptions.
In the YeS-2060 processor, all units for central control and the arithmetic unit
operate under microprogram control. The unit of system facilities for control and
the checking and diagnostic unit have mixed hardware-microprogram control. This
wideapread introduction of microprogram control is a feature and advantage at the
- same time of the YeS-1060 computer, since until recently, this principle was not
widely used for high-throughput ma:.hines.
The high requirements for operating reliability in the YeS-1060 are mPt by an
advanced checking and diagnostic system. This system includes hardware and software
facilities thaL interact both in the main operating mode and in the maintenance
mode.
The hardware facilities effect online checking of processed information, eliminati.on
of the consequences of failures by retrying up to eight times instructions and
sections of programs in the processor, retry of IO procedures in channels, and
correction of single errors in main sT.orage. To analyze the causes of failures,
processor facilities allow fixing in main storage the status of equipment when an
error occurs.
Under the conditions of preventive maintenance and servicing, it is possible to
diagnose eqiiipment by using special hardware facilities and a set of test prograr?s
and by executing microdi~gnostic procedures to locate malfunctions.. Online tests
for checking external devices in the process of executing user tasks allow co~i-
tinual tracking of the status of external devices and when necessary deciding
whether or not to use them in the system. 'I"nese capabilities combined with the
operating system recovery facilities create the prerequiaiLes foY efficient opera-
tion of the YeS-1060 computer at the user site. This ia also facilitated by the
" software system that includes the lateet vereion of YeS OS, application program
_ packages that extend operating system capabilities, and epplic~tion program
packages for various purposes.
YeS-1060 system facilities permit combining the resources of aeveral computers to
- execute a common task, ensuring in the process high throughput and reliability.
Cammunication between the individual computers can be effected at the level of
any system component by using specific multiprocessor facilities:
at the level of channels by using a channel-to-char?nel adapter;
at the level of peripheral control units by using a two-channel switch;
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at the level of the basic main storage;
at the processor level by using direct control facilities.
The facilities that ensure efficiency in system application~of the computer allow
creating powerful systems and multimachir~e computer complexes based on the Ye9-1060.
The YeS-1060 computer IO channels are physically independent standalone units that
are connected to the processor and profit by simultaneous access to main storage.
Information transfer rate depends substantially on the number and type of channels
usPd. Up to seven IO channels, supporting the byte and block-multiplexer and
selector modes of operation, may be conencted to the YeS-1060 computer processor.
The block-multiplexer channels have the two-byte interf ace which allows connecting
devices distinguished by a high data transfer rate.
To operate the computer in the virtual storage mode, indirect addressing facilities
have been incorporated in the channel to complement the address tranelation
facilities in the processor. Hardware retry of instructions in a channel has also
been provided. The availability in the channel of facilities to log channel status
makes it possible to recover system operation by program methods when errors occur
in an IO procedure.
Structurally, the YeS-1060 computer channels are made in the form of YeS-4001 units
that include four functional channels: one byte- and three block-multiplexer.
The block-multiplQxer channel can operate in the mode of a selector channel. The
block-multiplexer channels are controlled by hardware facilities; the principle of
- microprogram control is used for the byte-multiplexer channel.
The byte-multiplexer channel consists of the main multiplexer channel and four
selector subchannels. Throughput of a selector subchannel is SOOK bytes/s. The
integrated throughput of the byte-multiplexer channel is 1.5M bytes/s. The block-
multiplexer channel has a throughput of 1.SM bytes/s with the one-byte interface
and 3M bytes/s with the two-byte interf ace.
There are two versions of main storage for the YeS-1060 computer: ferrite cores
and integrated circuits. The ferrite-core main atorage unit has a capacity from
2M to 8M bytes, reference cycle of 1.25 microsecond and access time of 0.8 micro-
second. To speed up access to main storage, it- entire extent is divided into
four independent logical blocks. The YeS-3206 main storage unit is built on the
modular principle and contains one megabyte per rack. The power supply ia placed
in the same rack. Structure, circuit and design solutions for the YeS-3206 unit
have permitted reducing the bulk and raising the density of equipment packaging
compared to the main storage unit in the YeS-1050 computer which uses the same
ferrite cores.
The YeS-3266 semiconductor main storag~: unit for th~ YeS-1060 computer is made of
dynamic inetgrated circuits with 16K bits per package. It has the same interface
for communication with the processor and the same organization as the YeS-3206
unit. Capacity of the YeS-3266 unit is 8M bytes, cycle time is 680 ns and
access time is 520 ns.
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8.7. The YeS-1065 Comnur.er
_ With a throughput of f our to five million instructions per second, the YeS-1065
- computer is the top model in the YeS EVM-2. It is intended for application in
major computer centers and large data processing systems. This computer implemente
all data processing modes and uses all the architectural ar.d logic capabilities
provided in the YeS EVM-2. The main quality of the computer, high throughput,
predetermines the features of its application and the features of the structural
_ implementation.
First of all, the YeS-1065 model is a general-purpoae computer. In these terms, it
has to have the properties of universality and provide the capability of implement-
- ing the most varied classes of algorithms for user tasks. At the same time, it has
- to have the properties of a special system application. In these terms, the comp,i-
ter must have the characteristic features of an open systPm that allow new problem-
oriented devices to be included in it~ makeup. Considering this, one can formulate
the basic properties of the YeS-1065 computer architecture.
l. Struct~iral solutions are aimed at achieving the maximum rate of execution of a
random stLeam of instructions processing any data.
2. The computer structure ~rovides the capability of incorporaCing in its makeup
special processors to increase the rate of proceseing in systems used to solve a
limited set of tasks. The purpose of these processors is to increase at least by
an order th2 rate of execution of individual functions most often encountered in
the computing process at a specific user site.
_ 3. There are advanced complexing facilities in the computer to enable creating
multiprocessor and multimachine complexes for a general increase in system computing
capacity.
_ A processor structure that can be described as one with common resources was chosen
for the YeS-1065 computer. This assumes the availability of several devices that
prepare instructions for execution, but. the execution of these instructiona is per-
formed in one operating device. Nevertheless, even with this structure, it is ex-
pected that special organizational steps are taken to reduce the processing time
at all stages of instruction preparation and execution.
To reduce the data fetching and storing stage in the YeS-1065 computer processor,
a 32K-byte main buffer storage unit is used; it operates at the rate of operation
execution in the executive units. Information ia exchanged between main storage
and the buffer in 32-byte blocks. An additional gain in the operating raLe at the
stage of storage reference is obtained because the results of operations are stored
only in buELer storage witt~out immediate duplication of them in main storage.
These results are stored in main storage when the least recently used information
- is destaged according to the standard discipline.
In the arithmetic and logic unit, a common resource in the YeS�-1065 computer pro-
cessor,operation execution time is reduced by the implementation of the fastest al-
gorithms for oepration execiition and by dividing this unit into several independent-
ly operating units (operating devices) for information processing. Each of these
devices is oriented to executing a group of instructions close in type. This
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simplifies the structure of the operating device, reduces the outlaya for imple-
- mentation of each device and permits reducing the time for execuL'ion of operations
compared tio that for a general-purpose device, although total costa of equipment
incr~ase.
Provided in the structure of the YeS-1065 computer processor are four independent
units for execution of operati.ons: fixed-point arithmetic, floating-point srithme-
tic, arithmetic for procesaing variable-length fields and decimal numbers and,
finally, the fast multiplier (divider). Access to these units is independent and
each may operate concurrently with the others. There is alsc the capability of
increasi.ng total capacity of the arithmetic unit by connecting both similar devices
and pr~blem-oriented devices for information proceasing.
- The toatl throughput of all operating devices is several tens of millions of opera-
tions per second and is considerably higher that the throughput of the storage con-
trol unit and the central control unit (instruction processor). In this case, it
1 is advisable to include in the processor structure several instruction proceasors
~ and divide buffer storage into independent sections with their own control and ac-
cess to main storage, i.e. to have several storage control units. The YeS-1065
computer processor has two storage control units, each with a 32K-byte buffer and
two instruction processors. Each instruction proceesor manages its instruction
stream to jointly maintain the required load on the arithmetic unit.
The structure with common resources, like the multiprocessor from the viewpoint of
the operating system, operating with a common extent of main etorage, has a number
o~ advantages. First of all, there is the effective increase in throughput and
provision for system viability. The computer continues functioning, though with
less throughput, when the separate devices fail. When a second arithmetic unit is
included in the computer, which is also a common reaource, the reliability of such
a computer system increases manifold. The inclusion of several instruction proces-
sors in the processor also simplifies organization of the structure of each. In
doing so, organizing a large number of overlap levels is avoided and the micro-
program principle of control is implemented.
In the computer with common resources, problem-oriented processor.s that raise the
overall machine throughput may be connected to all thE instruction processors with
the rights of a common resource. For this, they have to have an interface to the
instruction processor similar to the o~erating devices. For the instruction pro-
cessor, this connection of new devices boils down to implementing additional in-
- struction codes corresponding to the functions of the equipment being incorporated,
which is rather simple with the availability of microprogram control. Far more
complex is the software problem for these devicea that has to be solved individually
in each specific case.
The high rate qualities of the YeS-1065 computer processor are supported by a
powerful IO system, large main storage and service facilities.
Along with the traditional structural solutions, when the channels are rigidly
attached to the processor, the principle of floating channels (cross-call channels)
is used in the YeS-1065. The principle of the universal channel (IO multiplexer),
when execution of the functions of the byte- or block-multiplexer modes is enabled
by the use of microprogram control, has also been implemented. The channels are
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operationally adjusted for the required mode by reloading of microprogram storage.
AI1 the new functions of the YeS EVM-2 are performed in the YeS-1065 computer~
channels: indirect data addressing, IO operation retry and the two-byte interface.
Up to 16 channels, enabling total throughput of about 30M bytes/s, are connected to
the YeS-1065 computer. The main storage unit for this computer is made af 16i:-bit
microcircuits. The storage structure provides eight-way address interleaving.
Storage.size is 8M bytes, cycle time is 870 ns ,~nd access time is 650 ns.
A special processor for diagnostics and control, placed in the system control con-
sole, is used in the YeS-1065 computer. Its functions include performing diagnos-
tic procedures and maintaining direct contact with all central uaits in the pro-
cessor.
The YeS-1065 computer has an advanced error detection system, recovery facilities
~ to eliminate the effect of random failures through automatic retry of operations,
and error correction facilities using correcting codes. The microdiagnostic system
permits detecting malfuncCions during preventive maintenance and servicing. The
computer structural features govern the specific functiona of the conaole proce~sor:
tracking the functionitig conditions of the individual devices, acquisition and
an~alysis of information on failure~, disconnection of malfunctioning devices and
di+agnosis of them, and decision-making on system configuration. To do this, it has
large internal storage and the required set of its own external units.
Ccmclus ion
D~evelopment of the Unified System of Computers has made it possible to a conaider-
able extent to so~ve the problems of equipping the national economy of the countries
i.n the socialist community with computer facilities. The Unified System is now a
powerful, advanced system of computers in the socialist countries, has been
rassimil.ated into production and has found widespread application in various sectors
of the economy. Work on the Unified System has not ended with the development of
the first and second phases. The main directions of further development for the
Uciif ied Sys tem are :
increasing the efffectiveness (throughput/coat ratio) of computerQ with respect to
the YeS EVM-2;
improving technical parameters and operating characteristics;
increasing the effectiveness of introduction into various spheres of the national.
_ economy through functional specialization of hardware, use of programmable hardware,
built-in hardware control facilities and organizing data processing networks;
increasing further the effectiveness of stating and solving problems, including
solving the problem of usir~g a common information base and further introductien of
problem-oriented language facilities; and
reducing the hardware and software maintenance costs by providing high reliability,
and improving the mett-~ods of diagnostics and effective redundancy. The determining
feature of this development is the shift to the new technological design base
, using LSI circuitry which is predetermining the crear_ion of fourth~generation
computers.
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BIBLIOGRAPHY
1. "IBM SysS:em/360. Principles of Operation," ed. by V. S. Shtarkman, Nbscow,
Sovetskoye radio, 1969.
2. Gorbatsevich, S. L.; Makurochkin, V. G. and Cheremisinov, V. M., "Development
of the Main Units for External Storage in the Unified System of Computers," in
"Vychislitel'naya tekhnika sotsialisticheskikh stran" [Computer Technology of
the Socialist Countries], IVo 6, 1979.
3. (Jermain, K.), "Programming for the IBM/360," Moscow, Mir, 1973.
4. Larionov, A. M., ed., "Yedinaya sistema EVM" [Unified System of Computers],
Moscow, Statistika, 1975.
5. Zhimerin, D. G., "Application of Electronic Computer Technology in the
Socialist Countries," in "Computer Technolo~y of the Socialist Countries;'No 5,
Moscow, Statistika, 1979.
6. Katzan, H.,~ "Operating Systems," Moscow, Mir, 1976.
7. Katzan, H., "System/370 Computers," ed. by V. K. Levin and L.D. Raykov, Moscow,
Mir, 1974.
8. (Colin, A.), "Introduction to Operating Systems," ed. by V. V. Martynyuk,
Moscow, Mir, 1975.
9. Lapin, V. S., "Developrt~ant of Ccoperation in Data Teleprocessing. New Tasks,"
in "Computer Technology of the Socialist Countries," No 4, Moscow, Statistika,
1978.
10. Lapin, V. S. and Semenikhin, V.S., "Coricepts and Prospects for Development of
- Data Teleprocessing in the Unified System of Computers," in "Computer Technolo-
- gy of the Socialist Countries," No 1, Nbscow, Sratistika, 1977.
~ 11. Larionov, A. M.; Levin, V. K. et al., "Basic Principlea of Design and Technical
and Economic Characteristics of the Unified System of Computers ~YeS EVM),"
UPKAVLYAYUSHCHIYE SISTEMY I MASHINY, No 2(4), 1973.
12. Larionov, A. M.; Levin, V. K.; Przhiyalkovskiy, V. V. and Fateyev, A. Ye.,
"Technical and Op~rating Characteristica of Models in the Unified System of
Computers," UPRl~VLYAYUSHCHIYE SISTEMY I MASHINY, No 2(4), 1973.
13. Enslow, P. H., ed., "Multiprocessors and Parallel Processing," Moscow, Mir,1976.
14. Peledov, G. V. and Rayk.ov, L. D., "Vvedeniye v OS YeS EVM" [Introduction to
the OS for the Unified System of Computers], Moscow, Statistika, 1977.
].5. "IBM System/370. Principles of Operation," ed. by L. D. Raykov, MQSCOw, Mir,
1975.
16. Przhiyalkovskiy, V. V. and Lapin, V. S., "Architecture of Open Systems for Data
Teleprocessing Networks in the Unified System of Computers," AVTOMATIKA I
- VYCHISLITEL'NAYA TEKHNIKA, No 2, Riga, 1979.
_ 17. Przhiyalkovskiy, V. V., "Some Results from the Development of the Unified
System of Computers and Prospects for Further Development of It," in "Computer
Technology of the Socialist Countries," '~0 6, Moscow, Statistika, 1979.
- 194
FOR OFFIC[AL USE ONLY
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18. Pykhtin, A. Ya.; Gorelov, V. I. et al., "YeS-7920 Complexes: New Terminals
with Broad Capabilities," in "Computer technology of the Socialist Countries,"
No 4, Moscow, Statistika, 1978.
19. Rakovskiy, M. Ye., "Decades of Cooperation," in "Computer Technology of the
Socialist Countries," No 6, Moscow, Statistika, 1979.
' 20. Fateyev, A. Ye.; Roytman, A. I.; and Fateyeva, T. P., "Prikladnyye programmy
v sisteme matematicheskogo obespech.eniya YeS EVM" [Application Programs in the
Software System for the Unified System of Computers], Moscow, Statistika, 1978.
21. Larionov, A. M., ed., "Elektronnaya vychislitel'naya mashina F.VM YeS-1050"
[The YeS-1050 Electronic Computer], Moscow, Statistika, 1976.
COPYRIGHT: Izdatel'stvo "Statistika", 1980
8545
CSO: 8144/1811
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