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JPRS ID: 10656 TRANSLATION ANALOG AND DIGITAL INTEGRATED CIRCUITS BY SERGEY VIKTOROVICH YAKUBOVSKIY ET AL

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APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R000500084030-5 FOR OFF[CIAL USE ONLY - JPRS V10656~ 14 Ju~.~r 1982 Transiation ANALOG AND DIGITAL INTEGRATED CIRCUII'S ~ ~ BY SERGEY VIKTOROVICH YAKUBOVSKIY ET AL~ FB1$ FOREIGN BROADC~4ST INFOEiM,4TION SERVICE FOR OFFICIAL iTSE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 NOTE JPItS publications contain information primarily from fosLign newspapers, periodicals and books, but also from news a~;ency transmissions and broadcasts. Materials from foreign-l~ng~sge sources are translated; those from English-language sources are transcribed or reprinted, with the original phrasing and Q+ther characteristics retained. Aeadlines, editorial reports, and material enclosed in brackets are supplied by JPRS. Processing indica~mrs such as [Text] or [ExcerptJ in the first line of each item, or foltowing the last line of a brief, indicate how the original information was processed. Where no processing indicator is given, the infor- mation was summarized or extracted. Unfamiliar names rendered phonetically or transliterated are en~losed in parentheses. Words or names preceded by a ques- tion mark and enclosed in parentheses were not cle~r in the original but have been supplied as appropriate in context. Other unattributed paren~hetical notes with in the body of an _ itea originate with the source. Times within ~tems are as given by source. The contents of this publication in no way represent the poli- cies, vsews or at.titudes of the U.S. Government. ~ COPYRIGHT LAWS AND REGULATIONS GOVERI~TZNG OWNERSHIP OF MATERIALS REPRODUCED HEREIN REQUYRE THAT DISSEMINATION QF THIS PUBLICATION BE RESTRICTED FOR OFFICIAL USE ONLY. APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2047102109: CIA-RDP82-00850R400504080030-5 - FOR OFFiCtAL USE ONLY ~ JPRS L/10556 14 July 1982 ANALOG AND DIGITAL INTEGRATED CIRCUITS Moscow ANALOGOVYYE I TSIFRC~VYYE INTEGRAL'NYYE SKHEMY in Russian 1979 (signed to press 5 Apr 79) pp 1-335 [Book by Sergey Viktorovich Yakubovskiy, Nikolay Ars.en'yevich Barkanov, Boris Petrovich Kudryas~ov, Lev Ionovich Nissel'son, _ Mikhail Kikiforovich Topeshkin and Lyubov' Petrovna Chebotareva, - Izdatel's~vo "Sovetskoye Radio", 6~,OOa copies, 336 pages, UDC 621, 396] CONTENTS , Foreword 1 Chapter 1: Termi~cnology in Microelectronics and Classification of Tntegrated GYrcuits....~ 5 1.1. Introduction 5 1.2.i. Integrated Microcircuits, Ele,~ents, Co~onents........... 6 1.2.2. Design Elements 6 1.2.3. Simple and Complex IC......a 7 1.2.4, I~i_croassemblies and Micm~its 8 1.3. IC Q assification 9 1.4. System of ~nr~ditional IC Iksignations 10 Qzapter 2: Methods of Fabricating Integrated Circuits 18 2.1. Fi1m and Hybrid ~echnology 18 2.1.1. l~aterials for Hybrid IC's 19 2.1.2. Zhe Fabrication of the El~ements of Hqbrid IC'A........... 21 - a - [I - USSR - F - FOUO] FOR OFFICIAL USE QNLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR 4FFICIAL USE ONLY ~ 2.1.3. Making Electrical Connections in Hybrid IC's 24 2.2. Semiconductor Technology 24 2.2.1. Materials ~or the Companents of Semiconductor IC's � and ~eir Manufacture 26 2.2.2. ~ie Fabrication of Integrated Circuit Structures......... 29 2.2.3. Separating a Wafer Into (hips and Mounting the IC~s...... 34 ~ 2.2.4. Zhe Hermetic Sealing of IC Qlips 36 2.2.5. ~e Manufacture of IC Packages 37 ~ 2.3. Specific Features of the Technology of IC's With a High Level of Integration 40 Chapter 3: Digital Integrated Circuits 46 3.1. Desiggation and Application 46 3.2. Logic Functions Which Can Be Realized U~ing Digital IC's......... 46 3.3. Zhe Classificatj.on of Digital Integrated Circuits and ~eir Main Ele ctrical Parameters 51 3.4. Transistor-Transistor Logic C3.rcuits 55 3.4.1. ~e Ma~or Electrical Parameters of T'1'L Integrsted Circuits 7Q 3.4.2. ~ie Ftm ctional Complement of the TTL Seri~s�������������� 3.4.3. Some Specific Features of TTL Integrated Circuit 72 Applications 3.5. Emitter ~ioupled Transistor I.ogic Circuits.. . � � � � � � � � � � � � � � � � � � � � � 85 - 3.5.1. F~ctional Composition of the ESTL Series 88 3.5.2. Basic Electrical Parameters and Typ3.ca1 Ct?ara^zeristics 102 of IC Typ? ESTL 3.5.3. Certain Special Features in the Use of IC Type ESTL...... 106 3.6. Digital Integrated Circuits Based on M(JS Structures 115 3.6.1. ~e Operational Principle of Integrated Circuits Using p-~annel I~S Transistors 115 - b - FOR O~'I~'[CIAL US~ ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000540080034-5 FOR OFFICIAL USE ONLY 3.6.2. Static Circuits II~ing p-Cizannel 1~6 Transistors........... 120 3.6.3. Quasistatic and Dynamic GYrcuits 122 3.6.4. 1he OperaLional Principle of Complementary I~OS Tran~sistor Integrated Circuits 125 3.6.5. ~e Ma3or Series of Integratefl Circuits IIsing rDS Structures 128 3.7. integrated GYrcuits for Memories..... . L36 3.7.1. Memory ~lements Using ?~ipolar Structures 137 3.7.2. Memory Elements Using I~DS Structures 140 3.7.3. Memory El.ements Using (~DS Transistors........ . 141 ~ 3. 7.4 . S torage Ele~nen ts Employing MdOS S tructures . . . . . . . . . . . . . . 142 " 3.7.5. Storage Element~ Based on "Silicon on Sapphire" S tructures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~45 3.7.6. Storage Elements Based on New Materials 145 3� 7� 7. Major Series of Memory Unit Integrated Circuits and Zheir Ftmctional Structure 147 3� 8� Prospects for the Development of Di~tal Integrated GYrcuits. 150 3.8.1. Integrated Injection Logic 151 3.8.2. MOS Circuits With n-(hannels 152 3 . 9 . :~ii cro,:.alcul ato rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.10. Microprocessors 158 3.10.1. (haracteristics of a Microprocessor 160 3.10.2. Medium Operating Speed Microprocessor Configur,ation...... 163 3.10.3. I~roved Operating Speed Microprocessor Configuration.... 169 Qiapter 4: Arialog Integrated Circuits a.is 4.1. Function and Application...:.. . . 21$ 4.2. Operational A~lifiers 21$ y � C ~ , FOR OFF[ClAI. USE bNLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFIQAL USE ONLY 4.2.1. Jperational Amplifiers With a Z1wo Stage Structural ~onfiguration 225 4.2.2. Amplifiers With Field Effect Tra~sistors at the Input...... 233 4.2.3 Amplifiers With Super-Beta Transistors 234 4.2.4. 7,he 153UD5 High Precision Operational Amp].ifier............ 239 4.2.5. Hig~ Speecl Operational A~lifiers.. � 2~ 4.2.6. Micropvwe~r Operational Amplifiers 242 246 4. 3. Integrated Ci~.rcuit � Comparators . . . . . . . . . . . . . . . . 250 4.4. In tegrated Circuit AnaloB Multipliers ~ 263 4.5. Analog Integratecl Circuits for Radio Receiving Equipment......... 263 4.5.1. ?1ie Diffe:rential Amplifier 4.5.2. Low Frequency Amplifiers (UN'Qi) 265 4.5.3. Speciali�r.ed Integrated Circuits 270 4.5.4. IC's for the Construction of Selective Circuits............ 274 4.6. Integrated Circui.ts for Analog to Digital and Di-gital to � 276 Analog Tata Conv~ersion 291 4.7. Analog Switches 4. 8. Inte ,rated Circuit Voltage Regulators . . . . . . . . . . . . . 296 Ghapter 5: Providing Reliability of IC ilntegrated Circuits j 312 in the Product~on and As~embly Apparatus... . . . . . . . . � � � � � � 312 5.1. Design-Technological Principles of High Reliability.. . � � � � � � � ~ � � � � � 314 5,2. Operational Quality Contorl........ 314 5.3. Rejection Tests .............................e.���..� 5.4. Effect of External Factors on Apparatus Production 323 ~ 325 5.~. Form~ng and Trimming Leadouta 331 5.6. Tinnfng and Soldering 341 5.7. IC Asgembly on Printed Circutt Boards....... - d - ' FOR OFFI CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR ~ 5.8. IC Protection Against ElectricaZ Effects 345 5.9. Dismantling 352 . Tab le of Con tents 354 i i I - e - I~'OR OF'[~"[CIAL USE OM.Y APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 FOR OFFICIAL USE ONLY [Text] The products list of the basic aeries of analog and digital integrated circuits produced by t~~ electronics i.ndustry is surveyed: Methods of their fabrication, parameters and ch$i~acterisCics, as well as the operational principles of the basic components axe treated. ~ The developmental trends in logic circuits are indicated. Basic data is given fer microprocessors as well as the specific features of their applications. Factors which influence IC reliability are covexAd, the specific features of IC applicaCion in the design of radioelectronic equipment are described and recommendations are made concerning the - prevention of IC failures with exposure to various external loads as well as during proc~uction process operatione. The book will prove ta be useful to engineers working in the field of radioelectronic equipment design and Chose intereated in questions of s~tecting the IC component base and specific featurea of IC applications as well as for studenta in the appropriate apecialties. The book contains 73 tsbles, 186 illustratione and 64 bibliographic citations. Foreword In the main trends of national economic developtnent for 1976 - 1980, set by the 25th CPSU Congress, among the major ways of improving production efficiency it calls for a"decisive improvement in the quality of all kinds of products whieh are pro- duced, an expancion of the assortment, an increase in the production of new kinds of products which meet rbodern requirements" [1]. It is impossible to solve this problem without the further develapment of electronics, which provides not only for the creation of complex automated controla syatems for production processes in the most diverse sectors of the national econotay, but also for the develapm~nt - 1 - FOR OFFICIAL USE ON~.Y APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY of fundamentally new product~ for mass consumption. The expansion of the area of applications of electrrnics devices is one of the spacific features of scienti- f ic and engineering progress at the present stage. The development of electronics, starting in the 1960's, was related to the appear- ance and rapid improvement of integrated circuits ~IC's). Integrated circuits make it possible to design modern complex electronic devices.with sizes and weights acceptable in practice, as well as guarantee their high reliability. Integrated circuits have found the most widescale applications in the design of digital equipment. The properties and characteristics of IC's are determining to an increasingly greater extent the technical characteristics of camputers. Modern digital inte- grated circuits are complex products which realize the functions of entire blocks ~ and assemblies of computers. It is specifically this which is responsible for the appearance of a completely new field in electronics: microprocessing design. While digital IC's were t?~e basis for the design of third generation computers, - the production mastery of microprocessors, which are YC's with increased functional complexity and universality, m3kes it possible to process digital signals in a - new way and thus anticipate the widescale introduction of digital data processing techniques in the most diverse fields of engineering (even in those where the application of electronics had previously not.had a substantial impact). Fourth generation camputers are being designed around microprocessor sets ~4 to 5 individual packages). Three stages may be conditionally singled out in the development of digital IC technology and circuit design. The first was the development of the basic series of integrated c~rcuits which execute simple logic functions (NAND, NOR, AND-OR-NOT, etc., where, as a rule, the complement of each series contained flip-flops). At this stage, IC's were designed with from 10 to 50 components. The second stage was the development of more complex functionally complete units (c4unters, registers, decoders, half-adders, etc.) having from 50 to 500 compo- nents. The functional complement of the previously developed series is being constantly expanded by virtue of such new circuits. The third stage is the development complex functional devices having an inte- gration level of from 500 to 10,000 components on a single chip. This stage arrived at the start of the lOth Five-Year Plan. Pocket engineering calculators with broad capabilities for performing calculations based on preprogramming for the problem to be solved were designed using third stage circuits. In the process of the development of digital integrated circuit electronics, unipolar IC's with MOS structures were developed and found wide application along with bipolar circuits: p and n-type~ complementary ~CMOS), MUS with nitride insulation (MNAS) and some others. ~It is specifically the digi*_al circuits with MOS structures which made it possible to bring the number of elements on a chip up to 10,000 and to design such complex circuits as main memories ~OZU) having a large data volu~ne, as well as random access memory circuits and memories with long term storage of data when the power supply is turned off. - 2 - FOR OFFICIAL U~E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY Experience with the applications of the entire diversity of technological pproaches to IC fabrication, developed during the last 10 years, has confirmed the convenience of the application and good technical characteristics of bipolar TTL and ECL circuits, as well as circuits with MOS structures. Both the Unified - S}*stem of Electronic Computers (YeS EVM), created thro~xgh the joint e�forts of CEMA member nations, and the broad family of small computers and calculators (from the simplest school calculators with four arithmetic operations, up to uni- versal programmable calculators which can be used in scientific research) have been built on the basi;s of these circuits. Z'he past decade also gave equipment designers a new analog component base: a - large assortment of universal operational amplifiers, comparators, analog-digital and digital-analog converters, voltage regulators, switchers, as well as a set of low, intermediate and high frequency amplifiers. The application of analog IC's has made it possible to simplify the adjustment of instruments, increase their reliability and precision, and in many cases also eliminate the nececcisty of servicing. ' In recent years, the design of equipment using unpackaged IC's, with overell hermetic sealing in modules, has become an independent direction. Such an approach makes it possible to obtain a high compoment density and significantly reduce the size and weight of special equipment. � The domestic electronics industry;produces a large products list of modern digital and analog integrated circuits, which has become the main component base for modern radio electronics equipment (REA) for industrial purposes. The price which must be paid for high radio electror..ic equipment reliability is the correction application of integrated circuits and the observance of their operational modes; violation of these conditions because of inadequate knowledge of the technical properties, electrical paramaters and operating modes is also the most frequent cause of failures. The goal of this book is to provide basic technical characteristics of digital and analog integrated circuits, set forth the methods.of manufacturing them and the functional complement of a series, as well as devote attention to the specific features of IC applications in'the development of radio electronic equipment and make recommendations for the assurance of integrated circuit reliability in their production and installation in equipment. The material presented in the book is based on the results of generalizing ti?e experience with the development and applications of integrated circuite. The collective of authors expresses their deep gratitude to doctor of the tech- nical sciences, professor B.F. Vysotskiy, candidate of mathematical physics, B.N. Fayzulayev, candidates of the technical sciences Ye.I. Gal'perin, G.A. Podol'skiy, V.I. Kotikov, as well as V.L. Shilo, who took an active part in discussing the contents and structure of the book and made a number of valuable comments concerning the material content and its layout. The authors are also grateful to V.N. Bulanova and V.A. Ushibyshev for rendering assistance in the preparation and formating of the manuacript. ~ - 3 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPR~VED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY The authors ask that all remarks and proposals on improving the book be directed to the following address: Moscow, 101000, Main Post Office, Box 693, Izdatel'atvo "Sovetskoye Radio". The authors - 4 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 _ FOR OFFICIAL USE ONLY [Text] Chapter 1 Terminology in microelectr~nics and classification of integrated circuits i.i. ~ntroduction Microelectronics is a developing field of elec~cr~rtics Basica,lly, it is the creation of an integrated element bg,ae used to develop apparatus. The term integrated el'ec- tronics combines the "element~" as Hell as the "app~aratus" mioroeloetranica. ,Ma.ny concepts in the field have still not este,bliohed thetnselvrs firmly= th~refore, _ questions of terminology in Ruasian, as Well as in m~,ny foreign l~nguages are fair].y complex. ~n 1969~ the Intaraationsl Electrotechnical Comaiission (MEtC) issued, the second supplement to public~ticfn 147~-0 ~i9bb) [2] in Which, for the first time, terminology Nas p~esented in the field of integrated. circuits. The supplement included the defi,nition of seve~al of the awgt com~wn terni~ such as ; microelectronics, microcircuit, int~grated microcircuit etc. In our country~ the first attempts to regularize terms and 3efinitions xere attempted in 1967 When a norm "Integrated mi~rxircuits. Terminology" ~ras iss~:ed. The lack of status of this document m~de it impossible to recammend it as compulsory. In connection xith the considerable a~cpa~nsion of the use of integrat+~d circuita, the necessity arose of a governmont standard on terminologiQal questions in the field of microelectronics xhich xas developed on the basia of the above-menti~~d.norm and the MIIt publication and~ 3n 1~71, it xas approved by the U8$R Goastandart G06T 17021-71 included. 16 terms and alang xith g+aneral terms such a`s intagrat microcircuit~ semiconductorintergrat~d microcircuit~ there were alao given ein le- valued definitions for parts of integrated circuits (for example~ substrate~ hous- ing). ' - 5 - FOR OFFICIAL USE ONLY . APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFiCIAL USE ANI.Y Terms whose definit:lons were given in the above-mentioned GC6T were widely used in technical documents. However, the development of microelectronic means, the ' increase in the wiring density and in the number of elements on one chip tuul al- ready led~ in 11973~ to the necessity ~f reworking this GC6T for the purpose af . correcting it and introducin new terms. In 1975, this work was completed by the approval of G06T 1?021-75 [4~. Below axe given ths terms as per GC6T 17021-75~ their definitions and the synonyms of these terms which a.re widely used in productian arid in technical literature. 1.2.1. Integrated Microcircuics, Eiements, Components An integrated circuit (IC) is a microelectronic article tha,t fulfill~ a certain function of converting and processin signals and ha.s a high gacking density of the electrically connected elements ~or elements and components) and chips. This article is considered a single whole f~om the standpoint of the requirements of tests, acceptance~ 3elivery and Qperation. In abbreviated form, integrated iatcrocircuits are called IMS. The synonym of an integrated microcircuit is the term integrated circu3~t or, still simpler, micro- circuit. Df all the indicated terms~ integrated circuit (IC) is.the most fre- quently used. It ha.s two subordinate terms, whose description is given by the above-mentioned G~6T. These ase concepts of an element of an integrated circuit (or simply element) and component of an integrated circuit (or simply component). An element of an integrated circuit means the part of the IC that rea.li~es the . function of some simple electroradio element (for example, transistor, diode, resistor, capa.citor). This part is inseparable from the IC chip (or its substrate). The element cannot be separated from the IC as an independent article; therefore, - it cannot be tested~ pa.cked and operated. E~camples of integrated elements arer a film resistor in a hybrid IC and an integrated transistor in an IC semiconductor. An integrated circuit component also means a par~t of an IC that realizes the fur.ction of some electroradio el~ment. However, before assembly this paxt was an independent article in special packing (com~lementing article). In principle, a component may be separated ~om a m~nufactured IC. ~camples of integrated compo- nents axe~ a transistor without a housing or a ceramic capacitor in a hybrid IC. - 1.2.2. Design IIements In developing technical documentation for IC or in preparing descriptions of IC designs, writers of the indicated documents must freq,uently use such terms as housing~ substrate, boaxd, wafer~ chip~ as well as some special terms that deter- mine special features of the internal structure of t:-,o IC. The IC housing is the par~t of the IC structure intended to protect it from exter- nal effects and to connect it to external electrical circuits by lea.douts (IC are packed in the housing). The types and aizes of the housings are also subject to government standardiza.tion (see GoST 17467-79 . - 6 - - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2047102109: CIA-RDP82-00850R400504080030-5 The IC substrate is an intermediate product intended for elements of l~b~idjs~$ ~ film IC, intereleinent and (or~ intercomponent connections, as well as cont~et pads tc be applied to it. � The IC boaxd ~s part of the sub~trate (or the entire substrate) of the~l~ybr~d (or frequently film) integrated circuit~ to xhose surfaae the film e~ements of the IC~ the interelement and intercomponent connections and co~tact Pads are applied. . The semiconductor xafer is an i.ntermediate Pr~IC se co ductarst~Ita$ oiuld be (usua.lly it is a round thin disk) usea to make noted tha.t in IC production this term is uaed not only for the initial inter- mediate product, but also for a plate with elements of semiconductar microcircuits formed on it (therefore, this term is used during the entire technolc~gi.cal process - from its beginning to the cutting of the group article into individut~.t chipa). IC cnips are the parts of the wafer obtained after it is cut (usually they form a network in the shaPe of equa.l rectangles) , in the vo].ume and on the surface of which axe formed elements of the semiconductor microcircuit~ interelement connec- t ions and contact pads. A contact pad, present in any IC, no matter what i.ts technological or functional features are, is a metallized pa+d on the plate or on the chip i~tended to connect contact leadouts and integrated circuita~ as well as to monitor its electri~ca.l paramet ers and modes. An integrated circuit without a housing is a term xhich recently acquired great importance because such circuits a.re used widely in microassemblies and microcir- cuits. While in the usua~ IC the housing serves to protect against ex~ernal ef- fects, the IC without~ a housing has no such protection of its own (at least~ from mechanical effects~. Fbr connection to external electrical circuita, an IC with- out a housing must ha.ve its own leadouts and its full protectior; is provided by the housing of the device in which thie IC is installed. The leadout of an IC without a housing is a conductor connected electrically to the contact pad of the chip and mechanically to its surface. The main purpose of the leadout is to 7Provide an el$etxical contact to one of the cireuits oit~he~_ IC without a housing when it is connected to externa~ electrical cireuits. ou~s of the IC without a housing carry a conaiderable p~.r't of the heat.~Ledadouts of IC withou~ a housing may be hard (round, columnar or beam-ahaped~. leadouts ma.y be used for mechanical fastening of an IC xithout a houaing~ xithout pa.sting it. 1.2.3� Simple and Complex IC Until recvntly there was no decisive concept of the complexity of integrated cir- cuits in :Literature, either abroa.d or domeatically. When defining the term "laxge-scale integrated circuits" (BIS)~ an attempt was made to use~ as the 'basis, the quantitative factor as xell as the factor of the functional complexity of the mi.crocircuit. In the~first ca.ae~ suggestions were made to define the BI8 as a circuit containing 50~ 100 ar 10,000 circuit elemsnta. For example, to define -7- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 - FOR nFMlt'IA1, 1151: 4Nt.Y a"large digi~al circuit" an attempt xas ma,d.e to use an elementary digttal switch as a counting unit. In this case, it was considered that a"large" cir- cuit must ha.ve no ~ass tha.n S00 digital switches. Concepts of "small," "mediwa" and "large" scale integration began to penet�rate domestic leterature from abroad. However, depri~rad of numerical definitions, theae concepts in each indiv3dual , case~ expressed only the subjective concepts of the author. In the seventies, following ~his tradition, in scientific literature, the terms "very large in- tegrated circuit~" "superlarge integrated circuit" and even "colossal integrated circuit" appear. . Supporters of defining BIS,depeneli.ng upon its fluzctional complexity, proposed dividing the circuits into four integration levels: elementar~, circuit, subsys- tem level and finally, system level. The study of a11 the proposals led to the idea. tha.t a quantitative factor must be used as a basis for a definitian that defines precisely the qua.ntity of the elements in the microcircuit chip or housing. GfJ~T 17021=75 defined the term, "degree of integration of the integrated circuit," as an indicator of the degree of complexity of the IC, characterized by the number of elements and components. The degree of integration is defir~ed here by formula K=1gN, where K is the coef- ficient defining ~he de~ee of automation, rounded to the nearest largest integer,, while N is the number of elements and components in the IC. In accordance with this formula, an integrated cixcuit of the first degree of integration is ca.~led an IC containing up to 10 elements and components inclusive. t~?.;~:C of the second degree of inte~ation contains f~om li to 100 elements and componeazts incluaive correspondingly, IC with 101 to 1000 elements and components inclusive should be called IC of the third degree of integration. Similarly IC xith elements from 1001 to 10,000 or from 10,001 to 100,000 are IC of the fourth and fifth degrees of integration. ~ . When designing electronic apparatus and selecting the elementa, the eo-called packirig denaity of the elements in the integrated circuit is of great importance. By pa.cking density is meant the ratio of the number of elements and components of _ the integrated circuit to its volume (without taking into account the volwme of the leadouts). 1.2.4. Microassemblies and Nlicrounits GC6T 17021-75~ besides using terms with a direct relation to integrated circu~.ts gives~ in the form of reference material~ a whole series of terms related to t:~e field of application of IC. Such terms belong to the concept of microelectror,~ics. Here it is defined as the field of electronics that spans the problems of rdsearch, design, maxiufacturing and the use of microelectronia products with a microelectron- ic product meaning~an electronic device xith a high degree of integration. The term "microassembly" has several synonyms used in technical literature and documentation, but the definition of thia term was not alxays given clearly. Thus, for example~ before 1975 "~croassembly" meant a microcircuit consisting of various elements and integrated circuits. The synonymsfor microasaembly may be the terms used in literature auch as~ hybrid, integrated functional unit GIFU ~ large integrated functional unit (BIFU)~ a large hybrid integrated circuit ~BGIS3 and a hybrid la,rge integrated. circuit (GBIS). - 8 - FOR OFFiC1AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 Gd6T 17 02L-75 defined the micraassembly term as a microelectronic art~.c~~e ~~e~� fulfills a certain functior. and conaists of elements, components and integrated circuits (with and without housings), as well as other electro'ra~io elemen'ts, in vaxious combinations, developed and manufactured. by develcpers of concrete radio- - electronic appaxatus for improving its niniaturization ind.icators. 7.'he.~C~T does nat define a microa.ssembly as an article with or ~rithout a housing, i.e., a micro- assembly may or may not have its oxn housing. Thus,a microass~~ably is not classi- ' fied by the C~T by its complexity. A microunit is a mi.croelectronic article which, besides micaro- assemblies, ma.y contain integrated circuits and components. Fin$lly, the niniaturiza.tion level term of a microelectronic article characterizcs the quanti- tative measure of the effect of using the totality of technical solutions, directed. to the full utiiization of the a,dvantages obtained ~`rom the reduction in volume~ weight and power used by the appaxatus. Indicators of the REA [Ra.dio-electronic apparatus] miniaturization level are~ REA meeting the mod.ern technical standard of microelectronic articles= other articles used in ~tFA meeting the mod.ern le�vel of miniaturiza,tion; efficiency of comprehensiv~ miniaturization of apparatus; technical compatibility of "noninte- grated" articles of electronic equipment~ and electric equipment with integrated. circuits. !..3. IC Classification - Depending upon the manufacturing teehnology, integrated circuits may be semi- conductor, film or hyhrid. GCBT 17 0?1 -75 gives the following definitiana for these three vaxieties of IC. A semiconductor integrated. circuit is called an IC all of whase elements and inter- e?.ement connections ase ma,de.in the volume and on the surface af the semieonductor. The semiconductor integrated circuit may also be called a semiconductor micro- - cixcuit. Sometimes the semieonductor integrated circuit is called a"solid" (or solid-body) circuit. This term found its xay into domeatic literature due to unqualified translations f~om the ~glish*. Gt~T 17021-75 defines this term as ina.dmissible. A film intsgrats~d circuit (or film circuit~ ~?hose elements and interalement con- nections are ma.de in the form of films is called an IC. This film and 'thick film IC axe vaxia,tions of technical designs. The difference between thin film and thick film IC may be qua,ntitative anli quali- tative. Integrated circuita with a film thicknesa of up to i micron belong to thin film IC conditionally while inte~rated circuits xith film thickness greater than i micromoter belong to thick film IC. Quslitative differences are determined *Solid state electronics (bhglish) aemiconductor electronics. - 9 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 FOR OFFIC.IAL USE ONLY of the films. Elementa of thin film IC are by the ma.nufacturing technology b thermal-vacuum precipitation and cathode applied to the substrate, as a rule~ Y b 8i~ screenin6 Sp~,ying. xl~i.le elements of thick film IC are a~acie primarily y With subseci;~sa~ burning in. brid ~.crocircuits) are Finally~ hybri~i inte~ated circuits (e~quivalen~ term hY IC containing, besides elements~ simple ~f h bTid IC is~a~multichip C~aetotalPs of semiconducta: IC). A particu1as ~ase o y ity of several IC ~rithout housings on one substrate). u on their f~nctional PurP�$e~ inte&rated. circuits are divided into two DePendi'ng p ital. basic categories ~106 ~d ~g p~og 3.nte~rrated circuits (anala8 mi~r�~ircuits) are IC intended to convert A d process signals that change in accoIrdanct~ a~l nhear anharacteristict(linear�micro- particular case of analo8 SC is an circuit). Digital integrated circuits(digital o~heridigi al codeB~A variati n ofdthe process signals expressed in a binary ti~6 with a digital microcircuit definition iC t~hee ~j,logic microcircuit (opera binary cod.e are described by logi ~ . and digital IC are developed a.nd menufactured bY n~axiufacturing As a rule~ analo8 enterprises in the form of a series� b~Ch series is chaxacterized8b~hich, in etheir of completenesa. A series co~?tains severa~ IC of distinctive type turn, ma.Y be divided j.n~o rated. types. According to GC6T 17021-75~ a seriea of integrated circuits contains a totality of IC which can implement vaxious functions, buiohave a~8g ~eg e~h~compositionCOf form and are intended to be use~ a~~~i~~`i~. a promising series is bei.rig exPan ~ ases and their conditional desi~ations axe IC that have concrete funotiona~ ~~ts~ By a t~ of ~te~ated circuit is ~ called rated types of integra o es and meant a totality of rated types of IC that have concrete functional pu~'P ~ their conditianal designationa. tions - 1.4. 5ystem of Conditional IC DesiSna The entire diversitY of mar?ufactur~d integrated circuits accordin6 to the adopted. i tion syatem is divided into three groups~ semi~or?ductor, conditional designa eeentl maaufactured in a limited quanti- hybrid and others. Film IC~ xhich are p~ Y ty, as well as vacuum IC and ceramic IQ~ are fre~lu~?tly referred tc ae the last The ~coupa indicated above ar81a~s~ ~~Be~Q~duc orglC withoutihous~ inga) ; ~�up' tion 7 ig as ~ semiconductor IC (desi~na 2~ q, 8-- hybrid IC; 3-- other IC. to the nature of the functions implemented in radioelectronic apparatus~ According modula,tors~ triggers, IC are subdivided into subgrouP$ ~f~ e~~ple, oacillators, r ~ ; ~t i _ 10 - FOR OFF[CIAL USE ONLY ~ APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPR~VED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 Rmnllfler:~) :~rici ty~r~ (for wcun~le~ .Ereg,uency, ph$se~ duration, volta,ge a6t~lv~ters~. The classification of integrated circuits in accord~nce with their functional pur- poise is shown in Table 1.1. ' - According t~ the aclopted syatem of dnsignations, an IC muat conei~t of 4~~on~t~. The first ele~ent a digit carresponding to the deai~-technological ~oup. The second element two-three digits assigned to a given IC series as the ardinal number of the development. Thus, in the first two elements are three-four digits that determine the total number of the IC se~ies. The third element two letters~ corresponding to the subgroup and the IC type (see Table 1.1~. The fourth element the ordinal numbar of the IC~development in a~,iven series in which there ma.y be several equal in the funetio~a.l criterion of the T.C. It may con- sist of one digit, as w~ell as seweral d~.gits. G:~ST 18682-?3 does not limit this number. Below is shown an example of a con~itional des~.gnation of an integrate3 $eml.conductor operational amplifier with an ordii:~.l Qf the series development 40, the ordinal number of the development of the ~iven circuit in the series according to the func- tional criterion 11. ~ w . _ c.~~,wA(1) ~2~ ' 40 yQ ~3~ � " !I,~~ad~aBa~u ~ep I pl73A,~�f~n~KJ :N[/KpOCXCMd~ /!0 I QIS///Ii(;.iU�yll/~GHOM!? /l~Ofl3HON~/ 4t J .~c~Nh~ri cePu[~ ! I Bud (no ~py~,:r,s:l.7.i'll:~byC~`ly/ r/~13NdyeHab) ~ f6~ /Iodapynnct ;~~'~;r,lh~db/U NOMBr0~Od3~OJD:i.?l~'ll 0'QNNO[lCCiOI(!! i ` ~ ~7) ! ~.7;' n'~'ri,,.''J'~Y.97:f~YNO-~11L'XHO/JOZ!lyBCKONlf C/C/lJ/1HL',N,ihl ~ - 1. Series 5.. Sut~group 2. UD 6. C~c~dina~ number of given series 3. C~dinal nurr~ber of a microcircuit Group (accoz~ding to the design- development according to funetional teehological makeup). ~ criterion in the given saries 4. Type ~according to functional purpose) - 11 - FOR OFFICIAL US1E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR OFFiCiAI, l1SE 4NLV Table 1.1 Flanctional classification of IC - ~ Sub ou T e Letter Desi~ation Name Letter ~ Le~ of the rated ~i~_ Desi a~ tion ,t~(~ tion ascillators G ~ Harmonic signals S ~ ~tec'tangu].ar aigna].s G ~ (inclwding self-axcited multivib~ra,tors ~ blocking - oscillators etc.) ~ I,inearly chan6in6 Signa].s L Speaial ahape signals F GF Noi$e M ~ Otha~rs p ~ ' Detectors D Amp].itude A ~ ~3e I DI ~ec~uency S � ~ Phase F DF Others Switches and K GSarrea~t T ~ _ keys Volta,ge . ~ ~ Others P KP Logic elements I, IIement AND-N!m A ~ E].ement ~t NO?r . Ye ZYe Flemea~t AND . I LI IIement ~t L I'I' Eleme~t N~ N ~ ~ Element AND-QR S I,3 ELement AND-NCI~~~t-N~ H ~ ' ~ ELeme~nt AND-~t-N1J~ R LR ~l.ement AND-OR-NQP~AND-OR K LK ~ ~lenient C~t-NQP~~t M LM ~~~g D I,D Dther$ P LP Multifunctional Kh AnaloB A ~ circuits Digital L Combined K ~ Other P KhP Madulators . M Amplitude A ~ Frequency S ~ - 12 - FOR OFFICiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 F'OR OFFIC'IAI. USE ONLY r � ~.7. Table i.i continued ~inctional Clasaification of IC ub . ou T r e I,ettl~r Desigaa- rlame I,etter Name Letter t~.oa of ~ ~ Des~gna- ~a,~,,,iAnation the rated tion . Triggers T Type JK V ~ TV Type RS R TR Type D M TM Type T T ~TT Dyna,mic D TD Schmid.t L TL Combined (tgpes DT,RST etc) K TK Others P TP Amplifiers U High frequency*~ V UV Intermedia,te f~equency* R UR . Low frequency* N UN Pulse s3gaals~ I UI Repeatera Ye UYe Read-otit and retrievel L UL Irldica,tion . M UM ~ DG`~ T UT Dperational and = differential* D UD Others _ p ~ *Yoltage and poxer am,plifiers :(inc].udirig low-noiae Filters F Upper f`requencies V FY Lower frequenciea N FN Band Ye FYe Re3eetor R FR ~Othera P FP Shapers A Rectang~lar pulses G AG (biased multivibrators, bloaking oscillatora, etc. Speaiel shape pulecss F AF Addreea currents (shapers A AA of voltages or currents) D3.scharge currents R AR , ( sha,pers of voltages or curr9nts) ~ Uthere P AP - 13 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 Tabls !.i continued ~ Fluictiona.l Cla+ssif%;ation af IC ~ Letter Sub ou T~-e . De81gna_ tion of pa~ Letter Na~me Letter the rated D~ai~a- ~i~- t= � ~e ~ tio~ ~ A ~ Modulatars M Anrplitude ~ ~ F~eque~cy s , Pt~e F ~ Pulse I ~ Othera p ~ Sets of N Dd.odes . D ND elements ~ansiatora T ND Resiators R NR Cape~citors Y'e ~NYe Combined ~ ~ _ Others P . NP Converters P FYequeacy S ~ Phase F PF Duration D ~ Yoltage N ~ ' Po~+er M ~ Level U ~ Code-analog A PA Analog-code B PA ~~~a R PR 4thera p ~ Circuits for Ye Rectiflers V YeV secondary poxer Converters M YeM Voltage stabilizers N Y~ sources T YeT Cuxre~n~ stabili~era Y~ Others p . ' Delay circuits B Pa$aive M ~ Active R _ BR Obhera p ~ Selecting and 3 Amplitude (signal level) A ~ comparing cir- Tf~ v sv P~eque~cy S ~ cuits F SF - Phase SP ~ Otihera p - 14 - F'OR OFF'ICIAL ~JSE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 Table i.i continued ~.�~d ~nc~ional Classifieation of IC Sub~{rouu T~g Le~ter . . > Desig_ Name Letter Name ~tt~ nation of the rated . Desi~a- ~ tion ~ Memory ma,trices ~ ~ ~~'86e elements l~fain memoties (4~) M ~ permanent memories (PZiT) Y RV ~U r~ith contrbl circul.ts U ~ . PZU with control oi~uits Ye ~e P~U xith control cf:~cuita T ~ attd one-time p~ograming i~U ~rith cont~dl circ~,i.te ~ ~ atld multiple p~bg~eiaB ~naI,cg menwry (A~1) ~rith A ~ contlro�1 circui~s ~iers P RP Elements of I Registerg ~ ~ arithmetic and A~,d~s M ~M discrete devices ~~.f-adder8 L ~ t~ottnters Ye IYe Cdders V IV (~ambined K II� Dthers I~ IP ~ A lett~r is soa?etimes added to the e~d of the conditional de+signstion that de- finestF,e technological spread of the electrieal parameteY'g o~ the g'iv~oa rated type. The concrete value of the elect~i~cal paramete~a axid the ~ffereuce bistx~en the rated tyges is ~i.ven i.n the tachnical docu~e�tatia~ (Par exa~mple, IC~33LAlA differ+s ~rom ~ci33r~,iB) . - 15 - ~'OR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R044500080030-5 ROR OFFICtAL USE ONLY In some series (this is also stipulated in the technical docu~esntation)~ the let- ter at tY,e end of the conditional deaignation of the IC defines tha ty~~ of the housing used for the given rated type. For example, the letter P deaignates a plastic housing~ xhile the letter M-- a ceramic housin,g. Far microcircuits utilized~in xidely used devices~ the letter K is at the beginnin8 of the conditional designation. The desi~nation then appears as K1~OUDii. If~ after the letter K, there is also shown the letter M ahead of the seri,es nw�ber~ for8exa p e~eKM155~1~� all the given $eries is manufactured xith a cera~a3.c housing ( A series made for export(With a pitch of housing leadouts of 2.54 mm) is especially stipulated with the letter E before the letter K i.ri the aonditional.deaignatwithout (for example, IIC561LS2), while the series in the vaxiation Kithout housing~ leadouts being connected to the chip of the microcircuit ia sti lated by the letter B ahead of the series designation (for exan?ple, I~52~+RP1A'4'~. For IC without housings, in the shortened deii~at~ficationi(for examgle,~ a~er a hyphen to cl~aracterize a corresponding des gn 703LB1-2)s wit:~ flexible leadouts-i*i ~th ribbon leadouta, includi.ng those made with polyamide film-2= fri.th hard leadouts-3; on a common~P anethe fila~-e5di with separated xithout loss of orientatio~ (for example, pas con+act pads xithout leadouts (chip~-6. It should be noted that before the intraiuction of GC6T 18682-73 [6] (i.e., before 1973) ~ the a.ssignment of condi.tional designationa. ~8~?C~receiv~edanew Qona,i,the existing technical-norm documentatio~. Afber 1973, tional designations. HoKever, for a oertain numbar of IC for which no new techni- cal documentation xas issued. old conditional desi~?ations xere continued. The old and nex conditional designationa differ by the letter deaignationa of sub- groups and types (the lattto the uee ously existing documenta,tionf types in G06T 18682-73 as compared Pr An example of the old desi~atian of an IC type i~33i ia ahown on the next Pa88� *Modification "1" is applied to microcircuits with a number of leadouts no ~eatar trian 16� - 16 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 CePuA ~l~ L . - � AO~AdKOBbIU NOHFfi ~3~" 60R11W (RO ~yNlYy!lOHlfAb-. ~ p6 33 ~ ~ xp~y ~r~xy B DoKHOu ~ cep~ru) . I~kaXO~?u ~oM~p v~jv~aomX~ aQxxou ~av~~ � n0~~~//0 U eVa (p0 ~ NKI~UOXQ/lINON Hl1~ilC9CNU/OJ ~ ~l ~p IUid ~/ID NOHCliIQ~IKRIL/IR0'I1ICXND/JOtflUCCNOIMy (/CIIO/IHLNI/M i. series 4. S'tibgroup atyd type (aocord- ing to ft~netic~"s1 purpose) 2. C~dinal number of developme~t~ . 5. G~oup (according 'to design- (according to fluictional ~r.~i.te~ri:oai in tx~nologic~l. "n~If9tip) the given seriea) 3. (lydinal nwnber of dev~el.opme~tt of the given ser{as BIHtiiOGRAP~f - i. Basic directiana of natia~al ecano~r dev~elopm~nt fo~ i976-19~.� ~os"c'ox, Politizd.at, 1976. ~ 2. Second supplement to publicatian MFK-147-0'~(19~~� Basic pi~a;toete~a atid characteristtcs of semiconductos devices 'and �gene~r~l p~inciple"s of ~aieture- . ments. General informat~o~ aad t'er~iaolt~y, 3. GCb'T 1?021-7~1. Microcircuita�t Terms and definitians, - 4. C,t~T i7021-75. Integrated. microcircuitB~ Te~rms and definitic~ GosT 17~7-?9� Iritegrate~ �miaroc3rcuits ~ Ba'~ic ei~es. 6. GL~T 1868~-73. Inte~rated ~c~rooi~oui:ta ~ w:aesifications ~d eys~~eis of con- ditional designat~on~. . CQPYRIGHP~ Isda~el'stvo "Sovetskoye rardio"~ i979 2291 ~ CSO: 1863/209 -~.~:z. - ~ F~R OFFtCtAI. USE ONLY . APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY CHA~TER TWO. METHODS OF FABRICATING INTEGRATED CIRCUITS 2.1. Film and Bybrid Technology At the present time, film technology can be used to make passine components (resistors, capacitors, inductance fo ils) and also fabricate the connecting con- ductors, contact pads and microwane circuit components (such a stripline wave- guides, attenuators, splitters). Actine film elerer.ts (transistors and diodes) are as yet fabricated only under laboratory conditions for research purposes. Thus, the purely film IC's produced in the USSR and abroad are passive IC's ~these are usually resistive voltage dividers, aets of resistors and capacitors, and RC networks). Film integrated circuit components are most often used in conjunction with miniatu~e radio components, the componenta in hybrid IC's. Hybrid IC's, being inferior to semiconductor IC's in terms of reli~bility, component density, and production cost, have special circuit design advantages in a number of cases by virtue of the Lse of a broad products list of outboard components ~transistors, micro-inductances,~ capacitors~. Hybrid technology is extremely flexible. It makes it possible ro construct elec- tronic devices relatively quickly which perform rather complex functiona. The set of equipment for the fabrication of hybrid IC's is less expensive than for the fabrication of semiconductor IC's, while the production process itself is substan- tially simpler, and for this reason, the mastery of hybrid technology is acces- sible to practically any inatrument making plant [1]. An advantage of hybrid technology is also the higher percentage yield of good IC's (60% to 80% as compared to 5 to 30~ for semiconductor IC's). The rejects which occur in the manufacture of a hqbrid IC can frequently be corrected. The design and planning methods for hybrid IC's do not differ fran the design methods fo r conventional electronic circuits becauae of the discrete nature of the film ele- ments and t.he outboard components. Becauae of the low parasitic capacitances and good in~ulation of the elements and components from each other, a hybrid IC has better electrical properties ~lower induced currents at?d parasitic coupling) than a circuit composed of discrete, "large" radio compoaenta. Hybrid integrated circuits are most frequently used in the design of analog equip- ment. It is especially convenient to use them to perform nonstandard functions, where large capacitors, high resistance, highly or~precision resistors are required. The components of film and hybrid integrated circuits ~resistors, capacitors, inductances) are made on the surface of the subetrate in the form of films of different materials (reaiative, conductive and dielectr ic materials). Both thin and thick films are used in the manufacture of hybrid circuits. The choice between thick and thin f ilms is governed by many con~iderations. Thick film IC's have th e following advantages over thin film ones [2]. They are less expensive to develop and fabricate in the case of a small production series; lower capital outlays are required when aetting up production (simpler equipment, less stxingent requirements on the production rooms); they have greater mechanical strength; they have higher moisture, corrosion and thermal resistance; greater - 18 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R044500080030-5 FOR OFFICIAL USE ONLY overload capacity of the elements, as well as lower parasitic capacitances of the interconnections and lower mutual coupling of the elements. Thin film integrated circuits have their own advantages over thick film o~es: one can obtain more narrow tolerances for the nominal values of the components without trimming (resistors and capacitors); a higher layout density of the components on the substrate is achieved, where these components have lower high frequency losses and greater radiation i.bmunity (by virtue of using a smaller products list of chemical elements with a high atomic weight). _ It is preferahle to use thin film hybrid circuits in very complex analog systems with strict tolerances for the elements, where extremely high stability is needed for the resistors. The scales of the proposed produc:tion of hybrid IC's also govern the choice of the type of films. If it is neceasary to have a small number of products, then it is not expedient to set up groduction of thin film IC's, which xequire significantly greater capital outlays, and preference is to be given to thick film:;technology. TABLE 2.1 The Parameters of Resistive Materials Specif ic Temper- Permis- Naminal Toler-~ Resistance, ature sible ance, X Material p , Ohms Coeffici- Power, fl ent of W/cm2 ~ Reaiatance (10-6/�C) - Chromium (on Cu with a Cr - sublayer) 20--800 +180 '.2.0 +5 ~ Nichrome (on Cu with a Cr sublayer) 100--300 +250 2.0 +5 Tantalum (on Au with Cr sublayer) 50--500 -400 3.0 +5 Sta~nic Oxide 500 +300 2.3--4.0 +2 NLT-3M alloy ~on Cu with a ~ Cr sublayer) 300--500 +200 1.0 +5 Metal ceramic on a palladiwn - oxide base up to +200 up to 1.0 +10 20,000 Conducting paint on a carbon base 10,000 500--1,000 0.15--0.35 +10 , 2.1.1. Materials for Hybrid IC's IC substrates are ma.nufactured from sitall [ceramic~glass, similar to pyroceram], gl~ss or ceramic. The major requirementa placed on aubstrates are: good . - 19 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOit OFFICIAL USE ONLY me~chanical and dielectric properties, inatching of the temperature coefficient of expansion to the other,.~terials, as well as high surface purity ~class~s 12 to 14 in accordance with GOST 278a-73). Substrates of various sizes are used for the manufacture of hybrid integrated circuits [3]. The most widespread are rectangular substrates with the following dimensions: 6 x 15, 8 x 12, 11 x 11, 10 x 16, 12 x 12, 12 x 16, 12 x 20, 16 x 20, 24 x 30 and 48 x 60 mm ~in this case, devia- tions from the nominal dimension amount to no more than 0.3 mm and the sides must be parallel within 0.5 mm). A number of substrate thickneases are employed: 0.6, 1. 0 and 1. 6 nan (with a deviation of no more than 0.1 ffin) . The substrate for thick film IC's should be heat resistant in arder to stand up to annealing at several hundreds of degrees, which is necessary for fusing and securing materials from which the IC components are fabricated. In order to reduce parasitic capacitances between elements, materials are chosen having a low dielec- - tric permittivity ~if this effect is not employed as a useful one). Substrates with a high heat conductivity, for example, made of beryllium ceramic, for which the thermal conductivity is only five times worse than for copper, are used in the manufacture of high power IC's. Regardless of the material, resistive films are characterized by the specific resistance per square surface unit area, . This quan~ity is an objective characteristic of films and depends on the specific resistance of the materials and th~ thickness of the film (but does not depend on the dimensions of the surface square). Chramium, nichrome, tantalum, MLT alloy, metal ceramic, conducting paints and pastes are used for the fabrication of res~stors. These materials make it possible to obtain a range of values of p~ fram 20 ohms up to 20 ROhms. For better ad- hesion to the substrate, the resitYVe metal layers are placed on auxiliary metal sublayers. The parameters of some of the resistive materials are given in Table 2. 1. [4] . The most suitable thickness for thin resistive films is considered to run from 0.01 to 0.2 micrometers. Having set the film thickness in this range, a material is chosen which provides the requisite specific resistance pp . In this case, one must take into account the fact that it is not always advantageous to select materials with a high res istance, since when removing them from the vacuum chamber, the thin films sametimes change their resistance by up to 50 percent as a result of oxidation in air. For thin film resistors, it is best of all to chose materi- als with p~ = 100 to 500 ohms,'and for thick film resiators, 10 ohms to 20 KOhms. _ Copper and gold -vith a sublayer of nichrane, aluminum or nickel are used as the materails for thin film conductors. Si1,iQOn monoxide frequently serves as the dielectric in the fal~rication of film capacitors. In this case, it is best of all to use aluminum, since in terms of its electrical properties, it is quite well matched to silicon. The th ickness of the conductora is chosen in a range of 0.3 to 1 micrometer ~a sublayer thickness of 0.01 to 0.03 micrometers). Gold is frequently used for the fabrication of the bonding pads. The thickness of the bonding pads is uaually chosen in a range of 0.5 to 4 micrometers. _ -20- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFiCIAL USE ONLY Thick film conductors should have a specific resistance of no more than 0.1 ohms/ _ and should allow for soldering in the region of the bonding paths. ~io kinda of = tr.ick film conducting materials are used: based on gold-platinum, which permit , annealing at temperatures of up to 900 �C, and based on silver, which permiC annealing at up to 700 �C. Siliaon monoxide, zinc sslfide, anodized tantalum, as we11 as chalcogenide glasses - (KhG-44, IKS-24) are used as the dielectrics in the fabrication of film capacitors. The properties of silicon monoxide films depend to a gi~eat extent on the rate of vaporization and the composition of the residual gases in the vacuum chamber. Films of zinc sulfide are less critical as regards the c'eposition conditions. When choosing the dielectric material, its structure should be matched as best as possible to the structure of the other materials of the iilm circuit. The maximum thickness of dielectric films is limited by the resulting internal voltage and is on the order of 1.5 micrometers. The minimum thickness of a dielectric film is limited by the porasity of the structure and the apecified working voltages (about 0.06 micrometers). ~ The specific capacitances, abtained when using silicon monoxide (e = 6) fall in a range of 5,000 to 10,000 pF/cm2. Anodized tantalum (E = 25), titanium oxides = 80) and barium ti.tanate (s = 1,000) can be used to obtain larger capacitances. The electrical strength of dielectric films depends to a considerable extent on the metal of the capacitor plate. Metals with a rather h igh vaporization temper- ature (for example, nickel and chranium) yield a greater number of short circuits, since the atoms of these metals, having a high energy, pass tlirough the thin film of the dielectric when applying the upper plate to it. Silver and gold can aleo be the cause of plate short circuita, which occur becauae of the intense diffusion (migration) of the atoms of these metals from the plates slong the grain bounda- ries of the film a short time following the application. ror this reason, aluminum is moat often used for the plates in thin filt,i IC's, since ~luminum has a low vaporization temperature and low migration mobility because c~f the oxidation processes at its surface. The electrical strnegth also depends un the presence of pores in the dielect~zic rilm, aince air in the pores is - ionized at a lower voltage than the breakdown voltage of the solid film. The presencc of microscopic pores can be related to the presence in the material being vaporized of impurities in the form of gas inclusions. Silicon monoxide and IKS-24 chalcogenide glass (e = 6, tan8 < 0.03, a breakdown voltage of no less than 0.8 � 106 V/cm, a temperature coefficient of expansion of 5� 10-4 1/�C in a temp- erature range of -60 �C�to +125 �C) are used for the interlayer insulation. 2.1.2. The Fabrication of the Elements of Hybrid IC`s ~ The major techniques for producing thin film components are thermal vaporization in u vacuum, cathodic and ion-plasma sputtering, and the precipitation of f ilms from vapor and gaseous phases. Thick film componenta are produced on a substrate by means of silk screen printing. The choice of the epecific film produetion - 21 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL LiSE ONLY technique depends on many factors, especially on the composition of the substance being applied, the condition of the surface, the substrate temperature, the requi- site thickness and the method used for=.~onitoring it. The method of depositing thin films by means of thermal vaporization in a vacuum has become the most wide- spread technique in industry. The major merit of this method is its universality. - One can obtain homogeneous layers of inetala, alloys, semiconductors and dielectrics of various thickness in vacuum installations of the same type, and also fabricate thin films from different kinds of substances while determining the ratio of the parts for various thicknesses of each sublayer. The process of producing films by means of thermal vaporization in a vaccum has the stages of vaporization of the material and the codensation of ita vapors on the substrate. The material is heated for vaporization. Joule heating is used in this case which is liberated in conductors when an electric current is passed through them. One can also employ electron beam heating, radio frequency field heating as well as an electric arc. When heated in a vacuum, the material melta, and then goes to a vaporized state. In conventional industrial vacnum installations, a vacuum on the order ~f 133.322 � 105 to 133.322 � 10'6 Pa [sicJ is employed. However, a deeper vacuum is frequently needed to improve the structure of the films (down to 133.322 � 10'8 to 133.322 � 10'9 (Pal)� The phenomenon of cathode destruction as a result of its bombardment with ionized molecules of a rarefied gas is employed to apply thin films by means of cathode sputtering. The cathode sputtering of films is accomplished at a pressure of 133.322 � 10-1 133.322 � 10-3 Pa in a residual air atmosphere or. in an inert gas ~most often in argon). A high voltage of. from 1 to 20 KV is applied between the cathode and anode to ignite a glow discharge. The advantage of cathode sputtering over thermal vaporization in a vacuum consists in the fact that one can use it to obtain an increase in the surface area and uniformity of the thickness of the resulting films ~the material is deposited o�:~ the substrate not from a point source, but fram the flat surface of the cathode, the dimensions of which can b~ considerably greater than the spacing.from the cathode to the substrate). An important merit of the technique is the constant chemical canposition of the material being sputtered, while in the case of thermal vaporization of the material, its camponents are vaporized at different rates, because of which the composition of the f:"~m can differ from the composi~ion of the etarting material. Films of diff iculty fusible materials can be obtained by means of ~athode sputtering. In the case of ion-plasma sputtering, an initial presaure on the order of 133.322 � � 10-6 Pa is created in the chamber. Then, a thermal electron high density current ~of several A/cm2) is produced between the cathode and the anode of the installation_4after which an inert gas at a presaure of up to 133.322 � 10'3 to 133.322 � 10 Pa is fed into the chamber, and a discharge is ignited by means of a high frequency transformer. The low energy ions occurring during the discharge bombard the substrate and remove the contaminants from its surface ("ion etching"). -22- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY - After this, a negative potential is applied to the target. The positive ions extracted fram the discharge plasma bombard the target at an energy sufficient to atomize the atoms of the target material. The atoms knocked out of the target move predominantly in a direction perpendicular to the target surface [5]. The great merit of ion-plasma sputtering consists in its universality. Metals with different properties, for example, tungeten and gold, can be atomized with equal success. Such alloys as nichrome and stainless steel permalloy are atomized with- out the dissociation of the composition of the material being vaporized. In the case of ion-plasma sp~ttering, complex (alloy) f ilms consisting of two or more metals can be fabricated by the simultaneous sputtering of several independent targets. Both pure sesaiconductor materials (silicon) and aemiconductor caaapounde can be atomized. A great advantage of the ion-plasma technique is its lack of iner.tia. The material is atomized only when a voltage ia applied to the target; the sputtering ceasea immediately after the voltage is turned off. The density of the depositing ion beam can be adjusted by changing the emission current of the tungsten cathode or the inert gas pressure. The deposition rate can be varied in a very wide range: from tenths of a nanometer up to tenths of a micron per minute. The uniformity of the film thickness with ion-plasma aputtering reachea one to two percent, which is considerably higher than in the case of cathode aputtering, where distortions are introduced in the nonconducting substrate, arranged between the Cathode and the anode. Because of the high energy of the atoms i.mpinging on the substrate, the strength of the film bond to the substrate where the film is obtaitted by the ion- plasma technique proves to be quite high. The main advantage of precipita.tion fram a gas phase consists in the ease of con- trol of the process and its individual stages. In this case, one can compara- tively easily introduce an additive into the growing film and obtain layers with properties specified beforehand. The technique is used in the fabrication of metallic, resistive and dielectric films. In this ~ase, as a result of the de- camposition of a camplex chemical compound or the chemical reaction of two or more substances, the reaction product is precipitated in the form of a film on the sub- strate. The reaction can occur with the action of heat ~pyrolytic decomposition), light (photochemical decomposition), or as thr~ result of hqdrolysis, exposure to an electrical field and other factors. Following the application of the passive film elements to a substrate, the follow- ing components are installed on it: transistors, diodes, capacitora, transfarmers and semiconductor IC chips [6, 7]. Components with rigid leads are secured to the board by means of soldering or welding their leads to the contact pads of the board. Components with flexible leads are secured to the board by means of epoxy glues or are soldered. In the first case, the component is electrically inaulated fran the board, and in the second case, it can make electrical contact. The manner of fastening components to a board should provide for good mechanical strength of the fastening, the absence of stresaes at the fastening point, chemical stability and neutrality of the mat~rials used for the fastening, as well as their high heat conductivity, low formation temperature and high working temperature of the resulting compounds. -23- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY . Epoxy glues have little shrinkage when they harden, good adhesion to various materials, do not liberate by-Products and are chemically stable. Their polymer- ization temperature can be chosen in a wide range of~*values, including normal temperature, by means of selecting the hardeners. Fastening by means of soldering the chips of unpackaged semiconductor IC's, transistors and diodes is accomplished by the formation of eutectic alloys between the aurface of the semiconductor and the gold layer on the board. The board is heated up to a temperature of about 370 �C, the chip is placed on the gold contact pad and pressed with a specific force. As a result, there i8tice alloalat the useparationeboundary.and the gold with the formation of a eutec Y 2.1.3. Making Electrical Connections in Hybrid IC's The leads of components which are fastened to a board are connected to contact pads, while the output contact pads are connected to~taeWiresawithediameters ofe majority of cases, such connactions are made using g fram 25 to 50 micrometers by means of thermal compression, contact or ultrasonic welding. The most widely used is thermal compression welding, in which pressure is combined with heating. The board and the gold wire are heated at the point of contact up to a temperature of 200 to 400 �C, the wire is pressed to the contact pad of the board with a force of from 0.05 to 0.5 N for a few seconds. The thermal comp- ression technique requires careful aelection and monitoring of the major para- meters of the process: pressure, temperature and welding time. Contact welding is accomplishe~d by using a split electrode. The contact quality depends on the contact area, the specific resistance of the separation surface, and the resistance of the parts being welded. Because of this, the welding condi- tions are to be carefully selected for the specific conditions. Ultrasonic welding, which is based on the simultaneous exposure to ultrasonic oscillations excited in the parts being welded and pressure in the weld region, provides for better quality of the weld joint than does thermal compression, as well as a lower welding temperature and a wider set of inetals which can be welded. It also makes it possible to weld using a group technique. 2,2, Semicnnductor Technology The special features of semicanductor IC's, which determi~etce~$~Poflintegratedes of their fabrication technology, are as follows [8, 9]� circuit elements is determined ~o a considerable extent by the area they occupy on the semiconductor chip. Thus, the cost of a transis=oximatel8 correspQndsXto mately equal to the cost of a diode, which in turn, app Y - the cost of a resistor with a nominal value of 4 ROhms with a tolerance of +30X or with a nominal value of 1 K~hm with a tolerance of ~20%. T~ie nominal values of elements having discrete prototypes are limited. It is not expedient in practice to use "pure" resistors with nominal values above,50 ROhm for masa produced IC's. ' -24- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080034-5 FOR OFFICIAL USE ONLY Capacitors having a capacitance exceeding a few hundred picofarads must be made in the form of individual outboard components. The desired nominal values of resistors cannot have small tolerances, although the ratio of the resistances of - resistors of identical shape on a single chip can be maintained rather precisely (l~.~to 2%), where their temperature dependence will be the same. All semiconductor integrated circuit camponents are coupled together by means of parasitic capaci- tances and conductances, something wti~ch is due to the dense packing of the compo- nents and the imperfection of the methods used to insulate the componenre. The advantages of semiconductor IC's over hybrid integrated circuits are as follows: --Higher reliability because of the smaller number of contact connections, the limited number of materials which are used as well as because of the fact that a semiconductor IC can be fabricated only from a monocrystalline, ultrapure semi- conductor structure; --The great mechanical strength as a result of the smaller dimensions (approxi-~ mately an order of magnitude) of the components; --The lower production cost of semiconductor IC's becauae of the more efficient utilization of the advantages of group technology. --Bipolar and unipolar (field effect) integrated circuits can be used as the active elements in semiconduc~or integrsted circuits. Semiconductor IC's (especially digital) with bipolar transistors are dis2inguished by the higher pulse speed (or ~orking frequency). Semiconductor digital IC's with f ield effect transistors having an MOS atructure are distinguished by the maximum packing density of the components and the least production cost. Analog IC!s , with field eifect devices have a high input impedance (more than 109 ahms) and can be quite economical in terms of the power consumption (microwatts). Uni- polar transistor technology makes it poasible to achieve better noise character- istics. Bipolar transistors increase the operational stability of cir.cuits in a wide range' of temperatures, make it possible to realize the maximum operational speed and - to design circuits with better load capabilities. Bipolar structures stand up better to electrical loads. It must be noted that the capabilities of unipolar structures are as yet far from completely uncovered.(they are especially good for future radio frequency devices and operational amplifiers). Because of the complexity of the equipment and the stringent requirements placed on the producti.on conditions for semiconductor IC's, their manufacture becomes economically expedient only in the case of mass production (millions of piece~ per year from one p~uipment complex). For this reason, in terms of semiconductor technology, it is expedient to fabrinate the following: digital IC's and IC's = for the realization of standard analog functions, as well as high re3~iability integrated circuits for the deaign of equipment with maximum component packing density. -25- FOR OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY 2.2.1. Materials for the Components of Semiconductor IC's and Their Manufacture Wafers of monocrystalline p or n type silicon are used in the majority of cases for the fabrication of semiconductor IC's, where these wafers are provided with epita~cial and so-called "hidden" layers. Compounds of boron, antimony, phosphorous, aluminum, galliwm, indium, araenic and gold are used as the doping impurities, by means of which the conductivity of the original material of the xaa~er is changed. AZuminum and gold are used to make interconnections and con- tact pads; silicon dioxide and polycrystalline silicon are used as dielectric coatings and insulation for elements. The materials used should have a very high purity: the impurity content in the majority of materials used in the manu- facture of semiconductor integrated circuits should �not egceed 10-5 to 10'9 . parts of the base material. By cha.nging the doping impurity concentration in various parts of a monocry~tal- Iine semiconductor wafer in a definite manner, one can obtain a multilayer - structure, which performs a specified electrical function and corresponds to a " known extent to that equivalent to a discrete resistor, capacitor, diode or transistor [8]. ~ The prc,cess of manufacturing modern aemiconductor IC's is extremely complicated. It is carried out only in special hermetically sealed rooms using specialized equipment. The major production proceas operations for the fabrication of semi- conductor aircuits can be broken down into six steps. 1. The mechanical treatment of ~he silicon. Circular wa~fiers with thicknesses of 250 to 400 um are separated from a cylindrical rod of monocrystalline silicon with a diameter of 60 to 100 mm ~in this operation, the thickness of the disturbed surface layer of the single crystal can exceed 80 um). Cutting and polishing of the wafers is carried out to remove the disturbed layer, as a result of which, the thickness of this layer is reduced to 1 to 2 um. Chemical etching is employed for the final finishing of the wafer aurface. n n 2. Epitaxial growth. The term epitaxy means a process of the oriented growth of a crystalline lattice of silicon on a inonocrqstalline wafer through the deposition of layers. When additional impurities are introduced, it is posaible to obtain epitaxial layers ~films) with a specified type of conductivity ~for example, one can obtain an epitaxial film~;with p-type conductivity on an n-type silicon wafer). The epitaxial layer, which takes the f~rm of a monocrystalline extension of the base material, has no mechanical defe~.ts or str~sses. Epitaxial growth is accomplished in special furnaces at temperatures of about 1,200 �C. The buildup rate of the film thickness is on the order of several microna per minu te . Epitaxial films 10 to 15 um thick are the most widelq used at the present time, however, to produce modern semiconductor digital IC's with a fast operating speed, the film thickneas must be reduced down to a few microns. -26- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000540080030-5 FOR OFFICIAL USE ONLY 3. The oxi.dation of the wafer surface. Oxidation of the wafers in an oxygen atmosphere or water vapor at temperature s of 1,000 to 1,300 �C is used to protect and mask the silicon surface during diffusion operations. The thickness of the built-up oxide ia on the order of one micron. 4. Photolithography. A set of photolithographic processes is repeated several times during the production process for the manuf~cture of semiconduc~or integrated circuits (from 3 to 14 ':imes). Each ti.me, a thin layer (about one micrometer) of a light sensitive emulsion is applied to the oxidized silicon wtfer: the photo- resist, which is exposed through a negative with the image of the mask (in contrast to conventional phototoagnification here, with a reduction). The requisite "windows" in the silicon oxide surface can be "opened up" in the photoresist after developing. The silicon oxide is etched away in these windows by a mixture of aumnonium fluorxde and hydrofluoric acid, and the silicon surface is thereby aelectively exposed. 5, Diffusion. This process is carried out in apecial diffusion furances at a temperature of about 1,200 �C using special doping impurities. The following diffusants are used to obtain n-tqpe conductivity: phosphorous, antimony, arsenic; boron, gallium and indium are used to obtain p-type conductivity. 6. Making interconnections. To create the "hook-up wiring" between trie elements on the semiconductor IC substrate, the ailicon wafer, which ~he elements formed on it (transistors, diodes and resistors), is coated with a Iayer of pxecipitated aluminum 0.5 to 2 um thick, which is then etched away at the unnecessary points through the corresponding windows in the photoresist (following the final photo- lithography operation). In this case, the outline of the connecting aluminu~ conductors, having a width of about 10 um, as well as the contact pads, remains on the semiconductor surface. . Several differents kinds ef production processes, which differ primarily,in the techniques used to vroduce the insulation between the individual integrated circuit components, are used at the present time in the electronics industry to make bipolar transistor semiconductors IC's. Planar epitaxial technology with the insulation of the components by means of reverse biased p-n junctions is the most widely used. Drawbacks to this method ~f insulating structures are considered to be the increased values of rarasitic capacitances and leakage currents between individual components, as well as their considerable area (taking into account the areas of the insulating regiona), the relatively low breakdown voltagea and the poor radiati.on immunity. How~ever, structures with p-n insulation are the simplest to manufacture. In isoplanar technology, the componente are insulated by means of etching groovea between the elements with the aubsequent thermal oxidation of the surface of these grooves. In this case, the layout density of the components is almost doubled, the radiation i~unity is increased as well as the IC reliabilitq, and the percen- tage yield of good integrated circuits is also increased. Polyplanar technology provides for filling the gaps between the components with - polycrystalline silicon, which makes it possible to increase the component ' -27- FOR OFFICIAL USE ONL`~ APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ~NLY layout density even more (by a factor of three times more than in the planar process), and to reduce the parasitic capacitances between the components and increase IC realiability. Technology utilizing anisotropic etchir.g of the grooves ~etching along the crystallographic axes) makes it possibie to obtain an even greater component layout density. The considerable diversity of technology pmcesses (both aimpler and more camplex than bipolar) is used when manufacturing semiconductor IC's with MOS structures [10]. MOS structures are formed with three layers: the metal ~M is the gate), the Si02 oxide (0 is the gate insulation),~and the semiconductor Si (S - the regions of the source, channel and gate). Standard technology ~metal gate with - single Zayer dielectric insulation about 100 um thick) makes it possible to _ manufacture MOS transistors both with a p-channel and an n-channel (in the first case, the charge carriers are holes, and in the second, they are electrons; for this reason, n-channel MOS IC's have a faster operational speed than p-channel - devices). The working frequency of digital MOS IC's, made using standard tech- nology, does not exceed 1 to 2~btEiz, while for analog devices, it is ~300 to 500 MHz. A two-layer dielectric is used in MNOS integrated circuits between the metal gate and the semiconductor: a layer of silicon dioxide about 50 um thick and a layer of silicon nitride (N) 10 ~to 20 Um thick. The MNOS structures have a reduced threshold voltage as compared to atandard MOS structures. A progressive technology using silicon gates ~regions of heavily doped eilicon about one micrometer thick) is also used to boost the operational apeed of MOS IC's. Using this approach, the speed of digital IC's has been successfully in- _ creased by a factor of three to five times, and the threshold cut-on voltage fQ~r ~ a switch has been reduced while the component layout density has been increasec3 by a'factor of 1.5 timea. The manufacture of MOS IC's on insulating substrates ~sapphire or spinel with an epitaxially grown layer about one micrometer thick) makes it possible to increase the speed of such IC's at the present time up to 100 MHz (up to 250 MHz in the future). The use of transistors ~aith different polarities (p-channe2 and n-channel) as part of MOS IC's makes it possib~e to create digital IC's with relatively high speeds ~up to 20 MHz) with a very low static power consumption (the product of the power con~umption times the speed has a level of about 1 pJ). These atruc- tures are called OMOS.(the letter C comes from the word complementary). - The fabrication of MOS IC's using double diffusion (first the p-channel is made, and then the n-layer in it) makes it possible to reduce the channel length down to one to two micrometers ~using atandard t~c':~nology, a chaanel cannot be made _ with a length of less than 5 um). MOS transistors which oscillate at frequencies of up to 10 GHz can be manufsctured based on gallium arsenide. In digital engineering, switches with a aignal delay time of less than 1 nsec can be obtained using such integrated circuit transis- tore. - 28 - FOR OFFICIAL USE ONI.Y APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR OFFICIAL USE ONLY 2.2.2. The Fabrication of Integrated Circuit Structures Planar epitaxial technology is the most widely used in the production of transi:s- tors on semiconductor wa~ers (it is also used for the manufacture of modern discrete transi:stors). The difference in the characteristics of the transistors of semiconductor circuits and "conventional" transistors can be due to the proper- ties of the insulating region, in which the transistor is located on the semi- conductor circuit chip, as well as to the arrangement of the collector lead (in integrated structures, it is almost always the "top" one). Integrated circuit diodes are easily made based on transistor structures. The emitter-base and collector-base junctions of transistor structures can be~_used as diodes. In some cases, t~e emitter-base junction can also operate as a stabilitron (Zener diode). After forming the p-n junctions, it is necessary to make the contact!.+pads at the requisite points and to connect the separate components of the semiconductor IC together. If the p-n jun~tion was produced by means of diffusion, then it is necessary to apply a metal layer to the aurface of the semiconductor wafer to obtain a good contact. This can be done, for example, by vacuu~ deposi~ion. After fusing the metal into the aemiconductor, low reaistance p or n-n struc- tures are ~ormed. The external leads are secured to the metal contacte by meana of thermal campression. One can avoid deposition an the ffietal cont$cts during tl~e epitaxial growth process by introducing, where n~cessary, heavily doped p+ or ' n layers. Then the external leads can be connected directly to these layers using the same thermal compresssion. ~ Separate working components are connected together or to the contact pad8 by means of depositing aluminum in a vacuum on the semiconductor wafer aurface , which is oxidized beforehand, and in which windowa are etched Chrough to make contact with the aemiconductor structure. The region between any pair of ohmic contacts on a semiconductor wafer can be used as a resistor. The resistance of such a resistor will depend on the length and cross-section of the region, as well as the specific resistance of the material. It can be calculated using the idfferential Ohm's Law. , Since the current in such a bulk semiconduntor resistor will flow through the - body of the semiconductor, the resistance of the resistors are lesa eubject to the influnece of external conditions than the ree~stance of film resistors. The temperature coefficient, depending on the doping impurity concentration, can differ, however, as a rule, it is high and is positive. The resistance of three- dimensional semiconduct~r r~sistoa~ ia limited only by the dimensions of the semiconductor substrate and in practice can run up to 40 KOhms. Resistors which are made in the volume of a semiconductor chip are frequently used as thermal compensating resistors (with respect to the region where they are located it~ actual circuits, they are called collector resistors). So-called "base" resistors (they are fabricated simultaneously with the base n-p-n regions of integrated circuit transistors) are more well known. This is = the major type of diffusion resistor, in which the conducting channel ie of p-typ~ ~ _ -29- - FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY ~ conductivity. Such a channel is "bordered" by the n-region. After the supply voltages are applied to the chip, the insulating p-n junctions cut off and the current cannot overflow from the resistive channel into adjacent regions. Addi- tionally, pinch resistors are widely used in IC's; these are nonlinear resistors which are "compressed�1 on the top by a cuteoff p-n junction. They are high resistance devices and do not have a"conventional" equivalent" this is a f ield effect transistor with a small transconductance). A three-layer p+-i-n+ structure can be used to create capacitors with a amall fixed value of the capacitance in semiconductor integrated circuits. ~ao layers of such a structure are very heavily doped with the appropriate doping impurities. The middle layer is undoped material. The capacitance.of the p+-i-n+ structures is determined by the thickness of ~he undoped layer and depends little on the inverse voltage level. A reverse biased p-n juncti~n is frequently used as a amall value capacitor. The dielectric in such a capacitor is the junction region depleted of carriers. For any semiconductor, capacitance will be a function of the width of the depletion zone and the junction area. When silicon is used, one can ob tain a specific capacitance of a p-n junction of up to 200,000 pFd/cm2 for a breakdown voltage of several hundred volts. Since the width of the depletion zone depends on the applied voltage, the capacitance of the p-n junction is also a nonlinear function of the voltage. Capacitors based on a p-n junction are polar capacitors, and for this reason they are not suitable for use in circuita with an alternating component. The latter drawback can be eliminated if two series connected p-n junctions are used. The capacitance of such a structure becomes independent of the working voltage polarity and depends little on its amplitude. - We shall treat in more detail some of the specific features of standard integrated circuit structures. The typical structure of an epitaxi~l diffusion transistor of a semiconductor IC is shown in Figure 2.1. Five diffusion layers are indicated in the vertical section through the structure. The emitter, base, epitaxial collec~ tor, hidden fusion n+ layer and the chip ~substrate). The specific resistance of the p-type chip is 10 Oh � cm. The epitaxial n-type layer which is 25 um thick, and built-up o* the surface of the chip, has a specific resistance of 0.5 Ohm � cm. The n+ diffusion layer ~usually arsenic) with a high concentration of doping impurities (more than 1019 atoms/cm3) is placed beneath it. The electrical xnsulation of the collector region fraa adjacent traneistors (when a positive voltage will be applied to the circuit relative to the subatrate) is assured through the presence of a deep separation diffusion region of p-type doping i.mpurity through the epitaxial layer to the chip. This diffusion is accomplished~~first. The base is formed during the second diffusion of the p-type dop ing impurity into the epitaxial region of the collector (during this same time, the base and pinch resistors are made). The typical value of the resistance of the layer formed during the second diffuaion (for example, with bAron to a depth of 2.7 um) amounts to 200 ohma/(] The emitter is the n-type region which is formed during the third diffusion (for example, of phosphorous) into the base region to a depth of about 2 um. The resistance of the emitter layer amounts to -30- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2047102109: CIA-RDP82-00850R400504080030-5 ' FOR OFFICIAL USE ONLY r - . 6~5 (1) Emitter ~itter . ~ - - ,Qv~i3uoyHan aNUn~mev B~ee ~ ~ aton~u~ s ~ ) AO p ~ ~ . .~rr o~'~'f�ector ~ I ~ + ' a v.' I ~ ~ p , 26,4 ( ~ . ~ ~ _ _J ' ~ - , ~ . ( 3 ~a~~amw~rt~ ~4 (4 ) A2~n~P ~ . Figure 2.1. Structure of a tranaiator ueing p-n junction inaulation fplanar technology). Key: 1. Diffusion insulated~p-region; 2. Base;~ 3. Diffusion insulation; 4. Collector. approximately 2 ohms/ Q,. The doping depths of the ~nctiona are: 2 um for the emitter-base junction; 3 um for the collector-base junction and 25 um �or the collector-chip junctinn. The plan view configuration of the traneistor ginea an idea of the dimensions of the structure on the ch~p surface. The emitter ia the diffusion region with a rectangular ahape haviag dimeneions of 25 x 40 um. It is ~ formed after the diffueion of the n-dpping impur�ity into the region of the p-base . (the base area is 64 x 102 um). The electrical contacts are made to the emitter, base and collector regions using aluminum metalization; the emitter contact ie made with stripline metallization 12.5 um wide. The contact with the base is formed by means of two strips arranged on bo.th aidee of the. emitter. The contact is made to the collector with a rectsngular metallized strip; it completely aurrounds the diffusion collector-base junction. As.can be concluded from an analysis of.the topology, a considerable portion o~ the semiconductor aurface is uaed far the itnr sulation of adjacent structures ~ram each other by zhe segaration diffusion region, which is run to a depth of 25 um. When the diffusion process is three- dimensional, the doping impuzity atoma di~�u8~ not only into the depth of the material, but also "leak out" in lateral directions. The @iatance to which doping impurities propagate in lateral dicectiona. is also ap.proximately 25 um. Such technology does not allow for attaining a high degree of canponent laqqut deneity on a chip. , - 31 - : FOft OFFICIAL USF ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR OFFICIAL USE ONLY The refinement of the fabrication technology for IC's witr. a h~.gh component laqout density on a chip is more or less related to the passive. i.r~ulation.of the elements, i.e., to the replacement of active regions of p-n junctions, which electrically- insulate active devices -in conventional bipolar integrated circuits with any kind of dielectric material. One of the f irst developments was the technique in which electrical insulation of the elements on a chip was accomplished ~y a thermally grown silicon oxide. In this technique, a layer of silicon dioxide is used as the dielectric insulation instead of diffusion regions ~Figure 2.2). The silicon dioxide forms the walls in the case of dielectric insulation as well as the bottom of each integrated circuit component and the structure is placed in a dielectric "pocket" (because of this the ~lectric leakage is low). Such technology makes it p~ssible to obtain higher volta~e integrated circuit camponents on a chip than in the case of insulation using p-;i junctions, however, the final advantage gained in terms of structure area is amall. - ~ ~ Figure 2.2. The sequence for the fabrica- tion of a transistor structure , ~ using the dielectric insula- tion technique ~the "epic" n process): a~~a) . e d~ a. Preparation of the wafer surface; " b. Deposition of the n+ layer 6~ ~b) and t'ne masking oxide; c. Masking and etching of the ~ ~n ; insulating depressions; ~ d. Dielectric oxide build-up; el ~f~ e. Deposition of the poly- crystalline silicon; f. Shaping of the wafer and ~ , polishing; a g. The final structure of the z~ (c~ ) ~rl , wafer. The polyplanar process is a further development of technology using silicon dioxide insulation of the elements. In it, the surface of the insulating groove is coated with silicon dioxide, while the grooves themselves are filled with poly- crystalline silicon, forming a smooth surface on the ch ip. The smooth chip surface makes it possible to use standard metallizati,on, simplifies the layout of the intersection of conductors at various levels and improves the overall reliability of the IC's. The polyplanar process, just as the process using p-n junE~ions for insulation, starts with the selective formation of hidden diffusion n+ type layers on p-type chip ~Figure 2.3), after which an epitaxisl n-type layer is grown on it. , Then a layer of oxide is i~uilt up on the chip, in which, by means of standard photolithographic techniques, windows are etched out underneath the inaulating -32- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080034-5 FOR OFFICIAL USE ONLY regions. Anisotropic etching of the silicon i8 carried out in the (100) crstallo- . graphic plane in the unprotected areas to form the insulating depressione. The depth of thd depressions is governed only by the g~eometric width of the hole in the masicing material on the surface of the silicon. Then a layer of silicon dioxide is grown in the resulting depressions where this layer is sufficiently thick to produce the requiaite electric insulation.� After this, in contrast to d~ther processes which are based on etching the depresaiona, polyc~ystalline silicon is deposited on the surface of the chip, which completely fills th~ depressions. The excess silicon is then polished away as a result of which, a smooth chig surface remains. At this point in time, the side walls of the structure are campletely formed and all subsequent production process operations do not differ from the atandard ones gdopted in planar epitaxial technology. n- n~ ~ (a) Figure 2.3. The sequence for the fabrication of; a tranaistor atructure using poly- crystalline silicon insulation - " ~ 6) (polyplanar technology). a- (b) sinz sint Key: a. Selective formation of the n+ hidden diffusion layer and B) the build-up of the n-type epitaxial layer; (1 nna~rour,ma~nnver.Ku K,vr~HUv b. Masking and etchiag of the insulating depressiona; n- a) c. Build-up of the inaulating ~~n P_ ~d~ oxide; onuKtNrcinnnii vucyu d. Deposition of the polycrystal- (1) .~uenHU`~~.. line silicon; n- e. Removal of exceas ailicon; `R`'p- (e~ 1. Polycrystalline silicon. Small dimensions of the componenta are characteristic of polyplanar technology. The oxide grooves are separated fram each other by a apacing of 10 to 15 um. With such a technology, the area needed for creating an element is limited only by the thickness of the epitaxial layer and the minimum width of the insulating groove. Given the condition of optimization of technoloqical process parameters, the area occupied by an element for a random access memory can amount to ~bout 0.004 mm2. The use of polyplanar technology has made it posaible to significantly boost the layout density and reduce the sizes of chips as compared to the capabilities of standard technology. Thus, bipolar n-p-n tranaiators, together with the insulat- ing region::surrounding them, can have an area of about 0.3 � 103 Um2. The area of the planar epitaxial diffuaion tranaietor shown in Figure 2.1 ia approximately 55 � 103 um2. ~ -33- FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR OFFICIAL USE ONLY For comparison, we shall give figures which show the layout density of inemory elements with insulation using p-n junctions, dielectric insulation as well as polyplanar insulation. A polyplanar matrix of inemory elements with a capacity of 1,024 bits can be placed on a chip with ar ~:.�pa of 2.6 mm2; while for the same matrix with dielectric insulation a chip with an area of 4 mm2 is needed and for a matrix with p-n junction insulation, an area of about 5.2 mm2. Standard iso ~lanar isoplanar technology makes it possible to obtain transistors with the smallest dimensions by virtue of the capability of producing thin base regions and small collector regions with oxide side walls [11]. The process of creating an isoplanar structure ~Figure 2.4) begins-with the formation of the n+ regions in the p-type silicon wafer. Then, a thin p-type epitaxial layer is grown over the entire surface of the wafer. The built-up epitiaxial layer is coated with a layer of silicon nitride from which a protective mask is formed to make the transistorsand resistors. The regions not protected by the nitride are etched away to a relatively great depth: down to almost the hidden layer. After this, lor~z term low temperature oxidation is carried out, as a result, the deep etching regions are filled with insulating oxide, while the region coated with nitride remain unoxidized. To make contacts to the collector regions, deep n+ diffusion is carried out. For this, the nitride is selectively etched with the correspond- - ing areas of the silicon, which are practically untouched by the insulating oxide. The deep diffusion regions prove to be surrounded by the insulating oxide, which _ separates them from the base regions of the transistors.. After creating the resistive regions, the nitride remaining on the wafer surface is etched away and replaced with oxide. Emitter windows are formed in the oxide in i~hich the dif-- fusion is carried out. Then the contacts to the base regions are opened up, the aluminum is de~osited and with its etching, the formation of the structures is completed. The further refinement of this tec:hnoZogy will make it possible to obtain trans- ~ istors with areas twice as small as campared to the original technological process through the capability of fabricating not only the base regiuns, but als o the emitter regions directly adjacent to the oxide regions. The reduction in the area of the transistors fabricated using isoplanar technology is illustrated in Figure 2.5. The isoplanar process providzs for th~ creation of structures with a high layout density, since with a minimum nwnber of technological variables, there is the capability of substantially reducing the dimensions of the inaulating region. In this case, the surface resistance is quite high, which makes it possibel to obtain optimal electrical parameters for the IC's. 2.2.3. Separating a Wafer into Chips and Mounting the IC's From several hundreds up to thousands of chips are fabricated simultaneously on a semiconductor wafer. The electrical parameters of the IC chips are measured even on the uncut wafer, and the nonoperating IC's are marked with paint [12]. -34- . FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY _ ~biunur~rcua~m~zrd (1~~ ~~yd6Kdp ~~e.wcm 3~urra~i~d ,v-cnou ~ (3)~ ` ~7 (5) A?v . , nf n Qx ~ ( Q ) p-nnrlCmuHa n+ a (7 )p ~nrrarar,w . ~ 8 ) I/umpud 3m~mdkcudnll~s~daJ ~ ~ NDBMHUA ~R~'~S ~ 5) D~u~e ~ir . 8 ~B - - ' + p-nnrrcnxhvd ~ i0 ) p-nnrci~xr~ . ~ 6I ~b) ~ a~ ~d) Figure 2.4. The sequence for the fabrication of a transistor structure using isoplanar technology. Key: a. The formation of the epitaxial laqer; b. The etching of the insulating regions; c. The formation of the insulating oxide and deep diffusion; d. Fina1 metallization; 1. Epitaxial p-layer; 2. p-wafer; 3. Deep diffusion; 4. Phc?toresiat; 5. Epitaxial layer; 6. Nitride; 7. p-wafer; 8. Silicon nitride; 9. Etching; 10, p-wafer. _ _ _ ' "Isoplanar I" "Isoplanar II" �1/,~o~dyap I" �Nao~naHap p'" 44,5yxM 44,Srnvy ~..~w~~.. ~..r~..~.~~.. .~~~~r~r ' ?3HKH 1 ~ ~13rnrn? ~ ~ i i~ ~ - ' 6 3 K j~ i~ 6 K ~ h~. . B C 1~ ~ ~ ~ >z roay � ~y: ( 2 ~~1,5MAfM ' /1/lOIVl0Eb2 ~ 1 ~ ( L ~ - - - 1600NirrL ^ Figure 2.5. A comparison of the areas of:memories made ueiag "Isoplanar 1" and "Isoplanar 2" technologies. Key: 1. Area of 1,600 um2; 2. Area of 1,130 um2. -35- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ON~.Y Prior to breaking the wafer into chips, it is glued to a special film, which maintains the mutual positioning of the chips following the separation and priot to the operation of mounting the~ in a package. The separation of a wafer into individual chips can be accamplished in various ways. Scribing and breaking the wafer are accomplished by applyiit6 a grid of lines on the surface of the wafer using a diamong cutter with the subsequent breaking of the wafer alo~g these lines with ~the application of bending forces.(the method is similar to that of cutting glass). After separating the wafer, some o� the "rectangles" can have visible chipped places, cracks and~~other defects. This is a frequently used and the simplest method of separating wafers. Equipment exists for making the grooves by means of a high energy laser beam with subaequent "cleaving" of the wafer. The marked nonoperating IC's are rejected right away while the remaining chips are inspected under a microscope (especially the points where there are chipped places). The chips are mounbed on the metal bases of the packages by means of brazing with the formation of a gold eutectic compound. In glass or plastic packages, in which there are no metal plates in the bases of the packages, the chips are fastened to the support frame with easily fusible glass in an inert gas atmosphere at a temperature of up to 525 �C. Then the output bonding pads for the internal leads of the package are installed. 2.2.4. The Hermetic Sealing of IC Chips To protect the elements of an IC (eapecially if the IC will be delivered as an unpackaged unit) against exposure to the external environment (imoisture, duat, mechanical loads), its chip should be hermetically sealed. The simplest hermetic sealing can be produced by coating the chip (or hybrid OC board) with a thin layer of protective varnish or compound (conformal coating). To protect IC's, one must use organic potting and coating materials which have ~ood electrical insulating and moisture protective properties, resistance to exposure to elevated temperatures and to the cyclical actions of low and high temperatures, as well as have no incluence on circuit paraneters, be elastic and reparable. The selfwlcanizing elastic type KL compounds based on low molecular weight silicone SKTN and SKTI-1 rubbers can be recommended, where these operate in a temperature range of from -60 to +300 �C and under conditions of elevated humidity, as well as type PEK hermetic sealing campounds based~'~on epoxy resin, modified with carbosilate rubber and polyester. These compounds are distinguished by their stre~gth, elasticity and freeze resiatance and provide for stability of the para- meters are well as i~munity to thermal ahocks and long term exposure to elevated humidity. Used as the materials for moisture protection are the SB-ls, UR-231, UR-930 and E-4100 varnishes, the EP-096 epoxy�cresol varnish, the K-47 and K-57 silicone varnishes, as well as the EP-~74T, EP-91, EP-92 and EP-9114 epoxy - enamels. K-18, viksent [sic] and MBK campounds are uaed to protect the surfaces of chips. All of the materials enumerated above possess good electrical insulating proper- ties: a volume resistance of p~1011 to 1013 ohm � m, a dielectric permittivity -36- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFF[CIAL USE ONLY of s= 3 to 5(at a frequency of 1 MHz), tan 8< 0.005 to 0.01 (1 MHz) and an electrical strength of 20 to 90 KV/m. However, conformal coatings which make it possible to create so-called unpackaged IC's do not proyide the requisite protec- tion against exposure to the external environment and can be used only in conjunc- tion with overall vacuum type hermetic sealing of the entire electronic unit or piece of equipment. For reliable protection against exposure to the envirot~ment during operation, the chips or boarda are packed in sealed packages. 2.2.5. The Manufacture of IC Packages As was indicated above, the major �unctaon of the package is to protect IC elemente against the influence of the environment, assure normal operation of the IC during the entire service life and provide reliable mechanical and electrical bonding of the board or chip to the other elementa bf the electronic assembly. The following requirements are placed on an IC package. The package should assure the requiaite electrical connections between the circuit elements and the leads, and at the same time guara~tee electrical insulation between the individual leads. The package atructure should provide for heat sinking from the IC chip; the package should be made of materials which are inert with respect to chemically corro~eive com~ponents in the environ~ment ~for example, oxygen, moisture and salts; in some cases, possible electrochemical processes . should be taken into account, such as corrosion in the presence of electrolytes). Moreover, the package should be sL..:ficiently strong to protect the IC elements against various kinds of damage during mounting and operation, but the package structure should be well suited to manufacture afld applications ~for this purpose, one must strive towards universality of the processes of mounting the ~C's in equipment). The package should have a cotrvenieat structure for printed circuit mounting with respect to the dimenaions and the arrangement of the leads. Also of no small importance is the fact that the package should protect the IC chip against the influence of light (and where possible, other external radiation), as well as absorb the natural radiation of the circuit componente themselvea and serve as a shield against external magnetic fields (or create a path for shorting the magnetic flux). Four kinds of structural and production process designs of IC packages are the most widespread. The metal-glass package has a metal cap and a glass ~or metal) base with the leads insulated and secured by means of glass; the cap is attached to the base by welding or soldering. The metal-ceramic package has a metal cap and a ceramic base; the cap is connected to the base by potting with a moisture resistant compound. The ceramic package has a ceramie cap and base; the Gap is connected to the base by soldering. The plastic pa~kage (the Ieast expensive) has a plastic body, wY?ich is produced by mea~s of compresaion molding of the chip and the frame framework for the leads. ~ The complexity of fabricating IC packages increases with increasing functional = complexity of the IC's, where the cost of a package in a number of caaea becomes greater than the fabrication coat for the semiconductor chip (or the substrate with the film elements). When an IC is housed in a package, defects frequently -37- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR G~FFICIAL USE ONLY TABLE 2.2 Integrated Circuit Packages Tiesigna- Weight ~imensions , ~ tion in witTi ~ GOST ~ " 9ub- � Sub- I~iumber 17467-79 strate . strate of Basic Characteristics Package or~~hip Leads 1202.14 Rectangular, metal- 4.5 19.Sx14.5x(4-5) ~ 16x8 14 glass 1203.15 The same 4.5 19.5x14.5x~3-5) 16x8 15 1211.15 Tf:~e same 7.0 22.Ox19.5x5 17x15 15 1211.15 The same 12.0 29.Sx19.5x5 ,!2.17 15 1303.36 The same 12.0 29x19x3.6 't6x16 36 1209.29 The same 17.0 39x29ic5 ;14x20 29 2123.14 ~ Rectangular, plastic 1.0 19x7..2x3.2 ~x3 14 2102.14 The same 1.2 19.7.2x3.2 5.x3 16 2103.16 The same 2135.24 Rectangulax, metal ceramic 3.4 29x14.5x4 4x4 24 2204.48 Rectangular, ceramic 5.0 31x16.5x4 8x8 48 3101.08 Circular, metal-glass 1.5 D= 9.5, H= 4.6 3x3 8 3103.12 The same 1.5 D= 9.5, fl= 4.6 3x3 12 4104.14 Rectangular, metal- -glass 1.0 lOx6.6x2.2 4.9x2 14 4110.16 The same 1.0 12.Ox9.5x2.5 S.Sx3.5 16 4116.24 Rectangular, metal- ceramic 1.6 19.5x12x2.6 7.5x5 24 4132.40 Rectangular, metal- glass 6.0 35.Sx23.5x4.5 24x15 40 4136.48 Rectangular, ceramic 12.0 36x24x5 30x15 48 4137.50 The same 12.0 36.5x24.5x5 30x15 50 4140.64 Rectangular, metal- glass 20.0 54.5x38.5x5 30x24 64 occur which are related to the poor quality of the mounting or sealing of the packages. For this reason, two to three packagea are sometiaaes expended before obtaining a good IC. Standardization of the structural design of packages plays a great part in improv- ing the reliability of IC's and microelectronic equipment. At the preaent time, GOST 17467-79 [state standard 17467-79] "Yntegrated Circuits. Basic Dimenaions", isin force in the USSR, which establishes the requirements placed on the shape and dimensions of packages and integrated circuits (Table 2.2). In acco~dance with this atandard, packages can be of five types. An outline drawing of the structural design of a rectanga~:ar package with leads perpendicular - -38- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY to the plane of the base and arranged within the bounds of the projection of the package body onto the plane of the base ~a package of the first type) ie ahown in Figure 2.6a. The second type of package with rectangular leads, perpendicular to the plane of the package base and going beyond the bounds of the projection of the package body onto the plane of the base is depicted in Figure 2.6b, while a circular package witH~leads perpendicular to the base of the package and arranged within the bounds of :.he projection of the package body onto the�plane of the base (the third type of package) is shown in Figure 2.6c. Finally, a drawing of a rectangu- lar package with leads arranged parallel to the plane of the base and going beyond the bounds of the projection of its body onto the plane of the base (the fourth type o� package) is shown in Figure 2.6d. ~ -d- ~ -4- . - ? ~ ~ ~ ~ ~ ~ ~ ~ $$-4-4? ' 6)(b) 0 ~ ,o D O ~ ~8~ - ~ - - p ~ O _ O � . 7~r ' � Z~(d) ~ ` e) (c) ~ ~ ~ - ~ ~ ~ ' `e a) Figure 2.6. Outline drawings of package structures. The fifth type of package is a rectangular flat "leadless package". The electri- cal connection of an IC houaed in auch a package is accomplished by r~Jeans of metallized contact pads about the perimeter of the package (Figure 2.6e). Packages which are similar in terma of their structural design are broken down according to overall size and connecting dimenaions into standard sizes, to each of which a number is assigned which consists of the designation of the package subtype (12, 21, 31, 41, 51) and a two place number which designates the ordinal number of the standard size. - 39 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY The spacing of the leads for the firat and second types of packages ia set at 2.5 mm and for the fourth and fifth types of packages at 1.25 mm. The leads can ' have either a circular or reCtangular cross-section. 2.3. Specif ic Features of the Technology of IC's with a High Level of Integration Integrated circuits of the first and second levels pf integration (see �1.6) have made it possible to integrate the circuitry of traditional electronic equipment ~these I~C's appeared exclusively because of the influence of equipment problema). Integrated circuits of higher levels of integration are more the resslt of tech- nological "initiatives": these IC's run ahead of the needs of equipment and are yet another step foreward in the continuing and continuous proceas of the further zvolution of electronics [13]. The transition from the low level of integration IC technology to LSI technology takes place under the motto "From Circuit Integra- ~ tion to Systems Integration . For example, following the appearance of IC's of - the fourth and fifth levels of integration, i.e., where the numb er of elements ia more than 1,000 and 10,000, it became possible to produce new, quite complex func- tional assemblies such as memories and microprocessor aets on a single chip. The increase in the level of integration of atandard devices co incides with the group technique of fabricating IC's on a semiconductor wafer ~or dielectric sub- strate), where several hundreds of identical circuits are produced simultaneously. Then the wafer is cut apart and chips are obtained, each containing one simple circuit (in which case, very many chips are rejected). The good chips are mounted in a package, wnere the chip is connected to the extemal leads of the package. The equipment manufacturer, by using connections made outside the packages (for _ example, printed circuit conductora);again combines a considerable nu~er of identi- cal circuits so as to obtain the requisite subsystem or syatem [14]. It is obviously desirable to eliminate intermediate operations (cutting ti~e wafer, mounting the chips in a package, connecting the chips to the package leads, mount- ing the individual packages on a printed circuit board and connecting them to the printed circuit conductors). For this, one can leave the simp le circuits an the original wafer, provide them with a definite system of interconnections, and th�re- by combine them into a subsystem on the wafer itself. The overwhelming majority of defects in integrated circuits appear in the systems for transition contacts and interconnectiona. The contact pads of the chips are connected to the external package leada by means of thermal compression bonds. - The breakage of these bonds which are made using manual labor is a rather wide- spread type of failure. In semiconductor IC's of the third and higher levels of integration, the set of simple circuits which are joined together in a complex circuit is placed on a single chip and these circuits are connected together by metal lized aluminum tracks. It is clear that in this case the overall number of ex ternal thermal compression connecti~ns is basically reduced ~equal to only th e number of package leads), something which leads to an improvement in the reliability. The reliabi- lity is also improved as a result of reducing the dimensions of the IC as compared -40- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY to the dimensions of an assembly consisting of the corresponding nvmber of simple IC's, since the structure proves to be stiffer, less sensitive to vibration~;and shocks. Increasing the level of integration leads to a further increase in the layout density, to a reduction in the overall dimensions, and consequentlp the weight of radio electronic equipment assemblies, si~ce the percentage of the volume and weight of the equipmen.t allocated for the gaps between the IC'~s, the packages of the individual IC's and the printed circuit boards joining the IC's is reduced. By virtue of the more optimal design of individua3. circuita taking the specific loads and connections into account, it ia possible to reduce the power consumption of individual stages, which in the case of a high level of integration, cati yield an extremely perceptible gain. . _ With the increase in the level of integration, it becomes possible in practice to realize a high operational speed for individual (usually micropower) simple circuits, since this reduces to a minimum the parasitic capacitance of connecting conductors. However, increasing the level of integration entails an entire series of difficul- ties which are manifest at various etages in the design of the IC's. Thus, with an increase in the level of integration, the ICdevelopment time rises substanti- ally. The labor intenaity of the manual design of IC's can be approximated using the following formulas: the design time for analog IC's is T8 = 70 � N~�55; for digital IC!:s, the time is Td = 45 � N~�55, where T is the labor intensity of the design work in hours, while N is the number of elements in~the IC. The design process can be accelerated by using machine techniques. In the case of com uter assisted design, the design time is substantially curtailed; P= 22 � ' � Ng�22. The given functions were derived by Bulgarian specialists within the framework of scientific and technical cooperation of CEMA member nations. The introduction of camputer assisted design enCails considerable preparatory work: the acquisition of expensive computers, the development of the relevant programs, and the mastery of machine design methods. All of this requires con- siderable funds and time, and for this reason, there is a certain amount of dif- ficulty in the development of IC's of ~igh levels of integration. The actual capability of increasing the level of integration of IC's is tied to a great extent to the refinement of the production process quality in the process of manufacturing series produced products, i.e., to increasing the percentage yeild of good "conventional" products. The better the technological procesa is worked . out, the more stable are its parameters and operating mode, the higher the percent- age yield of good IC, and the greater the level of integration with satisfactory economic parameters that a new IC can have. ~ The process of ineasuring IC paramete~s poses considerable difficulty. In order to be sure of the requiaite quality of all series produced IC's, it is n~cessary to make a large volume of ineasurementa rapidly. For this reason, the quality control and measurement equipment needed for testing IC's takes the form of a complex automated system which is computer controlled. - 41 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR OFFICIAL USE ONLY For example, a measurement system for testing integrated circuits should feed 500-bit code combinations to the cireuit. There are systems which execute up to 1~0,000 tes~s on one IC at a speed of fram 20,U00 to 286,000 tests per second, where up ta 250 measurements can be made per second on each IC lead. Despite the indicated difficulties, the level of integration of IC's is increasing at a very fast pace in step with the development of the capabilities of technology. It is anticipated that such a trend will be maiatained at least until the 1980's. Thus, the number of elements on a single chip for semiconductor IC's may reach 200,000 to 1,000,000 in 1980. According to forecasts, the ulti.mate poasible density of components for both bipolar and MOS integrated circuits will be achieved ~ by the 1980' s. The reduction of bipolar transistor dimensions is limited by junction breakdawn, the "punch-through" and doping impurity fluctuation phenomena. For circuits which operate only in dynamic modes, the package densitq is limited by the power disaipa- t ion. The reduction of MOS tranaistor dimenaiona is limited by the breakdown of the gate- oxide gap and the "punch-through" of the drain-source gap. The power diasipation and migration of inetal particles limita the layout density of MOS IC s which oper- ate in a dynamic mode and complementary MOS IC's. For static circuits using MOS transistors with single polarity channels, the power dissipation is a major factor which limits the number of circuit functions on a chip ~and consequently, the number of elements). The theoretical limit for the layout density of MOS transistors on a wafer amounts to 10~ to 108 elements per cm2, and for bipolar transistors, is 106 elements per cm2. Three major trends in the long term increase in the level of integration of semiconductor IC's have been noted at tMe present time. First of all, there is a further refinement of temporary technological processes and the development of new processes underway. Thus, the transition from photo- lithography and diffusion of the doping impurities to the use of ion implantation and electron lithography makes it possible to increase the layout density of - elements by an order of magnitude and substantially boost the percentage yield of good products. The layout density is also increased by an order of magnitude when injection supply circuits are used. Secondly, an attempt is being made to change over to larger chips by refining the processes of photolithography and diffusion and improv ing the quality of semi- conductor material. Thus, wt~ile the majority of IC developed during 1970--1973 had chip dimenaions on the order of 1.5.x 1.5 mn, in 1973--1975 chipa of from 2.5 x 2.5 mm up to 6.0 x 6.0 mm whre being used and by 1980, it is planned that series produced IC's will be manufactured on chips with dimenaions of 10 m~n x 10 ~n and more. Finally, the techniques of IC design are being refined, new circuit design approaches are being developed ~for example, one transistor is used instead of -42- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 ~ FOR OFFICIAL USE ONLY three in the basic circuit of a random access memory, but it is equipped with capacitors), and injection logic circuits are being introduced. The level of integration of hybrid integrated circuits will be increased primarily through the use of ir~.creasingly complicated unencapsalated semiconductor IC's [15]. The possibilities of this way of increasing the level of integration are consider- able, while the use of unencapsulated microasaemblies makes it posaible to design radio electronic equipment of any degree of complexitq. We will note that at the beginning of the 1970's, progress in integrated circuit technology which had made it possible to sharply increase the level of integra- tion of semiconductor IC's, was most effectively used by designers of electronic computers and their assemblies, and primarily, by memory designers. We ahall con- sider a few examples of such devices. In 1975, the electronics industry started the production of main memories of 4,096 bits using MOS transistors made on a chip with dimensions of 4 x 4.7 mm and containing about 20,000 elements. Progress in computer miniaturization through the use of IC's is characterized by the following data: desk type 8 to 10-digit computers (calculatore) produced in 1964-1965 weighed more than 25 kg; in 1970, camputers using aeveral large acale integrated circuits weighed about 1 kg and in 1972, the production of pocket caI- culators just bne'IC in a11 was atarted, where theae calculators weigh 200 to 300 g. At the present time, the eight digit C'Elektronika B3-04" pocket electromic calcula- tor has dimensions of 120 x 78 x 20 ami, weighs 200 g and has a power conaumption of 600 mW. The pocket calculator is designed around four IC'~s which contain 7,000 MOS transistors. Calculators have been developed which perform four arithmetic operations, whieh are placed in a cigarette case, fountain pen and even in wrist ~ watches. Pocket calculators for engineers are produced at the present time which perform 20 to 40 and even more operations, including taking logarithms, calculating trigo- nometric functions and converting polar to cartesian coordinates. Thus, the "Elektronika B3-21" electronic pocket calculator ~a 10 digit calculator) carries out 30 standard functions and operations ~arithmetic, power, trigonometric, loga- rithmic and exponential). Moreover, the pocket calculator makes it poseible to program calculations ~up to 60 steps). The electronic portion of the pncket calcu- lator is designed around four IC's which consume less than one watt. At the beginning of the 1970's, the central portion characteristic of any computer, i.e., the processor ~admittedly., having trunckated irroperties as compared to the processor of a"large" computer) came to be placed on a aingle chip primarily at the initiative of technologists who were looking for ways to apply their achieve- ments in the field of producing r~egular semiconductor structurea. Such semi- conductor circuits were given the name microprocessors. Microproceseors, in con- junction w~th other IC's (read only and main memories, input/output devices as well as interfaces) form a finite microprocessor circuit, whieh is bui7:t on one printed circuit board. Both a conventional computer as well ae a apecialized control computer can be made from it. Integrated circuits of low integration levels were previously for the desi:gn of the central processors of computers. It has become possible at the present time - 43 - ~ FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY to execute the majority of central processor functions ~admittedlq, at low opera- tional speeds) by means of one or more third or fourth integration level IC's. . ~ Microprocessor sets (tTiree.to five packages) are the new "building block" of camputer design. It is interesting that the appearance of such sets has caused a . great deal of trouble of equipment designers;, who had tc~ change their traditional approach to the design of digital and even analog equipment. The majority of modern microprocessors operate with word lengths of 4 and 8 b its, using para'Llel processing in this case. The difference between microprocessors and single chip calculators consist in the fact t'r?at they are program controlled devices ~the permanent or programmable microprogram is placed in an individual IC of the permanent memory). The advantage of microprncessors consists in the fact that where they are used in a specific system, only a small number of IC packages is required, while adaptation for the solution of a new problem is accomplished by changing the control program. Not just computer circuits can be made in the form of co~nplex circuit configurations. For example, the digital circuitry for a voltmeter with f.our to five decades can be~placed on a single chip ~in this case, an IC having 24 leads contains binary decimal counters with a division factor of up to 100,000, a control circuit for the digital display, a control signal generator, a data erase control circuit and a five place ring counter). Electronic wrist watches have become nrdinary, where an IC generats the time markers, com~erts them to a decimal code and turns on the appropriate segements of the light diaplays through encoders. The electronic industry is producing IC's for digital dialing telephone sets having a memory of 32 eight-place numbers. The IC'is made on a 3.5 x 3.5 mm chip and contains about 3,000 elements. In the development and fabrication of integrated circuits with levels of integra- tion, ques~ions of materisls science, semiconductor device theory and the circuit design of radio electronic equipment asaemblies merge into a single set of problems, and for this reason, IC designers are also compelled to resolve certain design questions which previously ceme within the competence of radio electronic equipment designers. For engineers who specialized in the field of IC design, this leads to the necessity of the unique "integrating" of knowledge from various fields of science and engineering. It is important to note the initiating role played by IC's having an increased level of integration in the planning of subsequent generations of electronic equipment. It is hecoming possible to construct not just highly reliable equipment, but also equipment which will prove to be sutomatically adaptable to the external environment. BIBLIOGRAPHY 1. "Mikromoshchnaya elektroniica" ["Micropower Electronics"], translation from the English edited by Ye.I. Gal'perin, Sovetskoye Radio, 1967. -44- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY 2. Khamer D., Bigchers D., "Tekhnologiya tolstoplenochnykh gibridnykh integral'nykh skhem" j"Thick Film flybrid Integrated Circuit Technology"], translation from the English edited by T.D. Shermergor, Moscow, Mir, 1975. 3. Sergeyev V.S., Bozhenin I.N.,."Integral'nyye gibridnyye mikroskhemq" ["Hybrid Integr~ted Circuits"], Moscow, Sovetskoye Radio, 1973. 4. Gonorer M., "Mikroelektronika tolstykh plenok" ["Thick Film Microelectronics"J, translation from the English edited by T.D. Shermergor, Moscow, Mir, 1973. 5. Veyko V.I., Libenson M.N., rielyuchev A.M.. "Lazernaqa tekhnologiya" ["Laser Technology"], Moscow, "Elektronika" Instit~te, 1970. 6. Lebedev O.T., Ogivin M.A., "Konstruirovaniye radioelektronnoy apparatury na osnove integral'nykh skhem" ["Radioelectronic Equipment Design Based on Integra- ted Circuits"], Leningrad State University, 1974. 7. Ushakov N.N.,"Tekhnologiya elementov vychislitel'nykh mashin" ["Computer Component Technology"], Moscow, Vqsshaya Shkola, 1976. � 8. Medlend G., Diken G., Richardson R., "Integral'nyye skhemy: Osnovy proyektiro- vaniya i tekhnologii" ["Integrated Circuits: Design and Technology Fundament- als"], translated from the English, Edited by K.I. Martyushov, Moscow, Sovetskoye Radio, 1970. 9. Ivanov-Yesipovich N.K., "Tekhnologiya mikroskhem" ["Microcircuit Technology"], Moscow, Vysshaya Shkola, 1972. 10. Penin V., Lou L., "Integral'nyye ekhemy na 1~IDP-priborakh" ["Integrated Circuits Using MOS Devices"], translated from the English, edited by A.N. Karmazinakiy, Moscow, Mir Piblishers, 1975. 11. Taryankov S.A.,"Dielektricheskaya izolyatsiya elementov integral'nykh skhem" ["Dielectric Insulation of Integrated Circuit Elements"], Moscow, Sovetskoye Radio, 1975. 12. Yefimov I.Ye., Kozyr' I.Ya., "Osnovy mikroelektroniki" ["Principles of Micro- electronics"], Moscow, Svyaz' Publishers, 1975. ~ 13. Khambata A., "Bol'shiye integral'nyqe skhemy" ["Large Scale Integrated Circuits"J, translated from the Engliah, edited by B.I..Yermolayev, Moscow, Mir, 1971. 14. Gurevich D.Z., Yelizarov V.N., Ruvinskiy B.I., "Bol'shiye integral'nyye skhemy i EVPi chetvertogo pokoleniya" ["Large Scale Integrated Cir~uits and Fourth Generation Computers"], Moscow, "Elektronika" Inatitute, 1970. 15. Chernyshev A.A., Aksenov A.I., Ivanov V.I., "Beskorpusnyye poluprovodnikovyye pribory" ["Unencapsulated Semiconductor Devices"], Moscow, Energiya, 1973. -45- � FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFF[CIAL USE ONLY CHAPTER THREE DIGITAL INTEGRATED CIRCUITS 3.1. Designation and Application Digital integrated circuits (Tsls) are electronic devices which make it possible to construct practically all computer assemblies and circuits. In the over- whelming ma~ority of modern computers and digital devices, the data being processed is represented in tY?e form of binary numbers. The variables and functions of them which can take on only two values, 0 and 1, are called logic variables or logic functions. The properties of logic functions are studied in the algebra of logic, while the devices which realize the logic functions are called logic elements. The simplest combination logic elements occupy an important place among modern digital IC's which are being produced by the electronics industry in both packaged and une~capsulated variants, along with complex circuits which realize the functions of entire circuits and assemblies (adders, counters, registers, memory elements). Among the existing logic elements (potential, pulse and pulse-potential), potential logic elements have become the most wideapread, the distinctive feature of which is the existence of DC coupling between the circuit inputs and outputs. Direct coupled circuit designs eliminate the limitations placed on the lower signal frequency [1]. Circuit designs using the multiplicity of potential type digital IC's are realized on the basis of a number of standard basic functional components. The logic functions which can be realized using logic elements incorporated in the series of digital IC's and those which have found the most widespread applications in the construction of computer circuits and digital automation equipment are treated below [2, 3]. 3.2. Logic Functions Which Can Be Realized Using Digital IC's The simplest logic function is the NOT function (logic negation), which is written as Y(X) = X. The truth values of the function Y(X) which are obtained by means of negating the variable X as a function of the truth values of the latter are determined from Table 3.1. Such a table is called a truth table. TABLE 3.1 Ne~ation is realized in electronic circuits by means of a NOT switching element designed around an amplifying Negation device. The signals at the switch output are inverted de~ending on the values of the input signals and corres- x ?'t�r~=X pond to Table 3.1. There exist 24 = 16 different logic functions for the two variables X1 and X2, each of 0 1 which is determined by four possible combinations of the 1 o variables [1]. Four of the most widespread types of logic gates are listed in Table 3.2 as well as the functions they perform, their designations and names. Each of the cited logic funetions can also be extended to a larger - number of independent variables, while the logic elements which realize these functions can also have not ~ust two, but also n inputs. In actual digital -46- � FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY TABLE 3.2 The Most Widespread Types of Logic Elements and Their Functions~ Variables Logic Function R1~0 0 1 1 Function Element Performed R2I0 1 0 1 Designation ~ Y= X~XZ 0 0 0 1 Con~unction ~ NAND y- glg2 1 1 1 0 Sheffer function OR Y= Xl + X2 0 1 1 1 Disjunction NOR Y= X1 + X2 1 0 0 0 Pearce function IC's, which take the form of logic gates, the number of inputs is limited bq the number of leads in the standard packages, and as a rule, does x~ot exceed eight. Following conversion of the Sheff.er stroke and negation logic functions, the conclusion can b~ drawn that the function Y(R1X2) = X1X2 is derived from the Y(X) = X function by means of replacing the argument X in it with the other logic function Y(X1%2) = X1, X2. Such an operation is called superpoeition. Complex logic functions can be obtained by using superposition. The system of simple logic functions based on which one can derive any logic - function using only the superposition operation is called a functionaZly com- plete system. For example, the f,ollowing five systems will be functionally complete [1]: f _ _ _._N - ! y e j{' - orp uaexe~ Tl~g~1~~'ASi I Yo~(lX~ - KONb10HKUNR. .COAjl1Y1Cti~0A Lq Y~Xj.+.~(~ - ~f19b10HRQNA~ d3s~unctioa i J y~ Ji6' - o.rp+~~axNe~. 1~egatiOR . 1 }'oX1X~ - ~O,B7+IQNK[1RA~ CQt'~ilt~Ct~.Q~ (3.Z) ypx - orpRnaxae, R~g$t~on . . { y~X~.~a(~ aHSb10HHW1A7 d~u~3ct3~ C~�3j Y= X1R2 con3unction negation (Sheffer etroke functton); (3.4) y= Xl + X2 dis~unc.tion negation (Pierce.function). (3.5) The functions missing in systems (3.2) (3~5) can be derived on the basis of the well known rules o.f algebraic logic [1]. Each of the systeme indicated above can be realized by meane of the appropriate logic gates. Thus, it is sufficient to have one NAND (or NOR) logic gate in order to use it as the basis for the construction of the entire diverse set of logic circuits. However, � such an approach requires a large -~umber of digital IC packages f.or the realization of the computer units and assemblies. In practice, logic gates ; -47- ~ ~ FOR OFF~C[AL USE ONLY i APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000540080034-5 FOR OFFIC~AL USE ONLY are incorporated in a digital TC series which not only realize a functionally complete system, but also have considerable diversity as regards the number of inputs, which makes it possible to minimize the volume of hardware in equipment design. With respect to the kind of logic function which can be realized, the basic 1Qgic elements can be broken down into the simplest one-step (AND, OR, NOT, NAND, NOR) and two-step (AND-OR, AND-OR-NOT, etc.) logic gates. It must be noted that all potential type logic gates can operate in two logic modes. The logic function which can be realized by the same element depends on the designations assigned to the electrical levels. If the "1" level is taken as the high level signal, "positive logic" is realized in the operation of an (NOR) gate. If a low signal level is taken as the "1" level, then we have "negative logic" for the operation of an (NAND) element [1]. As a rule, the data sheet designation of the logic element corresponds to the function realized in the "positive logic" mode. Complex functional units of both a combinatorial type (half-adders) and with a memory (flip-flops) can be designed around logic elements with single and two-step logic. All of the modern series of digital IC's as a rule include various types of flip-flops, which take the form of a device with two stable states, containing a bistable memory element (the flip-flop itself) and a control circuit [1]. RS, D and JK flip-flops are the types which have become the most widespread. A RS flip-flop has two information inputs: R and S. When S= 1(the "one" input) and R= 0(the "zero" input), the following signals appear at the flip- flop outputs: at the direct output Q= 1 and at the inverting output, Q= 0. When S= 0 and R= 1, the flip-flop output signals assume the opposite states (Q = 0, Q= 1). This flip-flop does not ha~ve a cloc~C input. The truth table for a RS flip-flop is given in Table 3.3. With the simultaneous arrival of a"1" signal at the R and S inputs, the output signals of the flip-flop are indeterminate, and for this reason, it is necessary to preclude the mode in devices based on a RS flip-flop where both of the R and S signals are equal to one. The RS flip-flop (a bistable element) is present as the memory in other types of flip-flops. _ A D flip-flop has an information input D and a synchronization (clock) input. The state of the flip-flop after the arrival of the clock pulse at the point in time (t + 1) coincides with the level of the input signal at the D input which acted at the point in time t. The input signal is delayed in a D flip- flop [1]. The truth table for a D flip-flop is given in Table 3.4. A JK flip-flop has two information inputs, J and K, as well as a synchronization clock input. In contrast to the RS flip-flop, given the condition that J= 1 and K= 1, it inverts the previous state (i.e., reverses with the simultaneous arrival of J= 1 and K= 1). The truth table for a JK flip-flop is given in Table 3.5. -48- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 FOR OFFICIAL USE ONLY TABLE 3.3 TABLE 3.4 - Truth Table for a RS Flip-Flop Truth Table for a D Flip-Flop Time. t BpeMw t BPCM~ T~l@ BplMA f t BQd1A ~i-~ f11re1WAYWan 3ann~bdewas PesYr~bTat' ~j~ IIMKA! r?ayy? ~l~m~~opweunp et~OMteuxa Result ~oAY Bxo~1 tn ~rnK'~woe; ~rnyw. ~ 3` ~:HEOAI,~ ~ J3xoA6~ 5) �x~a Q D U Q ~ Q I Q R S Q ~ Q 0 1 0 0 1 p 1 0 0 0 l 0 1 1 1 0 0 I 0 1 1 0 1 0 0 0. 1 0 1 1 0 0 1 ~ 1 0 1 1 0.' 0 1. 1 1 X X 1 0 0 0 1 0 1 0 0 I 1 ~ , 1 0 1 u o ~ Key: 1. Outputs (after the clock 1 0 1 t X X ~ . pulse is fed in). � Key: 1. Preceding information; TABLE 3.5 2. Information being entered; Truth Table for.a JK Flip-FloQ 3. Outputs; - - 4. Inputs; Time B~A ~ r gv~"" t+~ 5. Outputs. BdxaJ~+ 1nxM Bm~oaW Bxoy~ ~~x raino. Out Inpu~$ saw ro~ny~ee.) ~ 1) It should be noted that besides the Q Q ~ I K Q ~ functional class3fication given above, distinctions can be drawn between 0 1 0 0 0 I flip-flops in accordance with the 0 1 0 1 0 1 manner of data entry [1]. They can be 0 1 1 1 1 . asynchronous, where the information is 1 0 0 0 1 0 entered directly with the arrival of 1� ~ 0~ 1 0 l 1 0 1 0 1 0~ the information signal, and clocked, 1 ~ 1 1 0 1 where the information entry is accom- nlished or_ly *h the fe~3 ;,f au � enabling clock pulse (fed to a special Key: 1. Output (after the clock clock input).'. The actuation of a fli.~- pulse is fed in). flop can occur simultaneously with the arrival of the clock signal or after it is completed. The operational principle of flip-flops will be treated in more detail in subsequent sections in light of specific types of IC's. The conventional designations (functional schematica) of the logic elements and flip-flops given above which are incorporated in the most widely uaed digital IC series and examples of their realization by means of logi~ gatee performing various functions are given in Table 3.6. -49- ~ FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY TABLE 3.6 Functional Schematics of Logic Gates and Flip-Flops, Examples of the Realiaation of Varipus Functions by Means of Logic Gates ~ Element Function Element Function (Circuit Performed Circuit Perf~ NOT (inverter) Y= X AND-OR-NOT (circuit Y= R1X2 + X3R4 (Figure 1) based on NAND gates) AND (con~unction Y = glg2 (Figure 7) gate) (Figure 2) AND-OR-NOT (Figure 8) Y= X1R2 + X3X4 NAND (~Sheffer Y= X1X2 Asynchronous RS flip- stroke functioa) flop (the inputs in (Figure 3) the R and S groups are coupled using OR (dis~unction Y= X1 + X2 ~ logic) (Figure 9) gate) (Figure 4) A JK f lip-f lop , ' NOR (Pierce func- Y= X1 + X2 designed on the prin- tion) (Figure 5) ciple of two stage AND-OR (circuit ~ Y= X1X2 + storage of the data based on NAND gates) XgX4 (the inputs in the (Figure 6) J and K groups are coupled using AND logic) (Figure 10) A D flip-flop with a contro~ input and R ("0"_set) and S ("1" set) output (Figure 11) ' r-- ~ A r XZ & r = P X f YI X2 . F ig . 1 Pnc. l PNC. 2 PNC. 3 Pxc. ~ 6 . X~ Fig. 2 Fig. 3 Fig, 4 Fig. 5, & 'r2 x~ 8 ! ~ y X y � , X3 !P . ~3 TT ' Xy , ' & ~ Pec.6 Pnc.B ~ X~ Fig. 6. Fig. 8, s, T ~ ~ x2 f f y , T D X3 & S K X4 S Fig. 7 R _ PHC.7 PHC.9 Pwe. 10 P~tc. 11 ' -50- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR OFFICIAL USE ONLY ~ 3.3. The Classification of Digital Integrated Circuits and Their Main Electrical FarametGis The development of microelectronics over the past decade has promoted the appearance of miniature, highly reliable and economic computers based on digi-~ tal IC's. The constant increase in the requirements calling for increased operational speed and reduced power consumption of computer hardware has led to the design of various bipolar digital IC's, the development of which, as a rule, is undertaken in series. A series is a set of I~'s which have a s3ngle circuit design and structural and production process technology. Incorporated in a digital series, along with combination circuits which perform simple logic functions and flip-flops (memory elements) are also integrated circuits which take the form of entire arithmetic assemblies and modules. The series of bipolar digital IC's being produced by the electronics industries are broken down into the following types of circuits according to the types of basic electronic switches: resistor-transistor logic (RTL), diode transistor logic (DTL), resistor capacitor transistor logic (RCTL), transistor transistor logic (TTL), and emitter coupled transistor logic (ECTL). In these designations, the word logic is substituted for the concept of electronic switch. Digital IC's using MOS structures (enriched channel p-type transistors, CMOS circuits using complementary transistors, etc.) have become widespread along with bipolar circuits. Although the RTL, RCTL and DTL series continue to be produced by industry, they are only used to put together equipment sets for series produced radioelectronic equipment and are not used in new designs. The TTL, ECTL and MOS circuits have become the most widespread in modern equip- ment. Experience has shown that fihese types of digital IC's are distinguished _ by better electrical parameters, are convenient to use, have a higher level of integration and possess a greater functional diversity. Thus, for example, about forty IC's are included in the 155 series, while in the K145 series there are IC's having more than 9,000 equivalent elements on a chip. The promising series of digital IC's of the types mentioned above, which are intended for applications in industrial and consumer electronics equipment, are shown in Table 3.7. , . As has already been indicated, the ma~ority of digital IC's incorporated in a series take the form of logic gates which perform the NOT, NAND, NOR and AND-OR-NOT functions. These are the so-called basic functional elements. Their main electrical parameters govern the characteristics of practically all of the IC`s included within the complement of a series. The possibilities for joint operation of IC's of different series in the same equipment depend on these parameters. A number of the ma~or electrical parameters are common to all types of digital IC's and make it possible to compare them with each other. Such parameters include the following: speed, power consumption ~pcon~~ the noise immunity (Un), the fan-out factor for the output (load capacity, Kout~ and the fan-in factor for the input (Kin)� We shall treat each of these parameters in more detail [1]. The speed is governed by the dynamic parameters of the digital IC, which include~the - 51 - FOR O~FICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000540080034-5 FOR OFFICIAL USE ONLY TABLE 3.7 Digital IC Series for Geaeral Applications in Industrial and Consumer E ui ment Number of IC's in the Series Series (1978) Function TTL Integrated Circui~s K155 76 Construction of computer asaemblies and medium speed digital automation hardware. 133 43 The same 130 12 Construction of htgh speed computer assemblies and digital automation hardware K131 11 The same 134, 734 30, Construction of computer assemblies and digital (unencap- automation equipment with a low power coaaumption; sulated) 8 The same 530 8 The construction of computer assemblies and digital R531 15 automatioa hardware with a high operational speed K555 12 and low pawer consumption ECTL Integrated Circuits 100 42 Conatruction of high epeed computer complexea K500 39 The same . 700 (unen- ~ 37 The same capsulated) --------------~~~------------.~~M__r------------------------------------- Integrated Circuits Using p-Channel MOS Transistors 50~ 8 The construction of main computer memories for all types of computer systems K527 2 The same K507 3 Joint applications with the 508 and R508 integrated circuit series in the main memories of radio- electronics equipment - R145 51 Microcalculator construction Integrated Circuits Using n-Channel MOS Transistors K565 2 Construction of main computer memories (OZU) for all types of computer systema -52- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY TABLE 3.7 [cont.] Number of IC's. in the Series Series (1978) Eunction Integrated Circuits Using CMOS Transistors 164 24 Construction of miniature digital automation aad 764 (unen- 12 computer hardware with a low power consumption capsulated) 564 33 The construction of miniature digital automation 765 (unen- 9 and computer hardware with a low power consump- capsulated) tion K176 33 The same Integrat.ed Circuits Based On Glass Semiconductor Switches K524 2 Construction of erasable programable read-only ~ memories for computers and digital automation systems - Integrated Circuits Using Transistors With Nitride Oxide Insulation (MNOS) 509 1 The construction of erasable read-only memories for computers and digital automation systems 519 �2 The same following: tl~~ is the time for the transition from the logic one state to ' the logic zero state; t~~l is the time for the transition from t~he logic zero state to the logic one state; tZ~~ is the turn-on delay time; tZ~l is the cut-off delay time; tZ~j~r is the propagation delay time during turn-on; tZ~lr is the: propagation delay time during cut-off; tzd.r.avg. is the average propa- gation delay time; Ti is the pulse width and fr is the working frequency. The read-out levels relative to which the dynamic parameters are determined are shown in Figure 3.1. The average propagation delay time is defined in accordance with the formula: t = 0.5(tl ~ + t~ 1 ~~tlpop_0,5(r:AV+~~v~� zd.r.avg. z~.r z~.r This parameter serves as the averaged parameter for the operational speed which is used in the calculation of the time characteristics of series connected digital IC's. The following are the most frequently cited in the handbook data for digital IC's from the list of dynamic parametere indicated above: tZa~ and tZ~i the -53- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2047102109: CIA-RDP82-00850R400504080030-5 FOR OFF'ICIAL USE ONLY turn-on and cut-off delay times, as well as tZ~Or and tZdlr the propagation delay times during turn-on and cut-off. Potential logic gates, when operating as part of a digital device, can be either in a static mode which is characterized by one of two states ("0" or "1"), or in a switching stage. Depending on the type of logic gate, the power consumed f.rom the power supply will ciffer for each of these states. Some elements consume considerable power in the static mode, which increases only insignificantly at the moment of switching, while others, on the other hand, are characterized by a rela- - tively low power consumption in the static state and a considerable increase in the power consumption in the transient processes. Logic gates with a low power consumption in the dynamic mode are characterized by the average power consumption: 0 1 Pcon.avg. ~'S~Pcon. + Pcon.~' where P~on is the power consumed by the circuit in the "0" state, while pcon is the power consumed by the circuit in the "1" state. For these circuits, the power ~ consumed at the point in time of the transient processes does not exceed the power ; consumed in one of the logic states. Logic gates with a large dynamic power consumption are characterized by the power consumed at the maximum switching frequency, when the currents in the power supply circuits increase sharply, in addition to being characterized by the average static _ power consumptioil. The CMOS integrated circuits are examples of such circuits. _ - ~1) , Ma T-f15~C dlwx -60 ~ ~ ~Owu Mn 0 , ~ . Uia?+ n t ?.o (2 n t 0, ~ + 0 ~ ti0'~ ti~P~ ~ ~ ~lsyy ~rdY - ~ � a _ ~ v~ - ,---;IT ~ ~ 'h ~ uiroN ~ 0 45' Uex nax ~~p,r rmn .~irU in in m~.n Figure 3.5. The readout levels for Figure 3.2. The transfer functions of dynamic parameters. a 1~OT logic gate and the ultimate trans- fer functions for the family [ot IC's] obtained at various temperatures. Key: 1. Uout 2' Uout max. The static noise immunity of logic switches defines the level of the voltage which can be fed to the switch input relative to the "0" or "1" level without causing it to falsely actuate [1]. Since a logic gate in the static mode can be in one of two states ("0" or "1"), a distinction is drawn between the static noise immunity for the "0" level (U~) and the "1" level (U1). The valuea of U~ and U1 are determined from the tranafer functione (Figure 3.2)~. n n - 54 - FOR OF~ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000540080030-5 FOR OFFICIAL USE On1LY As can be seen from Figure 3.2~ the parameter Un is defined as the difference be- tween the minimum "1" level (Uin mi ~ and the point B voltages on the upper curve. The parameter Un is defined as the ~ifference between the voltage at point A on the lower curve and the maximum voltage for "0" (UD ) To completely evaluate the noise immunity of a circuit, it is necessary tonta~ce into account the dynamic noise immunity along with the static value. The dynamic mode noise immunity depends on the width, amplitude and waveform of the interference signal, as well as the level of the static noise immunity and the switching speed of the logic gate. The fan-out factor for the output (the load capability), Rout, characterizes the num- ber of similar gate inputs which can be connected to the output of the logic switch. With an increase in the load capacity, the possibilities for digital IC applications - are improved and the number of packages in the digital device under development are reduced. Simultaneously with an increase in the number of loads, some of the IC ~ parameters are degraded: the speed and noise immunity fall off and the power consump- tion increases. For this reason, high power buffers with Kout = 20 to 30 are inclu- ded in an IC series along with the main logic gates having a load capacitq of Kout = = 4 to 10. This makes it possible to obtain optimal indicators with respect to the number of IC packages which are used and the power consumption when desiguing digital devices. It must be noted that in RTL and RCTL circuits, the load inputs consume current from the output of the loaded element, while DTL and TTL circuits in one logic state de- liver current to the load, and in the other receive current from the load. The load is of a capacitive nature for MOS circuits. The input fan-in facbor (Kin) defines the maximum number of digital IC inputs. A dis- tinction is drawn between the input fan-in factor for an AND (Kin AND) and for an OR ~Kin ~R) $ate. In the existing series of digital I~'s, the main logic gates are made with a small - number of inputs (Rin AND = 2 to 4; Kin OR a 2 to 4). To increase the number of in- puts in individual logic elements, incorporated in a series, special inputs are pro- vided for the connection of an "expander", which provides for an increase in the fan-in factor of up to 10 and more. An expander circuit is correspondingly incor- porated in a series as an individual element. There are logic elements with eight inputs in a nunnber of IC series. ~ 3.4. Transistor-Transistor Logic Circuita Transistor-transistor logic gates (TTL) appeared as the result of the development of diode-transistor logic, through the replacement of the matrix of diodes with a multi- ple emitter transistor (MET). An MET is an integrated circuit component which com- bines the properties of diode logic gates and a transistor amplifier. The AND func- tion in a TTL awitch is performed in the base and collector regions which are common to several emitters. The basic structural difference between an MET and conventional transistors consists in the fact that it has several emitters arranged in such a~ fashion that direct coupling between them is practically eliminated by a passive base region which separates them. Thus, the MET represenCs a aet of several trans- istor structures, having a common collector and which interact directly with each other through the motion of the ma~ority carriers. We shall treat the operation -55- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY of a multiemitter traneistor using the example of a NAND gate (Figure 3.3.) with a simple inverter (unipolar switch) [4]. . , ~ o (2) ~rt (1) Rf a2~ " (1 f~ R~ ~.s ~ ~?~or ~ . t ~~p~ ~ . ~~~~d ~ ~ (4) � r ~ . X=-, ! . Xs~~ (a) d~ (5)~` Xa ' (b~ Figure 3.3. The current distribution in a NAND gate with a simple inverter where a"1" is fed to the inpur (a) and a"0" - is fed to the input (b). Key: 1. Uip m Supply volta~ge, Vcc3 2. U~ut' 3. Uout of approximately 5 volts; 4. U~ N~ � Oce sat ti 0.3 volts; 5. Uin' If voltages corresponding to the "1" level (Uin) are fed to all of the inputs of an MET, the emitters of the input transistor do not received the turn-on bias cur- rent (a sufficient potential differeace is not present). In this case, the current delivered to'the base of the MET through resistor R1 flows from the supply V~~ to the collector circuit IK [IcJ, which is forward biased, and then to the base of transistor VT2. Transistor VT2 is saturated in this case and the voltage at the output of the circuit corresponds to the "0" level ~Uout~� ~1 of the MET transis- tor structures are in the inverse active mode in this case, since their collector ~unctions are forward biased, while the emitter ~unctions are reverse biased. If the "0" voltage (Uout~ is fed to one of the MET inputs, the correaponding base-- --emitter ~unction is forward biased. The current fed to its base through resistor R1 flows in this emitter circuit. In this case, the MET collector current falls off, transistor VT2 cuts off and the voltage at the circu~t output becomes equal to the nln level ~Uout~ � _ _ _.~----X~ - . . ~a z~ v~ aZ R4 R . ,p~ Rd , t7'f v~ v~t ,PZ ~'a vn vy y~ YT4 ~fi i'~x ~ y Xi rr~ yi ~ra .vr,r ~ ~a ~ x~ � RJ ~ ~ p ~g) d1 (b) (c) d! . Figure 3.4. Schematics of an 8-input TTL NAND logic gate (a), an OR expander (b) and au AND-OR-NOT logic gate (c) - 56 - FOR OFFICIAL USE ON~,y APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR OFFICIAL USE ONLY - - - - Lir~ ~ occ a~ a't ~ a~ Rt v~ . . r~a t~t vDS v~f v~s ~ ~ ~ . , ~ Y a'~ r/0 . ~ ~ Rd roa . v~ ~ vr~ ' .aJ~a~ . 61 ~b~ 4~ ~cc R? ~ Vcc ~ V7fl m? 17Z � X~ f72 X= i73 r X= Xs ~ ~ ~ YO/ YBt ?~3 1~ ' ~ e, . , Figure 3.5. Baeic achematics of standard TTL series. ~ a. �NAND logic g~te (133LA1 and K155LA1 IC's); ' b. NAND logic gate with a large fan-out factor (133LA6 aad K1.55LA6 IC's) ; ~ c. Circuit with an opea collector (133LA7 and K155LA7 IC's); ~ d. OR expander (133LD1 and K155LD1 IC's). TTL circuits with a simple inverter have not found widespread applications because of the poor noise immunity, low load capacity and poor apeed of the unipolar aw{tch when operating as a driver for display elements. With the development and refine- ment of the technology, a dual polarity ewitch became the basic circuit for TTL switches with a complex inverter (F3gure 3.4a). The use of a complex inverter made it possible to increase the epeed over that of the simple circuit configuration (especially in devices with multiple layer printed circuit boards), as well as the noise immunity and fan-out, and also reduce the requirements placed on the transis- tor parameters; the latt~r led in turn to an increase in the percentage yield of good IC's. . ~ � Several variants of TTL series circuits are produced at the present time. Theae are the standard 133 and K155 series (functionall,y-�analogous to the SN54/74 devel- oped bq Texas Instruments); high speed series: 130, K131 (functionally analogous to the SN54 H/74H series; here, the H designatea increased speed); and the micro- power series 134 (functionally analogous to the SN54L/74L seriess here, L indicates a lower power consumption); series with Schottky diodee: 530 and K531 (functionally _ -57- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084030-5 FOR OFFICIAL USE ONLY analogous to the SN54S/74S; here, S indicates the presence of Schottky diodes in the structures); and the micropower series with Schottky diodes, R555 (functionally analogous t~ th~ SN74LS). al~~ ~{in V~~ a~ at as occ a~ � aZ� ps.a vr~ vra t~a ~ vrs Yr> ~ ' x; ~ ~t v~z v. ~ , � ~ X~ VT2 R6 ~ ~ ~ . R3 , . . RB~ X3 1 ~D2 Y ~ y . Xy VOk ~ ' . , I . Q~Ca, 6~(b, . r~v~ ~ ' ~ qi~r---~, YTf K~ ~ � ~ NT2 1 ~ X~ '~a , �vya vm. vo~ v ; . Figure 3.6. Basic schematica of the high speed TTL series. Key: a. NAND'logic gate (130 LA1 and K131LA1 integrated circuits); b. NAND logic element with a large fan-out factor (130LA6 and K131LAb integrated circuits); c. OR expander (130LD1 and K131LD1 integrated circuita). In terms of circuit design, almost all of the logic gatea incorporated in the indi- cated series can be formed by a combination of two basic circuita: a NAND logic gate (Figure 3.4a) and an OR expander (Figure 3.4b). An OR expander in con~unction with a NAND logic gate forms an AND-OR-NOT logic gate (Figure 3.4c). By connecting the expander (Figure 3.4b) to points 1 and 2(Figure 3.4c),~one can fncrease the fan-in load for the OR logic input. For all TTL circuita which have the OR expan- sion capability, the maximum fan-in is eight inputs. When one expander is connected the circuit propagation delay increases by approximately 5 nsec, while the power consumption increasea bq 5 mW. TTL logic gatea have a high fan-out load capacity (Kout = 10). The large output and comparatively low input currents promote good matching of the circuits to each other. As a rule, the complement of TTL series includes a circuit with an open collector output (Figure 3.5c) and a logic element with a large fan-out factor (improved load capability) (Figure 3.Sb). Basic schematics of each of the varieties of TTL seriea indicated above are shown in Figurea 3.5 to 3.8. -58- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFI( , _ _ _ _ - ..r, 'UN~I ' Xy ~ , ~ ~ VCC ~ ~~Qf ~ 1 RZ ~ AT4 I Rf ~ ~ ~ ~ ~ V,r3 '~IA ~ R8 .K76 ~ i?r "~72~ vM1 ~ t VT3 ~ VT4 X~ VOI XJ z ~ ~~4 r X~ ~ ~~6 Xy ' ~ , - ~ R4 (a) �p ~ ' . (b) �a~ Figure 3.7. Basic schematica of the micropower TTL series. Rey: a. NAND/NOR logic gate (134LB2 IC); ~ b. AND-OR-NOT logic gate (134LR1 IC). VCC ' . Rl i 7P2 � 'R6 ~ - ~ vr3 ~ i . ' ~ �V7b ~ y . ~ 'YT4 ' j I ~ ' ~ VDf Y I~D3 i~94 R3 Q4 R6 . . PT4 , . Figure 3.8. Basic schematic of $chottky diode TTL (NAND logic gate, 530LA1 and R531LA.1 IC's). We shall consider the operational principle of TTL circuits using the example of a NAND logic gate, which is shown in Figure 3.4a [4]. The circuit coatains simple n-p-n transistora (VT2, VT3, VT4), a multiemitter transistor VT1, as well ae resis- tors R1 R4 and diode VD. Such a circuit provides for the capability of opera- ting into a larger capacitive load with high epeed and noisf immunitq. The circuit of a basic TTL gate consista of the following elementary stages: the input multiemitter transistor VT1 with a low inverse current gain, a phase splitter, designed around a transfer transiator VT2 (this stage operates with a small ~orking current znd has low p-n 3unction capacitances); and the push-pull output stage VT3, VT4. Transistor VT4 is designed for a large working current and has a ahort satur- ation cu~off time during circuit switching. The input currents of the load switches flow th~ough this transietor to ground. ~ -59- ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 � FOR OFFICIAL USE ONLY Ue~x,d 't~~t~ vo1t8 U~�x,o U~t~ .volts U~ ~ ~ z ~Z ns'c . 3 , s . . ~o ~ C2~'~ ~ ' . 2 Y ~ ~ ~3 f ~ ~ (4) ~aw/ ~aovt 2 U ,~'~s 4S. ;0 f,s 2A ~ ~ex ~ (a) in ~J (b~ U~~ v Figure 3.9. The transfer characteristics of a standard series TTL NAND gate for T~ 25 �C (a), and in a range of temperatures (b); V~~ = 5 volts, Itout = 10 [fan- out]; the dashed curve applies to circuits with a correcting network. 0 1 Key: 1. Unoise cor. net.' 2' Uout min' 0 ' 3. U~oise' 4' Uthresh.l' The ability of TTL circuits to work into a large capacitive load ~t high switching speeds is explained by the fact that with these circuits, both the charging and dis- charging of the load capacitance is accomplished through the low impedance output ~ietwork. However, when switching the states of the output transistore, there is a point in time when they are both turned on. Because of this~ ahort term but high power current pulses occur in the power supply circuit, where these pulses can lead to the appearance of. interference pulses. To avoid this in equipment constructed with TTL circuits, it is necessary to design a power aupply with low lead inductance and to provide decoupling between adjacent sssembliea. We shall analyze the transfer function (F~gure 3.9a) of the NANb logic gate shown in Figuxe 3.4a. When Uin 1= 0(the ground potential is applied to one of the ~ emitters of transistor VT1), the base-emitte~ ~unction (b-e) of transistor VT1 is turned on, but the potential which is produced in this case, Ub ~1 ~ 0.8 volta, cannot turn on three p-n 3unctions: the base-collector ~unction (b-c) of transistor VT1, the b-e ~unction of transistor VT2 and the b-e ~unction of transistor VT4 (a potential of approximately 3 x 0.6 = 1.8 volts is needed to turn on this circuit). The potential at the base of transistor VT4 is close to 0 and transistor VT4 is turned off. The potential at the collector of YT2 and at the base of VT3, which is close to the supply voltage of +5 volts, turns on the b-e 3unction of transistor VT3 as well as diode VD, producing the current iout' The voltage at the collector of transistor VT4 is correspondingly equal to Uout ~~ection 1- 2). With an increase in Uin (at all of the emitter inputs to transistor VT1) up to the threshold voltage level Uthr 1~ 0.8 volts (point Z on the transfer function), -60- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-40850R040500084030-5 FOR OFFICIAL USE ONLY transistor VT2 begins to conduct, b.ut transistor VT4 is still cut off, and with a furth~ar increase in Uin up to the voltage level of Uthr.2 � 1.25 volts, transistor VT2 ~urns on, while transistor VT4 only begins to conduct (point 3 on the tranefer function). A further increase in Uin leads to an increase in the potential at the base of transistor VT1 up to 1.2 volts. This is altogether sufficient to turn on two ~unc- tions: the b-c 3uaction of transistor VT1 and the b-e ~unction of transistor VT2. Transistor VT2 turns on, and the current through resistor R2 increases, which causes a reduction in the voltage U~ ~2. ~n increase in the current through resistor R3 causes the potential at the base of transistor VT4 to increase and makes it conduct. The turned-on transistor VT4 (section 3--4 of the transfer function) shunts resistor R3, which sharply increases the transmission gain of transistor VT2 and causes a ~ further reduction in the voltage U~ ~2. Hawever, transistor VT4 has already been ~ turned on for some time while transistor VT3 is still not turned off, something which leads to a current spike and an increase in the power consumed from the supply. The current cor~sumption is limited in this case by resistor R4, as well as the bulk resis- tances of trans~.stors VT3, VT4 and diode W. This is the so-called short-circuit cur- rent which leads to an increase in the power consumption in the dynamic mode. With a further increase in Uin, transistors VT2 and VT4 Pa~N,HBm Pdyn~~ ~ change over to the saturation mode (section 4--5 of the 4D transfer function) (Figure 3.9a). The potentials Uc VT3 and U~ ~4 will be 1.2 and 0.3 volts respectively. ~ Their difference, which ie equal to 0.9 volts, is not ~ sufficient to turn on the base-emitter ~unction of trana- ~ ~ 1 3 k 5 f,i'1/'q istor VT3 and the ~unction of diode VD. The presence of , diode VD (Figure 3.4a) provides fvr shifting the turn-on Figure 3.10: level for transistor VT3 as well as reliably turning it The dynamic power as a off when Ugut = 0.3 volte. _ function of switching fre- quency where V~~ = 5.25 v, In real TTL circuits (Figure 3.5a), in contrast to the T= 70 �C and Cload = simplified NAND circuit (Figure 3.4a), an equal~zing = 15 pFd. network is tied to the base of the output transistor in place of resistor R4, where this network conaists of resistors R3 and R4 as well as transistor VT3. The insertion of the c4rrecting network makes it possible to produce s tranefer function shape close to rectangular (Figure 3.9a) and thereby improve the noise immunity in the logic "1" atate as om- pared to the notse immunity of the circuit shown in Figure 3.4a ~Un eq.net.~ U~~' The resistance of the correcting network is lesa temperature dependent than re3istor R4, something which provides a number of special properties for the circuit. At an elevated temperature (125 �C), the recovery time for transistor VT5 (Figure 3.5a) is short, which promotes a rapid cutoff of the circuit. This in turn reduces the short circuit current pulse (when transistors VT4 and VT5 are turned on simultan- eously) and means that the dynamic power consumption is also reduced. At reduced. temperatures (-60�C), the resistance of the correcting network exceeds the resis- tance of the resistor R4 (Figure 3.4a), which increases the turn-on current of transistor VT5 and correspondingly leada to a re~uction in the circuit awitching time. 7 - -G1- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-04850R000500084430-5 FOR OFF[CIAL USE ONLY As can be seen from the curves of Figure 3.9b, the ~ characteristic shifts to the left with fncreasing ~a".y~I , mA temperature, something which reduces the circuit noise 2 ~ iamiuni~y at a temperature of 125�C: ~ As was shown above, at the moment of switching of the ~ ~ NAND circuit, the current consumption increases, which Z Zv~,4y ~o~'~ in turn leads to an increase in the dynamic power con- ~ z sumption. -2 ' It can be seen from the characteristic curve (F~gure 3.10) that with an increase in the frequency up to Figure 3.11: 5 MHz, the power consumption rises to 43 mW as comp~red The input characteristic to 20 mW in the static mode. The current spikes in for the case w_.: te V~~ = the supply circuit, which is inductive, can produce ~ = 5 v and T= 25 �C. induced currents and degrade the noise immunity of the ~ equipment. We shall analyze the input characteristic (Figure 3.11) of the NAND logic gate shown in Figure 3.Sa. In the case of ~oint operation of TTL circuits, one of the circuits serves as the load for the other. Two modes are possible in this case. When the control IC is in the "1" state (point 1 on the input characteristic curve) - and the voltage at its outpu~ is equal to Uout ~Figure 3.12a,b), the b-e ~unction of transistor VT1 of the load IC is cut off and the current Ii~, which is governed only by the inverse current through the cut-off ~unction, is quite low. The control IC is shown in Figure 3.12b in the form of a switch. If the control IC is in the "0" state (point 2 on the iriput characteristic curve) and the voltage at its output _ is Ugut, the b-e ~unction of transistor VT1 of the load IC is turned on and the in- put current changes its direction: it flows from the power supply of the load cir- cuit through the conducting b-e junction of transistor VT1 and the cnnducting trans- is~or VT4 of the control IC to ground (Figure 3.12c, d). As can be seen from the input characteristic, when Uin = 5.5 volts, the input cur- rent Ii increases sharply, reaching a level of 1 mA. This value of the input volt- age is the ultimate permissible value and exceeding it can cause the circuit to fail. The value of the input currenr. I~n ~increa~es in a similarly sharp fashion with an increase in the negative voltage at the in~ut. For the majority of TTL series, the ultimate permissible value of the negative voltage at the IC input is 0.4 volts. In actual equipment circuits, the signal fed to the IC input does not have a strictly rectangular or trapezoidal waveform. At the moment of signal term- ination, decaying oscillations app~ear in the hookup wiring, which can cause false actuation of the circuitry. To grevent such false actuations, a number of TTL cir- cuits have been refined, as a resixlt oL which, so-called damping diodes, VD1 VD4 are connected to each of the muitiemitter transistor inputs (Figure 3.Sa). When there is no oscillatory process at the input, such a diode is tur~ed off and inserts an additional capacitance ati the circuit input of less than 1 pFd, which . does not degrade the dynamic characteristics of the circuits for practical purposes. With the first negative pulse which exceeds 0.8 volts, the damping diode turns on and limits the amplitude of the pulse to a level of -0.8 volts, the subsequent posi-- tive vc~ltage pulse becomes considerably less than 0.8 volts (does cause the -62- - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500084430-5 , 1 )FFICIAL USE ONLY vCC VCC VCC VCC la~ Urd UMn ~M A~rra'f R5 l~rt Cx~yvf RS ~ Cx~rArt ~a R/ eircuit 1 ~~+~a ~ ~ ~ vra ~ VT~ vr,r ~ ~ . voa ; ~ u~ar ~ ' ~ vrs ~ur , futin, waNV'~ (aI p~ tcl (1~ aia ~ea ' ~ird y Ar~ Vca Vcc p~ va~ cc ~ , vr~ vr> ~ ~ . ~ -~~j~ ~ ~y~, (A~ 61 EdI ~ U~t. 5 q Figure 3.12. Combined operation of a TTL signal source and load . Key: ayc. Circuit 1 generates "1" and "0" respecti~~ely; b,d. The equivalent circuits for these operating ' modes; 1. Uout for circuit 3. circuit to actuate, since Uthr = 0.8 volts) and the oscillatory process at the input decays rapidly. � We shal~ analyze the output characteristica of the NAND logic gate shown in Figure 3.Sa. The output characteristics are shown in Figure 3.13a for the logic gate at various temperaturea. With an increase in the load current, Iout~ the output volt- . age level will fall off until a certain value of the current is reached, Iout x ,^;5 mA, when the voltage drop across resistor R5 is amall~ In this case, one can assume that transistor VT4 operates as an emitter follower, and the alope:of the characteristic Uout - f~iout~ is small. With a further increase in the current, - I~out~ the voltage drop across resistor R5 increases, the voltage at the collector of transistor VT4 becomes less than at the base�and transistor VT4 goes into satur- ation. The characteristic curve changes its elope and then the current falls off linearly. The rate of drop is now determined by the nominal value of resistor R5. It can be seen from Figure 3.13a that although the slope of the characteristic is practically independent of the tempe~gture, nonetheless at a temperature of -60�C the current level decreases by approximately 0.5 mA, something which causes a re- duction in the fan-out capacity of the circuit. The output characteristice of a logic gate in the "0" state are also shown in Figure 3.13a for various temperatures. As can be seen from Figure 3.13a, the slope of the characteristic U~ (I~ ) changes with a change in temperature. - out out -63- r FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000540080034-5 ~ FOR OFFICIAL USE ONLY a~x�0 vout' v�].ts ~u~,e v~, volts a i2s'c . . . _ zs-------- J 2 60 Z , / ~out~ ~ > , . S - 15 ' ' 25 ~ ~~~M~ t~'0 ta'~ t 0� ,B U~ , V a UdeAn4 ~?p 3~? f,~ nse~ out 60 C ~5 . - ~ ZS 4 , . L~4 f . a~ ~out'~ ~ i r 1 ~ ~ r � ~ 10 30 dD ~o NA ta' t~~p a~ (b) dl Figure 3.13. The output (a) and dynamic (b) characteristic curvea for a standard series TTL NAND gate. Key: 1. "1,0" propagation delay time; 2. "0,1" propagation delay time. ' At a temperature of -60 �C, when the output current I~ reaches a value of 25 mA, the slope of the characteristic increases sharply andout8ubsequently, even a slight increase in Iouti leads to a substantial rise in tY~e voltage at the circuit output. . Thus, the lower temperatures are more critical from the viewpo3nt af tYae load ~an-out capacity of TTL circuits. We shall consider the operation of a NAND gate in the dynamic mode. As has already been stated above, the circuit speed is characterized by several parameters, and ~ inlp~rticular,Otie propagation delay time when switching th~e circuit on and off, (tZ~.r) and (tZ~.r) respectively (Figure 3.13b). When switching a NAND logic gate (Figure 3.14), the fraction of the propagation delay time due to transistor VT1 may be disregarded, assuming that the switch actuates instantaneously. Then, the overall signal propagation delay in the cir- cuit will be governed by the delay due to transietors VT2 and VT4: - l ~A v ='t:~i�vrs -I- ~:~i�vr4.-- In turn, the delay due to transistor VT2 is primarily governed by the parasitic capacitance charging time for C~1, which takes the form of the sum of the para- sitic capacitances of resistor R1 of the collector of transistor VT1 to the sub- strate and to the b-e ~unction of transitor VT1. The delay due to.transistor VT4 is determined by the charging time for the paraeitic capacitance CE2, which takes the form of the sum of the capacitances of the atructure of resistor R4 and the b-e ~unction of transistor VT4. , -64- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY When the gate is switched off, the signal propagation delay for the NAND logic gate, is determined primarily by the resorption time for the minority carriers in the bases of tr.ansistors VT2 and VT4. For standard TTL circuits at a ~ temperature of 25 �C, where Kaut = 10 and Cn = 15 pFd, typical values of the propagation delay time during turn-on and turn-off are tZl~ 7 nsec and fZ~.~ _ = 13 nsec respec~fively. It can be seen fram the curves shown in Figure 3.15 that with a rise in temperature, the propagation delay ti.me during tum-on falls off slightly wliile the propagation delay time in the case of cut-off, o~n the other hand, ~ncreases, eapecially in a temperature range of from 20 to 120 �C. With an increase in the load, the values of the propagation delay increase somewhat and an increase in the load capacitance has a greater influence than an increase in the number of IC inputs connected to the output of the TTL awitch. As has alre~dy been stated, various types of flip-flops and circuits designed rf aLound them - regiatera, counters, adders - are incorporated in a series of digital iC':s along with simple logic elementa. As an example of a standard TTL series, we shall treat the operational p:.inciple of JK and D flip-flops. The schematic of a JK flip-flop .is ahown in Figure 3.16. - As can be seen fram Figure 3.16b, the entire device consists of the main flip-flop T1 and the auxiliary flip-flop T2. The information is entered in the ma~n flip- flop at the moment of arrival of the positive edge of the synchronixation pulse which is fed to input C. During the action of the sync pulse in the upper auxiliary flip-flop, the data entered during the preceding cycle is preserved. Upon the completion of the synchronization pulee, the data is rewritten from the main flip-flop into the auxiliaxy one. Three operational variants are posaible " - - - - for this two-stage flip-flop. ~ ~ In the firat case,�a signal correaponding to "1" . _ a~ ~,s~ is fed to the information inputs J and ~__~F_~ K while a sync pulae is fed to input C. X~ The JR flip-flop then operates as a divide- vr2 -by-two circuit.(i.e., as a counter). x2 YTa ~is mode is utilized in the conatruction i i of frequency dividers and counters of any Q`~ -r~=z , degree of complexity. In the second mode, a paraphase logic signal is fed to inform- ation inputs J and K. The flip-flop then operates in a synchronous information Figure 3.14. The equivalent circuit write mode fram the J and R inputs. for�the generation of dynamic parameters. Following the input of the clock pulse, thia information appears at the Q and Q outputs, i.e, it is shifted to the next location. The given mode is utilized in the construcfion of shift registers, pulse distributors and synchronous counters. And finally, information in the form of the "0" level is fed to the R or S inputs. In this case, the flip-flop is -65- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440500080030-5 FOR OFFICIAL USE ONLY � .___.~-~i p.~ - - fS~d 'M? � ~C . ~ll 40 ~.a -U.n'S0. ~"i5�C, R~~ 1J 10 tN> . . ~-dn -?0 t9 d~ ~ r'C ty�a ~2~ Uri SQ. C~-30aaD,A~ ~Xl SO 1QOe C~d tNp~~ t~p~o:,~ l~0~1d~. - nsec.: . n~ . d,~ se , t-25'~, ~ p~ r~ ~cc~5 y~i T� 25`' ~ ~ � ta~ � 1~ p . ~ ?A t~~t P �-E~ -YO l0 d?7 71i17 ri'C 2 0 ~ KIo~ I Figure 3.15. The propagation delay times of standard TTL circuits as a function of temperature, capacitance and the number of similar IC inputs connected at the output. Rey: 1. V~~ @ 5 volts, T~ 25 ~�C and Itout = 10; ~ 2, V~~ a 5 volts, Cload � 30 pFd and Rout ' 10; 3. Rout(faa-out load factor]. forcibly set in the "0" or "1" state (the states of the J, K and C inputa are arbitrary). One must take into account the fact that the state when the signal corresponding to the "0" level is simultaneously fed to the R and S inputs is indeterminate. The possibility of the occurrence of euch a state ehould be pre- - cluded. The aircuit of D flip-flop ~Figure 3.17b) consysts of the main asynchronous RS flip-flop T3, the auxiliary synchronous RS flip-flop T1 which is used for writing "1" into the main flip-flop, as well as the suxiliary synchronous RS flip-flop T2 for writing "0" into the main flip-flop. The information write into flip-flops T1 and T2 takes place at the point in time t only with the apperance of the poeitive edge of the synchronization pulse which is fed to the count input C. At the point in time t+l (with the next clock pulae), the information appears at the output of the D flip-flop. Thug, a D flip-fl.op generates a"1" of output information at the ~oment of arrival of a positive synchronizatian pulse gradient, if a"1" was present beforehand at the D input. When a signal is not present at the count input C, the flip-flop maintains its previous state. A D flip-flop performs the function of a count flip-flop if the inverted out Q is connectcd to the D input. In the asynchornous mode, a D -66- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2047102109: CIA-RDP82-00850R400504080030-5 FOR OFFICIAL USE ONLY f~ . Nl Rf N! R~ lPtb' R1l ~3 YJ6 YI1I yl~ ' Y/l ~ Y/L~ I3 Rf . 6 � ~ ~ - Ytf ~ ' Y7t1 t ~ R6 RJl B/f + IP1B IPft J ~ Y ~4 9 ~ S ~ Ylf ~ ' m ~ Y1~9 YlYt ~ ~ . ~ y~ ~ . ~ YD5 ~ /2 9 a) ~ ~ TI ~1 ~ 8 I I I I ' s ~ I ~ O/ D~J I Di I ~ ~'1 I DS ~ R 73 & 4. ~4 I ~ ( . ~ n ~ ~ ~3 S T~ I. ~ ~ ~ j DB j 3 K~ & K7 Q 7 ~ A71 ` j ~ 1. ~ ( I. . C �I ( 9 0 ~ $ ~ ,I I ~ i 2 R cb~ L._._._._.. c~~ . e~ ~ e1 . Figure 3.16. Schematics of a K155TV1 JR flip-flop with 3AAID logic at the input; the basic electrical circuit (a), electrical block diagram (b) and its logic_structure (c). flip-flop operates in a manner aimilar to that of an RS flip-flop (the etates of D and C inputs are arbitrary). -67- FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY b ~ ~ M ~ . ~ O ~ ~ ~ ~ v ' ~ v Q ~ . ~ t/'1 4l ~ ~ ~ ~0 CJ ~ w~ o~ ~ U ~ u ~ ~ ~ ~o ~ ~ ~ ~ ~b ~ ~ u d _ ' . - - - _ ~ " ~ da ~ ' ~ ~ ~w m ~ ~ ~ p~ ~ ~ ~ ~ a~ w ~ b ~ A ~ ~ ' N ~ w ~ ~q b ~ ~ ~ ~ . Q ~ ~ o , 9O M ~ ~ ~ ~ ~ ~ o ~ ~ a ~ ~ f~+ ; b ~o > ; ~ Q Q h w I 4 ~ i: ti ti > > > > O ~ A ~ -68- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY . The integrated circuits of the high speed TTL series, an example of which can be the 130 series, make it possible to obtain a typical pYOpagation delay time of 7 nsec with a power consumption per elementary switch of 44 mW. The basic circuits of this series (Figure 3.6) differ from the basic circuits of the standard seriea (Figure 3.5) in the reduced nominal values of the r~sistors and lower parasitic capacitances of the elements. Since the output current of an ultrafast TTL awitch is increased, a Darlington configuration (transiatora ~T3 and VTS) is used in the output stage, which makes it possible to booet the current gain of the outgut trans- istor and therely~y assure approximately equal values of the output impedances of the circuit when it is switched on (governed by the top~emitter follower VTS) and switched off (governed by the saturation of traneistor VT6) which yields almost sy~netrical values of the signal propagation delay. The low output and input impedances of TTL circuits provides ama11 time constants for the parasitic load capacitances of. the printed board conductors, which makes it possible for this s~r ies of IC's to operate at clock frequencies of up to 30 MHz. Micropower series IC's, an example of which is the 134 series, make it possible to obtain an average value of the power consumption of 2~ ~ ~ ~ - an 0 0 ~ �0 c.2 'n p o o r-~I O ~ ~ ~ O ~ ~ ~ o ~ ~ ~ ~ ~ ~ . ~ ~ ~ ~ ~ ~ o0 ~ ~ ~ NN ~O O~ ~w ~~-1r~ai N~ ~e~ ~ m~ ~a ~ $i a a ~ o 0 0 0 0 ~ ~ x o 0 0 � ~ ~ ~ ~ ~ ~ ~ ~a ~a ~s ~s a~a a~ ~ ae ~ ~ ~ ~ o ~"~O ~ .o.~ � ~ r'' ~a+ . m p ~ ~ ~ ~ o O a ~ oor $ M M ~ � H ~ ~ ~ ~ ~ ~ ~ ~ ~~d~pC ~ O~ ~z~ m ~ ~7 v m I '~i'~+ _ o ~ O ~ ~N~d~~ v~ ~ v ~ m ~pp_ ,~'r., t~~~ ~ ~ p.N~e-OI~ ~ m~ mz ~~mZ b~~' O~~ ~ w ~ � ~ ~~p~ m ~Upz ~ ~~H~~p~ o+':m~ m ~q ~ ~ ~~O q~; O~ x~~D O ~t H m ~ ~ ~ G*, G1 N~ m Q r-1 N H m? r-1 C~1 H U -90- FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500480030-5 ' FOiE OFF[CIAL USE ONLY ' +,~1 N - - - - - - - _ - - . 4-I 1 O N ~ ~ ~ O~ r~i ~ .~-1 N j ~ ~ . . . . . . . ZO N lV N N t N N N N N c~t G~. 00 ~ rl c�1 a1 c'1 > ~ ~ ~ . 'r~' ,-Ui c~t H ,-~i N ~ A ~ r-~i ~ o 0 o~ ~ ~ o~ i m~ mz o ~ � ~ ' ~ ~ o~~ m o~ ~o~ o '6~0~~ > > ~ w� H ~ cv N a c%~ a~J ~ a� ~ a a - 91. - FOR OFF[CUL IJ~ ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED F~R RELEASE: 2007/02109: CIA-RDP82-00850R000500080030-5 m~ m ~p q N~ ~ c~ N N N N N c~1 c"1 ~N N . toV N N ~ . . . ~ . . . , N N N N N M ~ a c~1 N ~'�~t N N N N N N ~ ~ ~ ~ ~ ~ ~ O Ca^i c"1 C~ c"1 cr1 C~1 l"1 ~'1 ~"'1 ~ C^ C'1 c"1 N1 ~"1 ~ , - . z ~ . ' ~ o N N N N ~C N N N n1 N O r+ e''1 ~ .~-i ~ ~~p' ~ ~ C~ ~ ~ ~ .~-i ~ ~ ~ ~ m o o ~ '~o' ~ I I 1 1 ~ O ~ ~ ~ ~ x ~;.~o�~ ~ ~ ~ ~ _ ~ . m ~ ~ ~ H o ~ ~ ~ o ~ ~ ~ .~o 0440 0 ~ e_I ~~-1 Hm ~~-1 OI ~~q-~1 ' ~ ~~?1 ~ r1 ~ ~1 r~l rj~l rl rl ~ E ~ Fi ~ eT+ ~i ~i ~7 ~ ~ ~F7 iC ~F: ~ O O ~ ~~-I r'~ c'1 ~ ~ � ~ . , ~ ~ ~ ~O+ ~ ~ ~ aD ~ ~ cr1 r1 c"1 cY1 trl ch ~ ~ PG M~ H M H ~ H ~ ~ ~ ~ ~ F ~ ~ ~ H N ~ ~,1 a O p ~-1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ a~ a~ aa x aa ~a a m ~ ~ ' rl � H ~ ~ ~O W ~ C'~ ~ 0 ~ ~(vl-1 ~ 1 ~ ~ ~ M M ~ ~ ~ ~ ~ ~ ~ o 0 � � $ ~ g � � $ � � ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ " n ~ b m ~ ~ ~ ~ ~ ~ ~ ~ b m ~ ~ ~ ~ > a v $v x ~ ~ ~ ~ ~i ~ ao ~ ~i ~ -N ~ e i ~ ~ ~ ~ ~ ~ ~ N ~ ~ ~ ~ ~ ~ ~ ~ o ~ ~ m ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ H ~ ~ ~ ~ ~ v A A ~ A y > > ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~m ~ r~ r~ ao m a -92- FOR OFFICIfAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 . F't ~ ~ ~ C~-Iz. N~ ~ C~^l ('1 t`1 ~ C'1 ~~'1 ~ . . . . . . . �-1 N N (V N nt ~V N . . . . . . . 0 0.~ s r~ c~ r~ r~ c^ c~~ cn V � ~ N r~ z� ~ ~ . . ~ ~ N ~ r~l +-~1 ~ N ' ~ ~ H .p I i 1 1 .a ^ ~ ~ ~ ~ ~ � ~ > ~ ~ x 0 0 ~ ~ ~ ~ ~ ~o ~ ~ ~ ~ ~ o 0 ~ ~ ~ ~ ~ ~ ~ ~ Q~ M ~-1 ~ ~ ~ ^ ~ M O ~ ~ ~ WO Wp O ~ N ~1l, - +-1 I 'J~i .yG~i ~S '~i ~i ~ N N H ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ H ~ 1 1 1 1 O O � � g. g � � � ~ r ~ ~ ~ ~ ~ ~ ~ ~ N ~ v~ v~ ~ O ~ ~ ~ ~ N a~ .c m .c ao �~a cv ~ ~ ~ a ~ ~ + .~n o ~ � +00+ o ~Q'i m ~ .c ' i H'v p~~ ~ ~ p E3 b+'~' ~ o ~ ~ V N ~ ~ N~ V ~ ~-~1 P~ ~ i.t G ~ _ ~ ~ m~ ~af ~ ~ r-1 ~ N~++ ~ w+~ ~ FI ~9 r-i ~ U O i-I O O m U +~1 rl r~l ~1 > N /1 ~ ~ ~ .C ~ {~.1 1' ~ 1 O rl W ~ 15 I cd p+~ r! v.C rl O �rl .}1 O ~-I i~ 00 +-1 o .oo c~d+~ ~ ~ O~ ~ ~`'4~ a d ~ ~ ~ o ~ ~ ~ � ~i ~'i ~ ~ a o ~ ~ v ~ m b ~ ~ u1 ~ ~ H ~ ~j 'C ~ 3 ~ o ~ .C .C r+ i~l N +~1 H O 40 O+~ B ~ VI~ ~ ~H~ ~ ~ v ~ ~ X Pi~ ~ ~ x H V -93- - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ~ FOIt OFFICIAL USE ONLY i ro ~ ~ ~ - _ o.~ acv ~~o .ma' r+~ ~ z�~m ~ ~o ~ N ~ ~ ~ ~ , ~ ~ , b ~ ~ g~ _ o ~ ~ ~ . . ~ R~ � ~ . , o ~a a i oo m � v a1 .C +~O . ~ ~a~o ~ 40 ~ ~ ~ ~ O ~ ~ N ~ ~ ~ e~-~H ~ N ~ ~ ~ ~ ~ ~ ~ , ~ ~ ~ ~ . , � ~ ~ . A4 !y4 M ~ m pN O m .C ,-i p ~ ~ ~ N ~ ~ ; ~ b , w ~ ~ ~ ~ ~ ~ ~g~~ ~ ~ ~ ~ ~ ~ ~1 mN,l $fi o ,p �4 ~ N ~ ~ ~�~o � N _ ~ ~ ~ ~ aa ao ~ -�o ~ ~ ~ ~ ~ ~ ~o~ . N Qi rl ~ ? H N ,~1 +t O m m O �ri ~ ~ ~ N N ~4 ~ H m ; ~ ~ ~ ~ A ~ m ~ p ~ ao w~~ . ~ ~ C O ~ ,i~ ~Ot � i ~ ~ m .-i ~ ~ f~, ,-1 ~ > Ei ~7 H ~ r~-l x ~ N .~C -94- F'OR OFF[C[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-44850R444544484434-5 FOR OFF'iCl~l.L USE ONLY IC type 100TM1 (Fig. 3.23) ia two double D triggera of the ms type with separate _ inputs ~or setting S~ resetting R, aynchroni~ing C~ and Nith common synchroniza- tion input C. The da.ta is rece3ved on.the master triggar from input D at C=0 and CE=O. During this time, the slave trigger storea the data received by the trigger in the gtevious cycle.The data atoring accura xhen ~he signal changes at input ~ from state 0 to atate i. In thie case, trigger m oha,ngee to the stora,ge mode, xhile trigger s changea to the receiving mdda. Previouely recorded data in the m trigger ia transferred to the output of the circuit. At C~ 1~ the trig~er is blocked at input C. . To a~nieve the calauiating mode it is naae$sary to co~nect ouPtupuo~y Betting (S) and feed counting pulaes to input C or C~ ~Fig. 3.23b). Com 1B and resetting (R) are achieved at any moment of time, in~siependently of tr~e state of other trigger i:aputs (F'~lg. 3.24). . _ ~ _ _ . ~ r . _ . - - - - r ~ ` t r-'~ r ~ . r . i -:--TO o t t~.,~ t~y t~,o t~~ ~ - t o~~ ~,x t~ p~ r ~ . f~ ps r~�pR Fig. 3.24. Time diagram of a D trigger type 100TM~32 operation in the calcula.ti~on mode. IC type 100TI~33 i8 four D triggers Kith strobing elements at the trigger inputs. Strobing elementa are divided with reapaot to trigger �pairs by atrobi.zg outputs (G1, G2), synchroni~ation input C~ and common syn~hroni~ation input C. The data is received from input D at C= 1 and C~ =1~ in thia case direct data tranemission from the input to the output of the syetem may be blocked by signa,l 1 at the input of the strobing element. Da,ta etoring ocaurs xhen the eignals change at inputs G1 and G2 from state 1 to atate 0. Nhen all triggers are synchranizc~d with respect to the common input C, 0 muat be sat at the inputs of separate synchroni- zation or they must remain sxitched off. ilith segarate aynchronization of tr.ig- ger pa.irs with respect to C inputa. the common synG oni~a,tic~n input C must remain switched off , or si~?ial 0 must be fed to it ~Fig. 3�z51� - 95 - FOR OFF7~lAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 a~ . ' -~.w~~~w~~r ~ i . C ~ . n~~.+q'~~~~ ~ E ; . ~ r ~ f ~l : . s ;e t ~ p t t1 cvk\ tM N t1,~~vo ~1+~Fas o? - t~'p~/ ty, rr . ~,g. 3.25. Tia~e dia8rao of D trS~68er type lO.OTI~]33 � To provide proper operation of ths~trigger circu~ta,it is nece~searY to take into account a number of additi anal Fara.me~tax's shot~r~t in t~ ~e above-cited ~.i,me dia&rams ~ �n ~~9 s" ~i~~ auowable dslay time of the.� a~gnal ~'_ront or, aut~off at in- . puts 1~ cr S w~.th respoct to the poaitlve ayr?chroztisat~arl Ful+se front to~ `b� t;~�~ min~ mal allowable ti~ne for advance o~ t,tie f~ont and cut-off of aignals a~k in- ~ puts D or S wf th respect to the p.oeitiv.e front of the synahroulwation pulse. i'he values of these ~arameters mupt be aa follows~ ~onD ~rith respect to the D in-� put not leap than 2.5 ~QBeco~dsi.ta~s x~th respect to the S.inpu~ no~ less tha.n 3.5 nanosecon~, ~yD rrith respac~ ta. the. D input not la~s tlian 1�5 nanoseconds and ~~S with re~pect to the S input~ not ].ess tha~n 1�5 n~nos~0~~� IC type i00ID164 is an 8-chaz?nel multiplexer ~ith an inhibition input W made of - basic logia elements. The presenc.e of the inhibition input makes it possible to org~anize high level decoding airau~.ts and. impleiaeut an "OR wiring" operation of ' circuits for multiplexinS (combinitlg) over eight channels. IC type ZOOIYe160 (12-input parity check circuit.) is: a combinati;on of nine logic elements that im- pl9ment the "OR lockin$" to fuilctia~?. The cirouit is. designed to dete~ai.zle a paxiicy of worda up to 12 b3.~Es~ laa~?g. Tha~ output voltage corre~pond~ to level 1 if an odd number of digit "unita" is p~eser?t at tha aircuit inputs� -96- EOR OFFICIAL USE ONLX APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040500080030-5 IC type 100IP1?9 is a high-speed carry unit and is designed for combined use with iC types 100IP180 or 100IP181 in hiETh-speed acting arithmetic and logic devices, ogarating with long xords. The circuit consists of ten OR-NC1r-~ lagic ~ elements in waich the collectors of the input transistors are co.mbined in an - "OR wiring" circuit. IC type 1002P1$1 are high-speed universal arithmetic-logic devices (ALU)~ designed to implement 16 logic functiona and 16 arithmetic opera- - tions with two four-bit numbers. . A~...~ and BD...B3 are da,ta inputs. Input variables A and B in the positive logic circuits are fed in the complementary code and output funetion Y, in this case~ is also formed in the complewentary code. The direct code of variables A, B and oi output funcetion Y is uaed in the operation of the ALU in the negative Zogic functioz~ (0 corresponds to the upper level and 1-- to the lower level). Inputs S~...S are used to assign the code of the functian being implemented. Depending upon the signal at output M~ the device implements logic or arithmetic operations. ' Full internal carry circuits are built-in in the AI,U circuit. In~ut C is the caxry input from the previous atages. The carry sigrcal into the following stage ~s formed at output X2. The combined utilization of IC t;~pes 100IP 181 and 100IP179 maJces it possible t~ almost halve the arithmei:ic operation ti me for 32-bit xorda. Two complementary group carry signals (outputs X1 and X3) produ~ed in the ALU are used in the accel- erated carry operating mode. The im~lementation of logic transformations of in- put variables A and B~.s done when signal 1 is fed to input M which blocks the internal caxry circuita. The value of the typical parameters of the ALU in inplementing arithmetic opera- tions uith words from 4 to 64 bita long~ using accelerated carry circuit~ in 100IP1?9, are shoxn in Table 3.14. For the combined operation of series 100 and ~ IC series ~33 and ~55 circuits~ IC type 100PU12~4 is used. It consists of four 2-input level conv~-rters for transferring f~om TTI, to IC of the ESTL type, as well as type 100~i112s, which consists of gour 2-input level converters for transferring from F~TL to IC type TTI,. We will con3ider the operation of level converters in greater detail. Fig. 3.26a shows one of four leve~ converters included in IC type 100PU124. It consiats of input diodes VD1-VD4~ an input etnittar repeater ~traneistor VTl)~ a differential am~~li.fier ~transistors 11T5 and VT7), operating in a current switching mode~ emi.t- ter i~epeatera(transiators VT4 and i?T8) ~ as Hell as a source of reference voltages (transistors VT9 and VT10). TTL feed voltage (5.0 volts ie s"ed to leadout 9 and, the ESTL faed voltage (-5.2 volts ? 596) is applied to lesdout 8. Leadout ~6 (common) is grounded and the load i~s connected to paraphase outputs 4 and 2. For strobing all four elemen- tary convert$rs located in this IC, aecond inputs of each converter are combined at _ leadout 6. � -97- FO~t OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500480030-5 " FQR AFN'1('IA{. l1fiF: ONt.Y 8 ~P1 Y!!5 . ~ ~ Z !S ' R1 Ra R6 AB R10 RfZ Q VDJ YTd V79 ~ ~D,, t~r~ vrv vre ~ ~ a v~ro ' vo~ v~a vDZ v~2 ~s vr~ vne � V~9 V7B Rq RS l77 ~P9 ~71! ~P13 . a a, . . _ . r6 9 V7f R2 VT3 VT3 YTfO R5 pd p~ VT8 pfS ~ Vr4 VT7 . : Cf q3 ~D7 (/J2 k. , . R1f r7f2 YT V70 ~ vDa ~,~s vr9 VL'4 YDO t � ~1 A7 AO Rl4 ~04 ~ 2 ~ Fig.3.26 Level converter for transferring from the TTI, to the ESTI, (IC type 100PU124 ta) and for tranaferring from the I.STL (IC type 100PU125) (b). When using the circuit as a one-input level converter~ the re~erence voltage U . (le3dout 1) is fed to leadouts 2 or 3 depending on xhether the circuit must pro- duce an inverted or noninverted conversion. Thus, in case Uon2 is connected to input 3 and 1 is present at input 2, tranaistor VT3 ia open~ Hhile tra6naistor VT10 is closed.. The voltage of the VT3 tranai+stor colleator is about 1 volt xhich is enough to block transistor VT8 reliably. The current through opan trtsnsi~torVT7 enters the base of transietor VT9r insuring its seturation,as a. result of which -98- � FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ~ Table 3.14 Typical parametersof the ALU type 100IP181 xhen operating xith accelerated carry circuit type 100IP179 Word ~~6 ti~ Number of IC length, nanoseconda bits ilith series iiith accelerated type 100~181 type 100~179 carr_y cdt-iy in~U . in ALU circuit ~ xit?h accelerated carry 4 7 - 1 - 8 11 - 2 - ~2 ~4 13 3 1 ~6 ~7 16 4 1 32 3o i8 8 2 48 43 . 2o i2 3 56 22 16 4 The reference voltage aource forma the bias voltage for the current oacillator (traaisistor VT6). Thia voltage ie taken off ths eaitter of transiator VT10. Two ~ reference voltages are also credted, [Tap~ 1.8 volta and Uo~~ =-0.7 volts. Volt- age Uon~ from emitter of tranaiator YT9 ia fed to one input pf the differential amplifier (base of transistar VT7), the voltage from reeiator R12 enters the base of sti11 anothar curreat osci~.]ator (traneiator VT2). iTheu a 2.4 volt signa~ is applied to the input, a voltage of about 0.05 volts originate$ at the base of tranaistor VT3 and the voltage aa1 the basa of trarisistor VT5 xill,in this case, be approxima,tely equal to 0.8 volts xhich carrespa~?ds to level 1 in the E~3TL cir- - cuits. Transiato~ VT5 is found to be open, leval 0 is established at output 4 and level 1-- at output2. To supp~esa interfereuce pulaes ariginating at the moment of s~ritching in the feed circuita of the TTL circuits~ diodea YDl aad VD2 are in- stalled at the lev~l converter input. Fig. 3.26b sho~rs a circui~t of one of the four level converters in IC type 100PU125. The circuit consiats of a curre~t kay (tranaistors VT3, VT5 and VT1Q)~ equipped With a stable current oscillator in the emitter circuit (transistor SIT6 and re- sistor R9) and an output stage (aimilar to the inverter in the TTL circuits)~ operating in ~he sat~aration mode (transiators VT4, YT7~...VT9.). Feed foltage 5.0 volts � y96 is ap~lied to leedout.9 ancY feed voltage -5.2 volte �~6 is applied - to leadout 8. Leadout 16 (common) is grounded. A bia.s is applied to the stable current oscillator from the internal source of reference voltagea (elemeats YTl, VT2, YD1...YDw, Rl...R4) and txo reference voltages are also used~ Uoni =-2.8 volts~ taken off the colleotor of traaaistor . VT2 and Up~Z =1.29 volts, entering from the emitter of tranaistor YTl. Reference voltage U is used. to fix the output voltage of 0 xhen the circuit inputs are con- , nected, to the -5.2 volt voltage eource or are free. - . -99- FOR OFF'ICIAL US~ ONLY ' , APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 voltage U�~b,x < 0.5 volts is eetablished at ou~put 4, aorreapo~ding ~a ].ev@~ 0 of the TTL circuits. When logic 0 is fed to in~ut 2, tranaistorl[T10 opens and VT3 closes. The voltage on the base of transistor 11T9 r~duced to the level of 1 volt which leads to the closing of transisto~ VT9� The voltage on the collactos of transistor VT3 increasea ~ which leads to the opening of txan~#~ator i?~f'8. Lc ~ a result a voltage is eatablished at output 4~rhich corr~sponds to level 1 of TTL . circuits (U~=2.4 volts). When all four elements of circuit 100PU125 are used~ reference voltage~�~~o~ leadout 1 is fed to corresponding inputs of a~]. four elements. In designing funetional units using level co~averter circuits, it should be taken f.nto account � that the zero level U�~,x < 0.5 volts is somewhat higher tharx the ~ero level of TTL circuits (U~~~~ 0.4 volts) xYil.ch reduces the noi~e resiatance of the latter by 100 millivolts. The branching coefficient of level contertere when operating at inputs of IC series 123, 155 is no greater than 8, and at inpute of IC series 130 no greater than 6. IC type 100RU401 is a supe=opexative memory ~rith nondestratctive readout and con- sists of a matrix of trigger memory elements organized a$ 16 one-bi~ K~8� The ma,trix is equipped with a circuit for address and bit control. The electrical functional circuit of such a memory (F'ig. 3�27a) consie~s of 16 triggera (elements for storing data) organized into a two-dimena~onal (along X and Y) 4x~ matrix (VT1-1...VT4-4), 8 address forme~s (F),, read-in amplifiers( 3t7 0~311 1) and two read-out amplifiers (Cy O,C~4 1). The circuit operates in three modes~ data storing, read-out and read-in. Ad,dressing (selection Khen rea,d.inS out and reading in) is done by si~au~taneously feeding level 1 into eelected acldreas buses (X~Y). Zero level must be maintained at all address bueea not selected. when there are no signals at read-in amplifier inputs (UBX 3no U1~X 3hl '0) the si~al from. the selected cell of data storage ia fed. over the read-out bu~es to the input of the read-out amplifier 0 or 1. Depending upon Whether 0 ar 1 wexe read-in in the selected cell~ level 1 is formed at the output of the corresponding amplifier. The interrogated cell stores ita data. Switchi,rlg the trigger to the nex state will occur only when new data is received. To read-in 0 or l,it ia necesaary to supply level 1 simultaneously to the selected bus~s x~ Y and to one of the read-3.n buses (3n o or3i? 1 respectively) The data storage element (Fig. 3.27b) is an unsaturated trigger with direct coup- ling ma.de with two three-emitter transistora VT1 and VT2~ and three resistors. In the storage mode~ the trigger has emittera E2...E5 oPerating while the circuita of emitters II, ~6 are disconnected. In the read-out and read.-in modes, the trig- ger has emitters II~ D6 operating~ ~r~'iile circuits of emitters ~.��$5 ~e discon- nected. Read-out and read-in is done over ~he P1 and P2 busea. IC type 100RU402 is an associa~ive memory device. The associative memorY device (AZU) is designed for opsration with 2-bit Words. Beeides storage functiona~ the -100- FOR OFFICIAL U~E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 � Y~ v. ys ~l) . f ~ ~ f D rr,, r;z ' F � ~t,: r:.. � ~.3 ~t,~ 2 . e ~ /,L~I~ D TJ,1 t,i.: , ~ : TJ,: - ~ . 7:r,1 * ~ T4,. ' j i Eavx 6Y�0" . ' D la..d' D ~ aI dY q3 ~3) ' v~, ~�~z . f:~ap,+dtiaa .wc+~a 31 3~ P~ J2 J.t 3~ ~s P= . ~ 0/ .~ig. 3.27. ~.ectrical functional circuit of a superoperative memory (a) and a data storage element (b). 1. 8x 3nl input read-in 1 3. bit bus 2. Bb?,r 3n / output read-out l. ~;Z'J does ax~ithmetic operations on the stored numbers. At the basis of the AZU desib-:: i~ a system of access by a ta,g --~�the access to the needed word and its ' s~lec~ion is made by a ~ag contained in the desired xord itself. Assoaiative selectior. (seasch moda) in microcircuit 100RU402 may be made under conditions of "masking" the interrogated data. The retrieval is over two buses for each addr~ss. Combinations 1-0 and 0-1 are used re~pectively for the retrieval of the 1 ar.d the 0 states. Combinations 1-1 correspond to the "mask," i.e., in this case, the re- action at tne "word comparison" output cc~responds to noncoincidence of the in~er- ~o3ated data and any data stored under any address. - 101 - F'OR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 3�5�2� Easic Electrical Parametere and Typical Eharaateziatice of IC typ~ T9?L - Digital type F~Ti, IC~ besidea the usuaZ list of electrical parameters typioa,l far ~ other digital IC also have spee3al static paraaw~ers~ input and output threshold � voltages . - . . . : : .~t t-, fl~ Ue..O -f,6 -f,4 -f,f ~-f,0 -0,8 -0,6 ~ex.yA ~ ~ ~4~ 61 � -4,B �.8 . �r ~ ~ _ t . / ~ -~o i f � ~ p i f - -1,2 ..0� 5~ ~ . f ~ ~ex,~ f - ->,4 ~Eax,~ ~ ~ ~ ~ f - -1,6 ~ ' ' ..0" ~ ..f" . pp~i !/~~9 � �-f,8~ I ~ Ue,~r n~ ~ ~pp U~ 3~ . . ~ ~2~� ~t? � E) Fig. 3.28. Characteristics of b~sic logic eleme~it of the ~'3TL aeries= a-- tran~fer (CR-NLS' output, solid linei C~ output, b~oken line) b-- inptrt, c-- output, xith rea~sct to current. 1. U 8x , volta input volt~ge 3. U,~, volts output 2. U~x nop triteehold ~.nput valtage voltage 4. I~x , mllliamps irnput curreat 5. Uo~ refer~nce voltage. - 102 - FOR Ol?FICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAI. USE ONLY _ Fig. 3.28a shows the typical transfer cdiaracteristics of a basic logic element of _ series 100~ K500 with direct and inverse outputs. By means of these cu-rves, it is possible to give the folloxing psrameter def~nitions for 85TL circuitss Uex rrop ~ Uex'vf i~nput threshold voltages =~g,,,~ b UBi,xntiP output th~ceshold _ voltages; U~x , Ud,~ input voltagesi U~L~x Uar~X output voltages of unity and zero. These parametc:ra may ba used to calculate the following~ vdltages of static noise reaiitance U~~ M=~blz nsP 'Ul ~d U~ ' U~ -U~ `~x logic ex ttoP noa 9x n~P - ~radient U~ =U86~x -U as well ~as the zone of sxitching d U = Ul - UU. - OMSt Bx no p ex n oP Taking into account the low valuea of output lagia and the unavoidable technologi- cal spread of rated elements (therefore, also of the electrical parametere of the keys). maximum and minimum parameter values were established for the ~STL circuits _ tha,t determine the trariafer characteristic (Table 3.t5). These pa.'"ameters cor- - respond to the alloxable valueB of atatic interferencea (for -~O~C 75�C) Ul~~,y > 12$ millivolts, U Ro,y > 155 miiiivolts= to deviation of output levels of 1 az~d 0(for t= 25�C), 4 U~k ~ 690 millivolts; switching zone (for t= 25� C~ J U~ ~ 3?0 anillimeters. ~ We will nox consider the input characteristic of the basic logic element 4R~N~~ ~ OR of the F~TL series (Fig. 3.2~)., The input characteristic of this circuit (Fig. 3.28~) has four zones. In zone 1 the input transistors are blocked and the inpu,t current is loK (equal to the lea.kage current between tha collector and the base). ~tire current I3 flows through the emitter circuit of trar~,sistor VTS. In zo~e II, as the voltage increases on one of the input tranaistor V'T1-YT4, it gradually becomes conducting. The input current increases xhich increases collector current J~1 dua to the cor- responding reduction in collector current I~ of transistor VTS. A~t a certain value of voltage UeX , collector current I~ is reduced to a value considerably lbwer than I~ . In this case; the current throu~gh resistor R7 remains practically constant. In zone III~ as voltag~ U ex increases further~ current I~ and voltage UR7 will increase as a result of which the differential input imped,ance of the circuit will rise sharply. In zone IV, the transistor becomes fully conducting and picks up all of current IK1 .N I3 = const. In the cut-off state of the circuit~ at voltage 1 on output 2, its working point is located on zone I of the input characteristic~ while in the conducting state in zone III. Zone II is a transition ~one. In this atate the input impedance is minimal, while in zones I and III for U~equal to voltages 0 or 1 the input imped- ance is high. - 103 - ~FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500480030-5 - ~ 5~ c�^ om ~a0oc~ ~ ~ I 1 i! ' 1 1 I r'I r` r-~I N i ~ 1 I ~ ~ ~ ~O ~ N - o~' .i ~ c i~ ao ao ~ i ~ i r t~ ~ i ~ 44� . _ � ~ ~ � o '~~",~i '^ti~ o`~c�~ ~ ~ m r ~cd 4-~ o ~ ~ 3 ~ ~ ~ ~ W 0~ ~0 U O ~ il ~r~i tl ;1 ~ ef ~i e'1 ~~'1 � ~ ~ ~ r~-i ~ r"~ ~~-1 r~-I ~ ~ m ~ i-1 m � * t 1 1 U ~ ~ r..~ r..j r~l eil ~;1 cd _ ~ . U ~ ~O ~D ~ ~ ti 4-~ ' ~ ~ ~ p r~-I ~ ~ 1 ~ ~ O ~ ~ O ~ O l'''1 N ~ ~ ~ ~ ~j ~ ~ ~ Q m m . � ~ o m , b ~ ` o ~ ~ _ ~ . m o $ ~ ~ ~ ~ m , H ~ N ~ O ~ ~j. ~ a ~ ' ~ ~ � ~ ~ .~o a~ ~ o ~ ~ ~ U H � y1 ~ O O � N O , ~ ,~-I ~ ri ri ~ N I ~ ~ a @ 'd ~ 'd k oQ ~ N ~ ~ mqp' ~ 'a~a a cd O ~ ~ ? Hm ~ ~ ,.i � ~ .C ,-1 O ~ ~ O ~ ~ ~ ~ m ~ ~ ~ ~ ~ m 40 m ~ ~ ~ c~'i ~ a ~ w a ,a ~ ~a - ~ a~ r+ ~ ~ -104- FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 Table 3.16 Electrical parameters of IC aeries of ~~L i~arameter Ysl~ue_s Ambient temperature, minimal mdxi~mal t~. C - -o ~ Input current 0, Iax , microamp . 0.5 - ~ 25 Input current 1~ Iex ~ microamp. - 265 25 Output threshold voltage ~-�9~ - ?5 1, U~$~{ , volts - 1.04 - -f0 Ou~put threshold voltage - -1.605 75 _ 0, U~b~r noP ~ volts - -1.650 -10 Output voltage 1, U~~,X y -0.9 -~�72 ?.5 volts 0 -1.02 -0.86 �-10 Output voltage o, uB,,~x .volts -1.88 -1.6? -lo Current used I,,,T,.ma ~ - 25 75 Time of propa~a,tion delay ~rhen - 2.9 25 connected, t3RPd, nanoseconds .~ime of propaga:tion delay when - 2.9 25 disconnected t ~o ~ nanoseconds ~ Oiztput branching coefficient Z5 75 -10 Power ~onsumed P R,T . - 35 25 milliwatts (per logic element OR-NOr~OR ) ~ The output characteristics of the key at the transistor YT8 output (see Fig. 3.21) are shown in Fig. 3.28c. Depending upon ~~�he value of the givan voltage at the output, current Iei,x will flox into or out of the circuit. At e~h circuit state~ the reduction in U~b~K at the YT8 transistor output lea~da to this transistor being more conductive~ and an increase in outflowing output current Isb,x . An increase in UdMX ma.kes this transistor less conducting and increasea the infloyring output current I~b:~ . A further increase in U~~x nre,y make the emitter repeater fully nonconducting, after which the current xill be determined by the load imped.ance - which will determine the slope ~f characteristic I6rrn ~Ue?~x The low output impedance of the emitter provides a high loading cagacity of the F~TL circuits on DC. Hoxever~ the actual loading capacity in the dynamic mode~ due to the input capacitance of the cirouit and the capaaitance of the xiring ia re- duced to KFQ3 = 15� - 105 - FOR OFF1ClAL USl. ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 we will now consider the dynamic parameters of the TaBTL elrcuits. The ~3~c p~iti4m- eter that dAtermines the c~jmamic gropertiea of ~h~ aircuit is the propagation delay time when connecting and diaconnecting 0~ t~~p), ~TL circuits are the quick- . est digital IC. At normal conditia~s and loa.d impedanGe R~ 51 ol~s ~ t~,h,Q~, t~ical ~ propagation delay time is 7 nano~econda. The delay time iB measured at the level of 50y6 from the full gradient of the logic level when the circuit ia switched. It may be seen from the characteristics shown in ~`ig. 3�29 t~t the greatest effect on the propagation dela~ is prod.uced by a change in the feed voltage, the voltage bias level and by an increase in the capac~,~ive loat~ciA6. FSTL series 100~ K500 are considered to have identical electri~al parameters and differ only in functional composition~ the type of 'i,~~~^ing and the operating con- ditions. Table 3.16 shows the values of the operati.ng electrical parameters of the basic logic elemertt of series 100 and K~00 in a temperature range. The limiting allowable modes of operation for the ~TL series is shoxn below: Maximum feed voltage~ UNn ~ volta -7 for 5 mil].isec; -6 constantly Maximum input voltage UBx mAx ~ volts ~ Minimum input voltage Ub,. , volta -5�5 Maximum output current Ig~,x max, milliamp ~ 3�5�3� Certain Special Features in the Use of IC type BSTL We will consider the special fea,tures of using IC type ESTL on an example of the series 100. As already mentianed above, ESTL csircuits ha~e a negative feed voltage source of -5.2 volts � 596 and~ because of this, negative volt es of logic levela. Moreover, ESTL circuits logic levels ere low in absoiute valuA~Udb~^..'~ - 1 volt and U~,,,~ ~-1.65 volts). All this does not allow direct connectiaal to inputs and outputs of IC type ESTL to IC type TTI, or the use of ML5 structures. For the mutua.l interfacing of logics~ special circuits of converter 100PU121~F and 100PU125 must be used. In wiring apparatus of IC aeriea 100 (besides IC ~ypea 100LP315~ lOGLP116 and 100LP124) all unused inputs and ou~puts are left free. Unused inputs of IC types 100LP115 and 100LP116 muat be co~nnected to a.referer~ce voltage souxce (leadout 9 of IC type 100I,P115 and leadout 11 of IC type 200I~P116) or to feed voltage source UN~ _-5.2 volts Unused inputs of IC type 100PU124 are connected to feed sc~urce UN~ = 5.0 volts + 596 through a resistor rated at 1 kohm. No aore than 20 unused inputs may be connected to ane reafstor. If it is necessaxy to feed a conatant si~a1 0 to inputs of several IC, it may be obtained from any logia lC aeries 100 tha,t forms si~al 0 xith the caruiected inputa. The number of loads which may be oonnected to the output of auah an elem~ea~t ahould not exceed 24. - 106 - - FOR OFFiCiAG ~!SE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080034-5 ~ . o,r t~ ' t~A1~"Y~p~~ � frv'ti P�HC fR~ 2 ~ tkv - 3 ~ t~av t ~v 2 ~ � >50 ?SO ~ !/i '~i6 -~2 -4,8 -4,4 . . or ?o . f~~v~t)ip~M," t~~ t~'e MC ~ lA/~ 1A0+ 4 tj P f1A~f ~ Z tv~ p r~ p Z f ~ 0 4o eo ~~,�~3~" y~� -z,6 -a; -,,e _,a . 61 ~ t~~r: taq v~ MC ~ s P y t~l' .-~o o zo ao~ 6o eo r. �c e _ Fig. 3.29. Relationships betxeen dynamic pe~rameters and~ resistiv~ loaci ;a), load capacitance (b)= vo~tage feed source (c)f biae voltage d i and temperature (e). ~ 1. nanoseconds � 3. picofarads 2. ohms The E.STL microcircuits considered.above allox a combination of direct and inverse outputs into a"xired QR" and a"xired AND" xith a combination coefficient Ko~ ~ ~ 4~ as well as a combination of a direct output xith an inverse one (Fi,g. 3.30). The latter combination method makes it poseible to receive and transmit ai~als ' from several elements nver one common comtaunications lina (Fig. 3.31a). . - 107 - FOR OFF'[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500080030-5 , ~ X~ n~ x~ ~n~ ns X, n' ~ X 7 0 X & 0 Y X Xs X1 Xf . xr � x/ Z ~ x D2 Yz . ti x ~ - X X ~S xs a) ~a) . s b) ~b) Xf r) ~c) . ~8� 3�30. Combination of IC type ~TL outputa into a"xired C1R" (a) i~nto a "wired AND' (b), ~ combination of direot and i.nver~e outputs (c) . It should be remembered that as the number of combined outputs is increased., the levels of output voltage change, xhich 1'ee,ds to a reduction in the aoise resistance of the IC. Moreover, in the "xi,rad CR" operatizlg m;od.e xhen eveia one IC is sxitched from state 1 to state 0, a z~ega~tive interference appeara at the output of ~the com- bined circuits (Fig. 3,'ilb) which may cause a~alae ope~catioti of the load eiement. The amplitude and duration of the interference dependa on the ~.ength of the com- munications line that connecta thQ elements in the "xired l~t." Takir?g ~he above into account~ it is recommended to aombine outputs xithin one b~ ~d, if possi- ble, outputs of IC which are beside each other. Taking the qutp~3t Pran the board of an IC that does not have an output coobinat~.on is reaomq?~$ed. r, ~ X. ~1~(~ - - - �-t - Y. , v . (/ar ~ I ~ y t J', - -~y ,1 f,~ ` r-- _ - - - C I r p" r~ ir' � _ ~*t~_-'------ ,G � '~9 ~~"9 ~ 4 ~ � ? T , .t. ~ r"�" P/ dJ ~8� 3�31. Circuit ~'or signal ~ran~miesion fron eaver~l IC type ~iTL over one common communiaatica~e line (a) aad a time dlagram (b) 1. Udx~ input voltage 3. U~-- output voltage 2. U~aM interfere~?ce voltago k� ~CneM i~terference time - 108 - FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-00850R000500484430-5 I~OR ()MFI('IAI, ll~~; ANLY 'i As already mentioned above, FSTL circuits have a fairly high load capacity (Kp4~ ~ 10) wh~^h is due to the lox input impedance of the emitter repeaters xith which the keys are eq,uipped and the low values of the input current (less than 265 microamperes). iTithin one lboard~ the load capacity increases to K pQ~ = 20 and for microcircuits 100LL110 and 100LYe111~ desi~ed to operate simul- taneously on three transmieaion lines, the load capacity is atill higher (~CPa~ = 30). It is recommended that the output of trigger circuits be loaded no more than with 6 inputs of IC loads. It is recommended to connect inputs of no more than Y6 key- loads to the output of circuits, combined in a"wired L~." In this case, the re- duced level of the output voltage and an increaee in.the propagation delay time should be taken into account. When the logic element operates with a�load resistor rated at 51 ohms (at Uc M y - - -2 volts) the delay increase xhen connecting one input of the IC load is 0.1 nano- ~ seconds, while the change in the duration of the output eignal front for an in- crease in the load from 1 to 10 inputa does not exaeed 0.5 nanoaeconds. In all cases~ when determining the alZowable number of inputs that may be connected to the IC output, i~ is necessary to take into account the aombination of several in- ~ ~puts within these IC. With the direct operation of elements with one another (over short lines of communicationa), reaistors of various ratings connected to voltage sourcea UNn =-5�2 voltg or to U~Ky =-2.0 volta may.be used in the emitter circuits of the output repeaters. The presence in the above-considered ~TL aeries triggers and logic elements of various types makes it easy to design typical functional computer units and dis- crete automatic system devicea. Fig. 3.32 showa a 4-sta.ge ahift register circuit. The outpu.~ part of the circuit is made up of 100T1~Q31 triggers, the parallel�da.ta inpui: ~ircuit is made up of IC type 100IS119, xhile the output part is a decoder with two inputs and- four outputs ma,de of IC type 100I,M].05. To increase the number of register stagea~ data is fed to input n_1 from the output oP the previous stage and to input Dn~ from the output of the folloxing stage. Depending on the type of signal, operations~ enumerated in Table 3.17, are implemented at inputa S1 and S2 by the circuit. S;mchronous binary pulse counter (Fig. 3~33) ia made of IC types 100TM131 (D5~ D6, D6.1), 100IS118 (D1...D4) and 100LM105 (D7). Input Q,~_1 implements the carry from the previous stage and output Q,~~ the cazry to the folloKing stage. The counter operation is controlled at input S of ICl00LM105. With 1 at the S input, the circuit implements the function of a counter. Yith 0 at the S input, the circuit operates as four triggers and receives data in inputa D~...D3. The combined utiliza,tion of FSTL and TTL circuits (Fig. 3.34) makes it possible to _ design special purpose units. Fig. 3.34a ahoxs an indication circuit, designed with IC type 100PU125 (D1) (seriea ~'!'L) and IC type 133LA7 (7~) (series TTL) using the NSM 6~3-20 incandescent lamp aa an indicatar. - 109 - FOR OFFIC[AL USE ONLY ~ APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONI.V Table 3. 17 Operations implemented by the four-stage shift register~ depending on signals S1 ~ and 52 Inputs Implemented operation . S1 S2 - 0 0 Blocking . 1 0 Shift ri~ht 0 1 Shift left , 1 1 De,ta received in inputs D(the cir- cuit operates as four triggers with seperate inputs and outputs) Table 3.18 Ra.ted resistance resistors R1 and R2 xith parallel matching P. ohms Rl~ ohms R2, ohms 50 8~ 130 121 195 100 162 2~ 15o z43 390 . Taking into account the high-apeed action of the F3TL circuits, special attention should be given to the arrangment of the communications lines between individua.l IC, as well as to boards and units. Circuita types 100LP115 and 100~,P116 which are paxaphase signal receivers from a tKO-wire communications line~ were considered previously. However~ da.ta tranafe~r between individual circuit boards ma.y be im- plemented by single-phase aignals (Fig. 3.34b). . When a single-phase si~al is fed from the output of IC series 100 (D1...D3) to one of the inputs of the IC types looLP115 (DS...D?) or 100LP116, a reference voltage must be fed to the aecond input, groduced in IC type 100LP115 (leadout 9) or 100 LP116 (leadout 11) located in the board from xhich the aignal is transmitted Fig. 3.34b). QZe reference voltage aource on the tranamitting board (D~i~) may be loa.ded in the receiving board with no more than 10 inputs. ~ch IC type 100LP115 or 100LP116 may be used as a reference voltage source (D4) when transmitting be- yond the limits of the board and as a aignal receiver from the communications line (DS...D?)� The reference voltage tran~~aission line must be decoupled at the transmitting and receiving ends by no lese than 1000 picofarad capacitars. ~ Three basic communications methods are i�acommsnded within the limite of aa~e board. The series method is used for a communications line not over 200 millimeters ' _ - 110 - FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 r ~ r ~ � p ~ t � ~ N ~ w'Q w w w w ~ n ~ ~ ~ ~ ~1 f0 h w ? ~ o ~ ~ ~f ~ V ~l t9 Q ~ ~ � O . _ ~ ~ 4c H ' . . , � ~ ~ . s� . w w w w W . . . � ~ M ~ ~ w N w ' . ~C ~ ~ � v r-I r1 - rl . ~ . ~ O . ~ ~ . � - - ~ . ' t1p ,~1 � . ~1 ~ O f ' m ~ ~ ~ c~ ~ w ~ ~ w w w ~ ' ~ ~ ~ ' i ~ ~ . ~ p F~ 1~ w ~ q y R v v nk U R ~ ~ ~ � ~ FI ~ . � ~ . N ~ � ~ ~ ~ w w ~ ~ 1N~,~ff M* ^ C! ~L N. w i: .h. f""~ ~ ~ ~ ~ O ' ' "-'p ~ U ~c O ~ O N~n b ~ iC 1'2 � ^a �~-1 R m . s~ , ~ ~ ~ ~ ~h ~'A ~ ~3 ~i N b ^',it w ~ N - ~ w w ~ v ~ . w ~ N ~ y~ ~ ~ ~ ~ li~ ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 - On-I c , 3 ~ $ ~ 4 DS ~ ! . ~ ? 2 S 2 ~ , . _ , lt,i s ' ; D . 3 ~ � ~ 1 d~ 4 ~ � :l. � ~5 S � t _ . ~f K � ~ f' q 1 . . . s S r .(i.d 2~ Q 3f C , Il'l 5 S ~ Z ! ~ 3 f a _ 2 4 4 i ~ 0 " ll~ d f 6~ ~ 5 i ~ ~ r f5 D.,.! . ' ~ . ~ & ~ t ~ ~ ~ . !/y r~ ~ ' j/ I4 f5 R 12 f / / ~ � s 3 ' ~:r ~ � ~ L_ _ . ~ . ' ~ ~ ~ n~- t . ~ . ~J~"l_._f'-'L._J"-LI-L!'-LJ' t - - ~ ~ - - .:~2 . t . ~ . - _ f 4~,z � t c~ ~8� 3�33~ 3ynchronous binary pu3se caunter from 0 to ls (a) and ti~e diagram of counter operatior~ ~b) . ~ - 112 - FOR OFF'ICiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-00850R000500484430-5 1~()It ()M1~1('IAI. IItiM: ()NI.Y ~ Df D2 ' U�n-SOet~q�.i . . ~ /ISI a ~ 4 y � -------t~~~ B NCMa3-?0 /1~r'~�~~ I j /Ar~e � b, D/' i I 2 rs !If ' a~ D2 ~ I I~ f ~ ~ - ~ Nl A D? ~ I I ~ ~C2 9: . f j ~ 06 / ~ I -5,10tS% . ~ ~ D1 D2 � ~f I 1~C3 ~7 f 1 . � ( ~ 1 � ~ D3 D4 j I Z~ . 1 I ~ � ~ D4 G1? ~ ~ ~ . ~ 3, ~ . ~ . f~fa,y`-te3~, ' ' � r1 ' ~'1 , Fig. 3.34. Some FSTL connection cireuitst a-- indication circuit= b-- data transfer circuit between txo boards of the devicei c and d-- eeries arid parallel matching of aommunica- tions lines. 1. Panel 3� Reference line 2. Communications line 4. -2 volts betxeen the IC ai~al source and the load resistor. IC loads are connected along this communicationa line. The recommended length of the communications line should not be greater ~han 30 ~ua. In the beam mbthod~ beam linea no longer than ~0 mm branch out at the end of xhich are connected IC loads. The load resiator is conn9cted to one of the IC loads. Finally~ in the concentration method~ from the point of connection of the load resistor, at the end of communicationa line 200 mm long, communicatione lines also 200 mm long branch out to IC loada. - 113 - FOR OFF'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 To eliminate "ringing" at the ai~al receiver i~.rut, it is r~commended that the data be tra,resmitted over a matched communications line. Fig. 3�3~+c~ d shoxs circuita for implementing the series and parallel methods for matching communica- tions lines. For communicati~ns lines xfth xave impedance A= 5~ ohms~ rated reslstors R1= 43 ohms and R2 = 240 ohms (xith aeries matching) au~d R1~.= ~1 o,hmd.. (with parallel ma.tching) are used. Another method for parallel matching~�(by means of two resistors~ R1 and R2. aonnected at the e~d of the line) is alloxed~ using the voltage of the bias level aource U~my =-5~2 volts f;86 to Which resistor~�A2 is connected. The recommended values of resi~tare R1 and R2~ depending on the wave impedance of the line, are shoan in Table 3.18. CC~YRIGI~Ti Izdatel'stvo "Sovetskoye r~dio"~ 1979 2291 cso~ 1863/209 - 114 - FOR OF'FICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ; 3.6. Digital Integrated Circuits Based dn MOS Structures Integrated circuits based on field effect structures have become widespread in recent years. These structures are so named because their operation is based on the regulation of the current level in the laqer of semiconductor near the surface by means of the influence of a transverse electrical field on the channel conduc- tivity. Field effect transistors with oxide insulation which form a metal-oxide- semiconductor (MOS) structure and transiatara with combination nitride-oxide insulation (MNOS) have found practical applicatione.~.in digital IC's. MOS structures are divided into two kinds: MOS transistors with built-in (doped) and with induced channels (Figure 3.35). In transistors of the latter type, the channel is created (induced) with the action of a control voltage which is fed to the gate. With an increase in thia voltage, the channel is enriched by the carri- ers. In doped channel transiators, the channel is created in the production process. In terma of the type of conductivity, field effect transistors are broken down into p and n channel types. In contrast to bipolar transiators, the current in the channel in MOS transistors is transfered by the majority carriers. MOS tranaistors are four-electrode semi- conductor devices. The electrodes ~firom which the motion of the majority carriers in the channel begins is called the source; the electrodes towarda the majority carriers move is called the drain and the gate is the control electrode. The fourth electrode is connected to aubstrate - the semiconductor region on which the transistor is:fabricated. By applying a voltage to the gate, one can change the current level in the channel (with a constant voltage at the drain), and this means, one can change the channel resistance. MOS transistors, in contrast to bipolar ones, are voltage controlled, and in this sense are an analog of vaeuum tubea. Three variants of NOT gates using MOS transistors ~aith induced channels are shown in Figure 3.36. Integrated circuits with MOS atructures have a number of advantages over bipolar circuits. They are simple in terms of atructural design, well suited for production processes, have a high noise iumunity as well as well ae a low power diasipation. An MOS switch occupies enormously less area on the aurface of the substrate as compared to a b ipolar switch. This makes it poesible to produce IC's with the equivalent of up to 10,000 switches on a single chip. The majority of digital IC's using MOS atructures which are being produced at the present time are based on MOS transistora with induced p-type channels, or as they are still called, p-channel transistors. Integrated circuits using crnnple- mentary MOS transistors (CMOS) as well as n-channel transistors have become wide- spread in recent yeara. We ahall deal with IC's based on MOS structures in more detail. 3.6.1. The Operational Principle of Integrated Circuita Using p-Channel MOS Transiators. - 115 - - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY S G D N ~ ~ Figure 3.35. Cross-section through a atructure with an induced (a) and a built-in ' p (b) channel. ~A07 ~l~ Rey: 1. Channel; " 2. Subetrate. ~ ($)a~~) H~ D 0 ~(1~ . n (b)a~~ ~ ~ . � , ~ . -Df,s t(~G~ ~~G~ + b se bias ~ r-x ~ r-~r v-~r ' x x x ~8) a~ (b) al e1 Figure 3.36. Circu its of inverters: using p-type channel MOS traneistor~ (a), with an n-type channel (b) and using complementarq transistors ~c). We shall analyze the operational principle of an MOS tranaistor with an induced p-channel [5] (Figure 3.37). If no voltagea are applied to the structure, the p-n junctions which are formed by the drain, sburce and eubatrate regions, are cut off. A negative charge of mobile electrons, which establishes equilibrium for the positive charge of the surface states Qsur ~Figure 3.37a) is formed at the separation boundary between the semiconductor and the dielectric. The elec- trical field is concentrated at the separation boundary of the semiconductor and the Si02 oxide. When a negative voltage is applied to the gate, an electrical field appears, the action af which i.educes the internal electrical field at the ~ separation boundary. With an increase in the negative voltage at the gate, the free electrone are diaplaced from the region adjoining the gate and a depleted layer is formed in it. With a further increaae in the gate voltage, the concen- tration of positively charged holea increases at the separation surface (Figure 3.37b). - 116 ~ FOR OFFIL"IAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080030-5 With a definite voltage at the gate, when a sufficient quantity of holes is accumulated in the channel region, the conductivity of the separabion surface becomes of the hole type and the p-type regions pr!rve to the joined to each other by means of the inveraion layer with the p-type cox~ductivity. This laqer also serves as the channel ~Figure 3.37c). By applying a signal to the gate, one can modulate the number of carriers (holes) in the channel region, i.e., regulate the current flowing in the channel. The channel of the transistor is ieolated from the major portiion of the subatrate by a high resistance bulk charge layer. For this reason, if several transistors are fabricated on a substrate, one can dis- regard their cross-coupling: A furthez increase in the voltage at the gate does not change the voltage in the bulk charge layer in the substrate, since the channel ehich is formed ahields the remainder of the aubstrate. However, the voltage drop across the bulk charge layer can be varied by applying a voltage to the subatrate. A negative voltage applied to the substrate turns on the p-n junctiona between the substrate and the drain and source regions. A posi- tive voltage increasea the bulk charge thickneas, reduces the channel conductivity and with a further increase, can lead to the complete disappearance of the channel. Thus, the substrate, just as the gate, can be used as an electrode which controls the channel conductivity. - - - , _ -Us ~ aa ~ Qn~ 0^~ 0n~ + ' p* rf. mOQ0M0 ~ ~ 00 00 ~eO~VVJ VN~TJ~ i . X~~~~~ ' ' DO~~0~0 e~~0~~ ~ ~ ~ ~~0~0 a~ (a) ~ (b) ~ . SJ (c) . ~ ~ , . ~ ~ ' ~~.~A~ microamps 3 ~ ~ ~ ~.-~zd , . . -ro ~ ~ ~ . i - - SUO ~ d . I . p -6 ~ . ' � _y I R � ~ 0 'p1 "1/G~ o ~ . ~ r~ ~d~ ~ d~ ~e~ ~ Figure 3.37. MOS trar.sistora with an induced p-channel. a,b,c. Varions degrees of channel enrichment; d. Saturation mode (the channel length decreases); e. An example of the volt-ampere characteristic. -117- , FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R040500080030-5 � ~ ~ FOR OFFICtAL USE ONLY -UN~_- VT3 ~ VT3 X~ $ Y'Xf'X2 ' X~ ~ Y Xf+X2 X~ ~ X2 VT2 y xr " vr~ vr~ vr2 � xi Xt X~ ~ ~ ~a~ � ~ (b) 6~ ~ -a~~ ~ -u,~ X' ~ ' � . vr2 X r�Xl !'~~'i VT5' . ~ A � . , ~ Y , VT3 ' vr> vra . X, X.X~ ~ X X~ ' ' ' , VJY , ~ VTT VT4 X ~ x~ , ~ Xz VT4 ~ ~ . Gi a . e1 ~ u ~d~ Figure 3.38. Schematic of basic logic elemente for p-channel MOS transistors and their functional~designation. a. NAND gate; b. NOR gate; c. AND-OR-NOT gate; d. NOT gate with a buffered output. The voltage at the gate for which an induced channel appears between the drain and the source is called the turn-on voltage (Uon). A certain drain current ID flows in the transistor channel with the action of a potential difference between the drain and the source. When the drain voltage UD ia low, the current ID ia directly proportional to the applied voltage and changes linearly. With an incrase in UD, the current ID will increase, aince the electrical field along the channel increases, but UD will simultaneously compensate for the voltage applied to the gate, something which causes a reduction in the channel thickness near the drain (Figure 3.37d), i.e., causes a reduction in ita conductivity and leads to a deviation of ~he function ID ~UD) from a linear law. Moreover, increasing UD leads to an ire~rease in the potential dffference between the chanzel and the sub- strate, someth ing which in turn causea the thicknesa of the bulk eharge along the channel to change. A further increase in UD leada to a reduction in the channel - 118 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFiCIAL USE ONLY length and the saturation of ID. The saturation condition is defined by the ex- pression: IUD limitl IUGI IUonl. -aMn ~~a -aM, v~n vr~t 0 0 I YTf3 -~1'f~S ~ V75 Y74X I Tt ; . 2 I 1 Xl t ~ l~T14 YT9 Y71t7 T~' ~ V7Y V7Y 1 ~ a,e �1 a ~ vra vr~ , i T~ m c sec. i ! ' ~ ~ ; "xc { vrs " vn S i rt ~ i . ~ . i , t,nxc ~ ~ ; ~ � v� vrr T, 0 - ~t,xxc vre � vra ~ . 0 ~~(c) ' f! ~b) ~ . Figure 3.39. Schematica df flip-flops uaing p-channel MOS transiatora. ~ - a. Static flip-flop; b. Universal two-stage flip-flop; c. Time diagram ehowing the operation of the push-pull flip-flop in a cou~t mode. As can be seen from the volt-ampere characteristic of an MOS transistor (Figure 3.37e), the limiting voltage UD lim dividea it into tw~o working regione: the � - triode mode region (1) where the drain current ID ~s strongly dependent on the drain voltage U~ and the pentode mode region (2), where the drain current ID almost does not change with a change in the drain UD. The breakdown region~(3) ie not used in operation [6]. We shall not consider examples of digital IC design based on p-channel MOS tran- sistors. Three kinds of circuits ueing MOS transiatora exist and are rather widely used: static, quasi-static and dynamic. The high input impedance of MOS transistors is used in quasi-atatic and dynamic circuits from wt~ich follows the capability of the parasitic gait capacitance of retaining a charge for a long time and maintainirig the voltage level across the gate. Circuits of this,typg are most _ widely used for the construction of fl'ip-flop devicea, registera and countera [1]. - 119 - FOR OFFICIAL U3E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY 3.6.2. Static Circuits Using p-Channel MOS Transistors Circuits of basic logic gates which perform NAND aad NOR functions are shown in Figure 3.38. For the sake of simplicity, the circuits ~f the substrate, which as a rule, is joined to the source of the transistor;:~are not shown here and in sub- sequent figures. In switching circuits with a cammon source, designed around p-channel MOS transis- tors, a negative drain supply voltage is used. These are so-called negative logic circuits, i.e., the lower voltage (low level) corresponds to the output "1" volt- age, and the higher voltage (high level) corresponds to the output "0" voltage. The circuits shown in Figure 3.38a,b contain two switchiirg transietors each, VT1 - and VT2, as well as one load transistor VT3. The gate of the load transistor may~ be connecte~ to the bias voltage source, which usually has a higher level (in terms of its absolute value) than the voltage being switched by the switching circuit. The gate of the load transistor is moat often connected to the source of the supply voltage for the drain circuits. To realize the "NAND" function (Figure 3.38a), awitch transistore VT1 and VT2 are connected in series with the load transistor VT3, forming a so-called tiered con- figuration. 3'he current can flow through transistor VT3 only given the condition that transistors VT1 and VT2 axe turned on, i.e., when signals are present at both inputs to the NAND gate. The number of switching transistors (the input fan-in factor Kin AND~ ~an be increased, however, it usually does not exceed four. Be- cause of the high input impedance of MOS tranaistors ~Rin > 1012 ohms), digital IC's designed around them have a high load fan-out factor ~Kout > 10 20). The load factor is limited only by the reduction in the switch speed with an increase in the number of loads, since the time constant for charging the parasitic capa- citance of the load with the current flowing through the load traneistor increases. When Kout = 10, the parasitic capacitance of the load will amount to Cload � ZO pFd. Considering the fact that the resistance of the turned-on load transiator usually falls in a range of 25 to 50 KOhms, we obtain a charging time constant of Rload~load - 0,5 to 1 uR�=, which corresponds to a maximum working frequency, fr, of about 1 N~'?~. A NOR gate (Figure 3.38b) is iormed by.the parallel connection of the switching transistors and the connection of their co~an drains to the source of the load transistor VT3. Here, the current path through transistor VT3 is turned on when one of the transistors ~.turns on: VT1 or VT2, i.e., when a signal is present at one � of the NOR circuit inpute. The number of inputs (the fan-in factor, KinOR~ ~a~ here be twice as great than in the case of series (multitiered) circuits, and runs up to 10. This is ~xplained by the fact that parallel NOR circuits have a~alue for KinOR Which is limited only by the reduction in the "1" level by virtue ofi the voltage drop across the load from the overall leakage current in the drain--source circuits of the input transistors. Since this cur.rent is quite sma11, KinOR can - reach 10, An increase in the number of input transistors in multitiered circuits though complicates the topology and reduces the level of integration of p-type MOS integrated circuits. Although Ki~~ doea not exceed 4, the tier configuration - makes it possible to realize more crnnplex logic functions, for example AND-OR-NOT (Figure 3.38c). � .-120- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR .OFFICIAL USE ONLY To increase the load capacity, the IC output is provided with a buffer atage. In these circuits, the load capacitarnce is always charged and discharged through the small resistance of one of the turned-on output transistors. The output stage of such circuits is similar to the push-pull transistor output of TTL circuits (Figure 3.38). When there is no signal at the input to the circuit, transistor VT3 turns on and the capaaitance Clog$ is charged; and when a signal is fed to the X1 input of the circuit, transistor 'VT3 turne off, but VT4 turns on. The capacitance ~load is rapidly charged through it. The load capability of such circuits can be 20 to 30, ~ The connection of two inverters makes it possible to obtain a simplified RS flip- flop which contains four MOS tranaistors in all. The complete schematics of flip- flops included the complement of an IC seriea built using MOS structures also includes the control circuits (the "0" and "1" get inputs, the count input, etc.), which can be realized by means of AND and OR logic gates. In the simplest atatic flip-flop ~Figure 3.39a), transistors VT5 and VT6 are used for the control. Let the flip-flop be in the state where the voltage level at the Q output cor- responds to "1", and at the Q output, ie "0"; in thie case, tranai,stor VT1 is - turned off and VT2 is turned on. When a"1" signal ie fed to the gate of transis- . tor VTS, transistor VT5 turne on, shunting the turned off transistor VT1. The voltage at the drain of transiator VT1 decreasea, which leads to the cutting off transistor VT2 and the turning on of transistor VT1. As a reault, the circuit shifts to the new state in which there is a"0" at the output Q and a"1" at the output Q. To change the circuit to the initial state, it 2s neceseary to feed a"1" signal to the gate of traneistor VT6. ltao-stage clocked flip-flop devices conaisting of a main and an auxiliary flip- flop are incorporated in IC series using p-channel MOS transistors along.with - combination circuits. The information entry in auch flip-flops which have inform- ation and clock inputs is accampliehed only by means of the enabling clock pulse. In a push-pull two-stage RS flip-flop (Figure 3.39b), the main flip-flop which receives the information is formed by transistors VT1 - VT4, while the auxiliary flip-flop device which clamps the state is formed by tranaistora VT9 - VT12, The control is realized by means of AND gates formed by transistors ~iTS-VT8 and VT13- VT16. We analyze the operation of the flip-flop. Let the main flip-flop be in the state where the voltage at point A correaponds to the "0" level and at point B i~ corresponda to the "1" level (R = S= 0). If in this case there is no clock pulse - T2, then there is the same probability at the atate of the auxiliary flip-flop will be either Q= 0 or Q= 1. However, with the arrival of the first clock pulae T2, the information will be rewritten into the auxiliary flip-flop frrnn the main flip-flop and it ia set to the Q~ 1 and Q= 0 atate. The appearance of the R or S information signals (when T1 = 0) will not change the state of the flip-flop. However, if a S m 1 aignal arrives at the gate of transistor VT7 and a clock pulse T1 arrives simultaneously with it, the AND gate actuates ~transistors VT7 and VT8), the voltage level at point B will change and - 121 - ' FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFF'ICIAL USE ONLY ~ will correspond to "0", and to "1" at point A. Thus, the main flip-flop will shift to the new state, which with the arrival of the next pulse T2 duplicates the state of the auxiliary flip-flop. Naturally the pulses T1 and T2 should be separ- ated in time. The schematic of a push-pull RS flip-flop (Figure 3.39b) is converted to a push- pull cam;plementing flip-flop if the Q and the Q outputs are connected to the inputs ot _*-he main flip-flop ~R and S respectively). In the absence of the count pulse T1, with each arriving pulae T2 the information will be rewritten from the main flip-flop into the auxiliary one (Figure 3.39c). With the:~~first count pulse T1 though, that AND gate actuates at both inputs of which there ie a"1" signal, and the main flip-flop is set to the state which is the inverse of the auxiliary flip-flop. At the point in time, the rewrite of information into the auxiliary flip-flop ia blocked, since T2 = 0. The next pulae T2 = 1 will set the auxiliary flip-flop to the state corresponding to the state of the main one. 3.6.3. Quasistatic and Dynamic Circuits As was noted previously, the property of a MOS transistor of retaining the charge in the parasitic capacitance of the gates for a certain period of ti.me is used in quasistatic and dynamic circuits. But in contrast to dynamic circuits, quasi- static flip-flops do not require the so-called "clock supply" during the informa- tion storage period. The clock supply is necessary when the information~.i;s entereci and it is realized by means of clock pulses: phases having a width less than the time constant for charging and diecharging the parAsitic capacitances of the gatea of the MOS transistor of the circuit. As com~ared to static type circuita, quasi- static and dynamic flip-flops make it possible to reduce the number of MOS trana- istor.which are used by a factor of two to three times. Two and three phase quasi-static D flip-flopa have bcome thf most widespread. We shall recall that D flip-flope, which are also called delay flip-flope, take the form of a device with two stable states and one information input. The truth table for a D flip-flop was given earlier ~see Table 3.4). We shall consider the operation of a two-phase quasistatic D flip-flop using MOS transistors ~Figure 3.40) [1]. The circuit consists of three inverters: HE1 (VT2, VT3), HE2 (VT7, VT8), HE3 (VT10, VT11); three gates VT1, VT6, VT9; and a phase pulse driver ~2 (VT4, VTS). Inverters HE1 and HE2 form a flip-flop circuit, one of the feedback circuits of which ia looped Chrough gate VT6 only where the signal ~2 = 1 is present. Gate VT9 cuts off ~with the ~2 = 0 signal) or connects the output inverter HE3 to the flip-flop circuit ~in the case of the @2 = 1 signal). Without a clock pulse (the signals (T1 =~1 = 0), gate VT1 is cut off regardless of the signal at its input. At the same time, the two other gates, VT6 and VT9, are turned on since the signal FZ = 1. There will be a"1" level at the output of , inverter HE1 and a"0" level at the output of HE2. The capacitance Cload Which was previously charged through turned on gate VT9 and the load ci.rcuit of HE2 (VT7) is rapidly discharged through turned-on i:ransistor VT8 and a level of Q= 1 is set at the flip-flop output. -122- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 FOR OFFIC[AL USE ONLY - To change the etate of the flip-flop, it is necessary to feed a signal of D m 1 to its input. Then with the a~rrival of the clock pulae (the signals T1 =~1 = 1), gate VT1 turns on. At the same time, gates VT6 and VT9 cut off ~since the signal Fz = 0), the feedback 1`oop for the flip-flop i~s opened and the output inverter HE3 will be disconnected from the output from inverter HE2. With the action of the signal D= 1, which is fed through the turned-on gate VT1, a"0" level is seC at the output of inverter HE1 and a"1" level is set at the output of inverter HE2. However, during the action of the clock pulee, the voltage level at the flip-flop ~ output does not change (Q = 1), since the charge on Cload has still not had time to change substantially. With the completion of the clock pulse (T1 m@1 = 0), gate VT1 cuts off, but since the signal ~2 = 1, gatee VT6 and VT9 turn on, which leads to a rapid charging of the cap~citance Cload through the turned on gate V9 and the load transistor of HE2 (VT7), as a result of which, the ~D flip-flop changes to the state Q= 0. Thus, following the completion of~the clock pulse, at the input of the circuit D= 1 and at the output Q= 0. -U~n ' Nf~ �NET NEJ y}2, Vt7 ' Y7f17 VT8 d ~ vrn ' aX D vr> vra vra v~ ~ ~ ~ , ~Z . ~ _ ~j YTd , , Figure 3.40. Schematic of a two-phase quasistatic D flip-flop uaing p-t~hannel MOS transiators. Quasistatic D flip-flope are frequently uaed to conatruct regiatera. In this case, the circuits which control the writing and shifts, as well as the phase drivers, are incorporated in the IC series. This circumstance makes it possible to use a single cycle external signal sisnilar to thst which we had as the single cycle signal T1 for the two-phase D flip-flop ~Figure 3.40) in quasistatic registers, which are multiphase systema. A drawback to .;uasistatic registera is the powr~ ::onsumption of the D flip-flops in the information atorage mode. For this reason, dynamic registers using p-channel MOS transistore have become more widespread. ' - 123 - ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-00850R000500484430-5 FOR OFFICIAL USE ONLY ~d~n TM~ . TIl~`~ -Qe ~ ; - . - � � nrt , . � vr~ ~ ~ ~ -~G. . 9A ~ Input v~a ~ v~ , t . er . ! , ~ ~ ' , ~ ~i -~-c~ ~-c2 .l..~y � , v~ ~~i . vrz vra ~ ~ aI(a) TI1 ~ Clock ' load � Pulse 1 . . ~ TI2 's Clock Ti N~ ~ Pulse' 2 - 1 - _ -W. TI2 ~j a~ (b) Figure 3.41. Schematic of a two cycle dynamic regiater using p-channel MOS tranaiators for n-digita ~a) and the sequence of clock pulaes (b). Dynamic two-cycle and four-cycle flip-flops are used as shift registers and provide for the requisite delay in logic and arithmetic units of computers and digital automation Qquipment. We shall consider the operation of a two-cycle � dyaamic register using p-type MOS transistors (Figure 3.41) [lJ. A register digit contains two inverters, using three transistors each (VT1 - VT3 and VT4-- VT6). The clock pulse TI1 is fed simultaneously to the gate of the load transistor VT1 of the first inverter and the gate of gate VT3. The clock pulse TI2 is fed t the gate of load transiator VT5 and simultaneously to the gate of the VT6 gate. We sha11 analyze how information is written in as well as its ahifting. Let a signal corresponding to "1" be fed to the input of the firat low order digit. As a result, the parasitic capacitance C1 is charged and tranaistor VT2 turns on. With the arrival o~ the clock pulse TI1, tran.~istora VTi and VT3 turn on and the parasitic capacitance C2 is discharged through the turned-on traneistor VT2. Upon the campletion of the pulse TI1, the charge corresponding to the "0" level is retained in capacitance C2, as a result of which tranaietor VT4 will be cut off. The clock pulse TI2 turns on transietors VTS and VT6, and for this rea8on, a charging curcuit will be formed for the parasitic input capacitance of the next digit. Thus, over two clock pulses, the "1" signal which is fed to the input of the first digit proves to the rewritten into the input of the next digit. -124- FOIt OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 FOR OFFICIAL USE ONLY We shall analyze the case where the input signal corresponds to the "0" level. In this case, transistor VT2 is cut off"and with the arrival of the TI1 pulae, capaci- tance C2 will be charged through the circuit of turned on transistors VT1 and VT3, which provides for.turning on transiotor VT4. With the am ival of the TI2 pulse, the capacitance C1 of the aecond digit is discharged through turned on transistor VT4 down to the "0" level. As a result, over the t une of two clock pulses, the "0" signal which is fed to the input of the first digit will be rewritten into the input of the next, second digit. Since the clock pulaes are fed to all of the register digits aimultaneously, the information shift process runs in all digita simultaneouslq. As can be seen from the achematic of the register ahawn in Figure 3.41a, the power consumption in each of the regieter digita occurs only at the moment of clock pulse arrival, when the load transistors VT1 and VTS are turned on in each digit. The width of the clock pulses is governed by the charging time of the parasitic capacitances (C1, C2,...) and amounta to 1- 2 ueec, which assures a low average power consumption per digit (less than that of quasiatatic registers.by a factor of three to five times). A high power output stage (transiators VT' and VT which provide for rapid discharging (through transistor VT or charging (through transistor VT") of the load capacitance Cload, is ineerted at the output of a dynamic resiters to obtain a good fan-out load capacity. The operational principle of a four-cycle dynamic register ia similar to the operational principle of the.two-cycle version, but four-cycle dynamic registers make it possible to obtain a higher working frequency for the circuit and a lower pawer consumption per digit. 3.6.4. Tihe Operational Principle of Complementary MOS Trsnsistor Integrated Circuits � As can be aeen from the inverter circuit ahown in Figure 3.36c, it ie composed of MOS transistors of various tqpes ~complementary, CMOS transietors). The n-channel ~ transistor is connected to the zero potential (to ground) while the p-channel transistor is connected to the positive power supply bus.+. Such a circuit provides for operation in a poaitive logic mode, i.e., the low signal level corresponds to the "0" output voltage while the high level corresponds to the "1" output voltage. The most widely used series of CMOS circu$ts operate in this mode. Digital IC's based on CMOS atructurea have a number of advantages over p-~hannel MOS transiator circuits: they have a low power coneumption in the static mode (at the level of unita of microwatts), a relatively high speed, good noise immu- nity and a rather large load capacity ~[Y]. The power consum~d by a CMOS tran- sistor circuit is expended primarily during the transient procesa in charging the output parasitic capacitances of the circuit and the internal capacitances of the transistor. For thia reaeon, with an increaee in the awitching frequency of a circuit as well as with an increase in the equivalent output capacitance, the power consumption also risea, something which is modeled by the eq~ation: - 125 - FOR OFFICIAL USE ONLY ~ APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPR~VED F~R RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICtAL USE ONLY . 2 pdyn 2Cloadfw cc where Cload is the equivalent load capacitance; fW is the working frequency and V~~ is the supply voltage. � . In the static mode, the power is govern~d by the power supply voltage and the leakage currents of the turned-off M03 transistor. Static, quasistatic and dynamic circuits can be designed around CMOS transistors just as in the case of p-channel MOS transistors. ~ We sha11 analyze the operation of the simplest static NAND and NOR positive logic circuits using CMOS transistors ~Figure 3.42) [1]. As can be seen from these . circuits, a parallel configurati~on of n-type MOS transistors and a series (tiered) configuration of p-type transistors are used for the realization of the NOR func- tuon. Moreover, each of the n-channel input transiators has the gate connected to a p-channel transistor. The p-channel t~ansistors are connected in parallel and the n-channel transistors are connected in series to realize the NAND function. When an Xi signal corresponding to the "1" level ia fed to the input of the NOR circuit, transistor VT1 turns on and VT4 turns off. As a result, the "0" level is produced at the circuit output. When a"0" signal is fed to both inputs, X1 and X2; transistors VT1 and VT2 turn off, but transistors VT4 and VT3 turn on, as a result of which, the voltage at the circuit output correaponds to "1" level, close ~ to the supply voltage V~~. Thus, the recharging of the load capacitance Cload is always accomplished through a turned-on p or n-channel transietor, something which increases the circuit apeed. To reduGe the dynamic power consum~sf~don, it is necessary to reduce the load capacitance Cload� The minimum supply voltage for a circuit using CMOS transistors is determined by the cutoff voltage Uoff p of the p-channel transistor, since it is greater than the voltage Uoff n of an n-channel transistor. The supply voltage is chosen greater than Uoff p� ~is provides a circuit using CMOS transistors with a high level of noise immunity and good speed. A comparison of the circuits of Figure 3.42 with similar designs ueing p-channel MOS transistors (Figure 3.38) shows that for the realization of the same functions, the CMOS transistor circuits are composed of a greater number of elements, some- thing which can lead to drawbacks for them. But the increased operating speed and low power consumption asaure their widescale application, especially for designing circuits with a high level of integration. In order to reduce the number of elements, a p-type load transiator ia inaerted in the CMOS transistor circuits (for positive logic circuits) ~Figure 3.42c). The circuit realizea an OR-OR-NOT function and contains five MOS tranaistora [1]. We ahall analyze ita operation. When X1 = 1 and X2 = 0, just as when X1 = 0 and X2 m 1, the pair of tranaistors of opposite conductivity will turn on (VT1, VT4 or VT2, VT3 respectively), some- thing which provides for closing the current c ircuit through the load transiator VTS to "ground". As a result, the voltage corresponding to the "0" level will appear at~the circuit output. When X1 = XZ = 1 and X1 = X2 = 0, the upper pair of transistore (VT3, VT4) or the lawer pair (VT1, VT2) is cut off, the current ~ circuit is broken and the voltage at the circuit output corresponds to "1" level. -126- FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY The consutrction of an OR-OR-NOT logic gate uaing p-channel MOS traneietora requires seven transistore. Thus, the comb ining of CMOS transietore ~vith a load transistor makes it possible to realize complex logic functions with a minimum of components. Flip-flop circuita can be realized based on the aimpleat logic circuits using CMOS transistors. As an example, we shall consider the operation of a complementing flip-flop (Figure 3.42d).il]. The circuit is composed of two D flip-flops: the main one which contains the AE1 and HE2 inverters and the in~aerted feedback gate B1, as well as the auxiliary flip-flop which contains the inverters AE3 and HE4 and the inserted gate B4. The main and auxiliary flip-flops are tied together through gates B2 and B3. The phase driver ~1, ~2 ia deaigned around transistore VT1 and VT2. . +aM~ ~ p YT4 YT! Y72 � . Y73 . _rt.. ~ Xt Y~X~ YTf ' n X~ ~ l~TJ i~r4 YTly YTf2 ~ � , +Wn ~a) . vra - ~ v Y�,~j'XL NEd 11~+7 X YT~ YT2 ~ !r/~~ f70 YT13 VT>9 � ~ ~ yC~ X~ Y7f ~ , 1 ~ . e'1 ~r~ ~~e ~""v~r~ vr~s . vrs ~ ~ Y-X~�X=+ ~�XY . YTJ YTk , a? Q~ lYL~1 NE? I79 VTIO YTf7 i'7yd l~Tf . Y72 X ~ .X Z , i ~ , ~ eJ ~d~ ~ Figure 3.42. Circuits uaing CMOS tranaistors. a. NOR; b. NAND; c. OR-OR-NOT; d. Complementing flip-flop. -127- FOR OFFICIAL USE ONLY- APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ~ FOR OFFICIAL USE ONLY Let the main flip-flop be in the atate Q' = 1 and Q' = 0 when the clock pulse is a"0" (i.e., when ~1 = 0, ~2 = 1 and gatea B1 and B3 are turned on, while gates B2 and B4 are turned off). Since gate B3 is turned on in this case, the voltage corresponding to the "1" levels (Q' = 1), in going to the gates of the HE3 inverter transistors, turns on the lower n-channel transistor and the auxiliary flip-flop is set to the Q= 0 and Q= 1 state. However, if the clock pulse is a"1" (@1 = 1, ~2 = 0), gates B2 and B4 turn on, while B1 and B3 turn off. The signal Q= 1 in going to the gate of the lower trana- istor of inverter HE3 through turned-on gate B4 keeps the inverter turned, and the state of the auxiliary flip-flop does not change ~Q = 0, Q= 1). At the same time, the level Q= 0 turns off the lower and turns on the upper transistor of inverter HE1 through the turned-on gate B2, as a result of which the main flip-flop is set to the new state Q' = 1 and Q' = 0. Following the completion of the clock pulse (the signals TI = 0, = 0, ~2 = 1), gates B1 and B3 are again turned on. The level Q' = 0 is fed through on gate B1 to th e gate of the upper transistor of inverter HE1 and turna it on, main.ing the state Q' = 1. Thus, the state of the main flip-flop does not change. At the same time, the level Q' = 0 turns o~f the lower and turns on the upper transistor of inverter HE3 through the turned-on gate B3, as a result of which the auxiliary flip-flop is set to the new state Q= 1. Q= 0. Thus, with the arrival of each clock pulse, the state of the main flip-flop changes, while upon the campletion qf the clock pulse, this state is transfered to the auxiliary flip-flop. The circuit of a static type flip-flop wae treated above, however, quasistatic and dynamic flip-flops can be conetructed with CMOS transistors, where these flip-flops are similar in terms of etructure to the corresponding circuits using p-channel MOS transistore. ~ It should be noted that quasi-atatic and dynamic circuits (flip-flops and registers) using CMOS transistors ntake it possible to significantly reduce the number of elements as compared to similar static type circuits as well as signif- icantly curtail t~e power consumption [1]. 3.6.5. The Major Series of Integrated Circuits Using MOS Structiures Integrated circuits based on MOS structures, because of a whole series of advant- ages, are becoming increasingly widespread. Technological successea have made it possible in recent years to aubatantially increase their level of integration and operational speed, which has to a considerable extent governed their applications areas. In this sense, circuits based on CMOS transistora are to be singled out in particular, where these transistors make it poesible to produce up to 10,000 elements on a chip. The production mastery of these circuits has made it possible to start the series production of compact and comparatively inexpeneive micro- calculators, memory matrices, electronic clocks and microprocesaora. The first series of IC's using MOS structurea were made using "high voltage" p-channel MOS circuits. The K172 seriea is to be numbered among them, based on which an entire family of desk top electronic calculators was created. The - 128 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY composition of the series was limited to four simple logic circuits ~up to 30 elements per chip) and a two stage flip-flop with input logic, These circuits had a poor speed ~tdel.prop. = 1 usec), a high power consumption (40 mW/gate) and h~gh output voltage levels ~in terms of the absolute value) ~U~ut =-7.5 volts; Uout - 2�3 volts) and were not compatible with TTL circuit levels. Also of some interest is the 186 series which was among the first to be created, the complement of which even included a set of 4;~8, 21.and~64 bit quasistatic chip registers and a 90 bit dynamic shift regiater. The IC's of this series had a poor operational speed and large power consumption, as well as a high netative "1" level; however, a negative input voltage to positivQ output voltage coriverter circuit was incorporated in the series (the 186 PU1), which provided for interfac- ing to TTL circuits. The absence of combinatorial elements in the geries some- what limits its applications. Defiecinecies in the initial aeries using p-channel MOS transistors were eli.mi- nated to a considerable extent with the series production mastery of IC's using CMOS structures: the 164, K176 and 564 series ~analoga of the CD4000 and CD4000A). The IC's of these aeries have a dynamic power consu~ption of 20 r,dn1/gate at a frequency of 1 MWz, while their sCatic power consumption is measured in units of , microwatts. The camplement of the widely used series of'IC's based on CM05 trans- istors is shown in Table 3.19 and the names of the analogs are given. As can be seen from Table 3.19, the complement of the CMOS aeries includes entire assembliea, besides the set of logic gatea and flip-flops: registers, counters, memory circuits and level converters, which provide far joint operation with TTL inte- grated circuits. Data on the etructural packaging of the indicated series and their temperature ranges are given in Table 3.20, while the main electrical oper- ational parameters of the basic logic elements of the seriea indicated above uaing CMOS transistors are given in Table 3.21: The application sreas of integrated circuits included in the series of IC's with a CMOS structure are rather extensive. We shall coneider several examples of K176 series IC applications to the conatruction of functional assemblies in equipment. Thus, a four-bit register can be realized using two K176TM2 integrated circuits, two K176LA7 integrated circuits and one K176LA9 integrated.circuits. Each bit of such a register consists of a D flip-flop and a distri~iutor, the preaence of which increases the functional capabilitiea of the regieter, making it a univer- sal device. A bit in a puah-pull shift.:regieter can be designed around the K176TM2 integrated circuit based on two single cycle D flip-flops. Single cycle, series carry frequency dividera are simplest in terms of their circuit design realization. They are made using D flip-flops by eonnecting the outputs of the preceding bits to the inpute of the eubaequent ones. The division factor of such a divider ie ICdi~ = 2h, where h is the numbex of divider bits. Single cycle dinide-by-two and divide-by-eight frequency dividera ~with series carry) can be designed around K176TM2 integrated cir.cuits, but ia more expedient . - 129 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 ~ FOR OFFICIAL USE ONLY TABLE 3.19 The Composition of IC Series Based On CMOS Structures and Their Functional Analogs in th~~CD 4000 (RCA) and CD 4000A ~RCA)__Series Subgroup, Kind and Ordinal Designa- Number s tion of Number of of the the Func- the Outline ' Functional Designation Design tional Drawing in (According Analog Appendix to Function) 3.1. [1] ~2l [3] I4~ Universal logic element (164, K176, 764) ~:LP1 07 ' Quad "exclusive OR" gate (164, K176, 564, 764) LP2 30 3.3.1 Ttao 3NOR logic gates and a NOT gate ~ (164, K176) LP4 00 3.3.2 quad ~NOR gate (164, K176, 564, 764) LYeS O1 3.3.3 ~ao 4NOR logic gates (164, R176, 564~ LYe6 02 3.3.4 Quad 2NAND logic gates (164, R176, 564, . 764, 765) i1`,A7 11 3.3.5 Two 4NAAID logic gates (164, K176, 564, 764) LA8 12 3.3.6 Three 3NAND logic gates (164, R176, 564, ~ 764) LA9 23 3.3.7 Three 3NOR logic gates (164, R176, 564, . 764) LYe10 25 3.3.8 Two 4NOR logic gates and a NOT logic gate (164, K176, 764) r,Lpll - 3.3.9 Ztao 4NAND logic gates and a NOT logic gate (164; K176, 764) LP12 - 3.3.10 A 9AND logic gate and a NOT logic gate (164, K176, 764) LI1 - 3.3.11 Six gated,NOT logic gates ~564) LN1 M314502A - Two D flip-flops with "0" and "1" setting (164, K176, 564, 764, 765) TM2 13 3.3.12 Four bidirectional switches ~164, K176, 764) KT1 16 3.3.13 Five inverting level converters (164, K176, 764) PU1 , - 3.3.14 Five bit counter ~164, K176) IYe2 TA-5971 3.3.15 18 bit shift register (164, R176) IR10 - 3.3.16 4 x 10 decoder (164, K176, 564) ID1 28 3.3.17 - Dual four-bit atatic sh ift register (164, K176, 564) IR2 15 3.3.18 Four bit full adder ~164, K176, 564, 765) IM1 08 3.3.39 Three AND-OR logic gates ~164, K176) LS1 - 3.3.20 -130- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL , [Table 3.19, continued]: ~i] [2] [3l [4] Six-bit binarq counter (164, R176) IYel 24 3.3.21 Four-bit universal shift regiater (164, R176) IR3 - 3.3.22 Z~ao JK flip-flops (164, R176, 564) TV1 027 3.3.23 16 bit main memory storage matrix (K176) RM1 OS 3.3.24 Eight-bit shift register (564) IR6 34A - 256-bit mai.n memory with control circuit (R176, 564) RU2 61 3.3.26 Decimal counter with decoder (R176) IYeB 17 3.3.27 ~,io D flip-flops with "0" set (R176) TM1 03 3.3.28 Six inverting level comrerters ~R176) PU2 09 3.3.29 Six noninverting level convertera (K176) ~ PU3 10 3.3.30 Modulo 6 counter with decoder for data . output to seven segment dieplay (R176) IYe3 - 3.3.31 Modulo 10 counter with decoder for data ~ output to seven segment diaplay (K176) IYe4 - 3.3.32 15-bit binary frequency divider ~K176) IYeS - 3.3.33 Four-bit series-parallel register (564, 765) IR9 35A 3.3.35 Three 3-input majority gates ~564, ' 765) LP13 - 3.3.36 Dual iour-channel multiplexer (564, . 765) KP1 52A 3.3.37 Six NOT logic gates (563, 765) LN2 49A 3.3.38 Four-bit bidirectional counter (564, 765) IYell MS14516A 3.3.40 Quad AND-OR logic gate (564) LS2 19A 3.3.41 Six level converters (564) PU4 SOA 3.3.42 Counter-divide-by-eight divider ~ (564) ~ IYe9 22A 3.3.43 Quad D flip-flop (654) TM3 42A 3.3.44 Quad RS flip-flop ~564) TR2 43A 3.3.45 T'wo four-bit counters ~564) IYe10 MS14520A - Four-bit comparator (564) IP2 MS145585A - Quad bidirectional switch (564) KT3 66A - Arithmetic logic unit (564) IP3 MS1~581A - Through carry circuit (564) IP4 ,MS14582A - Eight channel multiplexer (564) KP2 51A ~ - . 12-bit comparator (564) SA1 MS14531A - Triple majority multiplexer element ~ (564) IK1 - - - 131 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY [Table 3.19, continued]: [1] . [Z] [3l [4] Multifunction register (564) IR11 MS14580A - * * * Note: Integrated circuits of the 164, K176 and 764 series are functional � - analogs of the CD4000 series IC's, while the IC's of the 654 series aTe - analogs of the CD4000A series. ' to construct group carry dividers (using cross-coupled shift register circuits) with a low division factor (of from 4 to 10) uaing R176 series integrated circuits. In such dividers, the input pulsea are fed to a co~on bus for all of the digits; the arrival of the input pulaea at the bit inputs of a given group is determined by the state of the control output of the previoua group of ~igita. Dividers using cross-coupled regiaters have an even division factor of Kdiv = 2n, where n is the number of bits. By introducing additional feedback from the direct output of the highest order digit to the zero set input of the lowest order digit, or~e can produce an odd division factor: Kdi~ = 2n - 1. A series adder with carry storage can be realized using three K176LA7 integrated circuits and one K176TM2. The diatributor for the input pulse train to four � output buses is designed for use in multicycle electron~c devices and can be con- structed using K176LA7, K176LA9, K176TM2 and K176LYe5 integrated circuits. The operational synchronization of the digital information proceseing devices of such a pulse distributor is accomplished by means of introducing a clock generator, which provides for the generation of the clock pulae train and~:the multiplication of the pulses with the breakdown of the syachronized memory ~lements into groups. The number of inemory elements in each group is governed by the fan-out factor of the clock pulse amplifiers ofithe multiplication circuitry. For operation of the K176 series IC's wi~h high power elements, it is expedient to use this ser ies together with the circuit designed around the K149 series IC. The circuit is triggered from a power inverter, formed by the parallel connection of three K176LP1 IC inverters. Circuits of the K176 series can be used in conjunction with K149 series micro- circuits when triggering relays with current parametera of no more than 75 mA and voltage levels of no more than 15 volts, taking into account the permissible deviation in the power supply voltage. In the choice of the type of relay, it is necessary to take into account the change in the re3ay winding resistance as a function of temperature. . - 132 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY ~ TABLE 3.20 Types of CMOS Seriee IC Packages Working ~Designation of Series Tempera~ture Rind of~Package the Packages. Range, C Used in the Series 164 -160 +85 Rectangular metal-glasa 401.14-4 -10 +70 Rectangular plastic 201.14-1 K176 -60 +25 Rectangular metal-glass 401.14-5 564 Rectangular metal-~Qramic 402.16-1 The same 402.16-3 " 402.16-10 " 402.16-16 When designing equipment around K176 aeries integrated circuits, one must consider the fact that the coupling capacitance between the wires connecting the trsnsmitter microcircuits to the data receiver microcircuits is the load capacitance for the microcircuits which transmit the information, an increase in whiCh leads to an increase in the dynamic current conaumed by the microcircuits. In order to pre- clude the influence of crosstalk interference between individual conductors in asynchronous devices, the coupling capacitance should not exceed 100 pFd. When designing equipment based on K176 series IC's, it is necessary to provide for protection against the intrusion of pulae interference into the "power" and "ground" buses, for which it is recommended that decoupling capacitors be installed in the power supply circuits: low frequency and high frequency capacitors. The types of capacitors and their capacitances are chosen depending on the equipment design. The 5-bit counter (164IYe2 integrated circuit) and 18 bit shift register (164IR10 integrated circuit) included in the 154 series providea for operation at a fre- quency of 2.5 MHz. The ultimate permissible operational ~hodes of the 164 series IC's in a temperature range of 160 to +85 �C are giv~n below: Maximum supply voltage, Uip, volts 12 (for 3 seconds) . . . . . . . . 15 (for 5 seconds)[sid] Maximum input voltage, Uin ~aX, volta 15 (For 5 seconds) Minimum input voltage, Uin min volts -0.5 (for 5 msec) Maximum 2ero output curr~ent, Io t~in, mA . 1.0 The same for the one current I~ mA . 1.0 The loweat load resistance for w~iic?~the maintenance of the "1" 1eve1 is guaranteed, Rload, KOhn+~. 150 -133- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY TABLE 3.21 Electrical Parameters of CMOS Series IC's Series Parameters 164 R176 Power supply voltage, V~~, volts 9+ lOX 9+ 5X The "0" input current, I~n, uA, no less than -0.05 ~-0.1 The "1" input current, Iin, uA, no more _ than 0.05 0.1 "0" output voltage, Uou~ uolts, no uare than 1 ' 0.5 0.3 "1" output voltage, U , volts, no leae than out 8.2 Propagation delay time during turr�-on, tZ~~r., naec, no more than 200 250 (when C1 gd= (when Cload = 50 pFd) = 50 pF~) Propagation delay time 3uring turn-off, 200 250 t~alr, nsec, no more than (when Cload s ~when Cload = 50 pFd) = 50 pFd) Current consumption with "0" at the input, I~on, uA, no more than 0.1 0.3 ~ Current consumption with "1" at the ~ ~ input, Icon, U~, no more than 0.1 0.3 Static noise immunity, Un, volts 0.9 0.9 - Fan-out load factor, Kout 50 50 . - - +a.. vr~ ~ t~i, X, ~ . i~Tf T2 . ~yT3 ' y VT5 � X~ ~ ~ YDf Xd V/Q 2 Y~ . X' , YDY 4 . VT7 m X ~ ~ .m VT.i Y!3 Y YD3 x:, v~e m ' vDa VD1 VD2 VD3 VD4 , . d, ~ n . (8) (b) Figure 3.43. Basic schematics of 164 (176) IC eeriea for NAND (a) and NdR (b) gates. - 134 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 FOR OFFICIAL USE ONLY ~ . ' ~~0 Uout' volts-- ti~ P ~'~P~1) . - . . ~ 4pD ~ ~ ~ , ~A7 f'~~ . 60 Uout 1~ ' ~ p � o ' ti~ P ~aZ ~ 2~a Fd - ~ ~_?0 �0 ?0 . aJ ~9a~ 60 T,'G JO 60 90 J.1~ t~{( )C,7~ . ~ � ~ ~o , Figure 3.44. The functions Uout~T) and the propagation delay time as a function of the load capacitance for K176TM2 series IC's. Key: 1. Propagation delay fiime, nannseconds. Using the example of the 164 series, we shall conaider the design principles for circuits using CMOS transietora and eome of~the:specific features of their appli- , cations. As was shown above (Table 3.19), the complement of the series includea logic gates which perfbrm NAND and NOR functions. The 164LA8 (Figure 3.43a) can be taken as the basic IC for the reslization of the NAND function, while a . 164LYe6 integrated circuit~realizes a NOR function (Figure 3.43b). Practically all of the IC's of the 164 seriea are designed around these basic switchea. When the IC's of the 164 series are operated, the unused inputs in gates which realize the NOR function ahould be connected to the "ground" bus, while the circuit inputs which realize the I1AND function ahould be connected to the supply bus. It is permissible to tie the unused inputa together with the uaed input of the same logic gate, but in this case, the fan-out facto~ of the preceding circuit driving the combined inputs is reduced bq one. It'.us not permissble to tie the basic elements together at the outputs, with the exception of the base where the outputs of the basic elements are joined together (no more than four, all of the inputs of which are connected together. Qperation of the integrated circuits with a supply voltage reduced down to 6 volts is permitted, however, in this case the electrical parameters may not conform to the valuea indicated in Table 3.71. It is reco~nended that decoupling capacitors in the form of a set of two capacitors be inserted in the power supply circuits of IC's on printed circuit boards: low frequency capacitors ~up to 20 KHz) designed for 2.2 uFd for each 50~IC's and high frequency capacitors (to 1.5 to 2 MHz) designed for 0.068 uFd for.each 50 IC's. We shall discuse the impact ofE temperature and load capacitance on CMOS transistor IC's using the example of the K176 series. The curves for the output voltage as a function of temperature for the K176TM2 integrated circuit (Figure 3.44a) show that Uout and Uout,practically do not change with an increase~-in temperature, while the propagation delay ti.me as a function of load capacitance for the K176TM2 -135- ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE O1riLY IC (Figure 3.44b) show a greater dependence on load capacitance by ~the propagation delay time during cutoff, which with an increase Cload from 30 to 180 pFd more than doubles. , 3.7. Integrated Circuits for Memories The expansion of the applications areas of modern computer hardware has generated a rapid increase in the number of varioue classes of computers. The constant trend towards an increase in~the complexity of the problem solved by computers in turn requires an increase in the volume and speed of the calculations, hawev~r, the speed of solving any problem with a computer is limited by the memory access time: the access time to the main memory (OZU). Memories using ferritea which under- went considerable development in first and aecond gensration camputers do not allow for a substantial reduction in main memory accesa ~ime. Even with a reduction in the diameter of the ferrite cores down to 0..; mm, a main memory access time of only 0.5 ~sec can be obtained. At the same time, a ferrite mem~iry :::ich is fabricated by means of rather complex operations to thread the wires �through the coree makea it difficult to assemble them and even makea s~xch devices ~1ot technologically auit- able for production. The development of microelectronics hxe made it poesible to use semiconductor devicea ~bipolar transiatore and MOS atructures) for the cons- truction of inemoriea. TABLE 3.22 Characteristics of Memories Based on Various Camponent Technologies Characteriatics Type Elements Acceas Typical Informa- Power of Main Used Time, Informa- tion Conaumption Memory nsec tion Density Duri:~g ~ Capacity, bits/cm~ In~ormation bits St.orage Bipolar ~ Semicon- Transis- ductor tors 50...300 103,,.105 Up to 200 Yes MOS Struc- tures 250...1,000 103...106 200...300 Yes Magnetic Ferrite Cores 350...1,200 1-6...10 10...20 No It can be seen from Table 3.22 in which the parametera and propertiea of main memories based on various component technology are compared [7].that it is expedient to design memoriea with an information capacity of less than 105 bits, but with a high operational speed, using bipolar traneistors. Memories based on MOS structures have a capacity of 103...106 bits with a moderate operational speed. Memories with a memory volume of more than 106 bita are constructed using ferrite cores, where - 136 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080030-5 these memories have poor speed, but nonetheless the capability of storfng data without consuming power. Considering the fact that the ci.aracteristics of inemories ~ based on MOS structures with reepect to capacity, speed and power consumption are consta~tly being improved, one shod}.d anticipate their widescale development and applications in various computer classes in the upcoming qears [7]. The use of semiconductor structures makes it possible to substantially increase � memory speed, reduce the size and weight as well as increase operational reliability and eliminate matching elements~between digital computer hardware and the memory through the application of a single type of component base in the varioua hardware In recent years, because of the improvement of bipolar IC's as well as the expan- sion of IC series using MOS transistore, static memory elements have been created ~using bipolar structures as well se p-channel MOS transistors and CMOS transistors), as well as dynamic memories ~using p-channel MOS transistors and MNOS structures) and memory elements based on "silicon on sapphire" structures. We shall treat the structures of each of these types.of inemory elements in more detail. 3.7.1. Memory elements Using Bipolar Structures A static memory using bipolar structures ~transistors) takes the form of a matrix of inemory elements (ZE), each of which can be set in one of the stabl:e states. Such an element is usually a flip-flop or a gate. Main memories with 1,024 bits with an access time of less than 100 naec, equipped with control circuits, can be fabricated on a aingle bipolar IC chmp. One of the major parts of a memory is the matrix-store, in which the information storage itself is realized. The con- ~ struction ~organization) of a matrix is governed bq the manner of accessing (interrogating) the memory element s during read or write operations. In the structural configuration of a matrix with word access and one decoding step (Figure 3.45a), one line forms a m bit word. ~'he symbols A1, A2, An in the schematic designate the address:buses while P1, P2, Pm designate the bit buses. As can be seen from the schematic, the addresa buses are electrically coupled to each memory element for one word, while the bit buses are coupled to the memory element for one bit of all words. When a signal corresponding to the "1" level is present on the adress bua Ai, the state of each of the memory elements in the word associated with adress Ai can be read from the bit buses, P1...P~. If it is necessary to write information into a selected address Ai, depending on the informa- tion code, a"1" or "0" aignal is fed via the bit buses P1, P2, Pm to each of the memory elements Ail, Ai2, Aim� Ttte control circuits for the matrix are not ahown in the block diagram for the sake of aimplicity (a decoder with address drivera, read and write amplifiera), which are incorporated in the IC's to reduce the number of package leads and are fabri- cated on a single chip along with the matrix circuit. -137- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080030-5 FOR OFFICIAL USE ONLY _ _ . _ . - - _ ZEll ZE . , v, vt vm ~3~ 39n 33~, . ~f 33t 33,~ ll ' X~ . . ' d3H 33tz J32 ' ' ~r~ � A= . XY 3- 33ef ~~t ~iai? ~ ~ ~rr � . ' xp ~ P ~ . ~ pz R~? � . (a) ~ ~ ~ (b) Figure 3.45. Structural configuration of a matrix with word access and _ single step decoding (a) and a dual coordinate matrix with two decoding steps (b). ~ Rey: ZE ~ memory element [store location]. In the block circuit diagram of a dual coordinate matrix with two decoding stepa (Figure 3.45b), the memory elements are selected by means of the addreas busee X1, X2, 7Cn and Y1, Y2, Ym. When a signal corresponding to the "1" level is present on address buses Xl and Y1, only one memorq element.will be selected (ZE1), from which one can read ita state via the bit bus P wh ich is common to all elements. When writing.e "1" into the selected element via the bit bus, it is necessary to feed in a aignal corresponding to the "1" level. Thia is the organization of a matrix with m-n single bit worda. The simplest memory element ia an RS flip-flop, which can be conatructed from two ~ im~erters (Figure 3.46a). The emitters 1 of the multi-emitter tranaistors VT1 and VT2 are connected to the addresa bus Ai, the potential on which in the ateady- state is the lowest potential of the circuit. The bit buses Pi and P~ are con- nected to the emitters 2 of transistors VT1 and VT2 respectively. A reference voltage co~?on to all of the matrix memory elemente is fed to the bit bus Pi. The relationship between tbe re~erence voltage, Ureg, the voltage' Ubit which is fed to the bit bus Pj and the voltage U8 which is fed to the address bus, governs the operational mode of the memory element: write, read, and atorage of the information. We ahall analyze the operation of a memory element in each of the three modes. , The information storage mode is characterized by the relationahip: Ua �1--:1.l,~1/~IG) AP~-3w-�,1 :1-i-1-�A. l~l::?16) (~l!~~iFi)�IPa-�A . Pft(-� I�_)~ A-~-p�-+A P,T1.~A.P,~IA1l~NC) A�1 P.y(A/~1. P61. . (~~I I~1 G) E-~~~. rn �2(A1P�)-.~ (0. -11 �.1 ~ l~. ~1-�T 6~ ~,�M.�h,w ?~na 11lQrtYJIKM~ I 'r~CAOMMYt ~ v'~~1~ MI~~K Y~t~110~MM ~V RPAM - ~(~N~ Ycaoe� ~~.~j~r~oa . HIJA f1l~1C� n~ir/~a� . ' xl1',~ IIO 11'~1CIOPU:IC {T} :s(l): III � Illlp p~-}.f(~p~ f(~~ueu uuKia' U~Yai~~.~e 1 ~n.(�� I 12) 11) cTCK ~1 ~'.(-I-I-) I . ~ Conventional designations and abbreviatians: +--allocation operator; ~--exclusive OR; A--OAU storage cell (working register); R and - operating register No a and b(a, b~ 0 to 7); R--indexingaregisterb No v(v = 10 to 17~; RP --reault indicator regis~er, consists of ~our flip-flops: R, Z, P and M; 2m --borrow, Zm A 1- R; M--mainline; MB --exchange of M with rearrangement of bytes; Xe -~4-bit constant from instruction word ~ield; K-=second word o~ instruction; sink--region of inemory addressed through address indicator has been drained; ~1--gene, ral designation of the operations +(addition)~ -(subtraction), A~(logi- cal multiplication)~ V(logical addition) and +[as publiehed] (Continuation and key on:following page] - 170 - FOR OFFICIAL USr^, f1NLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ~ FOR OFFICIAL USE ONLY (non-equivalence); *2--general deaignation.o~ the operations inversion, LL/LP (logical shi~t left/right by one bit) and ~sL/Ta~ (cyclic ehift left/right one bit). Key: 1. OAU instruction ~ords 9. Conditional transfer with regard ~ 2. Copqing, setting . 3. Mixed � 10. Interrupt permission/inhibition 4. Unary ~ 11. Stop 5. Binarq � ~.2. Bnd of cycle . ' 6. IAU instruction words 13. Sink ~ 7. Conditional transfers 8. System Table 3.30. Structure of Improved Operating Speed IrIIC Utilizing Seriea . K589 and K556 Integrated Circuits Description Type Analog ?ticroprogram control unit K589IK01 3001 Intel ~ Central processor element K589IK02 3002 Intel Accelerated carry circuit K589IK03 3003 Intel Multimode buffer register K589IR12 3212 Intel Priority interrupt unit K589IK14 3214 Intel Bus shaper K589AP16 3216 Intel Bus shaper with inversion K589AP26 �3226 Intel Programmable permanent memory K556RYe4 . Table 3.31. Key Electrical Parametera of MR Microcircuits Employing Series 589 Integrated Circuits ~ Parameter K589IK01 K589IR02 K589IK03 K589I1t12 K589iK14 K589AP16 K589AP2 Maximum . static power require- ment, m~'�tno~X~ ~ greater than 900 950 650 650 650 650 65 "0" out- 0.5 0.5 0.5 0.5 0.5 0.5 0.5 put sig- (out~uts C1 to C4) n~l, 0.7 (out- 0.7 V;rynot ~ puts Bl to ~ Bl~~ . [Continued on following page] = 171 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080034-5 "1" out- put sig- n~l, U , V;'ynot < 2.4 2.4 2.4 3.65 2.k 3.65 3.65 ' (out- _ puts C to ~4) 2.4 2.4 ~ . (out- . puts� ~ ' B to . B4) ~ Length of cycle, ~ tts , ns >85 >100 - - >80 - - Pulse ~ length, Ti , ns >30 >33 - >25 >20 - - Time of delay in propaga- tion of signal from input ' Xi to output . Yi' 16 14 - 20 15 z y~s ~.~3 troller. The branch functions are located at address 342 y~z ~v� ~z 2~ (shown with an R). The addresses, one of which can be >6 y~~ o chosen as the next address, are indicated by the black >s ~ M~~ 6 squares. y~o f~ N 3 ~ ~~A0 19 The logic scheme for feeding flags to th~. microprocessor 6 ~ controller provides for storing the current value of the ~ ~s o P~Z tsU fed to the input F as well as feeding it out to the 5 ~4 ~ p~f 9 output F~ (Table 3.33). The two different groups of con- 6 0 ~ trol functions for the flags are called the flag output B ~z ~ p~o and set instructions. K> H K~ ~'�n ~B The flag c3.rcuitry contains three flip-flops, designated ~9 ~ as the C flag, Z flag and a simple latch flip-flop, 3~ ~e f4 F, which stores the current atate of the indicator fed to ?5 0~ the input F. The flag circuit can be used in con~unction Fig. 3.62. Schematic with the carry and shift circuite of the CPU array for spmbol of BMII and desig- the realization of arithmetic and shift microinstructions. udtion of the leads The flag control functions and load functions are shown in (K589IK01 IC). Tables 3.35 and 3.36 respectively. , We analyze the branching instructions of the microprocessor controller. The branching functions of the microprocessor controller. are chosen depending on the signals at the seven input buses UAp UA6. Using the leading edge of the sync signal, the nine bit microinstruction address generated by the next address logic is loaded into the microinstruction address register. This microinstruction address is fed out from the microinstruction address register to the microinstruc- tion memory via the nine output buses MAp MAg. The outputs of the microin- struction addresses are broken down into the row and column address outputs as - follows: MAg MA4 are the row addresses and MA3 r'fAp are the column addresses. Corresponding to each address control function is its own combination on the func- tional input buses UA. From 3 to 5 bits of this code combination define the kind of function. The format and coding of the functions are given in Table 3.34. A detailed description of each of the 11 branch functions follows below. The fol- lowing symbols are used to indicate the addresses of the rows and columns: STRn is the f ive-bit address of the next row; KOLn is the four-bit address of the next column; n is the decimal number of the row or column. We shall analyze the unconditional branches o� the microprocessor controller. The current microinstruction address, i.e. the contents of the microinstruction address register prior to the arrival of the leading edge of the sync pulse train, and some of the bits from the code on the UA buses, is used to generate the next microinstruc- tion address in accordance with an unconditional branch operation. - 176 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500480030-5 FOR OFFICIAL USE ONLY TABLE 3.33 De~ignation of the Leads of the Microprocessor Controller - . ~ Type of Active Contact Designation Functioa Output Logic Level 1...4 K4...R~ Inputs for the f irst part . - of an instruction 5,6,8,10 Kp...K3 Inputs for the.second part - "0" ' of an instruction 7,9,11 RK2...RKp Register second bit outputs Open collector 12,13 UF3, UF2 Control inputa for flag - "1" entry and storage 14 F~ Indicator output Three "0" - states 15, 16 UF~, UF1 Inputs for the control of - "1'~ flag feed-out 17 F Indicator [ tag] input - ~ 18 SRP Interrupt enable gating Conven- "1" output tional output . 19 S Synchronization input - "1~~ 20 - Common - - 21...24, . 37...39 UA.~...UAb Control inputs for the - "1" microinstruction addrese register 25 OS Common gating input - ~~1" 26...29 MA~...MA3 Outputs for the microin- Three - struction address states column 30...34 MA4...MA$ Outputs for the microin- Three - struction row addresg atates 35 RS Enable input for generat- - "1~~ ing the row address 36 ZM Input for loading the micro- - "1" insrruction address 40 - Power - - - 177 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080030-5 FOR OFFICIAL USE ONLY ~ _ . ~ i ~ ~ ~ ~ . o w a~.~ ~ ~ a~ .~C z e o 0 0 $ C] N ~C ~C aC � C! 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Z a ~ y.~ y ~~G ,.C ,C ~ 3 v f~ y~�~ s ~ x ~ q o 0 0 ~ q v~ a~ ~ ~ p C~i a~+ w w a~ ~ a+ cC ~ N~ x 9 ~ m u u u ~ a x O m 'G U 1-i w O O.ri ~rl rl W rl I~ U ~ m m m� � c ~ �oa Q`� ~o~c ~ j W O ~ Ul U1~,~.L~.C ~.C ral ~ z~ a q a n� a'6 ac~ aN a~ a~ a~ a a~ d a~ u u u ~ A. u r+ 0 o u o~ a oW o,~ o,~ o,~ oQ od o y y y N y~ q q ~ p ~ p w (A l~ K K >C X X iC ~C t~ ?C 1i N a 01 p' N~ N W N a1 GJ G~ ~.G C~ cd '17 b ~d ~d RJ ~C O ~O tn ~'-I o. a ~ o. ~ a~ a~' n�: o. ~ a a a~F F+ ~C y~ ~~d 'ti H~+ fr N F+ w N~ v ar u a m a+ ~ d~. ai d.. v a m R1 a~ w~ V~ di Q'i PQ W W P~l b0 P~1 O u C C. ~ C CsCsCsC ~.CsC~t s ~d 1+ ~ ~v . a a, a a a 7~c, ~a i'1e . . . . 'C ~rl ~ u r`K ~�1 ~-�Y ~H ' F� ~'1- r{0. N ~i c~1 ~'s r-~ CS O Vl � � � � d U rT- ~C- ~ o?- rt- -ri- fn ~ rl N M.7 V1 ~O 1~ CO O`+ a U Y ~ ~11 J ~Y ~ J 'J ~ u W 1J W a U N U U ~ U N 4 J 4 m ~ ~ ~ ~ ~ ~ ~ i ~ 'U LJ ~ ~j - CJ~ ~ M ~ cy'1 ~ W O a ~ ~ H - 1~8 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 [Key to Table 3.34, continued]: 14. Branch in accordance with the R4 - K~ instruction bits. TABLE 3.35. Flag Control Functiona ~qpe Designation Function UFL _UF~ Input to the flag SCZ Set the C and Z flags in 0 0 feed cir~uit accordance with the F output STZ Set the Z flag in accord- 0 0 ance with the F input STC Set the C flag in accord- 1 0 ance with the F input HCZ Store the C and Z flags 1 1 UF3 UF2 Output of the flag FFO Feed "0" to the Fy out- 0 0 feed circuit put FFC Feed flag C to the F~ 0 1 output FFZ Feed flag Z to the Fy 1 0 output FFI Feed "1" to the F~ 1 1 output - TABLE 3.36 Load Functiog-.-------.---.- _ . . . � A~peo ca~Aya~eA cspan AAp~o cneAynuleA aonaa~cr ~2~ 9M ~ MI~ A~I~ ( M~1. ( M~4 MI. MI~ MI. I MA~ J11A~ ISee Table 3.34 cM. Tasa. 3.34 � ~ t I 0 K~ I K~ I K~ K~ ~ K~ K� ( K, ~ K~ Key: l. Address of the next row; 2. Address of the next column; ZM = microinstruction address load input. - 179 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY !CC ' !ZR . 1CR I ~ ICE , . IfL lCf, IZf , ~ , ' !PR !LL 1~7l, IPX ' i i . ~ I ~ . ~ Figure 3.63. Diagrams of the address control function branches. The unconditional branches and their characteristics are enumerated below. ICC: branch in the next column; the UAp UAq are used to snecify the next micro- instruction address; the current column is defined by the MA~ MAg outputs; IZR is the branch to the zero row; the UA~ UA3 bases are used to specify the next microinstruction address in the STRp row; - 180 - ' FOR OFF[CIAL USE ONLX APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ICR is a branch in the current row; the UAp UA3 buses are used to specify the next microinstruction address in the current row, which is defined by the MA[+ MA8 outputs; ICE ~s a branch in the current column in t]~e group of row addresses and the feed3ng of the RK [instruction code register] contents to th~ RKp RK2 outputs; the U UA2 buses are used to specify the next microinstruction address in the group of row addresses defined by the contents of buses MA~ and MAg; the current column is defined by the contents of the MAp ....MA3 buses. The spnchronous output feed of the contents of the RK instruction code register to the RKp RK2 outputs is accomplished at the same time. We shall analyze the flag conditional branchea of the microprocessar controller. A portion of the address of the current microinstrucation, the contents of the selected flag (or flip-flop F) and some of the code bits on the UA buses are used to generate the next microinstruction address in accordance with the contents of the flag flip-flops. The conditional branches and their characteristics are enumer- ated below. ~ IFL is a conditional branch based on the contents of flip-flop F. The contents of the UA~ UA3 buses are used to specify the next microinatruction address located in the current of row addresses, which is defined by the contents on the MAg bus. If the current microinstruction address belongs to the group of columns KOLp KOL~, defined by the contents on the MA3 bus, then the next microinstruction address, depending on the contents of the flip-flop F, will be found in columns KOL2 or KOL3. If the bus MA3 defines the association of the current address with the group of columns KOLS KOL1~, then the n~xt microinstruction address, depending on the contents of flip-flop F, will be located in columns KDLyp or KOL11� ICF is a conditional branch based on the contents of flag C. The contsnts of the buses UA~ UA2 are used to specify the next microinstruction addrese located in the current group of row addresses, defined by the contents on the MA~ and MAg buses. If the current microinstruction address belongs to the KOL~ KOL~ group of columns, def ined by the contents on the MA3 bus, then the next microinstruction address, depending upon the value of flag C, be located in column KOL2 or KOLg. If bus MAg defines the association of the current address with the group of columns KOLB KOLZS, then the next microinstruction addreas, depending on the value of the flag C will be located in column KOLyp or KOLY1. IZF is a conditional branch based on the contents of flag Z. It is the same as the branch in accordance with the contents of flag C, but depends on the value of , the flag Z. . . We shall consider the conditional branches in accordance with the contents of the K4 K7 buses and the instruction register. The data on the K4 K7 buses, a part of the current microinstruction address and several bits of the code on !:he UA buses are used to generate the next microinstruction address in accordance wlth the contents of the K4 K~ buses. The data stored in the instruction register, part of the current microinstruction address and several bits of the code on the UA buses are used to generate the next microinstruction addreas in accordance with - 181 - FOR OFF'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080030-5 FOR OFFICIAL USE ONLY the instruction register RK. The characteristics of these branches are given below. IPR is a conditional branch in accordance with the contents of the instruction , register RK. The UAp UA2 buses are used to specify the row of the next micro- instruction address, which is found in the current group of row addresses defined by the contents of buses MA7 and MAg. Four bits stored in the RK instruction regis- ter are used to specify the column address of the next microinstruction. ILL is a conditional branch in.accordance with the left bits of the instruction reg~ster. Buses UAp UA2 are used to specify the row address of the next microinstruction, which is found in the current group of row addresses, defined by the contents on the MA~ and MAg buses. The contents on the RK2 and RKg are used to specify the column address of the next microinstruction. IRL is a conditional branch in accordance with the right bits of instruction regis- ter RI~. The information on the UA~ and UAl buses is used to specify the row ad- dress of the next microinstruction, which 3s located in the current group of ad- dresses of the row defined by the contents of the MA~ and MAg buses. The infor- mation on the RKD and RK1 buses is used to specify the address of the column of the next microinstruction. IPX is a conditional branch in accordance with buses K1~ K~ and the loading of the instruction register RK. The data on buses UA~ and UA1 are used to specify the row address of the next microinstruction which is located in the current group of row addresses determined by the information on buses MA6 MAg. The code on the K4 K~ buses is used to specify the column addrese of the next microinstruc- tion. Moreover, the information from the Kp K3 buses is written into the ins- truction register using the leading edge of the sync pulse train. We shall analyze the flag control functions. The type of flag control functions in the microprocessor controller is selected depending on t~?e signals at the four iaput buses, designated UFp UF3� The data at the input is stored in the F flip-flop during the low level sync series ("0"). The contents of the F flip-flop are loaded into the C and/or Z flip-flop based on the leading edge of the synchronization pulse. SCZ sets the C and Z flags in accordance with the F input (rewrites the signal from the input F). The value of the F input is asaigned to both flags. STZ sets the Z flag in accordance with the F input. The value of the F input is assigned to the flag Z. The C flag does not change. STC sets the C flag in accordance with the F input. The value of the F inpu~, is assigned ot the flag C. The Z flag does not change. ' HCZ stores the C and Z flags. The value of the C and Z flags does not change. The flag feed contral functions given below define the value of the signal which is fed out to the "flag output" line F~. -182- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FFO feeds "0" to the output Fy. A"0" is set at the F~ output. FFC feeds the C flag to the F output. The contents of flag C is produced at the F output . FFZ feeds flag Z to the F~ output. The contents of flag Z appears at the F~ output. FFI feeds the value "1" to the F~ output. ~A "1" is set at the output. We shall analyze the load function and the interrupt gating. The signal corres- ~ ponding to the multiprocessor controller load function is fed to the input bus for loading the microinstruction, ZM. If the "1" level appears on the microinstruc- tion load bus, then with the appearance of the leading edge of the sync series pulse, the data is loaded from the Kp K~ buses into the microinstruction address register (RAMK). The contents of the K4 K~ buses are loaded into the microinstruction address register flip-flop with the MA~ MA3 outpute, while t~e contents of the Kp R3 buses are loaded into the microinstruction address register flip-flops by the MA4 MA~ outputs. The highest order digit MAg of the microinstruction address register is set to "0". In this case, the digits of the microinstruction address register specify one of 16 possible column addresses by means of outputs MA~ MA3. Correspondingly, the microinstruction address register bits from the outputs of MA1 MA~ specify one of the first 16 row addresses. The interrupt enable gating is fed from the microprocessor controller to the corresponding output line, designated as the SRP. The active state (high level) is set on the line in the case where upon the ICC branch instruction control is transfered to column KOL 15� Usually, the signal from the SRP [interrupt enable gating] bus of the micro- processor controller is fed~ to the input SRP bus of the priority interrupt con- troller (BPP). The priority interrupt controller can respond to the interrupt by feeding a"0" level out to the RS [row address enable output] of the micro- processor controller, which blocks the feed of the next selected row address from the microprocess controller. Then, during'the feed-out of the new address of the - microinstruction to the row address line, one can supply the address from without, avoiding the multiprocessor controller, something which makes it poasible for the microprogram to shift over to the input of the interrupt processing program. The changed row address which is transmitted to the address lines of the microinstruc- tion memory, does not influence the contents of the microinstruction address register. Thus, the next branch function will employ the row address in the microinstruction address regiater, and not the changed roa addreas. We will note that the load function always blocka the branch functions on the UAp UA6 buses. However, it does not block the output enable for the contenta of the instruction register to the RKp RK2 buses as well as the receive enable in the instruction register from the contents of the K4 K~ buses when the ICE and IPX functions respectively are present on the UA buses. Morever, enabling of the interrupt gating and all of the ilag control functions are not inhibited via the microinstruction load bus/ The Central Processor Unit (CPU). This unit takes the f orm of a two-bit processor section of a data processor; it has 40 types of microinstructions and provides for -183- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 FOR OFFICIAL USE ONLY the execution of the following functiona: arithmetic operatione in a complentary binary code, APID, OR, NOT and exclusive OR logic functions, poaitive 1) and negative 1) increments, shifts to the left and to the right, checking a word, portion of a word or single bit for "0", and generating accelerated carry signals. The bZock diagram of the CPU (Figure 3.64) includes the arithmetic logic unit (ALU), the fast-acceas memory (Rp, Rg, T), a storage register - the accumulator (AS), the memory address register (RA) and the microfunction decoder. The CPU has three types of input data buses (M1, Mp; V1, Vp; R1, IC~), and twe types of output data buses (A1 Ap; D1, Dp) with three stable states. We shall analyze the opera- tion of a CPU which performs the azithmetic, logic and register functions of a two bit microprogram central procesaor. f1 A, fd Ao ZO Q~ f9 ,QoD~ ~ 1 oA - A I lrev.ra~ivori d~i~Oev 1~'X~ d~l4xP 23~Q I ' I~ ~ 2 3 ~ j Araucmpac~oaw na~vivmu MrKannusmner/uaiaa ~ I ~ ~ t~ C, I I sx i c~ ~ ~ 4~ Mn~nxmm~~ uvttrrx 6Y 7C~ ~s f, ~ - ecn, . F I'Winunrrnne~r,op hY~immrt~o j~ 9) n F4 ~ a a ~ i ~s f ; � ~ ~~PQ I I I ~1) R a.~v9~,r I ~ (COdbl . I ~ 1 .L---- - - . ? 27 f M~ IYO Oj Sj Mj ~yo Figure 3.64. Block'diagram of the central processor unit (K5891K02 integrated circuit). Key: 1. Output buffer; 2. Memory address register; 3. Accumulator; 4. Arithmetic logic unit; 5. Multiplexer A; 6. Multiplexer B; 7. Microfunction decoder; 8. High apeed registers Rp Rg T(S02U) [fast-accesa st~re]; _ 9. Shift to the right output. - 184 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY " Data from external sources ~peripherals, memoriea) is CPU fed to the CPU via one of three input buses. Data are ~o tranamitted from the CPU to peripherals vi.a one of two 9~n, u~ c~o a output buses. The data are stored inside the CPU in one 2f Mo ~ of eleven registers of a fast-access store (SOZU) or in ~ so ~o � an accimmulator register. Data is fed from the input s~ buaes, the regiaters and the accumulator ta the arith- 4~r, X metic logic unit through two internal multiplexera, A Z^'~ y s and B. The additional inputs and outputs serve to z6 f� propagate the carry, shifts and selection of a micro- ' fZ ~ in~truction. The schematic sqmbol for the CPU is shown `4 in Figure 3.65 while the designation of the leads is 6 f4 given in Table 3.37. The information existing on the ~s ~5 seven input bus linea for the microinstructions, deaig,. ~s ~ ~ nated Fp F6, are decoded inside the CPU for~the 23 eA ta selection of the arithmetic logic unit functions, the generation of the fast access atore addrese as well as for the control of multiplexere A and B. The input bua M is intended for transmitting data from Figure 3.65. Circuit the peripheral main memory to the CPU. The data are symbol for the GPU fed from bus M through the internal multiplexer to (R589IK02 IC) and the the arithmetic logic unit input. The input bus B is designation of the intended for transmitting data from the peripheral leads. input-output:~systems to the CPU. Data are also fed from [See Table 3.37 bus B to the input of the arithmetic logic unit through for key]. the multi~plexer, but independently of bue M. The breakdown inCo two buaes provides for relatively low loading of the memorq buses even in the case ~ahere a large ntunber of input-output peripherals are connected to bus B. In anather usage variant, the input buses B can be connected by external wiring to one of the output busea to obtain a shift by several bits operation (for example, bq one byte). In this case, the input-output units are switched by external circuits to the M inputs. The fast-access store contains 11 registers, deaignated ae Rp R9 and T. The signal from the fast-acceas store output ia fed through an internal multiplexer to the input of the arithmetic logic unit, and in turn, fram the output of the arith- metic logic unit to the faet-accesa store input. There is an independent register, the accumulator, to store the results of arith- metic logic unit operations in the CPU. The accumulator output is coupled through an internal multiplexer to the arithmetic logic unit input, and moreover, the out- put of the accumulator is connected to an output buffer ~having three atates) for output to the D output bus. The D bus is usually employed to tranamit data to the external main memory or to input-output peripherals. Multiplexers A and B select one of the twu arithmetic logic unit inputa depending on the data on the microinatruction bus. The data on bus M, the output of the fast-acceas atore and the accumulator are fed to the inputs of multiplexer A. -185- ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-00850R000500484430-5 FOR OFFICIAL USE ONLY TABLE 3.37 Designation of th~ CPU ~eads ' Tqpe of Contacts~ Designation Function Output I 1,2 V~, V1 External bus inputa - 3,4 R~, R1 Masking bua inputa ' ~ 5,6 R, Y Accelerated carry output lrwo statea 7 Cp Carry output Three statea g SPD Shift to the right output The same ~ 9 SP1 Input for the ahift to the right - 10 S1 Carry input - 11 VA Address enable input - . 12,13 A1, A~ Memory address output Three atates 14 Com~non - 15...17 F6...F4 Microinstruction code input - 24...27 F3...F0 The same - - 18 S Synchronization input 19, 20 D~, D1 Information output Three statea 21, 22 M1, MD Information input ' ~23 VD Data enable input - ' 28 Power ' Note: The output and input data at the X, Y, F~:..F6 leads is represented in a direct code, and at the remaining leads, in an inverse code. The high level voltage corresponds to a logic -"~i" ~ The data of bus B, the accumulator and the bus K data are fed to the inputs of multiplexer B. The data at the selected input of multiplexer B is always logically multiplied by the contenta of the corresponding K input to provide for flexible masking and bit checking capability. The arittmnetic logic unit is capable of performing arithmetic and logic operations, including binary addition in a complementary code, +1 and -1 operations, bitwise logic addition and multiplication, bitwiae "excluaive NOR" operatione and bitwise logic complementing. The results ~bf an arithmetic logic unit operation can be written into the accumulator or into one of the fast access store registera. To perform shift to the right operationa, th~re are individual "right ehift input" (SP1) and "right ehift output" ~SPp) leads. The carry input and output linea -186- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000540080034-5 (~1 and Sp) are intended for providing normal aeries carry propagation. The data at the Sp and SPp outputs are fed through two buffers, which have three states each, where output either to Sp or only to SPp is enabled. Moreover, the standard outputs for the high speed carry circuits R and Y make it possible to obtain a high speed carry for any word length. The capability of masking the arithmetic logic inputs by means of bus K consider- ably increases the universality of the arithmetic logic unit. During nonarithmetic operations, the carry circuits are used to obtain the logic assembly (OR) of all of ~ the word bits for the purpose of analyzing the operation result for "0" or of one of the registers ~for example, the ANP or ORR microinstructione). Thus, the CPU provides for flexible checking of bit contents. Bus K is also used during arithmetic operations to mask portions of the field being processed. A supplemental function of bus K is the transmisaion of constanta from the micro- program to the CPU. ~ A separate arithmetic logic output goes to the memorq address register (RA) and from it, to the output bus A through an output buffer with three states. Usually, register RA and bus A are used for transmitting addresses to a peripheral main memory. The regisi~er BA and bua A may also be used for selecting a peripheral when performing input-output operatione. A microinstruction is fed to the CPU F'inputs in each microcycle. The micro- instruction decoded, the multiplexers select the operands and the arithmetic logic unit performs the requisite operation. Using the negative edge of the sync pulse, the reault of an arithmetic logic unit operation is either placed in the accumu- lator or written into the selected regieter of the fast-accesa store. Mareover, the result of an arithmetic logic unit operation is written into the RA regiater in some operations. A new microinatruction can be fed in only uaing the positiive edge of the sync pulse. In the case of external control of the CPU aync aignal, the sync pulse may be omitted in the microcycle, and aince the carry, shift~and high speed carry circuits are not ayachronized, their outputa may be uaed in this cycle to perform a number of data checks in the accumulator and the fast accesa store. The contents of the regieters do not change in the case of operations in the absence of the aync aignal. TABLE 3.38 Microinstriar... F-Group Formats ~1~ ~yN u ~ p, P. - ( -rDYnns) , Key: 1. Group of functions (F-group). p 0 0 0 ~ 0 0 l 2 ~ 0 1 0 3 0 I l ~ 4 1 0 0 5 1 0 ' 6 1 l 0 7 I 1 1 - 187 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFiCIAL USE ONLY TABLE 3.39 The Microinstructiion R-Groug ~e contents d~f the microinstruc- Format tion being executed are defined by the functional group ~F group) and ~~p. pa F~ F, F} F, the register group ~R group) whicb ~~~~y~�~ ~p`~ are specified by the F bus code; ~1~ ' the F group is determined by the Ro 0 0 0 0 three high order digits of the R~ 0 0 0 1 ~ R, 0 0 I 0 data ~F4...F6), while the R group Rs 0 0 I l is determined by the four 1ow order R. 0 1 0 Q bits ~Fp. ..F 1 Rs 0 t l 0 3 Re R? ~ ~ ~ 1 R group 1 includes the regiaters Re 1 0 0 0 Ro~ 1 0 0 1 Rp...Rq, T and AS, ~:nd is desig- T l 1 0 0 nated by the symbol Rn. R group 2 AC t ~ ~ ~ and R group 3 contain only the ~ T l 0. I p register T and the accumulator I AC I l I o( I I I ~AS) . The formats and coding of the F aad R groups are given 3 I~C I ~ I ~ I ~ I ~ in Table 3.38 and Table 3.39 respectively. Key: 1. Register group ~R-group); ~�~o additional microinstructions 2. Register. relative to the result in the case � of "0" and "1" at the inputs of the K bus are given when considering the CPU microinstruction following the overall functional description of an operation. In the majority of cases, setting the signals at the K bus inputs to "1" and "0" is either the accessing or the absence of accessing of the accumulator respectively in the given micro- operation. The monemonic symbols for the microoperationa are included in each description as reference data. A mnemonic may be uaed as a microassembler language. A listing of microinstruction is given in Table 3.40. The execution of microinstructions for the "all zeros" and "all ones" atates of the K bus is illustrated in Table 3.41. An example of the decoding of the instruction~indicated in Table 3.40, for the case of the F group = 0 and R group = 1: logic multiplication of the accumula- tor contents by the K bus data, the addition of the result to the contents of register Rn and by the value at the carry input S1, as well as the writing of the results into Rn and the accumulator. An example of the decoding of an operation in accordance with the mnemonics ILR and ALR, indicated in Table 3.41: for the case of the ILR mnemonic and the K= 00 state of the K bus, the addition of the contents Rn to Che value at the S1 input and the loading of the result irito the accumulator and Rn; for the case of the ALR ma~emonic and the K= 11 etate of the K bus, the addition of the contents of the accumulator and S1 to the contents of Rn and the placement of the result�i in the accumulator and Rn. If the accumulator address is indicated in the address portion of the microinstruction, then the accumulator contents are shifted one bit to the left. The circuit for combining central processor units together (K589IK02 - 188 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 FOR OFFICIAL USE ONLY TABLE 3.40 Liseing of CPU Microinstructiona F� R� Instruction Nr~rPyK4M8 ~pynnn rpyrma F-group I Rn-I-~AC K)~-C~-' Rn~ ~ ~ 2 NO-{-(ACnI~-}-Ci-?AT ~ ATo (Bo /1 Ko)-+Cfl C~/ V[(Bi A Kl) /1 ATI~.-�ATi 3 ~[AT'oA(BoAKo)1V[~7'tV(BiAKt)1~-+A7}e 1 K V Rn ~ PA R-{-R-{-dl-?R l 2 K V M ~ RA !1~-}-K~-CI-?A~ 3 (AT V K)-~-(AT ~ K)-{-C1-*AT 1 (AC/~K)-I-{-C~~Rn 2 2 (RC n K)-1-}-Cl-? AT . . 3 (B n K)-1-~-Cl-?AT 1 Rn~-(AC/~K)-~-Cr,-'Rn 3 3 AT~-}-~ (B ~ Kj-}~-C;-+AT 1 C1V(Rn/~AC/\K)-~Co Rn/~(ACqK1-?R 4 3 C v~ATnA/~ C~ ; ATn( K)~A T . 1 C1V (RnNK)-.Co K/~Rn~+Rn - 6 2 C1V(Mnl~-+~Co KnM-~AT 3 'C~V(~7'~K)~Co KAAT-?AT 1 C1VtA~~K)-?Co� RnV(AC/~K)-?R 8 2 CiV(ACnln~Co MV(ACnK)~A~ 3 C1V(Bn/n-~Co ATV(BAK)-?AT 1 C!V(RnI~AC/~In~Co Rn~(AC/~K)-~Rn T 2 C~V (~'1AACnK)-~Co M~(ACnK)-?AT ' 3 C1V(AT~BnK)-?C, AT~(BnK)-+AT II p x M e a a x e e. 3paK ~ o6osNayaer onepauxa ~ecxnbqaautee NnN--HE� Note: The + indicates an "exclusive NOR operation. integrated circuits) to conatruct devices having a capacity of 2n bits is shown in Figure 3.66, The high speed carry circuit (SUP) ia intended for generating the group carries in the case where it is used jointly with CPU's. One high apeed carry circuit and eight CPU's make it possible to set up a 16 bit adder. The high epeed carry circuit has 17 information inputa, 8 information outpute and 1 control input, which ma.kes it possibl~ to control the output of the highest order carry, shifting it to the third etate. -189- FOR OFF[CIAL USE ONLY ' APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY TABLE 3.41 The Execution of ~ficroinatructions for the "All Zeros" and "All Ones" States of the K Bua M~flNICe Ka~ j I Mxe� . woxeKs onic ~..C~.../2~, AC ILR AC-~-Rn-I-~'+t-'Rn. AO ALR Afn}-C~-?AT ACM M-~-AC-{-C~-+AT Ali9A ATo-+Cno ATl-+ATa SRA Cfl ~.~+AT~ Rn-~RA Rn-}-Ci-.R LM I I 1-+PA , Rn-I -~-CI--.Il DSM -.PA M-}-Ct-�A~' LMM I1-?PA M-I-~-Ci -+AT D A AT-}-CI-?AT C/A AT-/-{-Ct-�AT C~r/....Rn CSR AC-I-}-Cl~/~n SDR � ~~_~...AT CSA AC-I-FCi-?AT SDA cM. . CSA B--T ~-C1-?AT LDI ptn~-C ~-.Rn lNR AC-}-Rn-I'Ct-'Rn ADR c~i. A~M cn+. AMA AT-~-CI-�AT /NA B-{-AT-~-C~-?AT A/A C~-?Ca 0-~Rn LR C~V(RnAA~-~Co ANR Rn/~AC-?Rn C,-?Co � 0-+AT CLA C~ V(M ~ AC)-?C~ ^ AC-�AT ANM cM. CLA Ci V(AT q 8)-�Co ANI AT n B-.AT cM. CLR Ci V R~-~Co Rn-+R TZR cM. CLA C~VM-?C M-+ATri LTM cM. CLA CiVA7'-+~o AT-�AT TZA NUP C~ V AC-~Co Rn V AC-?Rn ORR C1~Co Mn?AT I LMF C~VAC-�Co ~ MVAC-?AT IORM cM. NOP NOR CiV B-+Ca~ BV AT-?AT ORI C~-+Co Rn-'Rn CM~ C1V(Rnl~ ~7-'Co XN Rn~AO..~Rn XNM . Cl-.Co M-�AT LCM Cl V(M I1A~)-~Co A1 ~ AC-� AT XNl Cl-.Ca AT-+AT CMA C~V(ATnB)-'CoB~AT-+AT The schematic symbol for the high apeed carry circuit (K589IK03 integrated circuit) and the designation of its leads are shown in Figure 3.67. The state of each of the eight cutputa of the high speed carry circuit ia described by the following logic ~equaL�ion: _ . ' o ~ y'~Cn Cn -1- 1 ~ X y - _ . _ Cn -E- 2 s X~Yt YtYeXo -I- Y1Ye~n ' C" 3 � y~X~ y~yixl ~'tYtYoX~ ~'~}'t~'~Cn - - 190 - FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY . . 1 ~ 4 a y~X! -1- y,Y,X, -1- Y ~Y,Y~Xi -I- Y tY,YiS'~x~ -I' Y ~YsY1Y~Cn ~s~ b= Y~1r~ Y~Y ~X ~-1- Y~Y ~Y~X~ -f- Y~Y ~Y~Yixt Y~Y ~Y~Y~Y~X o -F' Y~Y ~Y~YiY~Cn . Cn 6= Ye1t~ -~i- Y~Y~1'C~ -1- 1's1'~YlR ~-I- Y~Y~Y ~YsX ~-F Yd~'~1' ~~'~yiXi -1- 1~~1'~1' ~}'tyi}'~ Xo-~- Y`Y~Y ~Y~Y~YsGn. . ~ = Y~1~~ -F' y~f'~X~ �F' ]'~Y~Y~X~ YeYy1'~~' t Y.Ys~'~Y~Y~X~ -h ~'~Y~Y~Y~Y~YsXi Y~YbY~YlY~YIY~Xo -f' . Y~YaY~Y =Y~Y~YoCn~ . � ~.f the "1" level is se~ at the RP [?carry register?] input; ~n + 8 in the third state, if the "0" level appear~s zat~ e RP inptlt . - . . . - lLaiv aqonar ~�r Sync Input 1 . E~Cd d~ ~ o~i ~ ~2) nn, ~ . , f~... FQ A ,Q A,Q A Q ~...fQ C fy...fQ C fy...fB C ~ Cp C~ Cp C~ Cp C~ . ~5~ Q/13~ ~ ~ ~!/J3= ~ ~ q/13~ r,~, cno c~ c~o cn,, a~o . c' fp...Fs fp...FS fO...FJ ~ ~6~ G N A' 0 I'1 A' ' 0 N A' r0���FJ ~ .'ro ia !7\ ..r7lOC0 . \ / NnNtrrr,Nma uiNr ! ~ 8~ nvc~m ar 6/N9 ~ 9~ ~bnaa.~r n'~'�n'm~w r. O~nr~+nvn ~aav~n ~ _ i Figure 3.66. Schematic ahowing the combining of CPU's (K589IRA2 integrated circuits) to conetruct devices having 2n digite. Key: 1. Memory data bus; 2. High order bits, F1...F6; - 191 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 . FOR OFFICiAL USE ONLY [Key to Figure 3.66, continued]: i 3. TsPEl = central processor unit 1[CPU 4. CPU2; 5. Shift to the right; 6. Low order bits, Fp...F3; 7. Carry output; 8. Constant or mask fram the microprocessor coatroller; 9. Memory data bus; 10. External bus. - _ _ _ . - - a Designati.on of High Speed Carry an cyll 2 X~ UP ~ Pins Cir ~i~ eada~ Level 27 ys ~M.~ 15 Kawr~nMn ~ 2~ l!bl7N~dMit! Asv~ ~I ~ ~6 zz ~,T~6...e, Typ~ s XS ~n.e 1p,f1 Xo...X~ ~xadb? ap~' Otltp, t N~� . fB.,.1;1 ~ ' 6 ~4 ~n~S 9 � 1'KZQ27 Ya,.~Y~ ~3~ ' ~1 X` a' pn arad po~aeeuewu~r _ v, rt c � ,!0 Xs Cn~4 4 Cn+e T~ ~~�0" 3 ~Z ~ 16 S~f ,f3 cro~- XI ~.a fr.fo~ ,,~.~CR.~ arYy~O~u~tput m~HUA - ~ _ ' 8 X~ Cn.z f3 TB - . /h,~i+ve ~ - - ~0 c~ 6 ~r~a~~ar - ~o., y ~ ~R+f . f4 Q~ixt - - Figure 3.67. 3chematic symbol for the hi~h apeed carry circuit (R589IK03 integrated circuit) and the designation of the leads. [SIIP = high speed car~y circuit]. Key: 1. Designation; 2. Function; 3. Inputs for the group carries; , 4. Cn+g carry enable input; 5. Z~ao states; 6. Carry input; 7. Common; 8. Three states. A variant for high epeed carry circuit uae (K589IK03 integrated circuit) in conjunction with a CPU (R589IR02 integrated circuit) is ahown in Figure 3.68. The multimod~ buffer register ~MBR) is a universal eight bit register, consisting of D flip-flops and output buffer circuits with three stable states. It has - built-in selective logic and an independent separate D flip-flop for generating a central proceseor i�c:~errupt query. One or sveral MBR's can be used to realize - 192 - ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 FOR OFFICIAL 1 , . _ - . _ a B~~�te 5 voit supply f, ~ C~.e Cy/1 G? CRH CWl . ~s x~ X~ C,.i Y xi K Qi�~ xi ~~ir.l XI ?'o f= . fj X x~ X~ X~ X v X c, ~ a m~l r~ a~ ~ kn~ vr~ ~[ia ~ 3) Un~ un~ Q7o Q'j d1 07j lY1 K ~wn'38 S VOZtS ' ~ ) P/! (6) CSMI Crr nle ~ (6) ~Ma~ ~I ~it�j X Y~7fN'~0 Ye X7 N! rM1s7 Xl Y~�/'r0 V9 ` X~ X ; X~ X~ X Y X Y ' e, ~~,y u~, u~a ~ u~ ~~3 (g) ~ an3 _ c 1 ~a~ . , , - ~ S~an (6) ~ ; ~ X� X? ~,~~o Ye , . ~ X r X ~ X ~ ~r~nPut 4~i 4'/1~ (9~ t~ ~ ; Caa~rry~~tput y Figure 3.68. Examples of high speed carry circuit applications ~K589IR03 integrated circuit) in conjunction with CPU's (R589LR02 integrated~ci~cu~ts). Rey: 1. Carry from the microproceseor controller; 2,3. CPU's; 4. Carry to the microproceesor controller; 5. Carry regiater; 6. Aigh speed carry circuit; 7. Carry from the microprocessor controller; 8. Carry to the microprocessor contraller; 9. CPU's. - 193 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 ~ ~ FOR OFFICIAL USE ONLY Figure 3.69. Schematic symbol for the nultimode buffer register (K589IR12 integrated circuit) and the designation of tile leads. [MBR ~ multim~de buffer register] . ~f c , z ev ~ n ~I ~ ear ~ , , A , 3 Af - 6 . ' s ~t: ~ o: ~Qs e ~ ~ 3 1`'~R 9 ~4 ~ Qq , Di ~ i3 �t >6 Os ~ D~ . Gi 4 >6,Q1 n4 ~e Di OS ' 1B 11e ~ Oe . - r v4 t4 q Oa 20,4~ ~ ~ ~ - . Oe ~ 22/le ~ �e ! ~ 0 ~ ~ ~ . ' ~,~,p giater R . . Figure 3.70. Block diagram of the multimode buffer regieter (K589IR12 integr~ted circuit). - many types of interface~ and auxiliary units, euch as aimple data registers, buffer registers with data gating, multiplexera, bidirectional bus drivers, iiaterrugtible input-output channels, etc. The circuit achematic symbol of an MBR (K589IR12 iategrated circuit) ia ahown in Figure 3.69, while the designation of its leads is given in Table 3.42. We shall analyze MBR operation in accordance with the block diagram of it ehown in Figure 3.70. ~i;P information D flip-flopa repeat the input data at the high logic ~evel of tb,e input signal S, and the input informatioa is written in at the low logic - 194 - FOR OFFICi~t?L USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ' F'Oit OFF[(;~AL TABLE 3.42 Designatioa of the Multimode Buffer Registe~t Leads ~ Desig- Type Pins nation Function of Level Out- put 1,!13 VR1, VR2 Chip aelection inputs - (~1K1); "1" ~VR2) 2 VR Mode selection input - - 3, 5, 7, 9, 16, 18, D1...Dg Information inputa - ~ - 20, 22 4, 6, 8, 10, 15, Q1...Qg Information outputa Three - 17, 19, 21 states 11 S Strobe input - "1" 12 - Co~on - - 14 R Zero set input - ~ 23 ZF Interrupt query output T~,io - states 24 - Power - - level of the eignal at the S input. The outputs of each informati~n flip-flop are connected to the inverting output buffer ewitches, which have i~hree stable states. The internal bus for data output ~VD) gates each output buffer. When voltage is present on the VD bus, the output buffers are unblocked and the data ia fed to the output of the correspoAding output d$ta line ~Q1 Q8). The i:~puta VR1 and VKZ control the chip selection. When a"0" voltage is preaent - at the VK1 input and a"1" appeara at the VR2 inpu~, the unit selection ie enabled. The VR (mode ~elect) input definea ome of two operating m~dea. When there is a "0" signal at the mode select input, the device operates in an input mode. The output buffers are turned on in this mode. When a unit is selected, the right-in cont=ol is raalized using.the S input signal. When there is a"1" signal at the mode sQlect input, the device operatea in an output mode, in this case, the output buffers are tur.ned on regardleas of the aelection of a Unit. Thus, the writing of information into the register and output from the register are accomplished in accordance with the following fnrmulas: Zp a C/~ 8~ SK~ n BK2 BP (wi~ite into the register) VD = BP y BK1 BK2 ~information output fram the register). ~ -195- FOR OFF'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000504080030-5 FOR OFFICIAL USE ONLY u~,-se 5 volts au ply ~ e ~ ~ ~u?w ~ ~ . 1~ ~ap ( 5) HQP � 6~ . ~2~ Q'a"'u~r~la~' ~2~ ccxe~r . D6P,~t' (8) ~ ~ew: ea e ~il~ (il)~~~~ (1~ 1 ~iJ ~a~ n1 . 'ri~'t. ~b~ ~ Information Buses - G~ ng , ~ 13 ' (12 ~ ~ ~ ~ ly~ NbP R~Z~d/1 q ~2~ . ~8~ ~v ~r aw e~ ar ' ~'~'(14) (l~.~i~ea~~r~drr uN~-s6 �,~e~r~~' c~ ~ ~P Control q(2) ' ' Bu~ QA' dW ' . ~ ' ~/--~d~ . Figure 3.71. Examples of multimode buffer regieter applicatioas (R589IR12 integrated circuit). a. Input buffer; b. Interrupt controller; c. Output buffer; d. Bidirectional data tranemiseion. ~ - Rey: 1.'Input infarmation; 2. Multimode buffer regieter; 3. Output information; 4. Gating input; 5. System input; 6. Information buaes; 7. To the priority interrupt or microprocessor controllers; 8. System reeet; 9. Supply voltage = 5 volts; 10,11. Unit aelection enable; 12. Information buses; 13. System output; 14. System interrupt. - 196 - ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 - ~ ~ FOR OFFICIAL USE ONLY . ~ , E`.. 1IPCY ~ ti - � f~~ l~J/lo 7dJl! ~t~ ~ dA776 ' npePe?Ar- ~11d/!1 Mae . � � ~~ll~ u , t~~n` ~ ~ u~n, . f/la ~~2~ A ~ m ~ ~ - ~ ~ 4 taa~ r ~c~n ~ ~ ~ ~ sr c rr dC Figure 3.72. Block diagram of the priority interrupt controller (R589IK14 integrated circuit). . T1 = Interrupt blocking flip-flop; T2 = Interrupt flip-flop; Key: 1. PYiority coder and interrupt query flip-flops; 2. Current state flip-flop; 3. Priority circuit. The interrupt query flip-flop aervea to generate the interrupt query aignal in the processor system. When the system is set to the initial etate by the "zLro set" low level signal, the interrupt query flip-flop ~s set to "1", i.e., the given device does not require an interrupt. Simultaneously, the register R is set to "0" ~y this same signat. The interrupt query flip-flop output is joined together via an OR to the output of the device select logic c ircuit. It is asau~d that the MBR is in the interrupt etate when a"0" correaponds to the.output of the ZP [register entry~, which r.aakes it possible for a direct connection to the query input ~the active one ia low level) of the priority interrupt unit. When working in the input mode ~i.e., the low level appeare at the mode s~iect input), the input signal S writes the information into the data register and aete the inter- rupt query flip-flop to "0". The interrupt query flip-flop is aet to "1" given the condition that.a device ia selected (an interrupt signal ia generate~d ia the same way at the 2P output). Thus, the interrupt conditions are as followe: 2P ' = gKl ^ gK2 V ~ The interrupt aignal reaet ie accomplished in accordance with the following formula: Register entry reset = R v BK n BK2 = R V BK1 V~2 ~ - 197 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000500480030-5 ~ FOR OFFICIAL USE ONLY E~camples of multimode buffer register applications ~R589IR12 integrated circuit) are shown in Figure 3.71. . The priority interrupt cantroller ~BPP) provides for interrupting the task being performed. The interrupt sqstem, ~hich is designed using the BPP, provides for the following cap~bilities: eight aeparate interrupt levels fnr each block, pro- grammable priority, expansion capability of the 8K interrupt levels ~K is the number of priQrity interrupt blxks) and sutomatic generation of the interrupt vector. . TABLE 3.43 Designation of the Leads of the Priority Interrupt Controller Desig- ~'unction Type Level Pins nation of Otitput - _ 0 1, 2, 3 Pp...P2 Priority level input 4 ~p Priority level selection input - ~ 5 pg Interrupt output ~p~n ~ collector 6 g Synchronizat ion input ' 1 ~ ggp Interrupt enable gating'input - 1 0 8, 9, 10 RPp...KP2 Interrupt mode output ~ollector ~ 11 RSCh Enable input for reading the - ~ interrupt code 12 - Co~annon - - 13 RG Interrupt group enable output - 1 14 RGP Interrupt group enable input Two states 1 _ 0 15...22 ZPp���ZP7 Interrupt inhibit inputs O 23 RZ Write enable input - 24 - Power - ^ The block diagram of the priority interrupt controller (K589IK14 integrated _ circuit) ~Figure 3.72) includea the following: an eight bit register for interrupt queries with an eacoder; a three bit current priority regieter; a three bit priority coder with open collector outputs; and an eight level priority comparator. The $chematie�designation of the priority controller (IC589IK14 integrated circuit) is sho~,tn in Figure 3.73, while the designation of its leads is given in Table 3.43. -198- FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 . FOR OFFICIAL USE ONLY We shall analyze the operation of the priority ~ ~ ~ interrupt controller in accordance with the block ~ c~n ~ diagram shown in Figure 3.72. ~ P t n~ To determine interrupt queries, the priority interrupt ~ o unit is gated at the end of the execution of each 4 n za P3 o d ~ instruction. At th is point in time, if an interrupt ~ , query is confirmed in the priority interrupt controller, ~3 ar , the microproceasor controller shifta over to the micro- v program for interrupt procesaing. Interrupt ~ueries ~ , pass through the interrupt memory in the processor and ~ the priority coder to the priority comparator. The n S' interrupt queries are fed from the output of the pri- ~ ~ ority co~ler to the priority comparator. Thie value is n ~ compared in the priority comparator with the current prioritq of the priority interrupt controller ~the Figure 3.73. Schematic priority level of the priority ince~rupt controller designation of the which is atored in the current state register). A priority interrupt query, which is received during the action of the controller (K589IR14 interrupt gating (SRP), in conjunction with the sync integrated circuit). pulae causes the interrupt confirmation flip-flop to be set in the "active interrupt" atate (during the execution cycle for one microinstruction), seta the PR [interrupt output] (low level) aignal and the interrupt inhibit f]~ip-flop to the "1" state. Based on the PR signal, an interrupt instruction is generatted in the processor which can transmit the-oontrol directly to the input of the interrupt servicing routine. The microprogram which is usually a part of thia routine reads the eignal level interrogating the interrupt from the I~p KP2 interrupt code output buses. The informa*ion on the query level which is stored in the interrupt query memory can be transmitted to any of the input information buses of the procesaor in accordance with the signal fed to the RSCh [interrupt code read enableJ input. When the interrupt processing program has determined '~he query level, it usually rewrites this level back into the current priority regist~r of the priority interrupt con- troller. In thie case, the interrupt inhibit flip-flop is set to "1" and any of the subsequent queri~s at the given or lower priority level are blocked. The input to the macrolevel interrupt procesaing program can be accompanied by an interrupt vector which is generated in accordance with the information on the query level, in accordance with ~ihich the subroutine addreas corresponding to this level is generated. The exiting of such a macroprogram is uaually accompanied by the res~oration of the previoua contents of the current priority memory. The interrupt group enable input and the interrupt group enable output can be used when connecting several priority interrupt controllera in seriea, where each pri- ority interrupt controller can inhibit the interrupt for all subsequent controllei~s. The interrupt oonfirmation flip-flop is aet to the active state (low level) by the positive leading edge of the sync pulse, if the following conditione are met: -199- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040500080030-5 FOR OFFiCIAL USE ONLY a) The active query level (ZP~...ZP~) is higher than the current atatus Pp...P2; b) A"1" Aignal is present at the SRP [interrupt enable gating] input; c) A"1" signal is present at the F,G [interrupt group enable output] input; d) The interrupt inhibit flip-flop is reset. The interrupt output signal asynchronously sets the interrupt inhibit flip-flop to the "1" state and delays the query signals in the interrupt query memory until the sending of new information on the current priority (Pp...P2, VP [priority level selection] in accordance with the RZ [write enable input] signal) in the current priority register. The interrupt inhibit flip-flop is reset upon the completion of the sending operation. During thia procesa, there can be a"1" at the inter- rupt group enable output only in the case where the following conditions are met: a) There is a"1" at the RG input; b) The current priority does not belong the given group of levels (is determined in accordance with VP [pr iority level selection] 4igna 1); c) There are no interrupt queries at the given level. The interrupt code outputa RPp...RP2 and the interrupt � PR take the form of an open collector, eomethiag which ~,~i2 mm c, makes it possible to coi~hine them. ~3 G2 5 The noninverting and iuverting bus dr.ivers are parallel 3~ 3~ bidirecti~~nal eignal dr ivers for the contro], of the et. trunks ~buses) in digital computexs and t~ke the form of d3 four-channel switchers, which have one bus in each e~, ,y channel just for the reception of the data, one bus just ~t l11~N for the output and one bidirectional feedout and receive A4 bus. The information paeses through noninverting bus z drivers without being changed, and is im~erted in a~ inverting bus drivers. The sehematic aymbols for the B3 noninverting bus driver (R589AP16 IC) and inverting bus ey c drivex ~R589AP26 AC) are shown in Flgures 3.74, while the = d~signation of their leads ia given in Table 3.44 and Figure 3.74. Circuit their block diagrams in Figure 3.75. schematic deaigna- tiona of the ShF Data output control logic is provided to control the [bus driver] operating mode and direction of data transmission in (K589AP16 IC) and noninverting and inverting bua drivers; this logic is the ShFI [invert- desgined around two dual input AND logic gates. The ing bus driver drivera provide for the transmiasion of information when (K589AP46 IC). there ia an "0" at the chip aelection input, VR. In the case of a"1" signal at the chip aelect input, the drivere are in the turned-off state and the outputa have - 200 - FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFF[CIAL iJSE ONLY ~e, ~ c 2C~ ' ~ ~ 1/'r 4A~ ~A~ 6e2 ~ ~ sCt ~Z ~ ~ SCr ~ r~i , y~i a/GJ. ~ ~ 1~ lOMd C C 1fCj 9AJ 9A~ 1384 ~ C ~~d ~ C~i ?IAp >1Ay 1SS1! d rS~QI A b . ~A~' !d~' ~ Figure 3.75. Block diagrams of the bus driver (R589~iP16 IC) and inverting bus driver ~R589AP26 IC). ~ a.high output impedance (the third state). When an "0" signal i,~ present at the =VK input, the data output via the C and B buses is controlled by the signal at the control input for the data feedout, W. If a"0" signal is present at the W input, then data transmission is turned on fram the A inputs to output B. In the case of a"1" signal at the W input, the data is transmit::ed fram the B inputs to the C outputa. TABLE 3.44. Desigaation of the Leads of the Inverting and Noninverting Bus Drivers ~ Pins Designation Function Type of Level Output 1 VR Chip seleetion input - "0" 2, 5, 11, 14 C1...C4 Information output Three stateo - 3, 6, 10, 13 V1...V4 Bidirectional data trans- The same - ~ miseion inpute/outputs 4, 7, 9, 12 A1...Al~ Information inputa - - 8 - Common - ' 15 UV Control input for information output - - 16 - Power - - -201- FOR OFFdCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED F~R RELEASE: 2007/02109: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL US~ ONLY [Table 3.44, continued]: Data Transmission Logic Logic State at Outputs in the Inputs the Turned- Direction of Data Tranamsseion Off State VI~ W - 0 0 From input .A to output B ~ 0 1 From input lz to output C B 1 1 No transmissinn . G~ B , Schematic Circuit Symbols for TTL�Circuits; _ _ _ _ yCnO8Hb1E ~PA~DN4ECKNE 0603HA4EHNA TTJI-CX~EM 6 ~ a s ~ a i~,, 3 r~ ~ s e ~ & ' a ' ~ n s ' 9 8 4 a~ 3 w 8 ~ . ~ ~ g K 9 3 . K ' . pl ~'1 Puc.3. f. 2 Puc. 3.1.J Puc.3.1.~ . Puc.3J.1 9 & f ~ >3 ~ !F 3 ~ $ ~ 2 d z f ~$D ' 3 8 ~3 f 5 & ~ ~ 4 a ~ B 3 S ~ ~ 8 9 ~ !L 9 & d ~ 9 ~ ~ ~ X �Puc. 3.1.7 /ua 1. B Puc. 3.1.9 Puc. f.5 Ouc. 3.1.6 R T 5 T ~ ~ e: ~ 6 n ~ ~ ~ � 6 . & p ~ m$ e . ~ ~ ~ ~ 9 ~D K d ~ ~ f2 $ ~ S Puc. J f. lD , PuQ. ~ f.11 Puc. ~8 a~ Puc. J f.13 =202- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 _ - - ~ r 1 n ~ c . 4 S ~ n ~ T 1 � . r f2 9 0 ` a B Z 1 ~ 4 p S a~' 7 p � � iue ~ i. f5 Poa ~ l. f8 _ Yac.3.1.14~ ~ TT ~ 2 TT ~ _ ~ 2 f3 3 1S f3 CT2 ~ ~'1 ~y CT2 3 9 6 f0 d 2 2 ~ y f ~ 4 ~ D Ro p a 01 61 PNc. J L f4 iwc. J f.19 Pv~ ~ f.17 ^ 3 Af Y ~ A C1 " i AS ~ 9 ~ s ~!3 r C? 1J f4 A4 ~ y ~ B ~^1 p n ~ Yf 2 n s ~ 5 � y Q eZ 9 & !1~� fy ~ Df 4~ D S. y 04 SO ~ 1f D8 d ~ Wp ~3 0) ' ei Puc3.f.t2 ~ PuC.J. LT0 ppC. 3.1.10 PaC.3~1.Y1 , � Xf I!S ' X2 Xd ~ . Xk cr ~ a a�~ ~ c?, ~ Xi e, 'm Jn1 p 5 XB , s ~ ~ ~ X9 f1 Ao~ � Re ~ 13 ~t � , ~c. a. t.Ta Pwc. ~ 14 P~c. J L?s i ~ Xf MS 4 X2 . X4 D~. p~ D1 ' J ; X5 S ~ ~ f Z D 2 Z X8 ~ ' 2 ~ ~ ~ k 7 X9 4 e Ra ~ 4 7 X!l ~ 9 ~ X!? P~rr. J.1.Y6 . Ppc 3.1.19' Py~ ~ f.Y/ ~ - 203 - FOR OFFICUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 FOR OF~[CIAL USE ONLY - � ~ c~2 f. ~ k ~ X/Y A f3 ~ 1s p/ CIt� ~ 3 ~ C ~ D? p 4~ ~ ~ f ~ ff ~l Y2 � Dd y s ~ 1 D~ ~ 6 ~ g g~ 8 Z 4 E V lvRo 6 f 'S +f ~ ~ ~ d B ~ , Cl -f ' Puc.3.1.29 Puc.31.J0 Puc.3.1,31 Puc.3.l.3f 4 Af OJy A2 4r41 1 V 8 A S/y 6 A4 5~ fk f A1 ('Ifxa1 ~ f A2 S B . A3 a1 A3 ' ~ e1 B3 A4 ~ g s Af SN 04 4~ ~ 9 f2 Qf ef S1 w~ s~ ~ E3 C4 ~ e a Pf ~ . w~ ek Q f4 A2 S2 >D ~~'1A E W 3 Pf ~ 02 1e ' ~ Puc. ~~.34 pac.3.~.~ Puc.3. , Pac. 3.1. Jd ' Xf MS � X'1 . Xd ~ ' ~ X4 - . XQ ' X8 X9 f0 f0 ~gM f f 2~ . X. e ~ 9 N/A3 3 ~ x~ d ~ S2 S s Jn~f y~ f 6 p ~ 1 ~ 6 ' 17 xf 3 S` ~ ~ ~ f~ X2 f ~ 4 2 8 ~ d 2f � Pve ~ l, ~ Pao. 3 l, 39 Puc. J f. 4~ Pu~.J 1.37 - 204 - FOR OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL U! . ~ - . � d -f N/! ~ X~ HS X2 X2 X3 7 ~ ~ 3 X4 ' X,5 Xk P BP Pr X6 X6 , ~ d CO py ~ . ~ X7 � X6 6 6Z ~ , ~ ~ ~1 GJ ~ X1f 9 X7 s xf X8 ~p~ f5 a,q ~g V ~P f0 P JI',9 Puc.3 f.91 Puc. J f. 92 ~ /uc. 3. L43 . , ALD p 7 ~o ~ , � D~ K P> AGD ~6 ~ ~ 2 1 ~ d0 A2 616 17 23 ~ 3 2 A1 FO g A~ 4 6 ef ~ 2f 4 2f ff ' Q4 f~ ~ ' 20 B 9 ~ A3 /"1 Dd ~ ~ ~ ~3 yp f~ ~ 12 f5 � 6 JJ fd ~ ~ ~ >B Nr 1 ~ ~ � ~ Yd ~ ~ !4 o N Y4 Wj , a~ ~ - Puc.3.1.44 Puo.3.1.~Af . f . ~ DC ~ ~ ' ! 3 D3 ~1 6 � RB~ ` Ef 9 e C fd a ~ EZ ~f rz ~s a � n ~o s ~a E ~ C2 Plue df.47 irc.df.fe Ouc. 3. f. y6 IOu - 205 - FOR OFFICIAL USE ONLY . APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY ~ . i+~ D r ~ 2 ~ ~ DC p ~ ~ ~ fS ~ � f ~ f 7 t 1 ~ SA~ s~ 2 D , Z 4 4 p . D T 1~0 ~ 10 ~ P ; ~ ~ ~ ~a e ~ s ~ C4 T ~4 & 8 p P D 9 � Puc.31. SO /uc. J 1, 31 Ouc. 31.52 Puc. J 1. #9 , . 4' 3 f d ~ B Q TT g ~ ~M fZ 6 ' ~ 7 ~ f0 ~ ~ ' ~ 8 ~ aN ~ N ~ n . ~ ~ ~ ~ ~ ~ >M ' C ~ ~ K , ' Pua 3 f.5~ Poc. 31.55 PuC. ~ L5B iua 3~1.53 _ . ~ ~ ~ _ ~ . ' 3 b f ~ s e 3 n~c ~ ~ � , n3u~ � T . ~ 3 Il3QC ~ g ~ ~ ~ , . ~ 2 , Ac � M3!!C ~ M9!(C 1d a 1 ; . !4 n I~9Y(C ~ ~ { ~ hc. 3.f.37 i~c. J 1.5Q /aa.,~ f.6a - 206 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080034-5 _ . ` ~ . g ~co ~r~ s o ,rn ~ 1C1 Df f SM fCT O2 1 s i J fV ' ~ t 2 2c~ D~6 p' ~ v 1C3 1Y ~ 4 e A ~ a a ~ ~ a c Pv~ ~ I 60 , R~,~,L~f . PY~ J~~.62 . n Circuit Symbola for Emitter Coupled Traneistor Loqic Circuits YC1108HbIE rPA~N4ECKNE 0603HA4EHNA 3CT11-CXEM f ~ ~ . f ~ 7 ~ d d ~ ~ � ~ 8 ~ d ~ t f ~ 1 f4~ ~ ~ n ~ u ~z ~ ~y n ' ~ Ppc, 3. ?.1 3. P.Y /tia dt.d Pac.,~ t.9~ , , ~ . . ~4 y ~ . ~ ~p 2 ~r ~D ~ >4 -i ~6' � ~ tD Ppi; ~?.5 . Paa,~L~ PXg ~ j,f . ' PNI J~t d. � -207- FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 FOR OFFI~`IAL USE ONLY ' _ -----r-.. _ 3 ~ ~ ~4 f 4 q f ~ f 1 1 3 S ~ ' 4 f 2 � f 4 : ; + a ~ ,o ~ to ~ ' � rs ~Z ~ 1d f 1~f >2 1 >4 ~2 f ~ ~ ~ Puc. 3. t. ft Pua J x9 Pua ~ 4.f0 Puc. J 2,11, ~ $ ' k f Br ~ ~ 2 ~ /11l ` ~ ~ a a ~ s 7 //y $ 2, ~ ~ ~ , ny A~ ~ ~ ny ~a ~ . ~ ` Pua 3.1.15 Puc. 3 t.~6 . ~ P~~~f3 Pu~~t.f4 ' � .i ' ~ 3 0 T y R T C ~ 4 R T ' S a 2 Cc ~ D 2 6~E 3 DI T ' ~ 6~, ~ D 4 ~p ~ ~ 8 Cc Cc 2 T ~ s Co T . Rl ' ~ lly ~ S I' D !4 CI 8 ~ Cc ~`f ' i0 ~ ~f f4 T : , n er ; D s ci ~ ~ ' 4 ~y I~ p a ~ Cc ' /wc. J ~PD ~ ; Pp~3.?.fr, ~,P~JLtd ~ Puc ~t,f0 ; ~ -208- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000540080034-5 1~---- _ ~ D/ T ~ S >4 S ' DI ~ ' ~ . ~ ~E ;J S' C72 ~ 9 C C)f!7 4 pC SI A7 ~ s! ~ . 1n ~ ~ ~ s1 ~ 7 St pl ~ st 4 3 ~ 3 >0 pp 2 DR l~ 1 fZ 1 Od 3 . DL 2 S Z 4 D! � ~ 3 , a ~ ~ ~ 6 D3 Puc. d Z21 Puc. JY.YY Puc. 3.1.23 Puc. ~7.19~ r OJSI � 64x . _ B 3 1 Al1 a~ A1 � . ~3 ~ O 6 ~ 2 O ~ ~p4 f ~ 2 4 2 ~ A ~ ~ ' B ~ ~ 0 P ~ 7 7 Puc. d2.15 Ppc.,~ 2.2B ~iic.dt.Y7 Pa~ ~ f.?B DO dX D1 ' . DI Dd M 8N Di ~ G17 AC ~ S1 ~ '1 2 ~ ~ ~ si I ' N P C d ~I PI I S2 s ~ ~ ~ ,v~ ~ a w s~ ~ ~ ~ I I Puc.,~1,19, Pk~~t.d0 P~rc.d~,d1 Pd~~Y.df ~ + . 192 ~ _ ~ ~ - 209 - . FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY ! 1~~ ~ f ~a Ad6~ y ,n f ~ ~ ~ e f . ~n Z . f ~ ~ a p p cvz � f CV Jn1 ~ 6 V2 f 2 f V3 f ~ � C ~ f P2 D D Pa~.~Y~~3. P~rc.3,1.d~ ; ~ PKC.3.?.35 ~ o,~ i ~ ~ ~c nnay t 2 0 ~oza a ~ ~ i 2 ~ 3 0~ a ~ �a ~ vt ~ ~ v~ n ' ~ ~ ~ V3 ~ ~ . D ~ ruc 3? 36 ~ Pr~, J.~~~. PNC, 3.?.~6 ~4 ~p A/ly � D1' Y! � ~ a DJ N! - 2f AO y~ ~ . ~0 ~ � SI ~ Of d ~ A1 ~ ~ ~ ~ , ea Xs ~ fP N ~.e . c hrc.3lt.39 .PKR~tr'~ ~I~b9.Y~41, . - 210 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500084430-5 _ ~ - ~ r - D ~ ~ ~ . - ~ C ~ F ' 1l e ~ n ~ . c ~ ~ 4 r D b 0 CD D ~ 4 1S ~ ' Z 2 d P � 4 T . 6 ! a - D ~ ~ ~ ~ . 1~ ~ f2 f C ~ C i~ ,~?.4d hra.~?.4~ Aliv,~t.f5 , 4 q ~ . s f ' ~ ~ r f ~ ~ ' ~ ' ~ f i ~1 ~o T g � f R F qE R c ~ s o a s Ilrra 3t.4i hR J~t.t~ h~ ~~~I - 211 - FOR OFFiC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY , - - ~ 3 3 ~ ~ ~ a - ~ 2 ~ d ~f d ~ > > 1 ~ / ~1 ~ , ~ f n ~ d ' g ; n ~ ~r , ~ 11x~l31 Paa33.2 ~ P~rcJJ.3 Puc.J.J4 . d a' e ~ s ~ '2 ~ . b ~ ~ B ~ ' 8 ! ~ ~ 8 ~r ~ ~ a ~ f ~ H , ~ . Plr~ 335 PIv~~~6 Pa~~~7 . PK~'3.~I ~ 2 ~ . ~ ~ . f a ' ~8 ~ ' 6 31 ~ ~3 !d ~ DI ~ RI ~ ~ ~ 'r ~ u~ ~ I t ~ ~ ~,~~t9 l~~ ~~!f~ ~,~.~r~ ,%1~~~. , - 212 - ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 K ~ ~ K ~ CM ~ f~f 6 a ~ 2 > = C7~ ~ ~ a n ~r f ~ ' t ~ a f 4 D' i d ' D2 f/ K ~ ~ si e n n sa ~r i� ~a /r~,~d13 Pu~,~,~1! Poa3,3.15 /k~~I3.16 pC ~ 3 p ~p~ ~ ~ ! C/ ~ f ~ � X8 ~ 2 s ~ a . , Xs sa ~ � a . ~ e~ ~ ~ ~ Xa� n a ~ c2 2 xa 81 ~ ^ 9 ~t a Xi Xf Ip~ 3~.17 P~raJ~ti~ Pba~I3.19 f~ 4 ~ . , . . ~ 4 ~ i!r ~ f ' , ~ 4 ~ ~ ' . ~ a ~ R . � _ ~ ~ . ~ f a ,vs q --i . e m ~ op . ~ u ~ ~ oa ~ ~ ~t ~ ~ e ~ ,~,~~m . " Iy+v.,~~It~ . ~wc.~I3tt t~ . ~ - 213 - FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONL`Y ~ A1 A3 ~ A4 i � 77 ~p Mv~ra~rr- 8 Vf ~ ~ p A4 ~ ~ ~ Ad Cf ~ ~ g ~ . ~ ~ ~T Qp ~ ~ � e ~ . ~ G~ QO ~ C2 ! ~ Ouo.,~3.Y3 ~ Pvc.,~3.Yt . /uc. J3.15 - \1 oay . c~riv p ~2 A~ ~ Tp 3 ~ A8 > > ~1 T 3 TT 1 e ~ z n f3 a ~ ~ ~ e , vz e Pac. ~3.Y6 Puc.3.J 17 Puc. 3. PB , a , : ~ ~ y, - ~ 4 crz ? ~ y ~ B ~ ~ R 1 A,4~ d d . f ~ 4 f ~ Z c f 8 ~ ~ r. y e 1f ~ ~ 6 f ` C 9 Pu~3.3?9 P~3.,~d9 . Pu~JddJ ~ s� pf � � c~ Ct1 4 ~ OZ ~ R ~ A R~ DO d ' b ~ Df ~ ~ ~ Clt ~ ~ >f DZ ~J d f4 k t a t 1� ~ ~ 04 e r, s C ~ r D4 P~c.3.3.dt PuC33.dd Pac.~ddf - 214 - ' FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY - - ~ 3 � 1 1 1 ,QC K ' ~2 _ . _ 3 ' 4 O . 10 ~ 5 ~ ' 6 f4 9 ~ 8 >1 ~ f0 ~ sy SM f3 ~ 1 i ~ ~ 5 q RC-- Puc. 3 J 3B A' ~ ' A4 P e3 � ~ A ~ ~ . 9 .2 ~ A3 ' S4 ~ . ~ K ~ ~ g e2 Sb 4 y >5 > >M s ~ 2 a n ; 2 , A2 ~ K K ~ ~ ef - ' sz ~ g Df k 14 d ~H I 10 D2 s. C A. Y M. Si d~ A7 lf Dp e f3 6 a~y ' PuC.,~3d9 ~2 D8 � � � 198 . Puc. J J 35 Puc. 3~,~6 iu~ ! 3.97 f� ~ . . - , . ' � . _ _ ~ T 2 ~ 6 V 3. ~ ~ S 9 ~V CT2 1 � ~ ~ CT2 ~ 2 7 S y T V 3 4 a~ " y C f ~ V 9 3 A1 2 I 2,q2 Z 4 f . . 2 ~ ~ Sf f3 Qy 4 f4 ~y ~ 2 3 ~ T ~ ~ R1 g ~ ~ � s ~ 4 !3 Y q !1 V ~ S1 Q8 ' ~ ~ 2 ~ 7 f 6 S 4 ~ >f Q Po' B ~ ~ ~ 1p 5 !4 T 2 S3 ~ ~!7 C P ~ ~ ~ ~ ' p 7 ~ V ~/7S' tt >5 ? 1~ ~ f5 p f2 ~ >4 Sy - ~P~~3.~40 , Ptrc3Jf41 . Puc.~J.4f Puc.3.343 PwC33g# ~~c.3.,~~5 ~ - 215 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R040500080030-5 FOR OFFICIAL USE ONLY BIBLIOGRAPHY 1. Bukreyev I.N., Mansurov B.M., Goryachev ~I.I., "Mikroelektronnyye skhemy tsifro- - vykh ustroystv" ["Microelectronic Circuits of Digital Devices"], Moscow, Sovetskoye Radio, 1973, pp 7-50, 99-104. 2. Drozdov Ye.A., Kamarnitskiy V.A., Pyatibratov A.P., "Elektronnyye tsif.rovyye vychislitel'nyye mashiny" ["Electronic Digital Computers"], Moscow, Voyenizdat, 19 68, pp 73-120. ~.�Papernov A.A., "Logicheskiye osnovy tsifrovykh mashin i programmirovaniye" ["The Logic Principles of Digital Computers and Programmir~g"], Moscow, Nauka, 1968. 4..Naumov Yu.Ye.~, "Integral'nyye logicheskiye skhesy" ["Logic Integrated Circuits"J, Mo scow, Sovetskoye Radio, 1970. 5. Baliyev K.A., Karmazinskiy A.N., Korolev M.A., "Tsifrovyye integral'nyye skhemy na NIDP tranzistorakh" ["Digital Integrated Circuits Using MOS Transistors"], Moscow, Sovetskoye Radio, 1971, pp 15-27, 252-290, 355-362. 6. Crawford R., "Skhemnyye primeneniya N~OP transistorov" ["Circuit Applications of MOS Transistors"], Translated from the English, Edited by M.S. Sonin, Moscow, Mir, 1970, pp 9-21, 106-111, 126-134. 7. Shebanin V.V., Tyukhin A.A., Tomov VnI., "Integral'nyye funktsional'nyye uzly d lya 2apominayushchikh ustroystv" ["Functional Integrated Circuits for Memories"], Moscc~w, Sovetskoye Rad3o, 1976, pp 7-27 (the series "Elementy radioelektronnoy apparatury" ["Radioelectronic Equipment Components"]; No. 3)� 8. Akuchenko N.A., Sokolova G.N., "Tendentsii razvitiya zapominayushchikh ustroystv" ["Developmental Trends in Memories"], ZARUBEZHNAYA ELEKTRONNAYA - TEKFINIKA [FOREIGN ELECTRONICS ENGINEERING], 1974, No. 3. , ' - 9. S taros F.G., Krayzmer L.P., "Poluprovodnikovyye integral'nyye zapominayushchiye ustroystva" ["Semiconductor IC Memories"], Leningrad, Energiya, 1973. 10. Mur, "Mikroprotsessory i tekhnologiya integral'nykh skhem" ["Microprocessors and Integrated Circuit Technology"], TIIER [PROCEEDINGS OF THE IEEE], 1976, No. 6, pp 5-11. Ferkhofshtadt, "Otsenka tekhnologii mikroprotsessornykh BIS" ["An Evaluation of Microprocessor LSI Technology"J, TIIER, 1976, No. 6, pp 5-11. 11. Shilin V.A., "Tsifrovyye elementy i ustroystva na priboralcYi s zaryadovoy r u n svyaz yu [ Digital Components and Devices Using Charge Coupled Devi.ces"]~ ZARUBEZHNAYA ELEKTRONNAYA TEK~INIKA, 1974, No. 5, pp 3--4, 47�-84. 12. Grinkevich V.A., "Mikroprotsessornyye komplekty BIS" ["LSI Microprocessor Sets"], ELEK~RONNAYA TEKHNIKA. SER. 6. MIKROELEKTRONIKA [ELECTRONICS ENGINEERING. - SERIES 6. MICROELECTRONICS], 1976, Vol. 5, No. 2. ' - 2],6 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR pFFICIAi, USE ONLY 13. Val'kov V.N., Il'y~shenko Yu.M., "Tsifrovyye integral'nyye skhemy, milero- protsessory i mikro-EVM" ["Digital Integrated Circuits, Microprocessors and Microcomputers"], Edited by V.M. Proleyko, Moscow, Sovetakoye Radio, 1977, ' pp 49-60 ("Electronics" Library"). 14. Aleksenko A.G., "Osnovy mikroelektroniki" ["Microelectronics Fundamentals"], Moscow, Sovetskoye Radio Publiahers, 1977. 15. A1'tman L., "Perspektivy primeneniya odnokriatal'nykh mikroprotsessorov" ["Prospects for the Application of Single Chip Microprocessora"], ELEYTRONIKA, 1974, No. 8, pp 26-34. - 217 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY ~ CHAPTER FnT~, ANALOG INTEGRATED CIRCUITS 4.1. Function and Application Analog integrated cir.cuits ~AIS) are intended for real t~me signal proceasing where the output information of such an IC ia similar (analogous) to the input signal. The following analog IC's are treated in this chapter: operational amplifiera; integrated circuit voltage comparators; integrated circuits which multiply analog signals; IC's for radio receivers; switching circuita; analog to digital and digital to analog converter IC's as well as integrated circuit regulatora. In contrast to devices using digital IC's, each analog device has a considerably greater number of electrical parameters which make it possible to come up with a complete model of it. Moreover, the application of an analog IC is always ape�ific: a large number of ultimate operating modes with respect to the power supply, signals and load must be specified. In contrast to digital IC's, a certain number of external camponents must be connected to each analog IC where these components establish the requisite transfer function of the device. The major types of analog circuits will be treated in this chapter and examples will be given for the design of radio equip- ment assem~lies around these circuits. 4.2. Operational Amplifiers An operational amplifier is an amplifier by means of which one can construct equip- ment assemblies having parameters which are dependent practically on the propertiea of the negative feedback circuit in which it is inaerted. The major function of an operational amplifier (OU) is the construction of circuits with a fixed gain and precisely synthesized transfer function. Op amps can be used to construct the most diverse hardware: voltage regulatora, signal generators, video amplifiers, active filters, scaling�; logarithmic response, differentiating, integrating and other amplifiera. A standard general purpose amplifier can be used in 100 to 150 circuit configurations. The circuits for the first IC op amps were sunilar to their discrete prototypes ~with certain limitations imposed by the specific features of the integrated circuit structure). However, by the end of the 1960's, IC designers began to actively use new integrated circuit atructures and circuit design approaches to improve op amp performance [1, 2]. Regardless of the complexity of the basic circuit configuration, an integrated circuit op amp consista of an input differential amplifier, a voltage amplifier, a DC level shift circuit and an output power amplifier. Depending on the number of stages which make the major contribution to the overal gain, a distinction is drawn at the present time between three atate and two stage op amps. The op ampa which were developed at first had a three state etructure. Beginning in the 1970's, op amps have been designed using only a two stage configuration in which states 2 and 3 have been combined. -2],8~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 The first stage of an op amp is designed in a differential amplifier configuration. A reduction in errors, amplificat2on bf the DC crnnponent of the signal and an increase in the input atage impedance are achieved by virtue of the input stage operating in a microampere current mode of the emitters. All of the input para- meters of op amps are governed by the properties of its differential input stage. The second atage of the first op amps was designed in a simple differential config- uration. When a two-state amplifier circuit is used, the second atate has a coTmnon emitter ~OE) configuration. Besidea booeting the gain, the second stage provides for impedance matching of the input and final stages. In order to eliminate the DC voltage component which occurs in an op amp circuit with direct coupling of its stages, a special DC level bias ~shift) circuit is additionally introduced. There is no special shift circuitry in two stage op amps, since its function is sutomat- ically performed by the second stage. The final (output) stage of an op amp serves to match the high output impedance of the amplifier stages to a low resiatance load, i.e., makes it poasible to obtain a low output impedance for the op amp. It is usually deaigned in a push-pull config- uration operating in either the class AB or B mode. A class A output stage is sometimes used in very simple op amp circuits. Operational amplifiers are uaually powered fran two symmetrical aupplies which provide positive and negative output voltage amplifudes which are equal in value. For the majority of modern op amps, the supply voltages can vary "arl~itrarily" in a rather wide range (frequently fram +3 to +15 uolts), eomething which makes~it possible to construct both economical circuits and amplifier with a large ~or asymmetrical) output signal ampliEude. The poasibilitiea for op amp applicationa depend on its electrical parametere. More than 30 parametera are needed to com- pletely specify op amp performance [1-4], where theae parameters make it possible to create a so-called parametric model. This model makes it poesible to explain operational amplifier .quality without additional testing. Knowledge of the major parameters of integrated circuit op amps makes it possible fo~ designers to design a circuit without long term bread�boarding and to prevent op amp operation in an impermiasible mode, so as to reduce the probability of failure. Thus, an exhaustive parametric mode allows for the rapid aelection of the requisite type of operational amplifier for a given assembly. Operational amplifiers are characterized by the gain, which is equal to the product of the gains of all of their stages: ~ ~w) _ ~T K,, N U where KU(w) is the voltage gain of the op ~mp withou~ feedback; Kn is the gai.n of an elementary stage;~ w is the frequency and N is the number of stages. The DC gain of aeveral integrated circuit op amps reaches 5� 106, but it falls off with an increase in frequency. The amplitude-frequency response of an op amp is compos~d of the frequency characteriatics of the individual atagea operating with various currente a~id loads. Each amplifier etage has ita own time constant and can be represented in the~~form of the equivalent RC network. For this reason, the - 219 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 FOR OFF[CIAL USE ONLY Ko~~ K~, dB ~ degreea ~ . >80 . d!7 ~ - ~ ' ~40 ` ~ . ?70 � ~ ~ ; YD . ~ ~ ~ ~ \ ~ ` ~ ~ ~ f , Sz ~ ~ ~ . ' 0 ~',+lAd ' H ~ ~Gi 1D ~17 ~ f~q 1Dd !7a ~ f,/'qt - ~ ~ ~ . . Ql Figure 4.1. The overall amplitude-frequency ~a) and phase- frequency (b) response for single stagp ~solid curves), two-atage (dashed curves)~ and three stage (dashed and dotted curvea) operational amplifiers. overall amplitude-frequency reaponse (AChKh) of an op amp is approximated in general form by a Bode plot with several salient points (F igure 4.1a). Each stage introduces a phase shift of 90� at the high frequency; for this reason,tfhe-phase response of an op amp depends on the number of stages (Figure 4.1b). Because of the fact that there is a planned phase ahift in the signal of 180� at the output of an op amp for the operation of the feedback loop, the overall phase shift in an amplifier looped with negative feedback (OOS) reaches 360� at some particular high frequency. And if the product of the amplifier open loop gain , times the negative feedback trsnsmission gain at this frequency exceeds (or is equal to) unity, then this ~suses the aelf-excitation of the circuit. Stable frequency and pulse transfer characteriatica are achieved through the use of amplitude-frequency response equalization. For this, capacitive negative feedback loops are introduced which-change'-the slope of the amplitude-frequency responae of the closed loop system down to a rnlloff rate of 20 dB/octave, which character- izes a stable first order section. A eingle atage (ultimate phase delay of 90�) would be ideal in terms of op amp stability, but ita gain is insufficient (no more than 1,000). One equalizing capacitor in all is needed to s'tabilize a two atate op amp. Three-stage operational amplifiers can be equalized by using two outboard capacitors ~or two RC networks). It is difficult to atabilize op amps with more than three stages of amplification without aubstantially limiting their bandwidth. An important parameter of op amps is the input impedance. A diatinction is drawn between two types of input resistances: the eignal.input reaistance, i.e., that observed betw~een the op amp inpute (the ao-called differential input resistance), - 220 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY and the in-phase signal input resistance [common mode rejection] (resistance between the input and ground). The differential input resistance is defined by the expression: Rin dif ~Uin~~iin 2�T~Ib Y 2~T~Iin' where ~Uin is the voltage change between the op amp inputs; ~Iin ie the change in the input current, �T ia the temperature potential (at 300 �K, ~T s 26 mV), Ib is - the base current of the input transiator and Iin is the input bias current for the operational amplifier (taken from a table of its parameters). The in-~ahase input aignal resistnce (Rin ph~ is defined as the change in the input current with the action of an in-phase input voltage: _ Rin ph ~Uph in ~Iin where AUph in is the increments in the in-phase input voltage between the input and ground. - The input differential resistance falls in a rangeof 10 Rohm to 10 Mohm for bipolar op amps while the in-phase resiatance exceeds 100 Mohma. Because of the differn-~ tial input, an op amp amplifies the difference input voltage and ahould completely ' suppress the in-phase voltage. Aowever, an op amp does.not campletely suppress the ; in-phase signal and thereby introducea an error into the output signal. The ; parameter "in-phase signal suppression factor" ~Ros sf) ~~~n mode reje~tion ratio, CMRR] reflects this property of 8n amplifier. It makes it possiule to compare various types of operational amplifiera and to also estimate the error introduced by the op amp, and is defined as the ratio of the op amp voltage gain to the gain for in-phase input voltages. The difference in the base-emitter voltage drops of the input integrated circuit transistors, and to a leaser extent, the scatter in the nominal values of the remaining co~nponenta of the operational amplifier lead to the apperance of DC voltage at the output in the absence of ansignal~at the input. In order to aet the zero level at the op amp output, it is necessary to applq a certain balance (bias) voltage, Ubias, between the op amp inputs. All of the above mentioned op amp parameters depend on temperature. The tempera-~~~ ture drifS:s in the bias voltage and the input current differences exert~the major influence on the error in the function realized by the op amp. The temperature drift takes tl~+~ form of a change in the voltage or current with a change in the ~ ambient temperature by �C. Theae changea are superimpoaed on the input signal, as a result of which, the error voltage is aum~ed, while the error current yields a voltage drop acrosa the internal resistance of the signal source. - Z21 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 FOR OFFICIAL USE ONLY All operational amplifiers are deaigned for an output current ~Iout), which determinee the minimum resistance of the load at the naminal output voltage. Exceeding the given current can cause the op amp to fail. The output impedance of an operatio~al amplifier is defined by the impedance of its output ata~e and amounts to 20 to 20,000 otuns (depending on the circuit design and the function of the op amp). The output impedance exerts great influence on the output signal amplitude, especially when the amplifier operatea into a low load impedance. As was stated above, an op amp can perform various functions, which are determined by its feedback. A distinction is drawn between basic circuit configurations for op amps, looped by negative feedback: inverting and noninverting. z+ Ri ~ ~ Z' ~ Out a ~t In z eax . In Z ~ ~ , ~ j Rload z~ Rload ; ~a~ ~ l= ~1 (b) Figure 4.2. Basic circuit configux~at.ions for operatio~l amplifiera. a: In~erting; . ~ ~ b. Noninvert~ng. ~ . In order to s unplify circuit design and analysis, the concept of an "ideal" oper- ational amplifier is introduced, which possesses the following properties: the open loop gain of the amplif ier Kp tends to infinity, the rolloff of its frequency response is 20 dB/octave, the input impedance of the op amp tends to infinity, the output impedance approaches zero and the amplifier does not introduce any errors in the DC component gain. When an op amp is uaed as an inverting amplifier ~Figure 4.2a), the phase of the output signal is shifted through 180� relative to the phase of the input signal. The transfer function of this circuit (when Ubias U' 0, Alin = 0, CI~tR and Rload = h88 the form: U i Uout~Uin - -ZO~Z2 where Zp is the negative feedback impedance and 22 is the impedance of the signal source. - 222 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080034-5 A noninverting operational amplifier configuration ~Figure 4.2b) is used in those cases where it is neceesary to match a source having a high impedance to a aignal processing circuit 'naving a low input impedance. In thia case, the phase of the output signal duplicates the phase of the input eignal. The transfer function of an ideal operational amplifier in a noninverting corifiguration has the form: -17 n.i. a Uout~Uin ~ 1+ ZO~Z2 Since the value of the gain for integrated operational amplifiers falls in a range of 5� 103 to 5� 106, in practice, the error arieing in manq cases due to the ~ idealization of this parameter (RU a) may be disregarded. However, one may not disregard the errors fram the DC component shift which occur because of the dif- ference in the base-emitter voltagea of the input traneistora and because of the flow of the input currents :~of the op amp through rhe signal aource resistance, since bhey can even exceed the input signal level. The input currentg ~Iin) of operational ffinplifiers are due to the base bias currents of the input bipolar transistora ~or the leakage currents of the gatea ~ for operational amplifiers with field effect transistors at the input). The input currents of bipolar tranaistora are needed to provide for the operating mode ~ (supply bias) of the input stage and have a value of from 50 nA up to 5~aA. Operational amplifiers with field effect transistors at the input have input currents of less than 1 nA.~admittedly, in a limited range of tempe~atures). Because of the nonidentical nature of the characteristica of the input stage transistors, the base currents can differ from each other by 20 to 30 percent and introduce a subatantial error even when the signal aource resiatancea are equal. _ The input current difference parameters ~Alin) ahows by how much one input current may differ from another. To reduce this fraction of the error, the internal resistance of th e signal aource should be chosen ae low as posaible. The dynamic characteristica of operat ional amplifiera are estimate~ by means of two parameters: the rate of rise of the output voltage vU out and its aettling time (t8et). The rate of rise of~.the output voltage ia understood to be the ratio of the change in the output voltage from 10 to 90X of its nominal value to the time over which this change has taken place, with a etepwise change~.in the input voltage: ~U out (U0.9'. - U0.1~ / ~t0.9 - t0.1~ The settling time is defined as the time interval during which the op amp output voltage changes from the time of the first intereection of the 10 x level until the final attaining of the 90 % level (of the nominal value) and primarily characterizes the pulse stability of an operational amplifier. - 223 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY By etnploying idealized operational amplifier characteristics, one can analyze various op amps configurations in a s unple manner. Idealization makes it possible to derive two rules which may be used for the analysis and synthesis of circuits - based on operational amplif ie~s: 1) No current is taken from the signal sourc~ at the input terminals of the op amp (a consequence of the fact that Rin 2) The voltage across the inputs of an opera~ional amplifier looped by negative feedback is practically equal to zero ~a consequence of the fact tiiat KU We shall cite two examples to illuetrate the application of these rules. We shall analyze the circuit of an adder (Figure 4.3a). By using rules 1 and 2, we calcu� late the transfer function of this circuit. Firat of all, since the current from the signal source is not branched off to the op amp input, the sum of the current s of all sources flows through the negative feedback circuit: I1 + I2 + I3 = Ip. Secondly, because of the fact that the voltage across the inputs of an operational amplifier looped by negative feedback is equal to zero, the voltage at point A ia also equal to zero and the preceding equation for the current can be rewritten in the form: ~ Ul + U2 + U3 _ Uout R1 R2 R3 RO The fact that the output voltage of the~operational amplifier, Uout~ ~Y be measured both re~ative to the "true" ground and relative to "signal ground" (point A) has been taken into account'.~.here. But in the latter case, this means that the output voltage is applied to the feedback resistor through which the current Ip = Uout~RO flows. If the naminal value of the resisters are R1 ~ R2 ~ = R3 = Rp, then the circuit operates as an inverting adder: Uout ~ -(Rp/Rg~ (Ul + U2 + U3~ We shall not consider the circuit of a logarithmic amplifier (Figure 4.3b). The p-n junction of a transistor is usually employed as the element having a logarith- mic response. We shall assume that~the voltage across the p-n junction ia equal to Up_n = K ln(Ip-n), where is a constant and Ip_n is the junction current. In accordance with the procedure presented here: ~1) No current is branched off to the op amp input, and for this reason, Iin ~ Ip-n; 2) Using the "unofficial ground" potential, one can calculate that Iin = Uin/R, and consequently, Uout s = Up_n = K ln(Uin/R), i.e., the amplifier can take the logarithm of the input voltage on a particular scale. As a result of the id~ealization of operational amplifier parameters, errors occur when constructing equipment based on them which become less, the closer the para- meters of the actual op amp are to the ideal. Operational smplifier designers strive to bring the op amp param~ters cloae to the ide~l onea: to increase the gain, the input impedance, the bandwidth and the reaponae speed. In this case, 224 ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY ~ Uin 1 'o~ r~'' ~P� ~ "~ir ,AJ ~5? ~trTf Uin 2 ; Uin ~ a~.~ . 7hra ~ A ~ M ~ .D(~er ~ Uin 3 . � . + IIout ' + Uout ~ ~ r~ i(a) ~ (b). Figure 4.3. Examples of operational amplifier circuit configurations. a. Adder circuit; b. Logarithmic amplifier circuit. efforts are made through the use of new circuit deaigns and especially, produc- tion process techniquea to reduce th~ values of the bias voltage, the input cur- . rents and the drift in them as well se the power coneumption of the device. An entire series of semiconductor op ampe which can broken dowa into four groupa has been created as a result of tne evolution of the circuit des.ign and produc- tion process solutions: the bulk of the producte are general purpose operational amplifiers which make it possible to congtruct equipment having an overall error - on the order of 1X; precision (instrumentation) operational amplifiers which have a very high gain, as well as gusranteed low levels of drift and noiae, which makea it possible to realize assemblies which operate with an error of no worse than tenths of a precent. Moreaver, the demand is high for operational amplifiers intended for the constrnction of wideband amplifiers with a slew rate of more than 50 V/usec, as well as micropower op amps which conaume less than 1 mA from the power supplies and are designed for uae in economical equipment (frequently powered by batteriea). 4.2.1. Operational Amplifiers with a Two Stage Structural Configuration The first operational amplifiers of the 140 UD1, 140 UD5 and 153UD1 typea had a - three stage configuration becauae of the fact that the technology did not at first make it possible to obtain high reeistance loade, or good p-n-p transistore. For three-stage amplifiers, nwaeroue auxiliary components are needed for frequency equalization, b~lancing, overload protection at the input and output as well as protection against flip-flop operation. Achievements in the field of technology and circuit design have made it possible at the present time to develop ~opera- tional maplifiers with a two stage etructure, since n-p-n and p-n-p transistors can be produced in one production proceae cycle, wt?ere these transsators are used both as an amplif ier and as an active load. 1~ao atage op amps operate with lower supply currents and have an increased gain. ' - 2Z5 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY Because of the use of integrated circuit input transistors with a high gain in such operational amplifiers, the levels of the input currents are reduced. More- over, the active loads on the amplifier stages, which are used instead of ~high resistance resistors do not require large voltage dropa to obtain the requisite operating modes, something which makes it possible to provide for stable op amp operation both at low (�3 volts) and high (+15 volts) aupply voltages, maintaining the high gain in this case as well as the output signal amplitude which is pro- portional to the supply voltages. A reduction in the number of amplifier atages down to two also reduces the number of salient points in the amplitude-frequency response curve down to two, and in the final analysis, reduces the number of fre- . quency equalization components to a single capacitor. Two stage operational amplifier circuits are protected against overloads at the input and output, and some of them also have internal frequency equalization components, which makes it possible to reduce the number of outboard components down to a single balancing resistor. All of the op amps treated in the following are structurally packaged in circular packages with eight leads. The socket con- figuration of these opartional amplifiers basically conforms to the pin configura- tion of the 153UD1 op amp. This has been done~ so that obsolete types of opera- tional amplifiers can be replaced without doing any additional w~ork on equipment. The electrical characteristics of operational amplifiers are given in Table 4.1. The 153UD2 Gener,ql Purpoae Operational Amplifier. Op amps of this type (Figure 4.4a) have a complex output stage (transistors VTS, VT6, VT9 and VT10), which is powered by the atable current of transistor VT1. The base-emitter voltage of this transistor is controlled by a regulator (transistors VT2...VT4 and resiators R1...R6). Transistors VT6 and VT10 have two collectors; one of the transiator collectora which is shorted to the base, takes the fona of a diode which regulatea the current of the "operating" collectors in a broad range of supply voltagea. The dynamic resistances of the collectors of tranaistora VT7 and VT11 serve as high resistance active loads for the first stage. Tranaistor VT8 provides for a constant bias at the emitter-base junction of transistors VT11 and VT7 bq means of resistor R7, and it additionally serves as a aingle in~~rter in the transition circuit fram the differential output of the first stagE to the single ended input of the second. Resistor R8 is intended to compensate for the bias voltage, which can be balanced by inserting a variable resietor between pins 1 and 5. Transis- tors VT13 and VT14, which are connected in a Darlington configuration, form the second stage, the dynamic load on which is the atable current generator (GST), which is formed by the open collector output of transistor VT16. Transistor VT16 has two collectors, one of which is shorted to the base, which makes it possible to effectively stabilize the current of the second collector of resietor of VT16. The bias is set at the base of the transiator by means of the current of the collectora of transistors VT2 and VT3 from the regulator circuit. The second collector current of transistor VT16, in passing through the emitter-base junc- tions of tranaistora VT17 ~in a diode configuration) and VT15, produces the bias for the opergfing point of the output stage in the AB mode and powers the second amplifier stage. The push-pull output stage consists of an'emitt~r'follower using an n-p-n tran- sistor ~VT20) and an emitter follower using a camposite p-n-p transistor ~ 226 - FOR O~F'IC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY N u1 O t*1 u1 O O O N O O O rl N O I 1 .-I O N ~n c+1 O m ~ O N 10 N N 1~ c0 r-1 N'1 rl ~--I ~ _ ~ ~ ~ ~ 1 O O N ri I.t 1 O O O O ~1 M d~ ~ ~-~-I N O O v1 t~ O N e-I e~i rl ~-1 D+ ~1'1 r"~ M O u1 q .-1 N u1 O ~G ~ ~ N ~ N O ~ ~O ~ O I I 0o I I ~ I ~ ~ O x~ ~rl ~ N ~ W O rl � e~1 ri ~O rl vl O 00 G~ ~ ~j u1 O O O O O O N rl I O I u1 r-I O rl ~1 N D+ O N c+1 rl f~ 00 O N r-I N1 r-I ri ~7 O r-I r-I N ~ 00 ~n O a0 rl ^Q O O ~ O O O O 1 O 1 O .-1 .7 N u1 N N~ ~ O .t ~O N ~1 O ~r1 t~ r-1 J N r-I ~ rl rl D+ H ~7' W ri ~ ~ ~q-1 O O O p u1 O O O 1~ O~1 O~ I O O t~1 O u1 00 ~1 ~C O c~1 M O v1 +--I N~O O O rl rl ',Z+ = ~ Vl ~O N ~-1 N ~ d Gl Nq r-I ~1 ~ ~ p u1 O O O M u'1 O O N~-1 O O M O ~T ~O N ~O O c~d .~7 N ~ N c'~1 00 `O O ~-i rl .-I ~-I '~i C a ~ ~ U r(~l c'~1 v1 u1 ~O ~ ~.7 I~ c0 O ~ M N~ O u1 r-I ~t OO c~'f ~O .-i ci'f eN-I 00 ' u ~ � ~n ~ N oo � ~ ~i W ~ O v~ N o0 u1 M N A r1 r-I . . . . . O ^ N ~ ~ M O~ O u1 O~t OO M cr'f ~-1 M ~O ~t '"~i C . ~ I~ rl v1 ~ C~ N CJ ~ w ~ ~ W w w w A p ^ }r fa ~ \ H~ q_Q N t0 00 W O N ~ O~+ Q N N H D 4-1 ~ rl Fra 1-i ~.1 RI q D b0 f~ 'r'~ ~ ~ a+ ~+w ~ a ~ a? a4 ~ ~f o a ~ ~ ao ~ ~ o ~ ~ eo ~ O~0 r~l rl CI D Pq ~ Ol tJ D O N � r-1 1.~ N ~ c0 H ~'C! 'd ~1 D4 R7 O C' N cJ ~ tA O rl O w V Ca ~ i~ t0 p. 'J ~ tA ~-~1 ~ O i~ 4 N Gl C! cq ~ ~ 1.~ .C eo ~ w o a~ ~ q p a a ~ w~ w~ cc ~v a a ~ a q ~o ~ a~+ ~ d ~ ao b a~ a.+ m a i+~ ~ a~ ii ~ tn CS a~ cd ~ p+~ aJ ~ CI m q p a r-1 o a~ ~ Q ~ m,.+ a+ s~ Y+ u-~ oo ao d~+ p,, o o~~+~ ~ a o u o � ~-I ~ cd rl r-I ~ H ~ rl O~ c0 00 Q O ~--I ~~'J rl rl rl � c0 rl O O E~ V U� 4 CJ i~+ Gl r'~+ ~d OG C3 'r'~ ~'J ONO ~D p~ RS U~ ~t ~ .a 9'J C 'd b0 fa rl 1~ e~ ^ ~ M'~ \ ~ ~ ~ ~ V ~ ~ '1 ~ ~ ~ ~ w Fi ~ ~ ~ ~ ~ � ~ ~ ~ ~ ~ w a o m ,i ~ ~ a? ~ a~ o ~ ~ a ,a a~ a N o o 0 a~i ~ ~ p q a ~ ~ A ~ o q a~i q ~ ~ ~ o ~+i o~+i~ ~ o o ~ u ~ ~ N HP~14HH NH GJ~,~a V~~c/~H, O H p 'a 'J P~''aUH H f!~ W E~ r. i. i. r. i..-. r. i. ~ ~ ~-i N c~1 ~Y' ~1 ~D I~ 00 O~ O r-I N M ~7 tI1 ~G I~ 00 O~ O v v v v v v v v v~,--~ ~ r-1 r{ rl ~--I ~-i ~--I N v v v v,i v v v v v v v - Z2~ - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040500080030-5 FOR OFF[CIAL USE ONLY TABLE 4.1 [contiriued]: Parameters 153UD5 153UD4 140UD10 (transistors VT21 and VT18). Transistor VT19 performs the (1) 2.5 5 4 function of a current limiter; (2) 5 50 - it turns on when the current (3) 125 400 250 through transiator VT20 (4) 35 15 50 exceeda 25 mA. Transistor VT21 (5) 0.50 3 - is protected against a short - (6) 125 2 50 circuit current in the load by (7) 94 70 80 a 50 ohm resistor. Transistor (8) - 0.1 +50; -20** VT12 aerves to protect the (9) - 1 15 output stage against flip-flop '(10) - mode operati~n. The plot of (11) 103 200 103 the gain as a function of (12) 150 - - frequency for.the 153UD2 oper- (13) 5 - - ational amplifier ~Figure 4.4b) (14) 10 4 - is equalized with a single (15) 5 2 - capacitor. (16) 13.5 5 11.5 (17) 15.0 6.0 15.0 An original circuiC deaign as (18) - 0.8 8 well as the use of an active - (19) No No� No load and an internal regulator (20) Yes Yes - have made it poasible to cut *~he value of the short circuit current the current consumption of the is given; 153UD2 operational amplifier Plus is for a positive output voltage; in half (Figure 4.5) as com- Minus is for a negative output voltage. psred to the 153UD1 op amp. Ia ~his case, the range of in-phase and differential input voltages has.increaeed, while the possible range of supply voltages has been reduced down to +3 volts. The ~ 153UD2 op amp is protected againat short circuits at the output and has a simple frequency equalization circuit. The 153UD2 op amp is produced in an encapsulated and unencapsulated~variant. The designation of the unencapstilated variant is 740UD5-1. Additionally, domestia industry is producing a number of unencapeulated linear integrated circuita ( Table 4.2). The 140UD7 Operational Amplifier. This type�of operational amplifier ~Figure 4.6a) - is a si.mplified variant of the 153UD2 op amp circuit. The 140UD7 amplifier has a complex input stage, the arms of which are designed in a complementary common collector--com~non base circuit configuration using transistors VT1, VT2, VT6 and VTB. A current difference regulator [2] using tranaietorsVT9 and VT10, the bias to the bases of which is aet bq meana of transiators VT5 and VT12 (used ae diodes) is amployed to maintain the output atage currenta constant. The voltage picked off of the first stage ia amplified by the aecond atage (tran- sistors VT14 and VT16, which is loaded into the large internal impedance af the s.table current generator and the inpuC impedance of dual emitter transistor VT18 - 228 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 - FOR OFFTCIAL USE ONLY a ~ ~ vr~ a~ 2 ~ ~T20 Y75 3 ~ ~ AS YfA9 vr~, I ' ~ ~ VI'Af' IPI~ yM VT8 ~Pd VT1S N~ ?~7y VT7 '~ry j/ Y~1f f'7y4 ~ VT4 n ~ ' I ~72 A4 ~ ~ R3 6~ . 07 tg~ ~ . /;a~ ~ ltage gain, dB ' gigure 4.4. The 153UD2 operational amplifier. ~ � a. Basic electrical 6p echematic; ~ 4Q b. The gain plotted as a function of frequency. zo ~ f Hz ' ' - >o' ~o~ ~n~ ~;rp ~ ~ (b) which is~connected in parallel with it, The stable current generator is designed around the dual collector tranaistor VTIS, which ie stabilized by transistor VT11 used as a diode. The output atege, which operates in class AB, is designed around transiators VT23 and VT24. Transistor VT17 (used as a diode) and tranaistor VT19 bias the operating point~of the output atage tranaistor. .Tranaistora VT21 and VT22 are protected against output stage overloading. They turn on bu virtue of the voltage drop across the'resiators inserted in the emitter-base circuit of the given transistors. Transistor VT13 and the second emitter circuit of transistor VT18 are intended to protect the output stage against flip~flop operation. The circuit has an internal equalization capacitor C1 with a naminal value of 30 pF, and for thia reason, the amplitude-frequency response of the op amp (Figure 4.6b) is completely equalized. The alope of the amplitude-frequency reaponae (-20 dB/oct) and the conatant sh ift at high frequency i~tiich ia equal to 90� (Figure 4.6c) allow for the use of the optrational amplifier as a follower without additional frequency equal- ization components ~Figure 4.6d). To increaee the alew rate of the output volta~e ~ 224 ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICiAL USE ONLY TABLE 4.2 Unencapsulated Linear IC`~i Produced by Domestic Industry The Encapsulated IC Designation Major Function Series (For Refer- . en~ce ) Operational Aaiplifiers. Direct Current Amplifiera 129NT1A-1... 129NT1I-1 Basic differential amplifier circuit 159NT1 710UD11 Operational amplifier 153UD4 740UD1A-1, 153UD1A, 740UD1B-1 The same 153UD1B 740UD5-1 " " 153UD2 740UD4-1 " " 140UD6 740UD3-1 . " " 140UD1 S~aitches 714KN1A-1... ~ 714KN1V-1 Anualog voltage switch with control circuit - 714KN2A-1, 714KN2B-1 Differential analog voltage switch - 716KN2B-1 Control circuit for electronic switches in - the 273 series of ir.tegrated circuita 716KT1-1 Dual bipolar chopper for switching analog signals - 743KT1A-1... Series integrated circuit chopper lO1KT1A 743KT1G-1 lO1KT1G K762KT1A-1, Integrated circuit chopper K162KT1A, K762KT1B-1 K162KT1B up to 10 volt/usec, a provision is made for reducing the degree of equalization. For this, capacitor C1 with a capacitance~:of 150 pFd is connected to pin 8(as shown in Figure 4.6e). The equalization circuit for the op amp consists of one external variable resistor which is connected to pins 1 and 5. ~ 230 ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR UFFICIA: , R3 - In 1 FX, ~Vl A1 , Bx/ R'rl Z ,V3 - - 6 eo~x - A~ out In 2 6x 6x? ~P2 a 6 ~ Oax 3 8 ~llt ? C2 . > ' . 1 . 470 Cl 30 C> 30 q4 10K a~ (a) ~b~ oJ C2 30 . . pJ ' pNC. 4.5. CE8M6I qBCTOTNO~ ROpPlKqqM ~ ~ Z ~ xae aasMCN~yoc~x (z a)e) x xx qacror Af 6 a- cr~x~t~prn~~, 6- c weKCMruneoll a2 awnaNry~top cNrxaae, s- c onepe~cee~ar no 3 B4 cxtaM~aatar. s- AJIfI pE1KNY� M~Ofp CMI'N~A~~ d-~JIII QqKNM~ 60J16tlIOt'O CRl~1~ ~ el . + Kn,~ Voltage gain, dB Uout' volts. ~i~a,~ f ~ . d0 . ~ a 6 / ' 8 . 0 . ~ * ~ f~ ~Z f, Hz 0 ~17� ~f1� f/~r ~i ~7a R7 ~j/;r - , y (d) ~ (e) d/' - Figure 4.5. Frequency equalization circuit for the 153UD2 op amp ~ (a-c) and their frequency responses ~d, e). Standard; b. With the maximum signal amplitude; c. With a lead with respect to the high frequency components; , d. For the amall signal mode; e. For the large signal mode. -231- FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFF[CIAL USE ONLY . � 1 ' ~ YTS Y7f2 yTlS y~g VT23 YTl7 VTYI V78 ' ~ V11 > Af0 , a~ vrfs aa ~ YT2 391t 6'1 i7~ ' . ~ . 6 ' Rf! VT22 25 V7k i714 VT18 y~ Y714 . VT7 VT24 ~ ! Y7AD 6 Rl ~P2 RJ 174 (?!3 R6 ~P7' ~ fM SOK fK 6K SGK fQ7 5X 4 . (a) u ~y~~ oltage �gain, dB ~ ee ~a . , . . ~y a~ . at -~aa f, xz ~ . f , xz - ~ ~p ~p' ~vf f ~a 8~ ~b~~l f0a f~~K (c)~ /1 � R3 ~ 10K � ex R! 2 ` ~ ~ - Daor ~ 6 Af . X 3 A f ' 't'.-� s+ , ~ R4 C3 � + p, 1 ~r 4 H, 4 ~Z ~J 5K ~ ~UMa ~UNO ~e) +1/rR ~a ~d) . e~ .w ~.ntrrt~. n.... . n r~ . . . . . ~ Figure 4.6. The 140UD7 operational amplifier. a. Basic electrical achematic; b. The gain ae a function of frequency; c. Phase-frequency response; d. Circuit configuration for a noninverting follower mode; e. Circuit configuration for the equalizing capacitanCe to improve the rise time of the output voltage. - 232 - ~ . FOR OFFICIA~ USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 4.2.2. Amplifiers with Field Effect Transistors at the Input A pair of matched field effect transistors is frequently used to reduce the input currents of an operational amplifier down to the level of the gate leakage currents of the FET's (i.e., down to a value of 10'9 A). The improvement in the fabrica- tion technology of IC's has made it possible to obtain bipolar and high qua~ity field-effect transistors mn a single production process cycle (on one chip). This, in turn, has made it possible to create semiconductor op amps which have an input impedance at a level of 1011...1013 ohms, and consequently, an initial bias current approaching 0.1 nA. One of the amplifiers with field effect traneistors at Che input is the 544UD1 operational amplifier ~Figure 4.7). The op amp is designed in a two stage configuration. The input stage takes the form of a differential amplifier with source followers in the form of a matched pair of n-type FET's (VT1 and VTS), working into active loads (transistors VT2 and VT4). The active load provides for a high stage gain and an extended permisaible range of of in-phase input voltages. Moreover, the use of field effect :ranaistors makes it poasible to feed in large differential input voltages. Inte,:na~ frequency equalization is employed to improve the frequency response of the amplifier. The second stage and the level shift circuit (transistor VT8), which is desi�gned around low frequency p-n-p transistors, are shunted by an equalization capacitance. The output stage and its bias circuit are designed in a manner similar to that of the 140UD7 op amp. The bias voltage balancing is accomplished relative to pins 1-8. The favorable input characteriatics make it possible to widely utilize the opera- tional amplifier in integrator circuits, operating with large time conatants and low values of the capacitances. However, the input currents of the field-effect transistors, which are the leakage currents, are greatly dependent on temperature. With a change in the temperature by 100 �C, the level of the input currenta increases by two orders of magnitude and reaches tena of nanoamperes (Figure 4.7c). Moreover, op amps with FET's have large bias voltages ~up to 30...50 mV) and a large temperature drift (40 uV/�C). The factors enumerated above have forced op amp designers to seek out other way~ of improving amplifier performance. One can use transistors for which the current gain excaeds 5,000 to obtain a low value of the input current, i.e., so-called superbeta tranaistors [21, 25]. Transistors with an ultrahigh current gain are produced on the same chip where the conventional n-p-n transistors are located by means of supplemental emitter diffusion. However, the breakdown voltage:of:~hese transistors is reduced in this case. The combination of low voltage superbeta tranaistora~,~with conventional n-p-n transistors has made it possible to more efficiently produce operational amplifiers with better drift input characteristica (bipolar superbeta transistors have resulting drift parametera better than thoae of FET's in a wide range of temperaturea). - 233 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ` FOR OFFICIAL USE ONLY ~ Rt A2 aa As e a~ a ~K a~K ~K 4~K anK so yr~s ~ vr9 ~ yT(~ Vlr3 ~ Rll , ~ SO VT3 YDf q~ ~ t75 ~ ~ � fD t . ~ 50K ~ vtfd a vno vr~w . vr~ , ~ vr~ ~ ~ ~ (a),a~, Voltage ~o e Iin, amps ~ Ga3n, dB 40 40 . � ?D ~-tl . f, Hz ' T. . , �J....{~..L .~~~1 ~ - w' , ~J ,;rq � ~60 0 7A Op ~17 T~ (b) ~I 41 Figure 4.7. The 544UD1 operational amplifier. - a. Basic electrical schematic; b. Gain as a function of frequency; , c. The input currents as a function of temperature. 4.2.3. Amplifiers With Super-Beta Transietore The 140UD Amplifier. This amplifier (Figure 4.8a) is deaigned as a two-state amplifier. The first complex stage ~transistore VT1, VT4, VT10 and VT12) consist of a differential voltage follower (transistors VT1 and VT12), which controls the common emitter amplifier. To reduce the input currents of the operational amplifier, super-beta transistora VT1 and VT12 are used at the input. Transiators - 234 - ~ FOR OFFICIAL USE ONLY ~ APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500080030-5 FOR OFFICIAL USE ONLY VT4 and VT10 provide for a low collector-emitter voltage of the input transistors, as well as an almost zero voltage between the collector and the base of these transistors. Such a mode is neceasary for reliable operation of transistore VT1 and VT12 as well as to reduce the temperature drift of the inverse currents of their collector junections. The stable current generator (transistor VT7) seta the over- all current for the input stage, while transistora VT2 and VT11 control the emitter currents of input transistors VT1 and VT12, and thereby atabilize the value of the input currents. Transistors used as diodes are employed to increase the maximum differential voltage in both branches of the stage, where these transistorsl~h~ve a high break- down voltage. The increase in the differential input resistance ie accomplished by inserting R2 and'R7 in series with the diodea ~transistors VT3 and VT9), while resistors R4 and R9 are inserted in the emitter circuits of tranaistors VTS and VT8 to balance the bias voltage at the op amp output. R2 ~i! YT14 q14 R17 T SA7 4K 3,3K 1K VT7 y~,~ V717 . ~ R1l A13' ~ ~79 610 3K ~ - ~ 3ZID . V723 - i f/Tf ~V3 f,SK pe VIlt ~2 V11B V775 YT4 1,SK SOM ~ V7Q YI2f 3 Y 35 VT24 VTf6 ~M VT!? YTL 5 VTA rr~ Rf3 VT22 ! 66 ~f5 V~ s Al R4 RS R8 yrfd R1f~ R1d 7,5K frr 40K >K 7,aK 40M SO 4 ~1 /sl Figure 4,8. The 140UD6 operational am~lifier. a. Basic electrical achematic; - I~,NA I b. The input currents as a ~ in' ~ fim?ction of temperature. ~ T, �C �-60 -?0 0 YD 60 f~7 T, Z ' QI ~b) _ 235 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 ~ FOB OFFICIAL USE ONLY . . _ _ - f e ' . ~ IPf 174 R7 ~ ~T9 i'T8 v~4 V724 i~IXd YT28 . ~7Zf _ . vrs vrta am e vn vrr~ ~ . vrzo ~ ~ Z vra vr9 ~ a ~n r'n' ~ a2 as ~4 . vr~v ~ vre ~ ,va ~ ~ ~ an � . ~ a~ (a) . /Ax~N~ ~ . ~6 Ii~, nanoamperes ~ Pxa ~.9. pnepeueoee~a ycaneTenb Tnna . ~aoYA~4: ~ a - opeeqMn~ubx~~ ~euTD~~aK~e er�~~i ' 6- tl~NtMYOCT~ ~OAIIMx TOKO~ OT tlMOtp~T~� pli. e~ l~~11C~MOCT~ tO~NlplHt~ rC11JlCN~~ ~ � OT 4lCT0t61~ t ~~uo+~eTO~~~ x~pakrepscrrR~ ~ -~q! ?p o 2o d~ ' ~17 T,'C ; Ka~ Voltage Gain; dB '0 Degrees f~17 ' . . �45 ~ E ~ . , m f, Hz _ f, Hz . 0~ f ~ ~ a ` p` {,`4 Figure 4.9. The 14WD14 operational amplifier. a. Baeic electrical schematic; b. The input currenta as a function of temperature; c. The gain as a function of frequency; d. The phase-frequency reeponse. - 236 - FOR OFFICIAL USE ONLY . APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 The introduction of local negative feedback (resistors R3 and R8) increases the speed and at the same time the stability of the circuit. The d irect current mode i~ governed by the regulator which is designed around transistors VT13 and VT14. The second stage of the operational amplffer is a Darlington configuration (transistors VT16 and VT19). Tranaistor VT17, which biases the operating point of the output stage tranaistors in class B(through transiators VT18, VT20 and VT22). The output stage is designed around transistora VT22, VT27 and VT26. The overload protection circuitry uses transistora VT21, VT23, VT24 and VT25. It limits the short circuit output current to no mor.~;~than 25 mA. Transistor VT15 protects the output stage of the op amp againet flip-flop operation. The incorp- oration of internal frequency equalization in the second atage circuitry ~capacitor C1) reduces the phase ahift and provides for an amplitude-frequency response roll- off of 20 dB/oct up to the unity+~.gain frequency (1 MHa). The use of auper-beta transistors has made it possible to obtain low input currents (down to 30 nA), and what is most important, very good temperature stability of the input current (Figure 4.8b). The 140UD14 Amplifier. In contrast to the 140UD6 operational amplifier, super- beta transistors are used in all stagea in the 140UD14 op amp.(Figure 4.9a). The op amp is designed in a two stage configuration. Transistors VT3, VTS, VT7 and VT9 of the input atage are used in a cascode circuit. The bases of transiators � VT5 and VT7 are connected through series connected transistors VT1 and VT2 to the bases of tranaistors VT3 and VT9. Thanks to this configuration, the super-beta input transistor VT3 and VT9 operate with a collector-base voltage close to 0. To increase the bandwidth, resistora R2 and RS are inserted in the emitters of transistors of VT3 and VT9. Transistors VTS and VT7 have a large breakdowa voltage and protect the low voltage super-beta input tranaiators against breakdown. Moreover, the emitter junctions of transistors VT1 and VT2, which are inaerted between the basea of the input transistors in opposition to each other, protect the input atage against breakdown by large~differential input voltag~s. The stable current generator using trans- istor VT6 provides for a regulated supply current to the input stag~ and thereby also clamps the level of the input currents. The biae voltage at the base of the stable current generator of the input stage is supplied from a voltage regulator (transistors VT13 and VT15-VT17, as well as resiators R8-R12). In a manner similar to the regulator in the 153UD2 operational amplifier, this circuit pro- vides for constant bias throughout the entire range of supply voltages. The currents of transistors VT5 and VT7 are regulated by the input current difference regulator, where transistor VT11 (used as a diode) and transistor VT10 are employed. The circuit of the second stage (transistora VT18 and VT21), the current of which is regulated byr the DC level of the firat atage collector voltage provides not only for the transi~ion from the differential output of the second stage to the single input, but also for a high gain by virtue of the active load (transiatore VT19 used as a diode and VT20), as well a~ for a ehift in the DC level. Transistor VT22 seriea to supply bias to the output atages. - The output stage of the amplifier is designed around n-p-n tranaiator VT28 and p-n-p transistor VT29. The stag~ ia protected againat an output short circuit to ground or to the power supply. The us~e of super-beta transiators in the 140UD14 amplifier hsa made it possible to obtain an input current 1eve1 Iin of leas than ~ 237 - ' . FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 ~ FOR OF`FICiAL USE ONLY ~w a4 ~r ae art ~ ~ ~av aan ~av ~e~ ~ ~ vn~ t~re vrn � vra . q6 A20 4 4 ~ 24 t5 vr~a ~ yr~ vr~s ~ y~2a f?f 3 YT12 ' � YT13 . ' YT2 YT4 YTS Y7e TR7 7'1? yn~ VTf4 . l~1fr.! ~ q/~I Af4 ;7K 7k ~QK ~K J00 f1D fSK d � ~6 ~a~ s1 , , tU~,~ V ua~ i ~ ~ vff~ vr>e vrsA Nae _ . � At d~ In lx~~ t~T a+ 3 Ai . 4 39 IA In Cl CZ a01 'aIt 06 ~Ol (b) _v~~ a~ ~o 61, ; Xp,d'E? ICU ~ Voltage gain dB (in dB) ~ . , ~zo e~ . 40 ~ a . ~ ~ ~ 4 f, ,Hz D 6 60 ^ - '~a~ f0~ 1�' '~sf,~'~ . ~1 , ~e) Ol Pxc. 4.10. Onepaqxm~xwA ycxnxrenb TunA 153Y~b: C~ Nsuei ~i;~r R~-a'r B~Fd ~ F~ 0 11pNN1~N11N~116I1~A !AlKTpM9lCN~11 C7t!� Y~~ 6- CXlMS SIIOANAM KlCN~�a, A- ON ~OSN~11 CXlMB qACTOT110A KOppEKqNt, t~ ~ 10~ ~ ' � usxexwocr~. Kos~finuxexr~ yCMAlpNll pa� t 470 1000 - /OMKIIyT0~0 YCRANTl11A OT qeCT0T61, B- S~- /NCMMOCTb KOl~IaH4NlNTO yCNJIltIMfl OT ~S� ~ ~~0 60 ~O Ib~ erord, ~eweircoe o6pernoll CH13N e~ac� ~ ~0 S90 60000 40001 rornoA KoppeK4xx s peMnra 'wacwra6eoro ycNreren~ � 220 ' . Figure 4.10. The 153UD5 operational amplifier. a. Basic electrical schematic; b. Schematic of the input stage; c. Baeic frequency equalization circuit; d. Open loop~amplifier gain as a function of frequency; e. The gain as a funetion of frequency, feedback components and frequency equalization in a ecaling amplifier mode. r 238 - ' FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 1.5 nA throughout the entire temperature range (see Figure 4.9b). The amplitude- frequency response of the op amp is equalized by extemal equalization circuits (Figure 4.9c). 4.2.4. The 153UD5 High Precision Operational Amplifier The 153UD5 operational amplifier ~Figure 4.10a) belongs to the class of high precision op ampa used for the construction of instruments. Its specific featurea are a low zero bias voltage (0.5 mV), low levels of drift and noise and a high gain (more than 106). But the major propertj of this operational amplifier is the fact that it makes it possible to maintain a high value of the closed loop gain of the operational amplifier with a high degree of precision (for example, one can obtain KU = 1,000 + Q.3X). The apecific features of this parameter determine Che basic circuit of the operational amplifier and the technology for+its fabrication. The input stage of the op amp is designed in the usual differential configuration. However, input tranaistors VT1 and VT3 take the form of a parallel connection of two transistors ~Figure 4.lOb) to reduce the drift. The first stage is supplied wit'h current by the stable current generator ~transistor VT2) and is loaded into identical resistors R1 + R2 and R4 + R5. The redu~fion of the thermal effect from " the high power output transistor elements ie achieved by the apecial arrangement of the input stage. Transiators VT1 and VT3 occupy a large area on the chip (approx- imately one-third of it) and are positioned croaswise to each other. Op amp circuit designers have diapensed with the uae of an active load on the input stage ao as to reduce the zero bias voltage and th~ temperature dependence of the input characteristica. The increase in the input impedance of the second stage and the corresponding reduction of ita impact on the input characteriatics are achieved by deaigning the stage in a complex common collector--conmon emitter circuit configuration using tranaistore VT7, VT9 and VT13, VT15 which are well- matched with respect to their parameters. The stable current generators of the second stage (transistors VT10-VT12) provide for stability of the input aurrenta and a high resistance load for the second stage. By converting the differential output to a single input, the active load impedance of the second stage provides for a high gain. The third stage has an amplifying transiator VT20 (a common emitter atage) with a load in the form of a atable current generator ~transistor VT16). Transistors VT18 and VT19 shift the operating point of the output power transistors VT25 and VT26 to clase AB, which eliminates distortions in the output. Moreover, transi;s- tor VT19, which is used as an emitter follower, makes it possible to reduce the output impedance of the operational amplifier. The output current limiting in the case of a ahort circuit is provided by tranaiators VT23 and VT24, which prevent the overloading of transistors VT25 and VT26. Tranaistor VT23 limita the current _ consumption by the base of tranaistor VT26. The amplitude-frequency reaponae of the op amp is corrected by two frequency equalization networks ~Figure 4.lOc). The plot of KU as a function of frequency is shown in Figure 4.lOd for the open loop amplifier, while the amplitude-frequency reaponses of the op amp used as a scaling amplifier are shown in Figure 4.10e. - 239 - . FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080034-5 ~ FOR OFF[CIAL USE ONLY a - . _ --a- - ix ~ 2K - aK vna vr2s ~ eK ~y vrr~ ~ y� ' ~ TOw ~ p V M v~ ~ VT31 V732 q23 t i~+~ vn 8 ~ ZS s vno~ C2 4 yT,~p Q2k M py yr/g R ~s,r 33 ~ 2d SK VTd3 ' ~ VTl7 . ~~K ' Y735 fi ~x 2 - � T F'73~ Vt3s YTJ 2 f723I~T?A ~ YTJ4 ~r y~'~ ~ 1~T21 I737 VT ' ~71 J R5 , RA! ,Pf~ R2d 117~ ~ ~2N ~ � ~~8~ . . ct ~ Ra aK ~ s aw ' A4 SM k Q/ 2_ Out ex a~ oA~ M : 6K 6~,r In 6K 2" d aa?ar ~ + a Out~ ~ + s Out t C3 ~ ~ ~ ~ AZ R3 R7 fir 17K 27~r , +V ~ 27K 27x � Il? fl+l ~C) IJ ~ VCC Figure 4.11. The 140UD10 operational amplifier. a. Basic electrical schematic; b,c. Frequency equalization circuits used to reduce the settling time $nd to increase the output voltage slew rate respectively. 4.2.5. High Speed Operational Amplifiers The litaited operational epeed ia one of th e substantial drawbacks to atandard op amps. General purpose amplifiera with equalization down to the unity gain level have a amall signal bandwidth of about 1 MHz and an output voltage slew rate of up to approxi.mately 0.6 V/uaec. But this drawback can be overcome if a high -240- FOR OFF[CiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 frequency channel is incorporated in the op amp circuitry. There exist many methods of designing the high frequency channel, which are basically distinguished by the circuit configurations of the equalizing networks and the types of amplifier stages employed [5]. Although semiconductor op amps also possess low parasitic capacitances, tihey nonethelesa cannot have a fast response without taking special _ steps, since one of the amplifier stages should be designed around an integrated circuit p-n-p transistor. The 140UD10 high speed operational amplifier ~Figure 4.lla) has an output voltage alew rate of 50 V/uaec and a unity gain frequencq of 15 MHz . The good frequency parameters of the op amp were achieved as a result of using a _ high frequency channel in the circuit, through which the high frequency components "bypass" the slow p-n-p transistor. Moreover, by virtue of a unique circuit design, the op amp is distinguiahed by h~gh stability of the parameters throughout the entire range of supply voltages. of +5 �16 volts. This op amp is deaigned in a three stage configuration. To increase the input impedance, the first differential stage uses a Darlington configuration (traneistors VTB, VT10, VT20 and VT19). To extend the gain bandwidth, resistors R7 and R13 are inserted in the emitters of fts amplifying transistors. The input stage is powered fram the stable current gener- ator (transistor VT13), The current fram tranaistor VT13 is fed to a special distribution circuit, which is designed arourid transistor VT17, dual emitter trans- istor VT12 and resistorsR8-R10. Transistor VT12 is inverted and provides "make-up" current fc~r the emitters of the input transistors. This distribution circuitry provides for little change in the input stage currents throughout the entire temperatttre range. The circuit for protecting the input stage against a high in-phase voltage is designed around transistors VT14 and VT16, while transistors VT1, VT2, VT4 and VT5 protect the input stage against differ- ential signal overloading. Transistors VT11 and VT18 play the part of an active load on the input s~age. Transistor VT15 (uaed as a diode) limits the level of the collectar-base voltage of these tranaistors. The second stage of the amplifier ia also deaigned in a differential circuit con- figuration.(p-n-p transistors VT21 and VT24). Transistors VT22 and VT25 serve as active loads for the second stage. The direct current mode of the atage is set by biasing transistora VT21 and VT22 with the regulated collector voltage of the input stage. The third amplification atage uses tranaistors VT27, VT34 and VT30, VT3.1, the load for which is the stable cu-rent generator uaing transistor VT29, the current in which is atabilized by the voltage, drop across the diode formed by the connection of the second collector of the tranaiator to its base. The output stage is designed around the dual emitter n-p-n transiator VT38 and the p-n-p transistor VT39. The second emitter of tranaistor VT38 serves to control the output p-n-p transistor. Such a circuit increases the speed of the p-n-p output transistor~ Transistors VT32, VT33 and VT38 protect the output stage of the op amp against over load when the output is ahort-circuited. Transistor VT33 protects the circuitry of the operational amplifier againat flip-flop operations, and at the instant of overload- ing, shunts tranaistor VT39. -241- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPR~VED F~R RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY There are three capacitors~~.in the op amp circiutry to i.mprove the transmission of high frequencies. Capacitor C1, which shunts one half of the differential input stage for high frequencies thereby convert~ its differential output t~ a single ended output. Furthermore, the high frequency signal bypasses the second differ- ential stage which is designed around low speed p-n-p transistors through capacitor C2. The high frequency signal component is fed from the output of the first stage directly to the base of the third stage transistor. Capacitor C3 (6 pFd) serves . to transmit a certain percentage of the high frequency components of the eignal from the output of the first atage to the input of the final (output) stage. High speed amplifiers are less stable than low frequency op amps, and for thia reason, to prevent oscillation in the circuitry, it is necessary to have parasitic capacitance between the op amp output and its inverting input. To reduce the indicated parasitic capacitance, special external equalization circuits are employed (Figures 4.llb and c), the composition of which depends on the task which the operational amplifier performs. The balancing of the amplifier is accomplished by inserting a variable resistor between leads 1 and 5. 4.2.6. Micro,power Operational Amplif iers Operational amplifiers are needed for applications in economical equipment, wh ich operates especially in a standby mode (frequently with battery power), which con- sume little power from the power aupplies. The 153UD4 op amp ~Figure 4.12a) has a current consumption of 0.8 ma for power supply voltages of Ui,p, [V~~] �+6 volts. The gain of the op amp in this mode is higher than 5,000. This op amp is desinged in a two stage circuit configuration. The firat simple differential stage (tran- sistors VT1 and VT5) drives an active".load (transistors VT2 and VT4) and is powered from a stable current generator, which is transistor VT3. The second stage is designed as a common emitter-cammon collector circuit (transistors VT18 and VT15). The collector circuits of transistors VT12 and VT14 serve as the loads on the second stage. The output stage is designed around n-p-n transistor VT19 and the composite [2, 5] p-n-p transistor VT17 and VT20. The operating point of the output transistors ia biased by transistors VT13 and VT16. Resistors R10 and R11 serve to protect the op againat output sliort circuits. The direct current operating mode of the first and second stages of the op amp is assured in the case of wide var iations in the supply voltages by a regulator circuit designed around transistors VT6-VT10. Two frequency equalization networks are needed for complete carrection of the amplitude-frequency response of this operational amplifier.(Figure 4.12b). The 140UD12 operational amplif ier is available ab the present time (Figure 4.13). This type of op amp can be used as the micropower amplif ier and as a general purpose operational amplifier. The amplifier is designed for operation in a wide range of supply voltages of +1.2 volts to +18 volts and is designed in a two stage circuit configuration. The amplitude-frequency reaponse is equalized with a single - 242 - � FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ern~ n~ i72 Q3 Rd . f74. V79 ` ~ R1 ~ ~TQ ~ Rf0 2 ~ Y d~! ~p atl V7i~i . ~ ~1f7 . ~ ~ ~ ~ � ~4 . . 4 � p~ yT'J R5 q7 pd 4(~'1 ' (8~ d! 1 ~ fe0 ~t . . - In 1 ~ t - A' ~ . , In 2 T r _ . l72 . sir -V +~r~ -a~ CC , + v~~ s~ b ~ Figure 4.12. The 153UD4 operational amplifier. a. Basic electrical achematic (the numbering of the pins of the 153UD4 op amp is given in parentheaes and the numbera Qutside the parenthesea apply to the 710UD1 unencapsulated;; ~ b. The frequency equalization circuit. ~ internal capacitor. Protection of the output stage against overloads is provided as we11 as protection against flip-flop operation. The major difference between this amplifier and other types of op amps is'the fact that the operating mode of the internal stabilizer-regulator, which determines the entire DC operation of the op amp, is specified from the outaide. By setting the bias current of the atabilizer-regulator, one can vary the op amp parametere from micropc4wer levela up to psrametese characteristic of general purpose operational amplifiera. � - 243 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000540080034-5 FOR OFFICIAL USE ONLY _ YT2 YTB ~ VTlf V~f VTf4 VTn V723 ~ d YT~ ~ R3 V~2f ~ ~77 3 ~ 2K C1 f00 6 Z VT3 vr>a ~ YT5 ~ v�5 A6 YT4 ~Tf9 ~ vr~2 VT6 . ~ y~p YT22 YT16 ~ A~ ~72 B7f~0 ~7.24 fOK fOK Y~p 4 ~a~~ W ' vCC VMd ' Ura ' . + + . . 2 - ~ A> e ~ 2 _ ~ A> . . Wxt ~ 3 ~ ~ B , ? d ~ (hxt d d i 4 a' . , vii ~ f00K - ~Q ~ ~1 ~1?~ ~ ; Ql. ~C~ ~ � ~ . . U a~n Vcc t ~ 1 2 ~ + . - Af 6 ~bax jj - Af 6 UErut ~6xi 3+ 8 Out ~Z 3+ 5 U + YTf ' k out UN~ . ' Rf a2 ~Mn _ Rf pt f00K " _VC~ ~d~ a1 mD~ v~ e Figure 4.13. Basic electrical schematic ~a) and the circuits for ~ supplying bias current to the 140UD12 operational amplifier (b-e). Circuits which illustrate the methods of setting the current of the stabilizer- regulator are shown in Figure 4.13c-e. The parametera of Che op amp for va~ious bias currents are given in Table 4.3. ' ~ 244 - FOR OFFICIAL USE (1NLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080030-5 FOR OFFICIAL USE ONLY , TABLE 4.3 Electrical Parameters of the 140UD12 Operational Amplifier Vp~=+3V V+-p~,n=+3V Vp~=15V Vp~=15V Ibias a 1..'i uA Ibias = 1.5 uA Ibias = 1.5 ~A Ibias S 15 uA Parameter . . . . . Zero bias voltage, USm [VO bias~~ my 5�Q 5.0 5.0 5.0 Bias voltage drift, ~ ~Usm/~T, uV/�C 3 - - - - Input currenta, Iin, nA 7.5 750 7.5 50 Input current difference, ' ~Iin~ ~ 3 15 3 15 Drift in the input current difference, ~AIin/~T, nA/�C - - - ~ Voltage gain, KU 50 50 200 100 Comnon mode rejection ratio, . - ' Kos sf~ dB 70 70 70 70 Output voltage slew rate, ~U out~ ~/usec 0.03 0.035 0.1 0.8 Settling time, t8et, usec 3 0.6 1.6 0.35 Input resistance, Rin, MOhms 50 5 50 5 - Output resistance, Raut, ohms 5� 103 1� 103 5� 103 1� 103 Maximum output curent, 2.g 5 2 10 Iout~ ~ Maximum output voltage, Uout~ volts 2 2.1 10 10 Maximum input voltage, lp 10 '~in volts 1 1 � Maximum in-phase input voltage, Uin ph~ volts 1.2 1�2 12 12 Current consumption, Icon1~ 25 125 30 '170 The presence of internal frequency equalization, the absence of flip-flop operation, the flipping of the inputs as well as protection againat output shor"t-circuita permits the wide utili.zation of this operational amplifier in various circuit con- figurations. . = 245 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY 4.3. Integrated Circuit Comparatora The necessity arises in a number of cases of converting analog signals to digital form. For this, among others, special devices called comparators are used, which are specialized operational amplifiers with a differential input and a single or paraphase digital output [7, 8]. The input stage of a comparator is designed on analogy with op amp circuits and operates in a linear mode, A"1" signal is gener- ated at the comparator output ~f the difference between the input signals is less than the comparator actuation voltage, or a"0" signal is generated if the differ- ence between the input signals exceeds the comparator actuation voltage. The ~ signal being atudied is fed to one input of the comparator while a reference voltage is applied to the other. _ A comparator may be used as a threshold gate in automation circuits to quantize a signal in high speed analog to digital converters. It can be used in self-excited oscillators, in pulse amplitude discriminators and peak detectors, as well as a read amplifier for magnetic and semiconductor memory signals. The major parameters of a comparator are: the sensitivity (the precision with which the comparator can differentiate the input and reference signals), speed (reponse, deter~nined by the actuation delay and signal rise time), fan-out load capacity (load (capability of the comparator ofi controlling a certain number of digital IC inputs). We shall consider the circuits of'-the most widespread integrated circuit comparatore, the parameters of which are given in Table 4.4 [9, 10], A comparator based on the 521SA2 integrated circuit (Figure 4.14) has two differ- ential amplifier circuits, an output emitter follower, zener diode~level shift circuits and a circuit for limiting the output signal ffinplitude. The differential input stage (transistors VT1 and VT4) have the usual low zero bias voltage for integrated circuit op amps. The emitrers of tranaistors VT1 and VT4 are powered from a stable current generator (transistor VT5), because of which the collector currents of the first stage transistors are almost independen�t of an in-phase input signal. The second differential stage ~transistors VT3 and VT6) have as their basis a balanced bias supply circuit. In the balanced state, the voltage of the single - output of this stage does not change w ith fluctuations in the positive aupply voltage. The base potential of transistor VT2 is thereby clamped (with an increase - in the positive supply voltage, the collector currents of transistors VT6 and VT3 - also increase, with the collector voltage of transistor VT3 remaining constant). To increase the current fan-out load capability, transistor VT6 is equipped with an emitter follower ~transiator VT8), The integrated circuit zener diode VI71, which is inserted in the emitter circuits of the second stage traneistors, has a reference voltage of +6,2 volts, which clamps the potentials without transiators VT3 and VT6 at a level of about +6.9 volta. Consequently, the permissible signal for the camparator inputs can approach 7 volts. Zener diode VD2, which is inserted in the output emitter follower circuit, ehifta the output signal level "downward" by 6.2 wolta, so as to make it compatible with -246~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY the input signals for digital TTL integrated circuita. Transistor VT9 isolates the output circuit from the bias circuit of the output stage current gen~rator (transistor VT5) with a campensating diode (transistor VT10 is used as a diode). Transietor VT7 (used as a diode) limits the peak-to-peak value of the output aignal on the positive side: for signal levels at the output greater than +4 volts, transistor VT7 turns on and shorts the differential output of the second atage. Because of the limiting of the amplitude, the apeed of the comparator is increased significantly. TABLE 4.4 Parameters of Integrated Circuit Comparators _~e of Comparator and Perameter Normal Value Parameter 525.6A1 521SA2 521SA3* Current consumption, I~an, mA: From a positive, power supply 13.5 10 6.0 From a negative power. supply ~.6.5 8.9 ' S.0 Zero bias voltage, UBm, mV 3.5 5.0 3.0 Common mode rejection ratio, CMZtR, dB 70 70 - Average input current, Iin, uA 75 75 0.1 Input current difference, Alin, uA 10 10 0.01 . Voltage gain KU 75 � 103 75 � 103 200 � 103 The "1" voltage, volts 2.5 to 6.0 2.4 to 4.0 - The "0" voltage volts =1.0~-to 0 -1.0 to 0 - The "0" output current, mA 0.5 1.6 - The turn-on delay time, tdel~ nsec 135 160 200 Input voltage, gaCing, Uin, gate, volts -1.0 to 0 - - Gating current, Iggte mA 2�5 ' - * Operating with a single +5 volt power supply The 5213A2 comparator is simple to.use, but doea not have any gating inputs.. In a dual differential comparator circuit with the 521SA1 ~Figure 4.15a), the outputs of two individual comparators are combined using emitter followers with OR logic. One co~on level shift diode and bias di~rider is used fot~.�.both camparators. The application of the dual channel design makea it poasible to realize a higher level of integration, as well as improve the electrical parameters of equipment, - 247 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080030-5 FOR OFFICIAL USE ONLY ~ ~e-� u~, voi~s N3 d � A,tp ' . ~T2 qZ ~ ' 40 , QO fT0 7~0 f,~c ~t~r . ~ ~ . ' ~or~~ Ubj-YO~o7 U~~2~ my A~ ~ . 750 f P � ~ , !?J ~ ~ . . ~ ~ ' ~ � d0 xY0 ~ t,~?~ 2 y~{~ ' ~ ~t0 v~ r '~0 . d . 4 (b) vn . � . , ~ vou~' v ~ ~ . ~ c~-zon�~ 2tiQ "~ypa ~ ;yit � ~ !?6 ~iD � ~ � !'T~0 ' p' yp~ ~ ~ ~ � d , ,nn e4 * . ~ ~ ~ ~a) ~ ~ , ~ to) ' ~ ~ , Figure 4.14. The 521SA2 comparator. a. Basic electrical schematic; b,c.. The rise tune Uout gs a function of 'l, the input voltage over-regulation and the load capacitance respectively. especially devices for reading magnetic memory signals. Because of the identical nature.of the parameters of both comparators, it is posaible to design dual thresh- old circuits, having a aymmetrical respoase to postive and negative values exceed- ing the absolute signal level over the threahold level. Comparators using the 521SA1 integrated circuit, in contrast to the 521SA2 device, have two gating inputs, as well as a parallel.�circuit configurati,on for the limit- ing networks for the output atage saturation level (transistor VT2 ie added in the second stage to reduce the peak to peak value of the eignal at the base of transistor VT7 when it is saturated). A dual comparator performs almost the same electrical function as two of the above mentioned single comparators, however, the power conaumption of this IC is only 50% greater. The basic circuit configuration for a type 521SA1 comparator is shown in Figure 4.15b. The.neference voltage is fed to one of the inputa, while the input signal is fed to the other. In the case where the input aignal exceeds the - 248 - FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 F~ , 2 VD2 VB5 . IP9 ~ t7f3� 1Z A2 ~ K � i,3K . YT2 4,3K 4~JN ~ ~ VT17 . p4 Rf0 . V7e VTl1 ~q . ~0 yy~ ~ VT/1 VTir gp . � � i?T YT9 17J VTq ~ . ~ , YH i91 YD4 i?fd ~ s . VTS . . 'R7' d . � 6 . 505K Vll! v~ . . ~ ' � VTJO p3 ' RA ~P1i f?0 '240 ~ 120 � ~ ' � Uou~~ 'Yal~s U~~~,Qs~dYY ' ~ ~ ~ e~-roMe ~ , Uqate + - - U~ ~ +~G~, ' ~o f . 1 o ta an x~v tae t,~. � , ~arf 6- Output to nsec ' ~bnr 6 + ~tl. EM~-" ' ~ Ulxi a- ~ � ~/u~n6 , vi.A~ V��lt~ ywt 7 ~rp � lGI~ Uref 2 a0 � t, nsec ~ e z -D~. a.~ c' ,n~r f4o R+~ . . g ~ ~ Ibl ~ `�P"t , U . F~gure 4.15. The 521SA1 dual comparator. a. Basic electrical schematic; b. External circuit configuration; c.~0utput voltage riae times ae a function of the input signal overregulation voltage levele. reference voltage, the output voltage switches to the poaitive or negative state (F igure 4.15c ) . The comparator configuration coneidered here can be uaed as a voltage comparator in analog-code converters, where one input is controlled by the analog aignal and the other is controlled by a reference aignal fed from a step resistive matrix. The circuit can also be uaed for a film or disk magnetic memory as read.amplifier. - 249 - ~ FOR OFF'IC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY Uga~e ~ Thresho~Id gates which are indicators o~+"'~-7 - n z of an output voltage relative to present - v~n 1 6 ' ' ~ precise limits form a special group of wn A2 ~~x circuits for comparator applications ~Figure 4.16). ~ Up,~ g out ~ ~�xZ N8 ~ P~' 4.4. Integrated Circuit Analog _ Multipliers Analog integrated circuit multipliers Figure 4.16. A threshold gate designed 8~e des igned to perform the oper- around the 521SA1 dual ation of mult iplying two analog quanti- tiea. They can be used in frequency comparator. doubler, phas e detector, and balanced ~ modulator circuits, as well as in automatic control ayatems as multipliers and squaring circuits. In cnnjunction with operational amplifiera, analog IC multipliers can perform division, extract roots and perform trigonometric functions. The existing types of analog multipliers can be broken down into two groups: ba}.anced modulators intended for operation in a wide frequency bandwidth (40 MHz and more) with small input signal levels ~up to 0.5 nol ts) and analog multipliers . themselves, which are intended for operation in a.narrow band of frequenciea with high level input signals ~up to +10 volts). The electr ical parameters of the 526PS1 balanced modulator circuit (Figure 4.17) are given in Table 4.5. The main assembly of the 526PS1 integrated circuit is a cross coupled quad differ- ential amplifier ~transistors VT1, VT4, VT5 and VT8). In terms of its action, it is similar to a co~on emitter amplifier, but its;.emitt er currenta do not depend on the input voltages. It is not difficult to note that the difference between the output currents of the amplifier (being the output quantity) is proportional not only to the input voltage of the amplifier (it is fed to input X, pin 10), but also to the difference between the emitter currents: AIout a f~Uin, ~I~). The emitter currents can be regulated by feeding a voltage to the bases of trans- istors VT2 and VT7 ~this voltage is fed to the Y input, pin 11) with pins 2 and 12 shorted together. The tranafer function of a balanced modulator is a function of the voltagea fed to the X and Y inputs, and has the form [11]: ~Iout n~sw:= (~o/~) [th Nr /2Rr1 x~th (Uxl2~r1) ~ 250 ' FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFF[CIAL USE ONLY If identical load resistors RA are connected to pins 8 and 9, then the output signal can be obta mned in the form of the voltage difference: U = uswz ~ AIRe ~ 4 R~ ~~h Nrl~~r);h (~x1.2~~ )1 (4 . i ) out An internal regulator (diodes VD1 VD5 and resistor R9) provide for stable DC operation of the circuit and set the bais for transistora VT3 and VT6, maintaining the emitter current constant for the quad amplifier. One can conclude from formula (4.1) that the output voltage ia a nonlinear function of the input potentials, however, at small values of the input voltages, the circuit operates as a~.linear signal multiplier, having the follawing transfer function: U.~: ~ Re/8~}) Ux Uy. The linearity condition for each of the inputs can be written in the iorm: ~ [U.x-lh (U.=1~r11/U,= < 8 where d is the permissible nonlinearity of the amplitude responae of the multiplier. The value of the hyperbolic tangent can be represented in the form of a series [12]: th -V~'-~--~ 1 f( U's 1'.F? ? r U~s 1~ r r a � . The values of the input voltages are given in Table 4.6 as a function of the coefficient d and the temperature. The linear range for the Y input can be expanded i~ a resistor Ry ia inserted between pins 2 and 12. Then the input current difference will be determined by the equation: e/ e Uyl(~~~+RY~~ ~4.2) where re is the resistance of the emitter-base junction. If Ry �(re m~T/Ie), then the value of re may be disregarded; then formula (4.2) is simplified: . . _ et ~ '2Uy/Ry~ ~LF. 3) and expreasion (4.1) will have the form: , - 251 - FOR OFF'iCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY �out � ~sd:-(~v RalRY) [~h (~xl~~r)1� But in this case, the linear input voltage will be limited by the direct current mode (which is set by the internal regulator) to a~evel of approximately 0.5 volts. A schematic for the use of the 526PS1 integrated circuit :.as a dual balanced mixer is shown in Figure 4.18. Since a dual balanced mixer uaually operatea with a low input signal level ~input Y) and a high reference signal level (input X), its transfer function:~can be written in the form: . U Uew: _ (~o Ra Url4~r) Ith C~xI2~r~) ~ . . _ ~ out - where Uy < ~T . ~ ' . ,v5 ae a vr~ vr4 vr~ rna ~ s~ ~ Q~ VDf ~ Sd0 YD2 ',n Rd fK ~ V12 . ri7 ~ . aM VDa A'4 1x ~D4 ~a ~0 VD6 d . R8 Rf R2 � e0pr ~ . 1d0 f10 ~ ~ ' ~ � . , Figure 4.17. Basic electrical schematic of the 526PS1 balanced modulator. In the case of harmonic input (input Y) and heterodyne (input X) signals, the ~ harmonyce nwp � mwl are present i~ the speCtrumrof Che output signal~of.an ideal twin:balaneed miacer. Limiting.ourselve~ to the dif�e~enee frequency output voltage ~w0 - W1~~ We can write the transfer function of a dual balanced mixer as: - � Unw: p=(1o Rn VY~BI8~1'~ . ~4. 4) ~ , . - 252 - ~ ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY TABLE 4.~ Parameters of Integrated Circuit Multipliers. Parameter ~ ~ 140MA1~ 526PS1 525PS1 Input control signal suppressioa factor, Rin c~ dB 46 8 46 Reference sigaal suppression factor, Rin ref~ dB 46 65 46 The dynamic control signal voltage range, D, dB 16 - - Control aignal gain, KU 2.9 - - Upper cutoff frequency, fup, MAz 2 40 1 Input impedance, Rin, MOhms - 0.050 20 Output impedance, Rout, ohms - - 30 Comierter transconductance, S, A/V - 5 - Multiplication linearity, percent - - 1 Supply voltage, Up~., V +12 +6 +15 Permissible input voltage, Uin, volts ~+5 - +10 , - Power dissipation, Pd18, mW 250 36 170 TABLE 4.6 Range of Permiasible Input Volta~es ~IJ V~= ~2~ 8~nwe~ (/K ~ Ws~r~o~ ~up~~. �0 a ~ or -e0 � +ss I +~o I +isd 1 ' 0.34 8~1 8.7 9.8 11~7 6 0,8 . 14.1 2Q.8 23 71~a ' 1,18 21 30 33~3 ~ ~0 � 18 1~48 ~6.7 38 42~8 ~ ~ 1~78 32 46~6 61 . . Key: 1. Uin/~T: 2. Valuea of Uin for various tempetatures, �C. where B is the dependence on the reference eignal level (the cali~iration ratio). One may assume for a low level reference aignal that B~(Up/2~T)Up = Ug, and therefore formula ~4.4) haa the form: ~.yx p's RM/18~~1 Ux Ur. ; / _ 253 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ~ FOR OFFiCIAL USE ONLY ' ' Rf ~ R2 ~ C8 UN n UP~ . tx . fk . ' o~ ~ ~x ~ Uin reg ~ . _Ve+r on , Cf 8 8 � ~ G3 ' . . Otit 2 ' 6 Af 3 ~ . ~bx~ Z ~ V U~n e~g.o,> y Z s>>.. ~ a' . ~ . ~ ~ . . 9,! Figure 4.18. Circuit c nfiguration of the 526PS1 integrated circuit used as a~dual balanced mixer. With an increase in the voltage at the reference input, the funct~,on becomes non- linear ~Figure 4.19a). The conversion gain, which is defined as the ratio of the intermediate frequency input [sic] voltage to the signal input voltage (Figure 4.19b) is measured in decibels: KI~, = 20 10$ ~U011t r~Uin 8~" a K~D � 20 Ig (Ueet= P~Ues o) ~ In the 140MA1 balanced modulator ~Figure 420a), the main multiplication circuitry is designed around transistors VT6, VT9, VT11 and VT14:~ The differential amplifier (transistors VTS, VT8 and VT12, VT15) controls the multiplier emitter currenta. The multiplier emitter current difference is made to he a linear function of:the input voltage at the Y input by inserting resistor Ry between the emitters of the differential amplif ier (pins 4 and 10). The current levels in the emitters of the quad of amplifier transistors ~VT6, VT9, VT11 and VT14 is regulated by the voltage at the Y input, and since the level of the currents flowing through the stable current g~nerators ~tranaiators VT7 and VT13) is atable, the difference in these currents is determined uaing formula (4.3). ~The linear input voltage range of up to + 5 volta is achieved by virtue of the high supply voltage of +12 volts. A Darlington circuit ~transiatora VTS, VT8,~~VT12 and VT15) is used to increase the Y input impedance. To increase the X input impedance, a differential stage ia inserted in the modulator circuit, whe~e this stage is designed as a com~on emitter configuration. This atage controls the~basea of the multiplier. Working fram the fact that the Y input is linear, while the input differential amplifier has the gain of [T+], the tranafer function of the modulator can t~e written in the form: . . _ ~ ~�y: � ~~1Rr) ~r ~ ~~xl~ry (4.5) , / ; - 254 ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY where Uy 2,~e R! R4 ~Z , 3 f' ~ A2 ~,a. . R5 ~ l4 ~ p f~~ S qZ ~ R/E ~ 4 y 315/1C/ 13 " -n,ee R3 ~ f4 , z~ . ,u~ . ' . Figure 4.23. Schemat,ic of a leve3. shifting an$/J.og multiplier using a 140UD7 op amp powered by a+15 volt power sup~ly. , 259 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 : FOR OFF[CIAL USE ONLY ~ A~ The ~current level Ip, on the level of X 'X ' which the entire DC operation of the circuit depends, is normalized by RZ ~Z means of resiatars~~.inserted ~ietween z~ ~ _ X ' pins 3 and 13 to ground. In this case, + the current flowing throt~gh diodea VDl ' Ra and VD2 can be determined from the , ' expression: , . n_......�....... _ . Figure 4.24. Block diagram of a R= Z/y. Id ~ Ip ~~Up~, - Ud)/500 + R voltage divider. t4.6) where ?;R is the nominal value of the resistorsiin ohms. ~ ~oe ~E" R4 AB ~7 qy Rfs At � ' 5K dK SK SAr dir ~ +~e ~ ~ ~2 s ~ 3 a~, - A~v~ s~o . A3 1fOHAi � ~ ~ ~ ~ Q~ . g ff 8~ fS 47D ~ f1JK 2K b~ A7 ~P7 1 � = qld K . . L ~6K . -12,60 rg~ qm S~6,r � . , r � al. , . _ . . Figure 4.25. &chematic of a voltage ~ divider based oa the 140MA1 integrated ~~x~~ circuit (a) and its trana- ~ ~er functions.,~b). a ~ a t o,a ~o ~s ~o y~e ~ 61 - 260 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR Ob'FICIAL USE ONLY . ~ R1 R � ~ ~ t ' d2K a~1~ ~r 2M ~r ~aK U~ g s . 'Af J 2 ~ ~ Ur ~ P - ~ , ' Q2 rP3 � . ~ f~6M f~6K e ' . . Figure 4.26. Simultaneous multiplication and divieion circuit based on the 525PS1~ integrated circuit. The configuration of the 525PS1 integrated circuit as an analog multiplier (Figure 4.22b) makes four quadrant multiplication possible for input analog " signals having a level of up to +10 volts with an amplitude of the output signal of +10 volts. Thus, the scaling factor of the circuit ia 0.1. In order to obtain a greater�output voltage amplitude, the circuit should operate from a positive supply of +32 volts. In this case, the output voltage of the multiplier circuit in the no-signal mode is 21 volts. In order to bring this voltage to the zero level, it is neceasary to add a bias circuit. In the analog mu~tiplier which is equipped with a level bias circuit, designed around the 140UD7 op amp (Figure 4.23), in order to match the DC l~vel at the multiplier output to the permissible input voltages-of the op amp, a divider with a division ratio bf 1i~10 is inserted batween them. A level shifting four quadrant multiplier with an output voltage of +10 volta can also be obtained without using an additional +32 volt power supply. In the circuit shown in Figure 4.23, th e multiplier operates fram a power supply with voltages~of +15 volts. In this circuit, the scaling factor of the~multiplier, K, is deduced by 10 times by virtue of the reductioa in the load reaistance, while the op amp, in turn, is used as a scaling amplifier~~arfth a gain of R= 10. _ As was atate3 above, various functiona can be modeled uaing analog ffiultipliers. We shall a consider a few examples from this area. A squaring operation can be realized, if a voltage U ie fed to the .R and Y inputs, which are connected together in the baeic circuit configuration. Then the output voltage can be determined from the formula Uout �~2, where U- UX ~ = Uy and the ecaling factor is: . a K 2Rload IORRRY . / . ; - i ~ -267,- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 I~'OR OFFIC[AL USE ONLY The division of two signals is accomplished by the circuit depicted in Figure 4.24 in which the multiplier is used as a negative feedbaek element for an operational amplifier. In this circuit, the op amp will strive to maintain.ground potential at ite iuverting input. Assuming tbat the input curreat of the op amp, IiA, is close to z~ro, we find tha tran~fer furction of the circuit: : K Ux Uy / R, Uz / Q= From which Ug R1/~IQt2)~UZ/UY). If we choose R1 ~~2~ then Ug =-~UZ/Uy). In the voltage divider designed around the 140MA1 integrated circuit (Figure 4.25), the two analog multiplier inputs are tied together; then the output voltage of the op amp will be equal to: NzlRt) a (KU~C/R~)~ ~YA~� . uX ~ -~t)I t~) ~ Consequently, this circuit generatea the square root function of the input sigaal. In all of the circuits treated above, the analog multiplier is used with a level shift circuit. It is poseible to construct a frequency doubler based on an analog multiplier. ~ For this, it is necessary to connect a high pass filter to the output of the analog multiplier. The operational principle of su~h a cirauit ie based on the trigonometric identity: (cos ool~ a 1/2 (1 -k oo~ 2m~. ! - The high pass filter does not pass paraaitic low frequency signals at the output. We will note that based on an analog converter, it is not difficult to design a - device, the output voltage of which ia proporticnal to the ratio of tt~e product of two analog quantities to a third component: = R(U U )/U , Uout R Y Z where UZ is the voltage which regulatea the level of the current Ip [see formula (4.6)]. A circuit for the simultaneous multiplication and division of signals designed around the 252PS1 analog converter ie ehown in Figure 4.26. 'The value of Ip is determined from the expression: ID ~ (UZ - Up~ - Ueb)/(R3 + 500). . / . - 262 - � � FOR OFFICIA~. USE OTiI.Y APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY Some applications of analog converters can be based on the fact that there is the capability of varying the resistances Rg and Ry in a linear fashion. ~ 4.5. Analog Integrated Circuits for Rad~o Receiving Equipment The integrated circuit camponent base ie being widely introduce i.nto modern communications equipment. The t~chnological etate of the art makes it possible to create a products list of analog IC's, which provide for the construction of practically all of the assemblies of--~adio receiving equipment. For example, the K242 series of integrated circuits, fabricated using thick film technology, can be - used at frequenEies of up 110 MHz. They are used to construct the channels of color television sets [15, 1"6] as well as other radio receiving equipment. The 235 series integrated circuits are designed for operation at frequencies of up to 200 MHz and have good aoiae parametera, referenced'~to the bandwidth (Un = 0.01 0.8 uV). Semiconductor integr~ted circuits are beiag widely introduced at the . present time. e uM~ s c~ t~ H a. 2 d R. 1P5~~~+ 3~r 3n ~ T L3 Eb~x 9 R3 ~ ~ . B ?x ~ ~ ~ r ~ . 1f A1 C4 6 Dx 1 4 4 � 4~ 2 f,fir Y72 V74 : ~ ~ s a s ~ . ~ . i4f 4q~ ~V7 0,01 6K ~K Y7J ' ' f3~3' 1} ~J ,PQ Rf0 ~ ~ . f W . Figure 4.27. The 175W4 high frequency amplifier. a. Basic electrical schematic; b.~Circuit configuration; C4, L2 and L3 are chosen from the calculation of the requisite frequency. ' 4.5.1. The Differential Amplifier Differential amplifiers were developed in the initial stages of semiconductor integrated circuit design. These amplifiers are universal and can be used in all assemblies of receiving and amplifying equipment. Only a qualitative improvement in them is underway at the preaent�zime: the expanaion of the frequency range, the reduction of the noise and powCt co~aumption and the increasing of the output power. ~ ~ , -263- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080034-5 FOR OFFICIAL USE ONLY an ~ g ~ 2~~a a a e~a .H ~ ~ ~ + a> ~ . vn vra ?T4 ~ e s a ~ QZ ~ ~ ~ ~ _ ~ Af rQK' R7 ~ ~ R> ~ ~74 ~ , . ~ ~ 1 f3 ~ d * J. yr~ ~ . . at q~ :K . ' ~ ~ ~ ' ' ~ , , Figure 4.28. The 175W2 high frequency amplifier. a. Basic electrical eehematic; b. Circuit configuration when used se a video amplifier. , ~ a2 f2K, R2 ~ ~ Lt . ~ f2~~oar' .at ~ Ai + rn v~a kb +v,w, ~ ~ ~ , 74 6 R4 Lf /d � , Cj , Rf q~, ~ ~ 7eOM1f ~ ~ A6 ~ Al ' ~ . ~ Y7f ~73 , Q~ B ~ Y ~ x ~ ~~r . ~ ~ ~ir A . , Figure 4.29. The R175US2 high frequency amplifier. a a. Basic electrical echematic; b. Circuit configuration. The simplest differential circuit with a stable current generator and a biae circuit is widely uaed in all stagee of a receiving and amplifying channel: the RF amplifier, mixers, local oscillatora, limiters, variable and fixed gain IF amplifier stages as ~rell as AM and FM detectora. The 175W4 integrated circuit (Figure 4.27) with a paesband of:.~50 MHz can serve as an example of a differen-~, tial amplifier. The direct current mode of the amplifier is eet by the bias of traneiator VT1 (by means of negative feedback resietors R2).. By;switching thg tap on the divider r264- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 (9, 11, 12), one can ad~uat the level of the collector current for transistor VT3. Transistors VT2 and VT4.fonu a differential amplifier, which ia powered by a stable current from transistor VT3. The coneiderable noise level (a noise factor of 6 to 8 dB) makes it difficult to use this IC in the input stages of receiving equipment. The 175W2 amplifier circuit (Figure 4.28) incorporates two additional transistors for the construction of a local oscillator. The frequency range of the given circuit is limited to 60 MHz and the noise figure to 6 dB. Yet another example of a differential amplifier is the R157US2 integrated circuit (Figure 4.29). In this variant, the control circuit for the current generator is designed around transistore VT3 and VT6. Resistors R2 and R6 as well as tran- sistor VT3 are intended for apecifying the operational mode of transistor VT4. Transistor VT1 serves as a preamplification stage. It can be seen from the ~a . 8 ~ ~I A R1 R3 RS d C1 C4 06wK ~ 1~T3 1 M a.. ~ YTf NT2 a~ f3 Z ~ 2 ~ p2 C3 ,Pd ~ ~f ~~n au zK cz ~ q4 pa q!b ~ ~ . . , , Figure 4.30. The 175W3 broadband amplifier. Key: a. Basic electrical schematic; b. Circuit configuration. circuit configuration that realized here using one integrated circuit are an RF amplifier, mixer, local oscillator and IF amplifier with AGC. The amplitude modulated signal is fed to the base of transistor.VTl, the collector load on which is a tuned circuit: capacitor C3 and inductance coil Ll. The gain of this stage can be regulated through the choice of the nominal value of resistor R1. The signal fs fed from the collector of transistor VT1 to the base of tran- , sistor VT2 of the differential pair (transistors VT2 and VT5), the current in = which is regulatad by transistor VT4. The generator circuit operates with this transistor, the frequency of which depends on the parameters of the parallel resonant circuit L3, C9. The 175UV3 amplif ier can serve as an example of wide band amplifiers (Figure 4.30). 4.5.2 Low Frequency Amplifiers (UNCh) The design of high power semiconductor integrated circuit low frequency amplifiers involves the solution of a number of circuit design, atructural and product~on . - 265 - FOR OFFICIAL USE ONLY ~ APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY process problems. First of all, economical output stagea must be developed having high power integrated circuit structures, where the stage should introduce little nonlinear distortion into the signal. Secondly, a technology must be developed for producing n-p-n struc~ures with a high permissible current density and an elevated gain on a single chip, as well as in~ection p-n-p structures with high gains. Further, it is necessarq to optimize the fabrication technology for integrated circuits with power output etructures, so as to obtain large permissi- ble currents (1 to 2 amps) and low bulk resistance of the collector with a small structure area. And finally, it is neceasary to develop an IC atructure which assures reliable operation and eliminates self-heating. - 4D2 k VDf Rf7 V79 VTf3 1~ !76 ' ~iK ~ ~ ' VTQ ~'T14 YTlB 6 , A5 ~7/4 4K !17 q9 Rf0 116 R1Q V7? VT4 4K 4k l~7X Y~3 r ~2K . V77 n 5 l~Dk ~Dd V7f VT8 YTf1 VT~ N3 q~ Q27K V710 3K a~ v~ v~s ~ IK ~ e n~ � ~ ro A4 R8 tl !2 Af3 ' 0,err l{fK t,J~r f,2K y a1 ' U~ ~ R3 ' C'~ f~h7 . . + c~ ~oo Figure 4.31. The K174UN7 power amplifier. wo ~ ox q~ e ~z ~ a. Basic electrical . achematic; . e c2 s ~ b. Circuit configuration. ~ 3 AU 11S ~ 4 A number of high power and preamplifier . ~ integrated low frequency amplifier cir- , cuits have been developed at the pre- ~ aent time, which depending on the type of radio receiving equipment, can be used in the following variants: an integrated circuit audio preamplifier plus an output stage uaing diacrete components; an sudio preamplifier plus and inte- grated circuit high power audio amplifier (or a aingle high power audio amplifier - IC) with a sufficient vol~~~e gain. The K174UN7 low frequency amplif ier circuit (Figure 4.31) has an output power of 4.5 watts. The input stage of the amplifier is designed around a composite p-n-p transistor (transistors VT1 and VT2), the load for which is transistor VT3. The preamplifier stage is deaigned around transistors VT7, VT8 and VT10. - 266 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500480030-5 For the purpose of reducing the load on the input stage, transistors VT7 and VT8 are connected in a common collector conf iguration. The load on transistor VT10 is the current generator made with trgnsistor VT9. The power output stage is designed around transistor VT14, VT16, VT11 and VT17, and delivers an output current of 1 amp. The bias current of the output transistor VT10 is governed by the current flowing through transiator VT9, and the voltage drop which appears across diode VD3. The bias current of the output transistor VT17 is governed by the current of transistor VT13 and the voltage drop produced across the "stack" of p-n junctions (VD4, VDS, and VT15). The circuit for stabilizing the DC operating point of the amplif ier uses transistois VT4 and VT5. An external network which equalizes the fraquency response at high frequencies is connected to pin 5, while a feedback circuit which serves to ad~uet the gain is connected to pin 6. The amplifier delivers an output power of up to 4.5 watts into a load of 4 otuns with a power supply voltage of 15 volts. The IC package has a heat sink radiator. The description of yet another integrated circuit audio amplif ier with an output power of 1 watt, the K1US744, ie given in [18]. . Audio preamplifiers are used as microphone and headphone amplifiers in radio ec~uipment and to amplify weak signals from various transducers. The considerable - ~ gain (KU > 1,000), the low noise and the good linearity are th~ ma~or character- istics of a preamplifier. - . C3 C4 _ . a""_~"" C~ ' _ ~ 9~,X � ' 6 70~ fa7' ~ ~ f � 4,JK / , 7JI' , ~1' � . ~1 M ' ~ ~01 ~TJ ~T4 N~1 ~ ~f~' ' 2 ~ vrt 9 ~ 2 ~ f 1 rr~ ~ ~Da 4~v ezo , . vrs !3 !12 Rb ' R,T CI ,Q3 ~ pr t~ � d , 1~ ?R ~R ~ ~ 3~3M A'R~ ~ ' o----- . . n ~ Figure 4.32. The K174UN3 audio preamplifier. a. Basic electrical achematic; b. Circuit configuration. The circuit of the K174UN3 audio preamplifier (Figure 4.32) contains a two stage input amplifier using transistors VT1 and VT2, with external loads and bias circuits, as well as a two stage output amplifier using transistors VT3 and VT5. The circuit makes a provision for incorporating external feedback through tran- sistor VT4. Diodes VD1 VD4 aerve for matching the DC level of the collector voltage of tranaistor VT3 and the base potential of the output transistor. ~267- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY - . - ~ YT3 . YT6 yrm u: v ~ ~ YD1 � f71 I~T~ J YTJ6 ~ 4 O,d3 YD4 ' J M ~cr ~va ~ve s ~ qJ ~7S 6 YO/ Y~3 l~DS ~ ~ 7d Y71d C3 ~17 q+ - RB m , ~ qt R3 i~T4 K JO s ~ + � � A1 ' . . 'b~ 2 dp0 Figure 4.33. The 538UN1 preamplifier. a. Basic electrical achematic; b. Circuit configuration. The amplifier is used with a large number of outboard components, which govern its temperature stability, frequency response and gain. With a resistance in the base circuit of transistor VT1 of R= 1 KOhm, the amplifier noise voltage refer- enced to the input is Un = 1.5 uV in passband of 20 Rflz. Improving the noise characteristics of the amplif3ers by means of refining the technology and optimizing the choice of the operating modes of the transistors is the basic problem of this direction in general purpose circuits. The 538UN1 amplifier (Figure 4.33) can serve as an example of a preamplifier with improved characteristica. The two stage amplifier circuit makes it poesible to obtain a gain of KU ~ 105. The input stage is designed in a differential circuit configuration (transistors VT2 and VT4). The input stage is powered,from an emitter follower (tranaistor VT1). A composite emitter follower (transistora VT8 and VT9) servea to match the input and output ~cages. The current of this emitter follower ie governed by the output potential of transistor VT7. Tranaistor VT12, the active load on which is transiators VT10 and VT11, inverts the signals fed from the output of the composite emitter follower. The output stage, which is designed around transistors VT13, VT15 and VT16, has good linearity and makes it posaible to obtain a harmonic distortion factor of Kh s O.1X. Transistor VT14 servea to protect the output stage against current overloade. An improvement is achieved in the temperature atability and power supply voltage stability by incorporating a voltage regulator in the circuit which uaes reverse biased diodes VD2 and VD3, which also reduce the collector-emitter voltage of the input stage transistors. - 268 ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY . . S~g ^ g ~H ~ � ~ V ` ~ ~1 ~ N . W w y,i N ~ ~r'I . w ~ . ~ ~ . ~ _ - - _ . ~ . ~ b ~ ~ ~ ~ ~f ~ ~ a ~ ~ ' ~ ~ ~ ~ ' ~ ~ . w a Q . . ~ . ~ ~ ~ ~ ' ~ ~ ~ . . _ ~ - N , ~ ~ ~ ~ . ' . ' ~ ~ $ . aai ~ ~ o~ c~ 7 ~ ~ . u ~ _ d m ~ . - � v co d ~ � r~l ~ ~ d ~ . . . . . � �d CJ ~ ia ~ a~.? q O � ~ ~ � ~ a~i c~i a"~D b ' � ' ~ ~rl N r~ ~ ~ ~ ~ ~ q~ � 1,-~~ PO C~ ed . ~ I ~ ~ ~s , ~ c0 .0 b ~ ~ ~ ~ . n ~ c^ ~ ~ ; ' ~ ~ � ~ ~ ~ ~ . . ~ . w ^ ~ ' ~ ~ ~ N - 269 FOR OFFICiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OF'FICIAL USE ONLY The regulator governs the entire DC operation of the integrated circuit. To improve the frequency response, an equalizing capacitance Cl is introduced into the circuit. The unit gain frequency of this IC reaches 15 MHz, while the noise voltage referenced to the input in a frequency range of from 0.1 to 10 RHz is Un = 1.2 uV with a gain of 500. External feedback from the IC output to the emitters of the input stage (pin 5) is provided for normal operation of the amplifier. To achieve stable operation of the amplifier, the capacitance of the internal feedback capacitor C1 can be increased by connecting an external capacitor C3 (pins 6 and 7) in parallel with the internal capacitance. 4.5.3. Specialized Integrated Circuits Integrated circuits are being developed at the present time for amplifying, limit- ing and detecting FM signals, as well as IC's for amplifying, converting and detecting AM signals, and frequency modulated IF amplifier systems. The K174UR1 integrated circuit (Figure 4.34) is intended for applications as an audio channel IF amplifier in a television receiver. This IC can be used in the FM channels of radio receiving equipment. We shall consider its design. The audio carrier is fed from the output of an external bandpase filter, which segregates the difference frequency of 6.5 MHz, to the input of a limiter-ampli- fier, which c~onsists of eight series coupled differential amplifiers (transistors VT1--VT26) ar~d two output emitter followers (transiators VT28 and VT27). The limiter-amplifier is looped by deep negative feedback through resistor R24, which suppresses the parasitic amplitude modulation (55 dB) in a wide dynamic range of input signal levels. The limited signal is fed from the outputs of the amplifier string to the input of an. FM quadrature detector, which takes the form of a balanced modulator, designed around transistors VT30--VT37. To obtain a signal which is ahifted in phase relative to the input signal and to control the bases of the transistors of the detector multiplication circuitr~ (transistors VT29 and VT37), an external parallel resonant circuit tuned to a frequency of 6.5 MHz (Figure 4.34b) ahould be connected to pins 7 and 9. The signal is fed from the output of the detector to the input of an electronic attenuator, the function of which is to preamplify the accompanying audio signal and provide for gain control. The electronic attenuator consists of two cross coupled differential amplifiere (tranaistors VT38--VT4~i), the arm of each of which is designed around a dual emitter transistor. The volume control is accomplished by means of a variable resietor connected between pin 5 and the common lead of the IC. Because of the fact that the intercarrier sound does not pass through the volume control circuit, it is not subject to the influence of background huun and noise induction. This simplifies the remote control of the loudnesa. There is a regulator in the IC which is designed around diodes VD1--VD6, traneistor - 270 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFF'If , _ ~ H � _ . ~ ~ ~ ~ e ~as~ ~ ~ c ~ . w V w ~ _ r~l . ~ ~ ~ . ~ . ~ ~ , C~ - - _ . _ _ . _ . - - .d ~ ~ - ~ ~ ~ 1+ o . e � . R ' r~l ~ � GO o ~ ~ D ~ i ~ ' ' ~ ~ ~ �a ~ N Q ~ ~ d ~ ~ ~ b . ~ a ' 4 ~ ~ ~ p a ~ d u a o ~ v~ ~ 3~ ~ ~ a al q rl .C o ~ ~ a ~ u ,a a~ ~ ~ S~a'~a ~ ��~d ~ ~-I H ~ _ - - - - r~l U ~ Rf a s ~ ~ ~ q ~ ~ ~ ~ ~~a~i ~ ~ ~ ~ ~ d~~ N ~ ~ ~ ~ ~ ~ N ~ ~ ~ ~ ~ Q ~ ~ ~ . . N a N ~ �n � ~ ~ . ~ � ~ Q ~ ~ ~ . ~ + u1 Q C~1 s a ~ ~ ~ ~ N ' , M ~ ~ ' N ~o ~ ~ Q � ~ . ; ` � ~ ~ ~ ~ ~ N . a ~ N � ~ . ~ ~ s~ ~ _ w ~ ~ ! ~ � Rl 4 N ~ ~ - 271 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY VT45 and resistors R46 and R48. It reduces the influence of a change in the supply voltage an the amplifier parameters. The 526UR1 integrated circuit (Figure 4.35a) is also intended for use as an audio channel IF amplifier in a television receiver. This IC can also be used in other - FM channels. As can be seen from the basic schematic, the 526UR1 IC is also constructed based on a combination of the differential amplifier and multiplier circuits treated above. The broadband amplifier (transistors VT1--VT22) serves ae a limiter-amplifier with a high value of amplitude modulation suppreseion (no less than 40 dB). The limited signal is fed to the reference input of the balanced modulator (the bases of transistors VT30 and VT37), as well as to the frequency dependent quadrature network, which includes external capacitor C, as well as the LC network which is connected to the second input of the multiplier between pins _ 4 and 3. The quadrature circuit converts the frequency modulated signal to a phase modulated one, which is then detected by the balanced multiplier. The demodulated signal is fed through a level reduction circuit (attenuator, transistors VT48 and VT50) to an audio preamplifier with electronic gain control (the control signal is fed to pin 10). The 526UR1 integrated circuit has a low frequency output voltage of Uout audio = 150 mV when UP~ = 12 volts. The K174UR2 integrated circuit (Figure 4.36), besides ita main function (video channel IF amplifier in a television receiver), may also be used to construct a high fidelity AM receiver. The intermediate frequency is fed from the output of an external lumped constant selective filter to the IF:amplifier, which has three stages (transistors VT1, VT3, VTS, VT7, VT10, VT11, VT12, VT17, VT18, VT19, VT22 and VT23). Electronic gain control is provided in the firat two stages, which are designed ~ in a complex differential circuit with a common collector-common emitter configu- ration. Identical diode structures, VD4, VDS, VD9 and VD10, the bias current of _ which is controlled by changing the automatic control voltage, are used for this. The paraphase AM signal is fed from the output of the IF amplifier to the inputs of a detector designed in a balanced multiplier circuit configuration (transistors VT33, VT34, VT35, VT46, VT47 ard VT49) as well as a limiter (transistors VT28 and Vi29). An external parallel tuned circuit, which is tuned to the intermediate frequency (38 MHz) is connected to the output of the limiter (pins 8 and 9 in Figure 4.36b). The internal resiators R61 and R64 of 5.1 KOhms each are used in this mode. The ~ignal is fed from the output of the amplitude limiter to the r~ference input of the detector (transistors VT39 and VT44). When two signals are present in the detector, a video signal is produced at its output. _ Besides the v~d~o signal, there are the doubled intermediate frequency of the audio subcarrier and the doubled intermediate fr~quencies of the chrominance subcarriers which app ear at the output of the detector. This is due to the presence of square-law components in the amplitude response of the detector. -272- . 1R OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500080030-5 FOR OFFICIAL USE ONLY . Q ~ ~ ~ _ ~ ~ ti y b ~ ~ ; ; ~ u ~ ^ tb ~ j ~ ~ ~ ~ ~ ~ ~ a N ~ a�~i A 3 a~i b , ~ w V ~ri ~r~l j y `~~p G! Ul 1~ ~-I f0 N ~ ~ ~ ~ `C '1'~ ~ .y ~ ~ a ~ ~ ~ Q ~ S ~ S ~ ~a, ~~w p ~ 4-~ H � ~ N N ~ 1.1 ~I b ~ 'a 'a ~ U O O N a, ~ ~ q A ~ Vbr~l ~ ~ ~ ti-1 � Cl a~ rl N cy U ~r1 cJ ~ ti P4 H r~l V c0 H .n , j b ~ N ~ ~ f~ ~ P~l U~0 H w ~ a w . ~ ti ~ � ti ~ ~ a R { ~ S a w A ~n' ~ " ~n ~ c~d ~ oc ~ ~ ~ ~ ~O a M Q ' ~ ~ a M J ti ~ ~ ~ ~ ~ ~ ' " ' . ' ' _ . . _ _ ' _ . . _ _ ' . . " ~ , ~ ~ w ~ ~ M Q , Q ~ , ' O~ ~ ~ ~ ' , ; ~ ~ ~ w N ~ b ~ ~ ~ ~ , .M ~ . ~ ~ ~ g ~ ~ ~ q , y ~ M~ ~ ~ ~ w g ~ , ~ ~ j ~ . ~ 7; ~ � , w .p . . . b � 1 ' Q wt 6 ~ ' ~O ! ~ ,n0 ~ ~ N H ~ ~ , ~ ~ ~ ~ v g . a . h ~ ~ ~t . ro q ~ M ' ~ ~ ~ � ~0 ~ , ; Q Q ; Q Q ~ , ~ - � a ~ " � ~ . ~ w , ~ 4 N r w 14 . . -273- FOR OF~'I~' CJ~E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OF~ICIAL USE ONLY The audio signal and the chrominance difference signals can be segregated from the video signal by means of frequency detectors after further amplification in the other units of a television receiver. The positive polarity video signal is fed to pin 11 while the negative video signal is fed to pin 12 from the output of the detector through the video preamplifier (transistors VT40, VT43, VT45 and VT5~1) and the phase inverter (transistor VT52). Because of the fact that the AGC system should respond to the average value of the received signal voltage, an AGC key:.ng system is used in the IC in which data on this signal is used which is contained in the horizontal blanking pulse. At the moment when the horizontal blanking pulse arrives at the input to the keying amplifier (pin 7) from the preamplifier, it charges capacitor Cl, which is incorporated in the keying amplifier circuitry, until reaching the correspond- ing voltage which is also used as the control voltage for the operation of the AGC system. The AGC voltage is fed from the output of the keying amplifier to the input of _ the regulating amplifier (transistors VT2, VT4). By connecting a capacitor and resistor in parallel to pin 4, one can change the AGC time constant. This pin can be used as the input for manual gain control. The AGC voltage is fed from the input of the regulating amplifier to the electronic gain control outputs of the IF amplifier stages and to the input of the threshold amplifier. The AGC voltage is fed from the output of the keying amplifier to the input of tfie regulating amplifier (transistors VT1, VT4). By connecting a capacitor and resistor in parallel to pin 4, one can change the AGC time constant. This pin may also be used as an input for manual gain control. The AGC voltage is fed from the output of the regulating amplifier to the electronic gain control inputs of the IF amplifier stages and to the input of the threshold amplifier. [Trans- lator note: Near duplication of these two paragraphs appears in original; apparently editorial error]. The AGC voltage is fed from the output of the threshold amplifier to pin 5 and is used as the AGC in other units of the television receiver (in the IF preampli- fier or in the television channel switcher). The actuation threshold for this amplifier is set by means of an external resistor, which is inserted between pin 6 and the common lead of the IC. The AGC level is ad~usted by means of an external resistor, which is inserted between pin 10 and the common lead of the IC. A provision is made in the integrated circuit for temperature compensa- - tion for the change in the electrical characteristics of the detector and the keying amplifier. 4.5.4. IC's for the Construction of Selective Circuita Work on the design of semiconductor IC's for aelective circuits is going in several directions (for example, IC's are being developed for activp filters, - as well as IC's which use the phase-locked loop principle [19]). The use of - semiconductor integrated circuit technology makes it poasible to find circuit design solutions which improve the quality of these devices and substantially reduce the dimensions of selective circuite as compared to similar devices using discrete components. - 274 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 � FOR OFFICIAL . _ _ - ~ ~o~--_ ; ' R~ : _ ~ RZ R5 R7 q~ ' A7K . VT1 1TK Vjn 11K . . ~ ~7i~ ~ ~~1 3 5 ' P'7Z y l~TR � ~ ' lpir ~ . ~ . . ~ix q1 ~ ! R4 4,EK 3 4~8K ~ k.dK ,0l1 � R. 20 10 K � ?0 ~ ~ ~K 2 ~ al ~ Figure 4.37. The 529UP1 amplifier. a. Basic electrical schematic; b. Design example of a low pass filter. . - - - _ _ - - a RZ RB R9 ~%f Af3 _ d YT4 J YTf ~73 VTQ ~ Y7d Y79 ~ AS ~P4 I ~ YT5 ~7 YT90 ' vr -of4 Rf RS Re af~ aft ia ~ ~ a ~ r~ e a~ H 6 4 + f~x 1f 2 ~ll��r " CZ ~ O,Df Af 1Z 3 9 a~ b) " Figure 4.38. ~'he K283SS1 gyrator. a. Basic electrical schematic; ~ b. "Grounded" inductance circuit configuration. When designing semiconductor IC's for active filtera, the primary attentioa is devoted to the development of the basic operational amplifiers. The op amp configuration as a second order filter section is the most widespread in active RC filter circuits. This filter sectfon is based on integrators,~and for it, three high quality amplifiers are requiredo In a number of cases, when elevated requirements are not placed on the sensitivity and Q of filters, one can use comparativelq simple IC's with a low gain. For example~ the 529UP1 integrated - -275- FOR OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY i circuit (Figure 4.37) contains three identical amplifiers on a single chip (overall current consumption of 3 mA and a single power supply voltage of 6 volts), each of which has an input impedance of 30 KOhms and a gain of 40 dB. A typical active filter section with a Q of 50 in a fzequency range of up to 200 KHz is realized on the basis of this IC. The research which has been done ~n the field of IC design for another class of active filters, gyrators, shows that the existing circuit design techniques for the construction of semiconductor IC's make it possible to effectively aolve one of the ma~or problems of the practical realization of gyrator circuits: assuring the stability of the DC mode when the parameters of the components change and when adjusting the value of the gyrator conductance. Hybrid IC's - the K283SS1--K283SS9 [20] (Figure 4.38) - make it possible to realize an "inductance" with a range of nominal valuea of from 1 mHy up to 100 Hy at frequencies of from 1 to 300 KHz with a Q of from 10 to 500 and a permiasible deviation in the gyration impedance of + 3%. These IC's are powered from two supplies with a voltage of + 6 volts. - The active filter IC's treated here can be uaed in low frequency audio channels of receivers. When developing IC's for high frequency selective circuits, it has proved to be convenient to use the principle of phase automatic frequency control (FAPCh) [PLL - phase locked loops]. A FLL system containa an oscillator, which is voltage controlled, a phase detector and a low pass filter. The development of IC's employing the PLL principle is one of the promising trends at the present time in work on- high quality radio receivers, which will make it possible to reduce the number of inductances, and consequently, the dimensions of the device. A further improvement in semiconductor IC's by means of increasing the level of integration and expanding the functional capabilities opens up the prospects of fabricating entire functional assemblies of communications equipment in a single production process cycle. 4.6. Integrated Circuits for Analog to Digital and Digital to Analog Data Conversion Mutual digital and analog data converters are broken down into two groups: analog to digital converters (ATsP) [A/D converters], which serve to convert dn initial analog quantity to a digital equivalent (or code) corresponding to it, as well as digital to analog converters (TsAP) [D/A convertersJ, intended for generating an analog output quantity corresponding to the digital code fed to the converter input [21, 22]. D/A and A/D converters consist of digital and analog circuita. The digital cir- cuits (counters, registers, decoders, adders, programming memories) control the conversion process in accordance with the conversion algorithm. Analog circuits. generate highly stable reference voltages, which switch the analog levels, amplify and convert them on a specified scale, and realize instantaneous storage and integration. Sets of IC's are being produced at the present time for the construction of the analog circuits of D/A or A/D converters. The breakdown of - 276 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY a converter into aeveral IC's, which takes place because of technological reasons, also has its positive aspects, since it makes it possible to construct various types of converte,rs in terms of their resolution using a single set of IC's. . 34 0 3 . ~ ~ R4 ~ Y74 ! ~S Q ~9f R5 ~ ~ ? 1P R2f . VT7 ~Tf7 p~ ~ 27 . vr,v v~~ � v�e 2f � o-- 14 VTf ~Pld ~ ~ VT ~T~ VT8 VTA7 qf~ Y7~'! Y719 ~ 2 g YT20 4 rY ' Rd N7 V711 R20 Q � Yt5 ~ V7y2 I?f4 Y 7~ RB Rf2 RJ4 . Figure 4.39. Basic electrical schematic af the voltage comparator incorporated in the 240SA1 IC's. The type and number of IC's needed for the construction of the digital circuits of A/D and D/A converters is governed by the procedure chosen for signal convers- ion, tlie requisite speed and the number of bits. CMOS c~.rcuits are used here for economical devices, TTL integrated circuita are used for atandard devices and ECTL for high speed converters. One can use the hybrid IC's of the 228, 240, 265 and 252 series for the design of the analog circuits. The 240 series is a functionally complete set of IC's, which is intended for the construction of multichannel (up to 30 channels) [23] 10 digit A/D converters with an input voltage range of + 5 volta and a conversion time for the maximum input voltage to a binary code of 100 microseconds. Six ~ [sicJ types of analog IC~'s are incorporated in the 240 aeries: the 240 SA1, 240 UD1, 240 KN1, 240 KN2 and 240 KN3. - The 240 SA1 integrated circuit (Figure 4.39) ia a voltage comparator, which is intended for performing the operation of comparing two analog quantities, with a resolving power of no less than 2 mV, and has an input impedance of 1 MOhm. The comparator is designed in a two stage configuration. The input differ~ential T Z17 ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY _ - - a4 . . m~r~ 1(QI VT2 R� ` Rf0 1B f ~ l '~S YTf4 Y7f0 35 N2f !p ~VB ~ ~d YT9 YTf7 (~T3 p~ YTf3 VTl5 S f9 70 V7fe VI10 Rf3 v� p~ ~ ~ An n v~6 ~re vrti , vr>9 zs ~P2 ~79 , 2 A23 23 : ' RS R~ VTff � . (/T21 � � ~'Td f3 � ~Tf2 ~y, Rf2 ~714 ffi 10 , ' 30(JeJ ol ' ' ' _9e + ~ ~ , Ly , Aa ~ A~ , n 0,47 . 1d 3U C4 C5 ~ ' t ' ~V3 f '!~!K 6r ~ , ~x C1 C R4 ~ . ~r~~. . . dI Figure 4.4~. The 240UD]:. operational amplifier. a. Basic electrical schematic; b. Circuit configuration. stage has tranaiecora connected in a Darlington configuration to increase the input impedance. The use of the 129NT1 integrated circuit pair in the input stage has made it possible to obtain a good bias voltage (2 mV). In order to limit the maximum positive output voltage to the level permissible for logic elements, the output stage is powered at a reducad voltage of +5 volts. The comparator can generate a current of up to 12 mA in a load, where the slew rate of the output voltage exceeds 10 volts/usec. -276- FOIt O~'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY fOJ A3 RY7 Rtl vr~ ~ ~ RA R/J ' R?2 i~T4 � tafP9~301 l~T9 ~ ~ ~ a2a R4 Rf0 YTl YT6 ' !~'!1 YTl4 ~lf~d',Y11~0 Y1I1 ~ Af6 ~ 4ff~ 5f6I A8 YTQ p~ RZ ~V1!? ~py ~ _ vrn vrta . vru ~ vrz ~r~ hro Y~~2 ~ a~ . ' ~ro~ R20 ~P1 Ytd QY~' RZd � V7~~ . � r � NI RYQ ~ . R~ ~D(df~ 321; ' ~ Figure 4.41. The 240KN1 analog switch. ' . The 240UD1 operational amplifier (Figure 4.41) operates as the input signal amplifier of an A/D converter, as well as an amplifier which sums the input currents in a D/A converter. Two differential amplifier stages and a differential follower make it possible to obtain an internal gain in excess of 8,000 in a wide band of frequencies (more than 100 KHz). An emitter follower (tranaistor . VT10) provides for a high common mode re~ection ratio. The input differential stage, designed as a Darlington configuration, has an input impedance of about 1 Mohm, an average input current of Iin ~ 1.5 microampa, and an input current difference of ~Ii~ = 0.2 microamps. The amplifier bias voltage is UbiSB ~ 2 mV, while its temperature drift is Ubias ~ 10 UV/�C.. The output power amplifier stage generatea a current of 5 mA in.the load. Ttao frequency equalization circuits are introduced into the circuitry to improve the frequency response; in this case, the output voltage slew rate is 2.1 V/usec. The 240KN1A,B analog awitch (Figure 4.41) is designed for connection of either a positive or a negative reference voltage at the output (depending on the i,*.~ut signals). - 279 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 , FOR OFFICIAL USE ONLY _ ~ _ _ - _ ..~o u n . ~ntm. ~ Kf YTS YT7 . a ~ ~ 2at~,~ 4 R!! u,:a ~ v~B vtff ~ ~ t0 QZ m 4 33 ~ 3S ~ aa vr9 n >t i . ~ ~ as a~ aa z.' vn vr~n d 19 d~ YT4 '7 . ' RR7 ~r~n o~ ~ Figure 4.42. The 240I~I2 analog awitch. a. Block diagram; b. Basic electrical schematic. ~ ~ ~ K~ n~~~~ ~ . ~ ~ ~ Yta vre . VTO . Al Ri 32 � � Ad R~7 AZ ~ fd ~ ~ ~ VT7 Vlk7. m H � !d f4 31 ~ ' A~ ~ aa Y~ ~r ~ ts r~ ~ . t'~' ~ tm K4 R4 M! ~~(J3,tsl 1f . . U n _ Figure 4.43. The four bit 240IQJ3 switcher. a. Block diagram; b. Basic electrical schematic. -280- ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-44850R444544484434-5 - - ~ . i ''T~ � R~ ha ~ ~ra Ate Ad ~ an ~ ~ vn vre vT~r ~ . e R� ~ro ~ A~e R~o Q5 ~ V7f4 . f3 ' 27 14 ~ da ' A6 V7Q ~ YTf6 R~ 11 ~ A7 ~ ' l?f0 YT>2 R3f ~ , p' ' R R97 p? ~ BJ? r7J4 L' A? YT4 ~a Rf4 Rld Aip YT1~1 R36 ~ td u ) ~ . a ~G ~ . + a~ ~ ~ ~e . . . ??o~ � Af C4 ' ~ ~ Y~2 . ~ ~a ~o ta 2e ~ ewx t R2 ~ Aa --o RI C2 fK ~ fK C3 QO Arx t ~ ~I01~ Q~ A1 fA! ~ ~~OI,I , ~ . Figure 4.44. The 240YeNl voltage regu:~ator. a. Basic electrical ar,hematic; b. Circuit configuration. If a"1" is fed to pin 4, while an "0" is fed to pin 5, a positive reference voltage appears at pina 26 and~25. If the potentials at the input change places, then a potential close to zero will appear at pins 26 and 25, while a negative reference voltage will appear at pin 27. The error in the.transmission of the reference voltages is + 2.5 mV for the 240KN1A switch and + 5 mV for the 240KN1B. -281,- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 � FOR OFFICIAL USE ONLY c crz d0ei~' ~ . z ar $ ~ ~ s~ ~ c > > c ~ ~ 4 4 ! d dr ' C> Uw � Af A2 A3 , A 1CA40f 2CA40f 1CA40f ZS~T40f dx . Figure 4.45. Block diagram of a double integration analog to digital converter. Af As !x I ~ A~ t40A7YJ ~~tr 2paXq> ~1 C 240A7YJ f 2q,Apf'S A4 ~ ,p~/ ?40ENf Figure 4.46. Block diagram of a 10 digit digital-analog converter. .,~p ~ - The block diagram of the 240IQ~I2 3 integrated circuit (Figure 4.42) con~ R~, . taine three bit reference voltage ~ ts 2e ~ ~ switches having a transmission error ' of + 10 mV. By feeding a"1" poten~- ~ tial to pin 20 and an "0" to pin 17, ~ S' ~ we obtain the positive reference ,va~ ~=J ~ voltage at pin 35 and a voltage close to zero at pin 3. If the potentials 4 ~ at the inputs are changed to the ~ , ,v~~ opposite values, then a negative � . reference voltage will appear at pin ,P,r r Ae , ~ 3, while a voltage close to zero will appear at pin 35. The four bit 240KN3 switcher (Figure Figure 4.47. Basic electrical schematic of 4.43)~ia designed for switching ~ the 301NS1 resistive matrix. negative and positive polaritq �-282- FOR ,OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 I~UR cN~h'i('IA1. iI~~H: (1NI.ti' ~ ------,i - 21(7d,fs) i~ ~ R1 R4 R~ N~o 15 , S i ~ ~ ~ V7Q " vT ~ VTfI ~D2 ~ 6 ! 1 3 V77 YT9 70l12,!'1) ~ 2f~ , Rff i Vtf VD! yTf2 S(?;f6! ~ ~ 2f7,f11 ~'T2 yT4 ' VTS 1 ~ 1(E~ f0) A7 ~ fs~ I 3/8,121 ~ 1 VT3 NTd A8 Vf9131 ~ R9 74(10,l~ o! ~ 8 ~ In C> > Out dx 51 1 25 ~ . ~6n C? 4+ 16 Af Uref. 5f 810 Q~ (b) Figure 4.48. The 252SA1 comparator. a. Block diagram; b. Basic electrical schematic of a single comparator; c. Circuit configuration for a single comparator. voltages of + 5 volts, depending on the control signal levels. The switch in the 240KN3 integrated circuit has a residual voltage of 1 mV, a leakage current of the turned-off switch of 100 nA, a resistance of the turned-on switch of 100 ohms and a switching time of 1.0 usec. The switch operation can be analyzed using the first channel as an example. When the "1" level is fed to pin 18 and the "0" level is fed to pin .19, the switch turns on, and the signal passes from pin 17 to ~in 20. When the potential at pins 18 atid 19 changes, the switch cuts off and the signal does not get from pin 17 through ~o pin 20. The 240YeN1 voltage regulator (Figure 4.44) makes it possible to obtain a stabilized voltage of + 5 volts with an instability in the output voltage with respect to curreut and voltage of no more than 0.06X; the average temverature coefficient o:: the output voltage is no more than 0.005~/�C and the load current for each output runs up to 25 mA. The regulator does not have an internal refer- ence voltage source, because of which, the reference voltage supplies are designed ~iround external zener diodes VD1 and VD2; the output voltages are ad3usted by variable resistors R3 and R5. The 240 series integrated circuits are made using hybrid film technology and use active outUoard elements of the 129NT1B, V,.2T202, 2T332, 2T364, 2T360, etc. types, assembled in a 155-36-1 package and operate from a+ 9 volt + 109; power - 283 - FOR OFF[CIAL USE QNLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFIC[AL USF. ONI.Y f R2 RS R11 R13 r(z013 A18 ?8 R1,9 ~ S 2 R14 ' A3 YTf VT3 ~6f1J1 q~~ . . 3 f 6 4 Ry 4 6 3 f'D1 Rn Af ~ ~ 2 5 R6 R7 Q9 V74 _ 3 f 6 4 2 VTt 23(f71 ' A2 A4 Z 5 4 6 S(1?). >2 . ~ ~ RB ~PfO Rf3 22(1~ . a~ (a) . ~MII ~Or~ d B ' ~ ~ Rt R4 Qr A~ y yp Z -A' ~q Oa+x . 20 3 S n 0 4 . R3 A5(NM) ?p s ~ uwn � f , Hz a t ~ ~ ~b) o~ ~c) ~ f~r Ppc. 4.49. OnepauROnna~ ycennre,nu Txna 2b2YA1: O- OPM114NIIX~A6HB11 SAlKTQI19lCII~11 C7IlM~~ d- CJflM~ ORJI109lHRA, A~` lA911CNMOCT6 Rb9~' QIN4MlNTa yCNAlIINA OT 4aCTMY CuYVe ~ p,r q~. C,~ nm C,. n~ � KDM~p I R'�Otims R~~KOhms Fd I Fd ~(6a ~ 1~ ~ ~ B.4 890 10+ 1.~ 1300 ~40 ~ 10 7.6 9450 4+10 6 ~ ~'7 10 ~0� 6 ~ s~4 Figure 4.49. The 252~G`)1~ operational amplifier. a. Basic electrical schematic; b. Circuit conf iguration; c. The ga~n as a function of frequency: Key: 1. (Without feedback). supply. The curves for the electrical parameters of the 240 series analog IC's as a function of temperature are given in [23]. The 240 series was developed for the construction of double integrating A/D converters (Figure 4.45). The digital portion of this circuit can be constructed using any TTL integrated circuit. - 284 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY The a3dition of a resistive matrix expands the functional capabilities of tl~e 240 series. When using such matrices, the series can be employed to construct D/A converters and other kinds of A/D converters. The possible circuit of a 10 bit D/A converter using a 301NS1 integrated circuit is shown in Figure 4.46. The matrices of R- 2R resistors are intended for converting a parallel digital code to the corresponding voltage level at the output. The major characteristics of the 301NS1 R- 2R resistive matrix (Figure 4.47) are: a division factor K of from 1/1024 to 1023/1024, a division step of h(1/1024), a relative division error S% 0.0135), the scatter in the nominal values of the resistors, ~R, is 0 to 100 ohms, as well as a maximum input voltage Uin of 12.6 volts. I IA 17 f~ a 25 6 i k 6 Z3 B ?f 11 10 fB f0 f9 f6 >2 172619 ~ AZ QS R1l7 Rf.s ~ ;0 430 4 {77 YTB VT9 vT~ YT3 ~'74 1~T5 VT6 ~ R1 R7 ~~11 N1J R2f RTS R29 A33 l'77. 5,1K 5,1w 5,1K ,f,1K ~1K 5,1k ,fi/K 5 J^ AS ~ A 7 6 ~ A I 6 .v S 7 6 9 6 7 6 9 d 1 6 d 7 6 9 7 6 d 7 6 A~ A2 ~d A~i A6 ~17 A8 1.? 3/i f: 3 4 f l 3 4 f 2 3/! 1 2 3 4 f 2 3 4 f 2 4 1 2 3 4 ,~'3 R6 Ald K1d A72 R76 ~P30 R3~i i.4A ~/,bN ~6K ~IK ~~/A' ~,QK 1~ .TO7,P ~'4 ~5 ~09 ff Bf4 Q16 Rf9 1 ~P23 14 R27 R28 ~Vdf Q35 !/l,i,y f,7K 2K 4,?M 3K B,SK ~7K 6 ~~,3K Z 69K !'J9A' 7K 106'~r , 1 3 f3 f5 Figure 4.50. The basic electrical schematic of an 8 bit digital/ analog converter which converts to a positive polarity current. - Another set of IC's intended for construction of A/D and D/A convert~:rs is the 252 series, which consists of seven types of IC's, based on which one can con- struct 8 to 10 bit converters for analog signals represented in the form of positive or negative voltages. Included in the complement of the 252SA1 integrated circuit (Figure 4.48) are three comparators with a current sensitivity of better than 2 microamps. The two stage comparator circuit provides for a voltage gain of no less than 1,000. The input stage of the comparator is designed in a complex differential circuit configuration and makes it possible to configure the comparator both with a high - 285 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE JNLY input impedance (the utilization of an input emitter fc,llc~wer: tr.~ntil:~c~~r:; V';'I ~ and VTS), and ~ith a reduced input impedance (the signal is fed to the b.~~es ol transistors VT2 and VT4). The 252SA1 comparator has an output voltage slew rate of no less than 30 V/usec for an input signal voltage of 10 mV (the emitter follower inputs are used in this mode). J Incorporated in the 252UD1 integrated circuit (Figure 4.49) are two operational _ arnplifiers with feedback resistors. Each op amp is designed in a two stage configuration. Two differential stages and a power gain stage provide far a ~ gain of no less than 7,000. The input differential stage, the arms of which use Darlington circuits, is characterized by the following input parameters: Rin ~ 900 KOhms, Ubias ~ 12 mV; Iin < 0.1 uA and ~Iin = 0.02 uA. To increa:~e the input impedance of the op amp and expand its gain bandwidth, inserted in the emitter circuits of the input stage are resistors having a nominal value of 50 ohms. An improvement is made in the frequency response of the operational - amplifier through the choice of the external frequency equalization networks; in this case, the small signal passband of the op amp (when Uin = 0.1 volts) is about 6 M~iz and the output voltage slew rate is 5 V/usec. The nominal values of the frequency equalization components should be chosen as a function of the gain by means of Table 4.?. TABLE 4.7. The Choice of Equalization UU 11 A~ 28 Elements for the 252UD1 ~.y pi AZ Operational Amplifier u~ 5 zs vex4 6 u 4 - a zs?n~t~ ;:r ~5zv,~~ 2~, ~emx AxJ 8 i ~ 5 U K() Ci~ n~r R~ OM n~ R~. KON ~exG 9 ~7 6~ R3 Ot1C ~ 1~ vFd IOh I ~ex> >o 'r.s 0 0 0 0 U� V6x8 17 G J_~ ~ 1l~ 3,90 51 10 8,2 ln8 25 PA 0 4700-L~~00 10 1300 26 240 1,2 1 4700 IU 24U 0,75 Figure 4.51. Block diagram of an 8 bit dig~tal to analog converter converting to negative Key: 1. Voltage gain, KU, polarity current. The 252PA1 integrated circuit is an 8 bit binary code to pos~.tive polarity current converter (Figure 4.50) and consists of 8 s~witches and a resistive matrix. The switches, depending on the digital combination at the IC inputs, control the output current of the matrix. When a signal which turns on the switch appears at the circuit input, a current flows in the load, which is normalized by the resistarices of the matrix and the reference supply voltage. The relative conver- sion precision in this circuit is no worse than + 0.4%; the current levels in each bit of the converter are given in Table 4.8 In order to construct a binary code to voltage A/D converter, it is necessary to connect an operational amplifier at the output of the 252PA1 integrated circuit, where this amplifier sums the bit currents (Figure 4.51). In this case, we obtain a D%A converter far a negative polarity. - 286 - FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400540080030-5 FOR OFFIClAL USE ONLY w q . a ` h ~ N eD M 1~ ~h N , p K ~ n ~ ~ N ~ ~ y ~ w ~ ~ A ~ h w a ~ ~ ~ b ~ Ao � n' ~ 00 s ~ O N ^ ~ rl Qt w ~ . ~ w �j b n N iJ C~+ ~ N a d Q' Q~ N ~ ~ ~ ~0 ~ ^ ~ b ~ 0 rl U h ~ ~ ~ 'l7 ~ � w ~ ~ ~ ~ . ~ N ~ N a N~. N R,~ , ~ ~ ~ G ~w ~ O ao a s ~o ti o ~ ~ . ~ ~ w a~ _ O cd . 00 U N ~ G 1~ . cd O ~ g S ~ ~ ~ N b m r~ ~f y~ N ~j+ ~ , M ~ ^ ~ w ~ W V ~p (n `1"~ w ~c ~ b ~ ~ ~ ~ ~ ' td Q~ � U ,ri A O w o, ~ U V ti N ~ ~ b w N C~ ~1 ~ , r", ~ 1~ ~ Ol Q ~ ~ ~ s b ~n ~ S"'~ - ~ w ~ ~ ~ Q a ~ , ~ COJ w os ~ ~ N b p~ ~ 0 N J ~ ` ~ tc ~ ni ~ a b ~t ~ ~ r~ N ~ ~ ~ n ~ N ~ n. eo Q J ep ~1 ^ N N Q t~ J Y b w Q t Q ^O b. ~ ~ ti . N P'~ b N ~ 20/ ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY Uinl A~ U � - z 18 �u~eaX Figure 4.53. Black diagram of an 8 bit ~ ner, ~f 2~ ~2 digital to analog converter, . � ~~Ilr.t ,S 7f z4 4 which converts to positive Uei4 S 2s2/!AZ 23 5 zsty/(~ 26 polarit; current . ~~a.s 8 2f 24 = de.6 .D pp 6 ~ RJ f~e, ~ f0 f,9 Q~ 750 ~ewe i~ � Cz in8 =400 _ 10 a:~aa The 252PA2 (Figure 4.52) 8 bit binary code to negative current c~mer_ter is dis- ~ tinguished from the preceding b~ the polarity of the diodes and the :reference power supplies. The relative conversion precision is also no worse than 0.4%; the levels of the bit currents correspond in absolute value to the analogous currents in the 252PA1 integrated circuit. When a summing amplifier is connected to the 252PA2 integrated circuit, we obtain a positive polarity digital to analog converter (Figure 4.53). A 10 bit binary code to negative current converter can also be designed using two 252PN1 and 252PA3 IC's, where the resistive matrix and diode switches are incorporated in the 252PN1 integrated circuit (Figure 4.54), while the 252PA3 IC contains the control circuitry (Figure 4.55). The relative operational pre- cision of this converter is no worse than + 0.1%. The block diagram of a 10 bit D/A converter (Figure 4.56) is based on the 252PA3, 252PA1 and 252UD1 integrated circuits. The four-channel 252KN1 current switcher (Figure 4.57), which is intended for the distribution of bi.polar current signals at a frequency of from 0 to 60 MHz with a transmission gain of 0.8 and a swit,ch on to off transmission ratio of 40 dB is included in the 252 series for the construction of multichannel D/A converters. The 252KN1 integrated circuit is powered by two power supplies at USUp 6 volts 1%) and switches a current of up to 2 mt~. An analog memory circuit can b~ designed around the 252KN1 and 252UD1 integrated circuits (Figure 4.58). There are no regulators in the 252 series, and for this reason, one can use integrated circuit stabilizers from the 275 or 142 series as the reference vol- tage sources. A prerequisite for the transition to the production of D/A and A/D converters as functionally complete assemblies (even on one substrate) was the creation of a br.oad compon2nt base of operational amplifiers, comparators, analog switches and keyers, digital IC's as well as reference voltage sources. Success in thin film te~chnology is also of great importance, which made it possible to create sets of precision resistors. ~ -288~- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY 'h ~ . 1 T ~y~ ~ N ~ ~ ~ ~ m t~ b w . t~ _ 1 Q.~'T ti j Q~ ~ ~ ~i a ~ ~ w Q Qh ~h y Y ~e ^ y C h w ^i "y ~T w h ~ 1 ~ w ~ ~ ~ N O w ~ ~ N ~ J ~ .1 Q . ~~~b y ~ Q~ ~ ~ cv ey ~ . ~ T b ~ ~ OO Q~ ~ w N~ ~ ~ ~ w ~ eo t~ ~o ~ ~ ~ S N w ~ '7`. ~ N M ~ ~ CJ ~ ' ~i ~ Q y ~ ~ ~ ~ Q t ~ , ~ton b � ~w . V r ~ w0 Q ``NM~ o N ~ ao w'�' ~..'o Q~ ~ q ~ N ~f1 N ~ n ~ ~ N N N ~ N w ~ ~ ao ~ tp ~ .t~ ~ ~ ~ w N Nro a Q~a ; , Q~ ti O _ �r~l U . ~ A ro~ ~o ~ S ~ t! td @ w ~ ~ a; Q ~j 4 ~i' ~ C M+ ~p ~ ~ ^ N M J ~ ~ q ~C N V w Y ! 'rl & 7 ~ , ~ U! N Q' ~ t fn ~ w~ r-1 4 � cd ~ eo ~ b ~t~A n U N y K M �H t ~ w h ~ ; ~ ~ N ~ ' (0 ~ N ~'J J ~ ~ ~T r1 C~ - I~ ~ h ~ w w ~ ~ k Q o~O~,- ~ i N b U `v �ri ~ h ~ ~ ~ ` ~ N ~ ~ H , w ~ y ~v ~n s OO w ~ ~7 ~ y ~1 ~ ~ b V1 y u1 m o Q V Q N ~ O Mj ~ ~ N ~T o. s0 t~ b G~ 4~ ~ w ~ _ o~o ~ ~ 0~0 ~ N M J ~ ~ ` ~ p N ~ N Y ly MS N q b: ~O ~ O Q s ; a Q . C. q~ n b 4 n R - 4 M N w N M~ � N~ ~ ~ Q ~ N A ' ' ~ ~l' , J \ N ~ h ~ - w w N Q . . ~'a ~ - 289 - FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAI. USE ONLY Uln Y ~f ~hxl 2 27 26 3 4 27 4 S 25 , S 2 Q 4 .A' 6 . I 7 3 ~ 25U/lY1 22 g 762/lAJ ~ 4 zst~~ 8 2f ~ 1p y 14 UOUt 9 10 1! f9 6 C 4700 f0 f9 f2 f8 ~ AJ 1f f8 1d f7 7S0 ~PI _ 15 ~ 2 ~ Figure 4.56. B]~~k diagram of a 10 bit digital to analog converter, which converts to negative ~olarity. ~1) Af.f (2) R20 fir 14 U~ t pl 4 ~au _ , , - Kl yd r RZ ~ . . l.~. ~ 3~ S R6 RZ! ~2 RZ4 Af.Z iRl Qa VT1 VDf ~n ~AJ~ AI ~ ~ ~4, ' Kb Y2 A1 S VD2 A~ V.Df! . 2 w YDd f 2 J q ~AR I Af.3 I _ K3 ~ VT2 ~ VIS j A2 R4 AA 21 ~ ay,~~ 8 + ~ ~ UAx4 A4 ~3 K4 (~a~ . . _...J ~ b y ZS 2B f 1 6 7~2213 6 8lO1B1910B >Y f3 f6 f7 T8 1f .1,.~ ~y~vo ~r 6~ ( b ) a~ Figure 4.57. The 252KN1 four-channel switcher. a. Block diagram; b. Basic electrical schematic. Key: 1. Input voltage 1; 2. Output voltage 1; 3. Control voltag~ 1; 4. Control voltsge 2. - 290 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500080030-5 . . . . TA13L~ 4.8. Parameters of the 252PA1, PA2 and PA3 Integrated Circuit Converters IlepaMrrpd 46Rf1A1~ R6ZilA4 R6~fIA3 Parametere 252PA1 252PA2 2 PA3 ToKx pa~pAAoB, MA 2,bf0,12G 2~6f0,128 Bit ~~/2)~if0,29G (1/2If0,1�~ Currents ' is (I/4)/1f0,4~~ (~/4)/~~f~~2r ~ (I/8)~if0,8g6 ~l/8)~~f0.2 ~ . ~ 1~16j/Ifl,6 (1 16)/1if0,4~ � 1/32/if3,2 . (1/32)/if0,4 I/64;~~:~6~4�,~ ~I/6411f~~8^/ /e . (1/,128)l~~12,805 (I/128;/lf 1,66~ ~ I 2b6 / 3 jlo - (I%512)l1f6,4~~ CYNMBpH(i~ 87(OANO~ TOK paspa� b~0,26, 6~~~2b ~1) Aoa, MA . MaKa~Manbir~8 ypoaeeb exoA~~oro ~ 2~ nanpAmeFiNa ynpaoneaNa, B 4 ~ ToK norpe6nenpn no nene ynpaenc- ~3~ NHA OAIIHM (lA3~fAJ~OM, MA ~ ` Key: 1. Total input bit current, mA; 2. Maximum level of the input control voltage, volts; 3. Current consumption for the control circuit of a single bit, mA. , d qp ~ A7 ~ Ucon3 . c~ c5 _ U. Af.1 A2.f 8 A1.3 ~ p~ tlY1 4 ? q6 ~ k3 f9 f_ A2.Z I ~dr a + Za n A1.2� 6~ ~Af.4 ~y +!J ~;f7 UOUt Uy"~2 /~2 ~ K4 Ucon2 22 R4 RJ R9 Af0 R3 Gf CJ Re C4 ~~B ~nda U on~? _ Figure 4.58. Block diagram of an analog memory. 4.7. Analog Switches r~nalog switches (AK) are used for switching analog signals in analog to digital and digital to analog data conversion circuits. Moreover, analog switchers are used as switching components in telemetry, blanking, data multiplexing circuits, as well as choppers in operational amplifier circuits with signal spectrum con- - version [25]. - 291 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400540080030-5 FOR OFFICIAL USE ONLY The following parameters are the classificat3on criteria for analog switches: the turned-on switch resistance R~, the residual voltage Ures across the closed switch, the leakage current of the channel Ileak~ the resistance of the turned- off switch Roff~ the input iznpedance of the control circuit Rin, the switchable current Iswitch voltage UsWitch~~ the level of the control signal current Icon ~or voltage level Ucon~~ as Well as the turn on and off speed. Both bipolar and unipolar structures are used for the design of analog switches. An analog switch can be designed in the form of an individual IC, or it can be composed of several IC's and other components. Bipolar integrated choppers of the lO1KT1 and 124KT1 types (Figure 4.59), based on the series compensation effect, can be used as the switching elemeizt for the construction of precision analog switches. There are two identical n-p-n (in the lO1KT1 IC) or p-n-p (in the 124KT1 IC) integrated circuit transistors in these choppers, which are made on a single chip (so that the transistors of these IC's have a common collector and contain four p-n junctions: two emitter- - _ base junctions and two collector-base ~unctions). The integrated circuit transistors of the choppers have a high degree of identity of their characteris- tics, which assures a small mutual scatter in the remaining parameters (and in the absolute values of the param~eters in ~he compensat~d switch circuit) as compared to discrete transistors. Both transistors of such an analog switch are in the same state, and for this reason, a small scatter in the parameters is assured by the opposing configuration of the two transistor circuits with respect to th~ residual voltage and current. ~ s,rln ~ ~ ex In � 8 l~lf (/,lp Tf yD! q~ 8 3 d Y71 U ~p ry YDJ q~ 8 s ~ ( p Af d~e~x s I Af Oax t~r2 5 t 1 vr? Out a M q) ~a) At ~b) Figure 4.59. The lO1KT1 (a) and 124KT1 (b) bipolar integrated circuit chopper. = The lO1KT1 and 124KT1 integrated circuit choppers are made in a circular eight ~ pin package, while thP 162KT1 integrated circuit chopper, which is sir~ilar to the 124KT1 chopper in terms of its parameters, is produced in a flat pack. The main parameters of the lO1KT1 and 124KT1 integrated circuits are given in Table 4.9. The electrical schematics of the application of bipolar integrated circuit choppers are shown in Figurce 4.59. Here IC's inserted in parallel, series and p~~rallel-series switch configurations are .used as single switches. _ The given IC's can also operate 3n structurally compensated switching circuits, where an improvement in the characteristics is achieved by virtue of the special configuration uf the signal source and load. The major difficulty in the application of the switch components treated above using parametric compensation c�onsists in the fact that the control circuitry is - 292 - FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 FOR OFFICIAL l1SF: ON1.Y TABLE 4.9. Maximum Values of the Main Electrical Parameters of Various Types of Analog SwiLChes Parameters lO1KT1A 124KT1A 273KT1 143KT1 190KT1 190KT2 168KT2 Re~istance of~the switch - - 100 100 500 50 100 when "turned on", ohms Switch leakage current when "switched off", nA - - 100 20 100 50 20 Turn-on delay time, usec 0.03 - 1 2.0 - - 0.3 Turn-off delay timQ, usec 0.4 - 5 1.6 - - - Resistance between 100 100 - - - - - emitters, ohms Leakage current between 10 45 - - - - - emitters, nA ' Residual voltage between 50 100 - - - - - emitters, microvolts ~ Number ot channels 1 1 1 2 5 4 4 complicated, where this circuit should be isolated from the signal source and the load. The hybrid 273KT1 integrated circuit can serve as an example of a medium speed switch with an isolated control circuit. The switch control circuitry uses a transformer here. The parameters of the 273KT1 integrated circuit are given in Table 4.9, while its electrical schematic and recommended circuit configuration are shown in Figure 4.60. A signal supplied from standard TTL integrated circuits is suitab].e for the control of the circuit. T~ o Inl ' Out 1 DX 3 ~ 0ax f ' 174~ ' ~T0 YT7 ~ Ox 4 Af d~,~x � ~ b6rt f2 ff f0 1S~ Rp , > � ua.z ct Re ~ ' +U ~i v~J ~ra +Usupr ly Q~ ~b ) ~T VT? IC5 6 ~ld , 4 ~T9 ~ 1 N7 ' 1 ~pd VT4 YT10 ' f3 ~ oJ ~8~ Figure 4.60. The 2731KT analog switch. ~ a. Basic schematic; b. Circ;uit configuration. - 293 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400540080030-5 FOR OFFI('IA~. USF ONI,Y Analog switches using field-effect transistors have become quite widespread at the present time. Field-effect transistors with a controlling p-n junction are vol- tage switched and do not consum~ any control current. These devices are suitable for switching both currents and voltages, since they are galvanically decoupled from the control and signal circuits. Field-effect transistor switches are controlled by voltages having an amplitude of 10 volts. The output signal levels from standar.d TTL circuits have a range of 0.3 to 3�volts. For this reasor~, to realize a switch circuit, it is necessary in the ma~ority of cases to use level interface circuitry. In the switch using field-effect transistors, equipped with a control circuit and incorporated in the 284KN1 integrated circuit (Figure 4.61), the analog switching circuit is designed as a T-section switch, which takes the form of a combination of series- parallel and series switches; in this case, the series switches and the parallel switch operate out-o~-phase. ' ~05----.-~ When the serias switches are turned on, '3fS71 the parallel switch does not influence v~'~ the circuit operation because of the v~k fact that its resistance is high as compared to the resistance of the turned- R~ Rz v�' on switches. After the transistors of the series switches are cut off, the YTf R6 parallel switch transistor turns on, ps shunting the parasi~ic signal circuit v~s q~ , with a low resistance, where this cir- Y72 RJ cuit is due to the influence of the interelectrode capacitances of the 2~4,6J A4 y~~ series switch and the resistance of the f~� 9'~~' cut-off switch. In this case, a con- siderably attenuated signal acts on the next switch. Because of this, T- Figure 4.61. Basic electrical schematic section switches can operate at a high. of the 284KN1 switch. switching frequency (with low noise). A drawback to such a switch is the large value of the resistance when turned on. However, this resistance does not depend on the magnitude and polarity of the voltage being switched. AtOti transistors (metal.-oxide-semiconductor) are of the greatest interest for applications as analog switches. This is expl,~ined primarily by the high value of tlie input impedance of the device (up to 10 5 ohms) for a signal of any pc~larity, something which assures good isolation between the controlling and switched circuits. Moreover, the fabrication technology for MOS devices is much simpler than the technology for bipolar transistors and field-effect transistors with a controlling p-n junction, while the MOS structures themselves are suit- able for an increased level of integration. Enriched p-channel MOS devices (the channel conductance riaes with an increase in ~ the gate-source voltage) are most frequently used in a semiconductor design. - 294 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFIC[AL USE ONLY f'7> VO> YOc~ Yp3 l~04 Y~S VTf VD1 Y!/2 YDJ VD4 ~Z yT~ 2t y 5 ~ l~D1 f4 j 7 >J 4 1~7t y ~ T 3 ~ V72 9 Y02 " - ~rd - 13 7 ~ ~ ~ i~T4 VDJ n ' YT4 � ~y f~7~ _ ~ d 4 ~ Y~4 . e~ (a) aI (b) a1(c) Figure 4.62. Basic electrical schematics of voltage switches. ~ a. The 190KT1 five-channel; b. The 190KT2 dual two-channel; c. The 168KT2 four-channel switch. 4 5 ~T1d YT2f Y~2d VlZ4 Y770 p N7f 4 l 1~717 VTjpf ""O r ~ T14 i'T2 YT3 Vl8 /(~T1y ~7 V717. ~T?d 2 ~1 7YJ vr2~ ~ J vna ~ ~'6 ~rio . -~-Q . ' ~ n ' Q~ (a ) ~ 6 eX~ Inl k'igure 4.63. The 143KT1 dual channel Uconl ~ . B MOS switch. q xf~ nx2 a. Basic electrical ~ ~ naxz~' ochematic; U t~,~ ~2 ~'7z Out2 b. Block dia~ram. con2 ~b~ 41 The 190 and 168 series IC's can serve as examples of integrated circuit switches and k~yers using MOS transistors. There are two IC's included in the 190 series: the .190KT1 five-channel voltage switch (Figure 4.62a) and the dual two-channel 190KT2 switch (Figure 4.62b). These IC's make it possible to switch voltages of �-~9,5- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OF'FICIAL USE ONLY up to 25 volts. The cont.rol signal amplitude may exceed 6 volts. The 168KT2 four-channel switch (Figure 4.62c) switches a voltage of up to 25 volts at a switching frequency of up to 1 MHz. The design of circuits where TTL integrated circuits are used in conjunction with the 190 and 168 series IC's is complicated because of the incompatibility of the output signals of these digital IC's with the input control levels for the p-channel MOS switches. This drawback is eliminated in the 143KT1 two-channel MOS switch (Figure 4.63), in which the channel consists of the switch and the controller. The parameters of this switch are given in Table 4.9. The 143KT1 IC controller contains a circuit for matching the output TTL IC levels to the input levels for the MOS transistors as well as a logic amplifier with a push-pull output to provide for rapid charging and discharging of the input capacitance of the MOS switch. 4.8. Integrated Circuit Voltage Regulators High precision in radioelectronic equipment is assured by the stability of the transfer functions of all of the equipment sections, which in turn are dependent on the stability of the supply voltages. Voltage regulators are used to obtain the requisite power supply conditi~ns [28]. An integrated circuit regulator has the following main parameters. The voltage instabilixy ratio is measured as the ratio of the change in the output voltage ~Uout 1 to the change in the input voltage which caus~~es it. It is expressed in %/volt. Kins U - ~Uout100%/Uout~Uin� The current instability f actor is measured as the ratio of the change in the output voltage, ~Uout~ tc, the relative change in the load current which causes it and is expressed in Kins I - ~Uout U ~ Iout100%/Uout ~ ~Iout' The ripple smoothing factor.is measured as the ratio of the amplitude value of the input voltage ripple ~Uin to the amplitude value of the output voltage ripple. This fartor is most often expressed in decibels: Ksmooth � 20 log (~UinJ~Uout~ ~dB~� Moreover, to design the circuit configuration for integrated circuit regulators, it is necessary to know the power level dissipated by the device, Pdis~ the maximum input Uin max and the range of voltages to be regulated ~Uout' An important characteristic of a regulator is its speed, corresponding to the speed with which it handles ~umps in the input voltage and load currents. Integrated circuit technology makes it possible to create various regulating devices [2]: from the simplest parametric regulators, for which one of the ~unctions of an integrated circuit transistor is used, up to complex compensation type regulators (Figure 4.64). - 296 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 � ' FOR OFFICIAL USE ONLV An error amplifier (usually one of the saIn s~x types of aperational or differential 2 amplifiers with a gain of about 1,000) Uon + Out amplifies the potential difference Uref ~ 3 between a reference source and a center tap of a divtder. The voltage divider and regulating element are inserted in a negative feedback circuit for this Figure 4.64. Block diagram of a compen- amplifier. Because of the fact that sation type regulator. the gain is high, one can assume that the voltage at the regulator output is Key: 1. Error amplif ier; proportional to the transmission gain 2. Regulating element; of the divider and the reference voltage 3. Divider. level: . ~ Uout - Uref~Rl + R2)/R2 where Uref is the reference source voltage. One of the types of zener diodes or a circuit based on current generators [2] is used as the element genera~ting the reference voltage. The circuit which is depicted in Figure 4.64 operates as follows. An increase in the input voltage by the amount ~Uin should cause an increase in the output voltage of the regula- tor by the amount ~Uout' But the output signal increment is fed through a divider which attenuates it by a factor of R2/(R2 + R1), to the input of the error amplifier. The amplifier should generate a signal for reducing the current through the regulating element and thereby substantially compensate for the anticipated error at the output ~Uout� The regulating element can consist of one or more transistors, connected in a Darlington configuration. The number of transistors depends on the load current, the output power of the amplifier and the quality of the transistors themselves. As a rule, transistors are not connected to an integrated circuit regulator in the case of low load currents. With load currents of 1 to 5 A, it ie necessary to connect two to three power control transistors to the IC. At the present time, several series of integrated circuit regulators are being produced, both semiconductor and h~brid, the electrical characteristi.:s of which are summarized in Table 4.10. ~ The 275 series of hybrid integrated circuit regulators are a set of IC's with � fixed output voltages, ranging from 1 to 24 volts. There are negative voltage regulators in this series. The use of temperature compensated internal feedback dividers is to be noted as a special feature of the 275 series of regulators. Such an approach makes it possible to reduce the impact of the ambient temperature on circuit operation, but at the same time reduces the applications flexibility of the device. In order to be able to make some ad~ustments, the center tap of the divider is brought out from the regulator circuitry. The 275YeN1-6A,B positive voltage regulators (Figure 4.65) differ from one ~ another in the zominal values of the divider resistors R11, R12 and R13. The - 297 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 FOR OFFICIAL USE ONLY 8 65f/ 423 13 f . R2 ~T~i . D~ l'D3 ~DS 1~D4 8 T. R~ C! O1 R4 f4 f0 vr~ rs v76 f3 c2 v� v~< v~e RJ2 ~ qf ~0 R3 ~ B 4 ~ R~ RS Rf3 ~ ~ 9 !Z 3 ,~f R~p 9f0 a) (a) 1412 (b) Q) Rlimit Figure 4.65. The 275YeN1-6A,B positive voltage regulators. a. Basic electrical schematic; b. Main circuit configuration. regulating element in this circuit consists of matching transistor VT3 and tran- sistors VT4 and VT5 which are connected in parallel. The error amplifier is designed around a differential stage (transistors VT7 and VT8) and a matching transistor VT2. The operating current of transistor VT1 is determined by the bias produced by means of diode string VD1 and VD2, as well as resistors Rl and R2. Transistor VT1 plays the part of an active load for the amplifying transistor. The built-in voltage divider is provideci with a temperature stabil- ization network (diodes VD4 and VDS, as well as resistors R10 and R13). Resistor R3 serves for the leakage of the collector-base currents of the parallel transis- tor pair VT4 and VTS. The regulator circuitry includes a protection circuit, designed around transistor VT6, and resistive divider R4 and R5. The protective circuit operates with an external resistor Rli~. Capacitor C1 is intended for eliminating self-excitation of the regulator. The output voltage can be ad3usted by varying the resistance of the interna~ divider by means of external resistors, which can be connected to pin 14. To protect the IC output against excessive current when its load is short cir- cuited, pins are provided for the connection of the limiting resistor Rlim� The load current, in passing through resistor Rli~, produces a voltage drop across it which is applied between the base and the emitter of transistor VT6. The load current increases until the voltage drop across resistor Rlim ~about 0.7 volts) turns on transistor VT6, which,limits the base current rise in transistor VT3. Thus, the rise of the emitter current of the regulating element is stopped (i.e., the output current of the integrated circuit). The nominal value of Rlim ~~~dB on the level of the permissible load current and is determined from the formula: Rlim � Ube~iload/Per V/Iload/per ~'~~Uin - Uout~~~Pdiss.per ~ 1.3), where pdiss.per is the permissible power dissipation of the regulator. - 298 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 FOR OFFICIAL USE ONLY 9 8 11 352f0 12 f4 YIJf Q ._L.. 1~T4 p 2 l'D3 B YT3 pf /~x YTf vr6 In 3 2'-~? ..Otlt ~ 4 R 1 im ~ vrz ,~a vrs >2 o,~ g A~ C2 C1 3 R5 rF7 4 0,1 7 8 6 f3 7 6 Q~ l S~ f f3 . 61 ~b) Figure 4.66. The 275YeN11:,8 voltage regulator. a. Basic electricdl schematic; b. Main circuit configuration. In contrast to the circuit depicted in Figure 4.65a, in the circuit of the 275YeN11A,B regulator with an output voltage of +12 V(Figure 4.66), the mis- match signal is amplified by a two stage circuit (transistors VT6 and VT2). The voltage at the emitter of transistor VT6 (the reference level) is clamped by zener diode VD3 and the control signal is fed to the base of this transistor. The 275YeN7A,B (Figure 4.67) negative voltage regulators ~Uout -'6 volts) are similar in terms of their structure to the circuit shown in Figure 4.66a. How- ever, the active elements are of the other type of p~larity, and'the regulating element (transistors VT3 and VT4) are designed in a Darlington configuration. The 275YeN12A,B negative voltage regulator is shown in Figure 4.68, while the Y~asic circuit configuration is similar to the circuit shown in Figure 4.67b. 7 654 32 f '!4 - ~T4 ~Df Rf ~3 R7 1~D2 VT5 VTf V7d R3 � YT7 ~T6 vn qe In 4 Out ~ 2 8x ~~I ea.r N4 R6 0 R9 ~ ~y 9 >f B 9 fC !3 f/ a~~a) (b) Figure 4.67. The 275YeN7 negative voltage regulator. � a. Basic electrical schematic; b. Main circuit configuration. , - 299 - FC~R OFF'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FnR OFHICIAL 11~F. UNI.Y Semiconductor reguZators have significant advantages ov~r hybrid ones, the active elements of which are discrete components. The merits of semiconductor regulators are expressed in the incre~sed stability of the output voltage in a ra~ge of temperatures, with changes in the load and ingut voltage. This is obtained by virtue of the gain reserve and the thermal coupling which exists in semiconductor circuits. 9 1f ~ 3 5 2 f0~ !2 14 - YT4 VDf ~ 1 ~ra VD2 ~'T3 VD3 R7 A9 t vrf v~ vTS t~rs. Yn ,vm 4 vr7 an ~ R3 AS R6 R8 7 6 4 ! Figure 4.68. Basic electrical schematic of the 275YeN12A,B negative voltage regulator. The 142 series of semiconductor IC's are compensation type regulators, which have a circuit for protecting against failure in the case of a load short circuit. An external divider is used in the 142 series regulators to ad~ust the output voltage. Such a circuit configuration makes it possible to extend the range of variable output voltages. A divider with a large division ratio degrades the value of the regulation factors, however, in a semiconductor circuit one can realize a gain reserve even with a large regulation range. For this reason, the temperature stabilization coeff icient for the 142 IC series is no worse than for the IC's of the 275 series (Table 4.10). The reference voltage supply circuit generates a ref erence voltage at a level of approximately 1.8 volts. Such an approach extends the control range of the output voltages of the IC in the low value range [26]. Moreover, the changes in the voltage across the emitter-base junction of transistor VT3 (-2.2.mV/�C) and the positive gradient of the voltage change across zener diode VD1 are compensated by means of diodes VD2, VD4 and the base-emitter ~unction of transistor VT2, which have a negative temperature coefficient of -2.2 mV/�C. A zero temperature coefficient can be obtained through the correct selection of the nom~nal values of divider resistors R1 and R2. ~ In the 142YeN1-2A,B voltage regulators (Figure 4.69), transistors VT6 and VT8 - which are connected in a Darlington configuration, serve as the regulating element. The error amplifier is made as a differential stage (transistors VT3 300 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY 4 ~ + Y/1 YT4 1 `7B -O~ Yl2 vT6 � !4 ~llt ~ 2 a~ ~ In ~J ~ A> V79 ~ Bx f6 ~ s f0 . f2 , ~T3 f2 C7 . ,G2 i~15 477 YD.~ ' � 4 ' 1 f0 9 1'D2 R3 R4 ~ S N3 ~ (~f - q~S~ ~ , ~b~ .QJ ~ ' � Figure 4.69. The 142YeN1-2A,B voltage regulator. a. Basic electrical schematic; b. Main circuit configuration. and VTS), the loads for which are field-effect transistor VT4 and the base circuit of the regulating element~. The differential amplifier is configured so that its full differential gain can be used. Transistor VT9 performs the function of a regulator circuit protective element in the case of an output short-circuit. The input for the electrical turning off of the regulator or feeding control signals to it uses transistor VT7. In the normal mode, transistor VT7 is turned off. When a positive pulse is applied (for example, from a TTL switch), it turns on and cuts off the base current from transistor VT6, and the regulating transistor turns off. The current sensor, resistor R1 (Figure 4.69b), is inserted in the circuit of the load current between the base and the emitter of transistor VT9 (Figure 4.29a). - When the load current exceeds the set value, transistor VT9 turns on and shunts the regulating element. The nominal value of resistor R1 is chosen as a function of the maximum output current. Curves for~the ripple smoothing factors K~m for the 142YeN1A,B and 142YeN2A,B integrated circuits as a function of the ripple frequency of the power supplies and output v4ltages are shown in Figure 4.70a and b, while the switching and settling times are shown in Figure 4.70c and d as a function of the load capacitance. The voltage traces of a regulator for the case of a pulsed change in the input voltage are shown in Figure 4.71a, while the traces for the case of a pulsed change in the output current are shown in Figure 4.72a. The curves for tl = f(C1); t2 = f(C1); (A1/a) = f(C1) and (A2/a) = f(Cl) for a change in Uin and Iload are shown in Figure 4.72b respectively. The given characteristics make it possible to estimate the speed of the regulators as a function of the nominal value of capacitor C1. - 301 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 hOR OFFIC'IAI. U~N: ONI,Y TAIiLL' 4.10. The Parameters of the 142 and 275 Series Integrated Circuit ltegalators out~ V Uin, V MA ~p x ~2~ 'Itin N(~ Vems' B U~z~ B 1 jm ~ ~ ~pe of I I~om. ~~ax. 4~~ ie ~~o X 142EH1 A 3...12 9... ~ 1b0 0~8 0~8 0~5 0,01 g o~l 0~2 1426H2 A 12...30 15...9 bU 160 0,8 ~'3 ~=g 0,01 G 0.1 0~2 0,44 27bEH1 6 1~2f10% 6...9 30 b0 0~6 0~07 0~25 0_04 27bEH2 ~ 2~4 f 10�~ 7...12 20 b0 0~6 ~ 0.09 0~2b n_oa 27bEH3 ~ 3~Of10% 7~b...12 20 60 O~G 0~19 0~25 p.~ 0_OZ 276EF14 G 4,Of10',6 8,b...l 2~ b0 0~5 0,1 0,25 0,~ 0~02 276EH5 ~ 6,Of 10�~ 9.b...14 20 60 O~b 0~ 12 0~ Ib 0_02 276EH6 s 6,Of10�~ 10~5...1b 20 60 O,b 0~12 O~Ib .Q~~ 0_02 Q76EH7 6 -6,Of10�r~ 10,6...1 20 60 0,5 O~12 O~Ib 0,~ 0,02 27bEH8 6 6,3f10�~ IO~b�~Ib 20 50 O,b 0~12 O;ib 0,02 875EH9 6 -6,3f 10�~ IO,b...lb 20 b0 O,b 0,12 b~ lb 0~03 27bEH10 9,Of104613,6...19 20 60 O~b 0~1b p~~ O.OI O~C2 0,01 275EH11 6 12,Of10~ 16~5...24 15 b0 O~b 0~2 0,02 0,01 276EH12 6 -12,Of10�~ 16,b...24 I6 b0 O,b 0~2 0~1 U,02 0lOl 27bEH13 & 12,6f1096 17...?A 15 50 O~b 0~2 0~1 Q7bEHl4 ~ -12~6f10~ 17...2~1 Ib b0 O,b 0~2 p~~ 0_Ol 0~02 Ib b0 O~b 0~22 0 ~ 0~01 276EH15 6 -16,Of10�~ 19~6... . 276EH16 6 24~Of109628,b...~ 6 36 O~b 0~32 0~1 0~02 Key: 1. Powex dissipation at 25� C, watts; 2. Temperature coefficient, Uout~ ~�~~C. 302 - ' FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 I~QIt OFFICIAI, ll~F; ONI.Y ~cr~d0 ~1~ K~~.~~J (1) 60 141fHfA,B ' 60 142fN1A,6 y~ I41fH1A,6 40 ,UdX~10~ VeX'~4~8 20 - u~�x 3B ~3) 20 - U~e?x-1z0 (4) gf ~ ~D 10Z ~~'t! l{> > 90 ~0= ' fd~lr!'I! ~a)" al (b) ~1 KHz - t~~~NKC ~2~ tytt~ MXC ~5~ ~ 4 141fN1A,6 4 f42EN7A,B T ~ 10 Z ' - f42ENfA,D >~l?�NfA,B , 0 , fOZ >04 C,nO~ 102 10'' C,~~ ~ (c) QI pFd (d) a~ pFd Figure 4.70. The ripple smoothing factor cf regulators plotted for the 142YeN1 and 142YeN2 integrated circuits as a _ function of the supply ripple frequency (a and b) and the switching time [2] and settling time [5] as a function of the load capacitance (c and d). Key: 1. Ripple smoothing factor, dB; 2. Switctiing time in microseconds; 3. Uin = 20 volts, Uout = 3 volts; 4. Uin = 40 volts, Uout - 12 volts; 5. Settling time in microseconds. Uexmax Uin max t, microseconds t,yMC ~ . o,rur0 a - M ~~d~ ~ icrovolts U U~ ~ ~ ~ l ou ~ ~ ~ l 5Gl7 / l tx(Ul w ~ ~ t l!1 ~ / t~(/I 150 UE�u ~ t t~(U! Uout ' t2 ~ t~ /(I~ t~U! 0 (a) t f0Z fOJ f0y; C~,~4+ PFd � a~ (b) a~ Figure 4.71. The change in the input voltage: a. Traces of the voltages and currents; - 30 3 - FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 h~,k uh~r~~t'~~~t. t~,h: uNt,~ Key to Figure 4.71. [cont.]: b. The time constants for the 142YeN1-A,B (solid curves) and 142YeN2-A,B (dashed curves) inte- grated circuits. ~/a _ ~ _ ~ ct-o ? r�->sHC ~ /M max 1D0 ~1/M maX 1NK~ - - - - - - ~ t t~ uFd 5~ _>D~K` ~ ~ Uout A ~ t~ b ~a~ t D ~2 ~~b) c~'n~' C) Figure 4.72..The change in the output current: a. Traces of the voltages and currents; b. The time constants as a function of the load capacitance for A1/a (solid curves) and A2/a (dashed curves). YD1 ,QB146 fQ ~ 4 t~ fJ Out /laar ea y ~ 4 GSw~r n f4 ~ 3 f4 Af 2 Cf + a~ ~t In ~ As Uout ?K TON a' c~ R~ ~ e ~1 + � 43~r 8 ~ p4 ~ A2 R~ G2 1, f0 Figure ~a.73. Modified circuit of a Figure 4.74. Schematic of a regulator 142YeN1-2A,B integrated with~improved output circuit voltage regulator . characteristics. with a ahort circuit pro- tection circuit made using an external divider. Protection against a load short-circuit is accomplished by means of a divider (resistors R1 and R2 which control the base voltage of transistor VT9) (Figure 4.69a) in the voltage regulator based on the 142YeN1-2A,B integrated circuit (Figure 4.73). Such a circuit makes it possible to increase the speed of the short circuit protection circuitry. In this case, the nominal value of resistor Rlim can be computed from the equation: Rli~ = 0.5 V/Iout max' Where Iout max is the maximum value of the output current. - 304 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 H'UR OFHICIAL USE ONLY Uin 1 ~11i U~`' ~"R~os~ Uout - ~ fQ UM.~ Vea z 4 >3 R3 +Uin2 ~ ~a 3 qk + 2dr ,7> A> > _ ~ ~iK ~ as *c2 R2 e 10 , f,1 f0 43K t~, ~ ti, Figure 4.75. Schematic of a regulator with a reference voltage - source powered from an external regulated voltage supply. oe~r ~ ~ ,~X In 1 J vr2 N6 ut I VT1 Rz '05 ~ 8 y~ 2T9Cdh 1,7 f7900A 1~ ff !7. C1 ~ 4 16f1 C2 Af 2 R4 YDf fp~ ' i~D> 4f0 ,Qdf4A 13 A1 Z Cf ~M � ,Q~4A 4 ~6 VTf d ~ R~ 1T4B3N 1'IK C2 ~pp A3 d. R~ YD2 R2 f00 f,2H Ir~lOJ 150 2K A4 Figure 4.76. Schematic of a parallel Figure 4.77. Schematic of a negative volta~e regulator. voltage regulator. The characteristics of regulators can be changed by incorporating several die- crete components in the circuitry. An improvement in the values of the coeffi- cients Kload U and Kload I is achieved in the regulator circuit ahown in Figure 4.74 by inserting elements VD2 and R4 in place of the output resistive divider. In this circuit, the change in the output voltage ~Uout ie fed to the input of the error amplifier (pin 12) through the zener diode. The output voltage of the x-egulator is: Usm:�UVD7 "~'Von~ Uout - UVD2 + Uref' � where U~2 is the zener diode voltage and Uref is the internal reference source voltage. Diode VD1 is incorporated in the circuit to protect the regulator at the moment the input voltage is disconnected (the voltage acroes capacitor C2 ' can prove to be excessive). The average value of the relative instability of the output voltage in this circuit with a change in the input voltage of 1 volt amounts to 0.01%/volt, and with a change in the output current of from 5 to 50 mA, is equ,al to 0.03%. An improvement in the relative instability is achieved in the circuit of the regulator shown in Figure 4.75 in that the reference voltage circuit is supplied from an external regulated voltage source, for which a second regulator designed -305- FOIt OF6'ICIA~. USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R400540080030-5 FOR OFFICIAL USE ONLY using the same circuit made be used. The condition Uinl Uin2 $hould be sat- isfied for the given circuit. A special feature of the parallel regulator circuit of Figure 4.76 consists in the fact that the current consumed by the IC fro~ the input voltage source re- mains constant with a change in the output current. The circuit operates so that with an increase in the current, the output voltage increases by a certain amount and is fed to the input of the error amplifier (pin 12), which in turn leads to an increase in the current in the regulating element of the IC, in parallel with which a network is connected which consists of zener diode VD1 and the emitter-base ~unction of transistor VT1. The total current of diode VD1 and the regulating element of the IC flows through resistor R2. A change in the current of the regulating element entails a reduction in the diode current of VD1 and a decrease in the base and collector current of transistor VT1. Consequently, th~ changes in the load current and collector current have different signs. ' A negative voltage regulator can be constructed using the 142YeN1-2A,B regulators (Figure 4.77). Just as in the preceding case, the 142EN1-2A,B integrated cir- cuit is inserted in parallel with the load and transistor VT2 plays the part of a damping resistor, the dynamic resistance of which changes as a function of the ?.oad current. The regulatimg element of the IC operates as an amplifier having R2 as a load. With a change in the load current, the output voltage changes by the amount ~Uout~ Which is fed through divider R6, R7 and R8 to the ~ input of the error amplifier, and upon being amplified, appeara across resistor R2. Transistor VT1 amplifies this voltage and controls transistor VT2 (i.e., the load current). The current in transistor VT2 changes so that the change in the voltage in the load is compensated. A bias voltage is produced by means of diode VD2 for transistor VT2. The resistor serves to produce the requisite working current for diodes VD1 and VD2. The minimum output voltage level of the regulator is limited by the reference supply voltage. In order to extend the output voltage range, one must use the circu it shown in Figure 4.78. This regulator is designed around two integrated circuits, which operate from unregulated power supplies with different polarities. The circuit provides for output voltage regulation from zero up. One IC serves . to regulate the voltage across the load, while the other serves to feed bias to the common lead in the first circuit. The amount of bias is equal to the internal reference voltage of the IC or exceeds it. In many devices, a regulator is needed having a bipolar output voltage (for example, to power circuits using operational amplifiers). For these purposes, one can employ the circuit shown in Figure 4.79. The circuit consists of two regulators for different polarities, designed around the 140YeN1-2A,B integrated circuits, which are connected together. The negative voltage regulator circuit is simi.lar to the circuit shown in Figure 4.77. The output current of the regulator is limited by the power dissipation of the IC, but it can be increased if an additional power transistor is introduced into the circuit. -306- FOR OFFICIAL lJSE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400540080030-5 hOR OFFICIAi. USE ONLY yn2 ~ dx1 A ~xf KQf05 R3 f,0 7 ~x f aJ SuX f Rf ~ ~ y VT3 1 t� k f3 JK * ~ 1f f2 ZT9306 pd ~ 4 f2 ~3 Z ? Rf Q4 2x ~ ~ 1 R4 C/ 5f0 9 CJ 10K ~ YDf ~ ef4A 4 1Q a ~ NS ~ 27B03Q VDf 4dK � ~ f,2K ~ ~~t ~ . ~qfo5 saxl ' 4 1 C4 Ox~ ~Z 1Z R6 C4 1 dx2 p A2 ~ 2 fir ~ � t ' ? . f3 qs 1,1K , d a> spp ' ~ f0 ~,r~r2~ f740dN Figure 4.78. Schematic of a voltage Figure 4.79. A regulator with a bipolar regulator with an expan- output voltage. ded output voltage range. The circuit of a regulator with an increased output current is shown in Figure ' 4.80. The maximum output current level can be determined from the equation: Iout max = Iouth2le' 1�dz m~s 1"~'~ale+ where Iout is the regulator output current and h21e is the current gain of transistor VT1. It is frequently neceasary to produce a regulated voltage which exceeds the maximum permissible input voltage for the IC. One must also use'several additional outboard components in this case. A circuit is ahown in Figure 4.81 in which the increase in the output voltage range is set by feeding a positive bias to the common lead of the IC (pin 8). This positive - ~ bias is provided by zener diode VD2. The regulated output voltage for the given circuit is determined as follows: . Uout Uref ~Rl + RZ) /Rl + U~2 where U~2 is the breakdown voltage of zener diode VD2. In this case, one must make sure that I~2 > IVD2 min (here, I~2 min is the minimum breakdown current of zener diode VD2). Keyed type voltage regulators (Figure 4.82) are used to increase the ef.ficiency of regulators op~rating at elevated output currents (especially if the voltage drop across the regulating element is great). Tran- sistor VT1 operates as a switch (either saturated or cut-off). When it is turned on, diode VD1 is cut off and the current in the inductance coil L1 increases: i !c = ~ Udt. 0 Here, U is the voltage applied to the inductance. ~ -307- FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY Out Out ~ v� ee?X ~ v~~ dbrx ~ In f790QA 35 ~ 4 f3 ~ A3 R! ~ 4 SQ f0 : Af >2 C2 q3 ~ f0 �~b f3 o z 2 q f4 ~ A~ fi RS T~ YDY YK ~ P Q~~ R2 d 6 Figure 4.81. A regulator with an in- 43K ,2 creased input and output ~ voltage. Figure 4.80. A regulator with an in- creased output current. The current through inductance coil L1 charges capacitor C1, which is connected to the inverting input, and feeds the e.v In ~T~ i~ u~,x current to the load. The output voltage vo�'~ increases until (capacitor C1 is charg- + out ing) the reference voltage is exceeded Uref a~ at the nnninverting input of the error - R2 amplifier. At this point in time, the . error amplifier cuts off the power to af vo~ the base of transistor VT1 and the unreg- ulated input voltage is cut off. The energy stored in inductance coil L1 Figure 4.82. A keying type regulator. serves as the reason for the appearance of the voltage pulse Ug, which is nega- tive. This pulse is absorbed by~turned on damping diode VD1. The current of the inductance IL is delivered to the load. When the current in the inductance coil falls below the load current level, capacitor C1 begins to discharge and the level of the output voltage (and conse- quently also the voltage at the inverting input of the error amplifier) falls off. When the voltage at the inverting input U~ drops below the reference voltage, the amplifier triggers the transistor switch (transistor VT1) and the cycle ' repeats. The output voltage of a switched regulator f luctuates about the voltage U ut - Uref ~R2 + Rl)/R2 with an amplitude which is determined by the sensitivity o~ the error amplif3er and the ratio of the nominal values of divider resistors R1 and R2. The 142YeN1-2A,B integrated circuits are used in the circuit of the switched regulat~r (Figure 4.83) as the device which controls transistor switch VT1. The self-oscillating mode in this circuit is determined by the 142YeN1-2A,B IC, choke L1, capacitor C2 which is inserted in parallel with the load, diode VD3 and zener diode VD2. The use of p-n-p transistor VT1, which does not require an additional power supply to cut off the switch, simplif ies the circuitry. The voltage across diode VD1 provides for cutting off the switch. The circuit has the following parameters: average value of the relative instability of the out- put voltage with a change in the input voltage by 1 volt: 0.05%/V; with a change " in the output current from 10 to 500 mA: 0.1%. -308- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400540080030-5 b'l1R l1F'b'1('1:~1. l ~~6' l)N1.~ ~ YD1 Y7f Lf 1l75 f1AG1~'~l ~J ~Nx BX b . - . ,ax A3 ~2 ' v~ Rf ~ Af 270 !6 fJ R4 4~7A' f0 f Be?X 56 8 2 Cl 2 A~ BS ~P3 l76 ~dK a~ f2K ~ 7ZOK 1.3 d ~Y 3i~K ~ ~ao ~ v~2 vva 'P7 Figure 4.84. A threshold gate based p~ry~y 2~2A ~2K on the 142YeN1-2A, B integrated circuit. Figure 4.83. A keying regulator based ~en designing a switched regulator, one on the 142YeN1 integrated ~uat determine the values of L and C. circuit. The following regulator characteristics are specified for the calculation of L and C: the ripple level AU, the output voltage Uout~ the frequency f and the maximum output current Iout max� By solving equation (4.7) for the inductance L, and assuming Iout max � 1.3 IL, we obtain the value: L = [1.3(Uin - Uout~~Iout maxfJ~Uout~Uin). (4.8) As was shown earlier, regulator circuits have an internal amplifier with a gain of about 1,000 and an output current of up to 150 mA. Moreover, a regulator is suited for operation at high supply voltages (up to 40 volts), especially if it is equipped with a heat sink. The internal source provides a reference vol- ~ tage which does not depend on temperature or power supply voltage changes. All of these factors make it possible to use the 142YeN1-2A,B regulators as'either an amplifier or a threshold gate (Figure 4.84). - Its threshold voltage is the reference element voltage. The minimal output vol- tage of this device is governed by the load resistance, the internal load resis- tance and the internal reference voltage source resistance: Uout min ~Uref 1~R1oad~~Rload + R1~' where R1 = Ri � R2/(Ri + R2'), while resistors R1' and R2" [sic] comprfse the ~ reference source voltage divider. The maximum output voltage can be defined as: Uout max - Usupply - Ure where Ure is the minimum voltage drop across the regulating element. -309- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 h't)tt l)F'b'il'IAI. t~1b: l1N1.1' Bibliography l. Gram, Proyektirovaniye i primeneniye operatsionnykh usiliteley" ["Design and Applications of Operational Amplifiers"], Moscow, Energiya Publishers, 1974. 2. Shilo V.L., "Lineynyye integral'nyye skhemy v radioelektronnoy apparature" ["Linear Integrated Circuits in Radioelectronic Equipment"], Moscow, � Sovetskoye Radio Publishers, 1974. 3. Marshe Zh., "Operatsionnyye usiliteli i ikh primeneniye" ["Operational Amplifiers and Their Applications"], Moscow, Energiya Publishers, 1974. 4. Gutnikov V.S., "Primeneniye operatsionnykh usiliteley v izmeritel'noy tekhnike" ["The Applications of Operational Amplif iers to Instrumentation Equipment"], ~ Moscow, Energiya Publishers, 1975. 5. Polonnikov D.Ye., "Reshayushchiye usiliteli" ["Resolver Amplif iers"], Moscow, Energiya Publishers, 1973. 6. Akmentyn'sh Ya.Ya., Zheyvome O.G., et al., "Integral'nyy operatsionnyy usilitel' s ponizhennoy potreblyayemoy moshchnost'yu" ["An Integrated Circuit Operational Amplif iers with Reduced Power Consumption"], ELEKTRONNAYA ~ PROMYSHLENNOST' [ELECTRONICS INDUSTRY], 1975, No 11, p 35. 7. Aleksenko A.G., Didenko V.I., Lebedev A.A., "Chuvstvitel'nyye integral'nyye komparatory" ["Sensitive Integrated Circu it Comparators"], "Mikroelektronika", Edited by A.A. Vasenkov, Moscow, Sov. Radio Publishers, 1973, Issue 6, pp 190-201. 8. Lebedev A.A., "Ispol'zovaniye vzaimnykh komponentov i blokov dlya povysheniya bystrodeystviya integral'nykh komparatorov napryazheniya" ["The Use of Complementary Components and Units to Increase the Speed of Integrated Circuit Voltage Comparators"], ELEKTRONNAYA PROMYSHLENNOST', 1975, No. 11, p 20. 9. Akmentyn'sh Ya.Ya., Vartin' V.R., Matavkin V.V., Shenin' A.E., "Komparator napryazheniya 521SA1" ["The 521SA1 Voltage Comparator"], ELEKTRONNAYA PROMYSHLENNOST', 1974, No. 4. 10. Akmentyn'sh Ya.Ya., Vartin' V.R., Matavkin V.V., Shenin' A.E., "Komparator napryazheniya 521SA2" ["The 521SA2 Voltage Comparator"], ELEIiTRONNAYA PROMYSHLENNOST', 1974, No ~0. 11. Kerekesner I.P., Rysin V.S., Timonteyev V.N., Tkachenko V.A., "Analogovyy umnozhitel' tipa 140MA1" ["The 140MA1 Analog Multiplier"], ELEKTRONNAYA PROMYSHLENNOST', 1974, No. 4. 12. "Spravochnik po vysshey matematike" ["Reference Book on Higher Mathematics"], Edited by M.Ya. Vygodskiy, Moscow, Nauka Publishers, 1970. 13..Renschler E., "A New Basic Building Block Linear Four-Quadrant t~tultiplier",' in Proceedings of the IEEE Linear IC Clinic, New York City, March 24, 1969. - 310 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500480030-5 h(11t l)M'M1( IAI, l~~M ()NI.Y 14. "Application Data. Data Book", Motorola Company, 1969, MC 1496. 15. Khokhlov B.N.,"Dekodiruyushcheye ustroystvo tsvetnykh televizionnykh priyemnikov" ["A Decoder for Color TV Receivers"], Moscow, Svyaz' Publishers, 1973. 16. Sukhov N.N., Oldin A.F., Chistov V.M., "Primeneniye IS serii 224 v talevizore tsvetnogo izobrazheniya" ["The Applications of the Series 224 Integrated Circuits in Colqr TV Receivers"], Moscow, Sovetskoye Radio Publishers, 1976, (The Series "Elementy radioapparatury" ["Radio Equipment Components"]). 17. Malyshev I.V., Tubeyev F.Ya., Arakelyan S.G., Kravchuk I.F., "Poluprovodnikovyye IS hcya priyemo-usilitel'nykh traktov radioapparatury" ["Semiconductor IC's for the Receiving and Amplifying Sections of Radio Equipment"], ZARUBEZH. ELEKTRON. TEKHNIKA [FOREIGN ELECTRONICS ENGINEERING], 1976, No. 18. 18. Zubachev S.G., Chaykin I.P., "Moshchnyy usilitel' nizkoy chastoty" ["High Power Low Frequency Amplif ier"], ELEKTRONNAYA PROMYSHLENNOST', 1974, No .0, p 38. 19. Shakhgil'dyan V.V., Lyakhovkin A.A., "Fazovaya avtopodstroyka chastoty" ["Phase Locked Loop Frequency Con*_rol"], Moscow, Svyaz' Publishers, 1966. 20. Smirnov B.N., Trayto B.G., Trof imov M.M., "Integral'nyye skhemy giratornogo usilitelya" ["Gyrator Amplif ier Integrated Circuits"], ELEKTRONNAYA PROMYSHLENNOST', 1973, No. 10, p 33. 21. "Spravochnik po tsifrovoy vychislite'1'noy tekhnike" ["Digital Computer Engineer- ing Handbook"], B.N. Malinovskiy, V.A. ~4leksandrov, V.P. Bogan, Ye.N. Briokhovich et al., Kiev, Tekhnika Publishers, 1974. 22. Smolov V.B., Fomichev V.S., "Analogo-tsifrovyye i tsifro-analogovyye nelineynyye ustroystva" ["Analog-Digital and Digital-Analog Nonlinear Devices"], Leningrad, Energiya Publishers, 1974. 23. Zhulla R.N., Kenyausis A.M., Martsinkyavichus A.K., et al., "Analogovyye gibridnyye integral'nyye skhemy serii 240" ["The 240 Series of Analog Hybrid Integrated Circuits"J, ELEKTRONNAYA PROMYSHLENNOST', 1975, No 8, p 50. 24. Nikolayevskiy I.F., Igumnov D.V., "Parametry i predel`nyye rezhimy raboty . tranzistorov" ["Parameters and Ultimate Operating Modes of Transistors"], , Moscow, Sov. Radio Publishers, 1971. 25. Stepanenko I.P., "Osnovy teorii tranzistorov i tranzistornykh skhem" ["Funda- mentals of Transistor and Transistor Circuit Theory"], Moscow, Energiya Publishers, 1967. . 26. Dodik S.D., Poluprovodnikovyye stabilizatory postoyannogo napryazheniya i toka" ["Semiconductor DC Current and Voltage Regulators"], Moscow, Sovetskoye Radio Publishers, 1962. , - 311. - ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 FOR OFFICIAL USE ONLY CHAPTER S. PROVIDING RELIABILITY OF IC [Integrated Circuits] IN THE PRODUCTION AND ASSEI~BLY APPARATUS 5.1. Dpsign-Technological Principles of High Reliability High reliability of semir,oaductor IC is one of main reasons they became the rasis of modern radioelectronic apparatus. The hign reliability of IC is insured by the group method of producing IC elements, by a stoaller number of interelement connec- tions and the lower level of poxer consumed. In the group production method, all IC elements are ma.nufactured in one technologi- cal cycle under rigidly controlled conditions, and with a minimum use of m~nual labor. The physio-chemtcal compatibility of materials and processes provide equal reliability of all IC elements. The reliability of the functional device, assembled with discrete parts~ depends on the quality of the complementing electric-radio elements (ERE) which are manufactured at many enterprises at~different times on dis- similar equipment. The connections between the contact pads on the semiconductor IC chip are made by thermocompression (or ultraeonic~ Welding. Yacuum sgraying of metal and thermocompression xelding p~ovide a reliable connection of the elemerrts. If xe compare a usual unit and an integrated circuit containing a thousand equiva- lent ~t'E~ then in integrated circuits, the number of interconnections by the "usua.l" method is reduced to 1-100th-1~150th. As a result, the reliability of the apparatus is increased because the number of the most probable sources of failures inter- element connections is reduced conaiderably, moreo�ver,~they are made by the most perfect methods. A number of IC types are charact~rized by low power conaumption. With low disai- pation power, the operating temperature of chip~increaeeslittle compared to the ambient temperature and~ therefore, conditions are favorable for retarclation of the physio-chemical processes leading to failures. - 312 - FOIt OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 h'c r The actual reliability of IC as the property to implement given functions and to preserve its parameters within given limits with time, determi:~ed by the oper~,ting conditions, depends on many factors~ the perfection of the rircuit, the quality of the initial materials and the complementing components, ar.:i th~~ quality and stability of the technological process of IC manufact.t,;-re. In IC production, monitoring operations axe carried out not only at the end of the final stage of manufacture, but axe converted to a quality control operation over the entire technological process. However, the technological process control is cleaxly insufficient because in the IC manufacturing process, not only are operator _ errors possible but also random deviationa, related to the quality of the materials and working equipment. Therefore~ a single system of checks and rejections of the finished products is introduced in each technologiGal process of semiconductor maxiufacture to detect IC with appaxent as well as hidden defects if possible. For this purpose single norms and methods of boundary tests Kere establi.shed that make it possible to determine reserves of electrical and mechanical properties when developing new articles, and check the efficiency of these or other measures intro- duced in the technological process in series production of IC. The true reliability of IC is determined only in operating the appaxatus. First of all, it must be concluded that the reliability of IC in operating vaxious series (made at various semiconductor plants~ is practically the same in devices developed in one and the same appaxatus enterprise. At the same time, the reliability of IC of one and the same series in apparatus, manufactured at vaxious plants, is found to be very different. This is the result of differences in the technological standaxd of manufacttire of the appaxatus which can also be ma.de in nonspecialized enterprises. The use of highly reliable IC does not always automatically provide such reliable appaxatus. The preservation of the reliability of IC in the appaxatus is deter- mined~ to a considerable degree~ by their proper use at all stages of development, production and operation. The proper use of IC here means the implementation of recommendations on electrical modes and assembling methods~ a debugged technologi- cal process of manufacture of the apparatus and the use of ineasures to protect IC from static electricity, thermal and other effects. Achieving and maintain maxi- mum operational reliability of IC (and consequently~ the quality of the appaxatus) depends greatly on the level of the processes of the desi~ of the appa~ratus, its prepaxation for production and the tune-up of tha equipment and the skill of the personnel. The purpose of this chapter is to acquaint the reader with several measures taken to insure the reliability of integrated circuits, as well as to make the necessaxy recommendations on using IC when manufacturing the appaxatus. - 313 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 5.2 Operational Quality Control To achieve a given level of IC quality in all production lots along with a thor- ough finishing off of the product design and the improvement of the technological process, a rigid operation by operation quality control is used in production. Due to this, an unsuitable product is rejected at certain stages of the production cycle. Moreover, constant quality control over the parameters of th~e technological process (for example, temperature, time intervals, gas consumption)~ technical con- dition of equipment, and a check , of the skill of the operators is carried - out. Tarle 5.1 lists the basic stages of the technological processes, the monitored characteristics~ and gives the criteria for evaluating the proper progxess of the process. The number of monitoring stages, the volume and type of monitoring (continuous or selective) are determined in each concrete case depending upon the required level of reliability of the IC (standard or especially reliable~, the type and importance of the stage of technological process. The second stage of production quality control is establishing relationships between types of IC fallures, the paxameters of the technological process and developing recommendations to correct them. An analysis of causes for IC failures is objec- tlve information that makes it pos$ible to improve the technological processes. table 5.2 shows an example of the plan-schedule of ineasures directed toward the elimination of causes of failures of semiconductor IC. The data in Table 5.2 must be analyzed along with the figures, references to which are given in the table. These diagrams show the relative change.in the shar~ of TC failures of a certain type, depending upon the period of implementation of the measures. The measures in Table 5.2 are numbered for convenience of analysis. The effectiveness of the internal measures is illustrated in Table 5.3 xhere the dynamics of the reduction in IC failures for the three above-mentioned causes is shown. 5�3 Rejection Tests IC ma.nufacturers axe interested in the best technological processes and strive to have thorough production quality control for the purpose of increasing the per- - centage of finished product yield~ and reducing the rate of IC failures. However, demands for reliable IC from the users cannot be satisfied only by im- proving the production process and the system of operation by operation quality control. A system of rejection tests of the finished product as a means of in- creasing the reliability of the product as compa.red to the level considered standaxd at the given moment plays a great role in solving such problems. Rejection tests of IC axe intended mainly for eaxly detection of (preworking) failures, caused by operator error as well as by random deviations related to the quality of the initial materials and the operation of the equipment in the process - of IC manufacture. The introduction of rejection tests far the entire product is based on the fact that the rate of IC failures, in the general case, decreases with time. Fig. 5.2 shows the chaxacteristic distribution of IC failures in production and the tests of one of ihe samplea of the apparatus. The greatest number of -314- FOR OFFICIAL L1SE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 failures (up to 8096) occurs at the stage of production and tests of small assembly units of the apparatus and decreases noticeably when these units are consolidated - (curves l~ 2 and 3) as well as for the entire product (curve 4). Wi~h the rejec- , tion tests, it is possible to remove microcircuits f`rom the production l~t that hav~ hidden defects and thus increase the reliability of the apparatus, "shifting" the failures of breaking in to the stage of rejection testing. Table 5.4 shows an example of the composition and conditions of rejection tests to which ]0096 of the IC produced are subjected. As may be seen from Table 5.4~ rejection tests are made in a logical sequence and axe interdependent. Methods and mod~es axe used for rejection tests that take into account the special features of the manufacturing technology and IC design. Here hidden IC defects axe detected~ but not failures that axe not inherent in the given technology and design. The selection of inethods and conditions of tests are based on the Imoxledge of the physical nature of the IC failures which originate at various kinds of clima.tic, mechanical and electrical effects. The levels of external effects are selected by the results of IC tests so that there remain certain stability reaerves. In setting up the sequenc e of carrying out the rejection tests, it proceeds on the ba.sis tha.t they must begin with such types of effects which will make it possible = to eliminate immediately IC with hidden defects tha.t cause the greatest percentage of failures in operation. At the final test stages, methods axe used that will make it possible to eliminate poor IC whose defects were not detected in the pre- vious tests from the production lots. Rejection tests include methods that facili- tate the stabilization of electrical parameters and reduce the spread of their values. The first rejection test is visual inspection aft~r the operation of dividi.ngthe xafars into chips and before the sea:ling operation. ~perience shows that this t~rpe of inspection is one of the most important methods that ma.kes it possible to detect many production defects which cannot always be detected electrically or in other types of tests. Visual inspection makes it possible to reject IC in which the following violations were detected~ defects of chip metal-coating (scratches and voids in metal-coated tracks and contact pads, signs of corrosion and flaking, unetched sections of inetal coatings, shifting in the metal-coated layout)~ scribing defects (cracks in the active axea of the circuit, under contact pads and metal coating~ splits and damage to the chip) or diffusion defects (nonuniform and parasitic diffusion). In some places there may be no pa.ssivated protective oxide on a paxt of the p-n junction, shifts of layers in photAlithography, and defects in the protective dielectric film ma,y be seen (remnants of the dielectric film on contact pads~ scratches and holes). Insulation defects can be found in IC chips (absence of se~arating insulation~ contamination of the surface of the chip), fixed or loose paxticles of foreign mate- rial on the chip's surface, defects of welded joints on the chip and housing lead- outs, as well as defects of wire leadouts (the sag ia greater or..sma.ller than tha norm; uneven flexibility of the wire, grooves, reduction in diameter; distance be- - tween wire leadouts that are less than the norm). ~ - 315 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ruK t~rh7~ ~n~, u~h: UNLY 'rable 5.1 Stages o~' the technological process and the approximate volume of operation by operation quality control,characteristic for IC production Monitored characteristics Evaluation criterion ' Manufacturing of semiconductor wafers Thiclmess, plane-paxallel~ roughness Percent of set value Structure defectsi linear, displacements~ Number per unit area inclusions Surface orientation Percent of average value ~pecific resistance Percent of set value F~ uipment Meeting technical condition requirements Passivation (oxidation) of surface ~uipment operation mode~ Allowable deviation range change of temperature with time Velocity of gas flow up to the start Allowable deviation of gas flow and in 'the process of oxidation velocity Thiclmess of the raised ~(or precipitated) Allowable deviation from norm layer Density of microholes and cracks Allowable number of defects ~er unit area Size of microholes ~ Maximum allowable size of holss F}~uipment Meetin~ technical condition re- quirements . - Photolithography Sizes~ combination, quality . Meeting requirements of of etching, microholes, presence of foreign visual inspection particles Properties of solventsi specific ~eight~ Correspondence to certificate viscosity, solid particle sediment, storage temperature Modes of drying and exposingi temperature Allowable deviation from the norm time bcposition modes~ intensity of light, time Adhesion quality Force for peeling film ~ Modes of etching processasi density Allowable deviations from the norm (frequency of etching sections), temperature, time (velocity of etching each level of passivation or metal coa.ting). Conditions for making each type of maski Same relative humidity, temperature~ dust in the Meeting requirements of visual environment; quality of surface (density inspection a.nd diameter of microholes, roughness of edges - 316 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000500080030-5 Table 5.1 continued Monitored character~stics ~luation criteria ~ Epitaxial build-up Conditions and storage time Allowgble deviation Thic~mess of epitaxial lay~r � Percent of set value Specific resistance Same Defects of packing, dislocation~ holes~ Meets of requirements of visual bulges, pits~ depressions, scratchea~ inspection irregular edges F1~uipment mode~ temperature of the Allowable deviation epitaxial tube, composition and parameters - of the gas flow Diffusion Depth of diffusion junctions Same of emitter and base Specific resistance . Percent of set value D~uipment mode~ temperature of diffusion Alloxable deviation tube~ composition and parameters of the ~ gas flow Meta1 coating Purity of xafer~ temperature Meeting requirements of visual of wafer and metal, film thickness inspection and force for peeling (including along the edges of the contact tne films windows) effect of shading Scribing when scribing with a diamond cutter~ slope Meeting requiremehts of visual angle, pressure~ velocity and direction of inspection cutter movement Wh~n scribing by quantum ~ optical oscillator beam~ poxer and reao- ~ lution capacity of beam; depth and width of ~ scribing; mechanical damage; cracks~ metal scaling, chips, scratches Chip assembly Temperature, time. ultrasoriiC power, chip Allowable deviationa ~ orientation~ ambient parameters Connection of internal leadouts , Temperature, pressure~ time for 5ame ma.king connection, metal composition~ rupture force, ambient parameters - 3i 7 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500080030-5 FOR OFFIC'IAL USF. ONI.Y Table 5.2 Approximate plan-schedule of~measures directed to the elimination of IC failures Type of IC Correctin~,measures Period of intro- failure ducing measures Y. Rupture of 1.1.Re3ection of potentially unreliable IV quarter of _ wire leadout due IC by centrifuging 1927 to failures of 1.2.Monitoring the rupture force of th~ I quarter of the thermocompres- gold wire 1973 sion connection 1.3.Monitoring the detachment force of I quarter of (see Fig. 5.1a) the thermocoa~pression connection 1973 1.4.Change in the design of the welding tool (needle) to increase the detach- ment force of the thermocompression 1.5�~~r~uc~~on of the technological IV quaxter of operation of "dropping" an IC on an Y973 oaken board from a height of 1 meter ~ 1.6.Introduction of a process of continuous II quarter of degreasing and annealing the gold wire ~975 2. Rupture of 2.1 Introduction of a process for spraying IV quarter of plating due to poor on aluminum by an electron beam 1972 adhesion (Fig. 5.1b) 2.2.Introduction of group spraying on by I quarter of electron beam from a water-cooled 197~ crucible ~3. Rupture of con- 3.1.Reduction in annealing temperature IV quarter 1973 nection due to for- 3.2.Reduction of burn-in temperature of IV quarter 197~ mation of intermetal- aluminum and replacing oxygen medium lic phases at the by nitrogen interface of dissimi- 3~3~Stabilization and monitoring the tem- IV quarter 1974 lar metals (see Fig. perature of the tool and changing the 5�1c) heating mode in the process of setting the chip on the base - 318 - FOR O~FICIAL USF. ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 Table 5�3 Dynamics of reducing IC failures Trype of failure Share of IC failures of a certain tYge..,~,6, of all f~�ilures,~. bv .Years ~Z ~ . ~ ~ Rupture of xire leadout due to thermocom- 13.7 4.1 4.7 2.8 pression connection defects Rupture of plating due to poor adhesion 18.8 2.7 0 0 Rupture of connections due to the formation 10.1 19.6 1.2 0 of intermediate phases at the interface of disaimilar materials ~ N~ ~ . . ~6 I"~ ~ . , . ~ ~ ~ ' . g4 n . f,o ~ _ Rd ~ga ~ ~ . R6 t? qB 2.f : 0,4 ' ~4 ~5 ' 0,2 ~ ~0 qT ~ ~ 1.2 ~ ~ ~ . ' II~IYIFl~III~~r 1RS ' It8lYI~~~III?(7YII~I~ ' . t9,~1A 1913x 1'314$ �~j5a. 1977a. 19/3a. 197~18 . d1 ~AD' llJdO/l~t70/Je~W~A , 41 ~ (i~ . 4,0 n f4 i 1~1 � 1,0 . O,B 3 ~ ' . ' , 0,6 ~ ' a4 ' 3.1,33 � 0,~ ~ .O._._ � I 7~[Yi L' ~~l Il ~(Y ' ;0; "w ~75~ !974t. ;,~C~P4,,'~!/ JJ:.:~J,7/IL�h.G.y F'ig. 5.1. Redu~tion in the number of IC failures (N) occurring far varioua reasons depf:nding upon the use of correction measuresi a-- break in thermo- pressure xeldingi b-- break in connections due to poor adhesion; c-- break in connectiona due to the presence of intermetallic phasea. 1. Peri-od of manufacturing. -319- FOR OFFICIAL USE ONLY ' APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400540080030-5 MUN l)hNll'IAL U~~: UNLY Table 5.4 Rejection tests Type Conditions Visual IC inspection Inspaction of chips under a microscope (not less than 80 before sealing magnification) to meet requ~rements on limiting the num- ber of defects of each type and their total number, shown in specification Annealing for param- eter stabilization: Hold IC at a temperature exceeding upper value in specifi- before sealing cation for 48 hours ~ After sealing Hold IC at upper value of temperature for 24 hours Cyclic temperature Alternate effect of upper and lower values of ambient tem- effect perature (transfer from one cha.mber to another for not more than 3 minutes). Number of continuously following cycles - 5 Lin~: loads Effect of line loads with accelerations of 1'0,000... 20,(?!JO g in the direction of the vertical IC axis for 1 minute Seal check~ sma,ll Check seal within 1x10-3...1x10-7 liters.~ m~second by leaks the mass-spectrometer method Average leaks Check IC seal, pressure-molded in Freon, in an indication liquid. Determine seal at 1x10'2 liters. ~ m~second I,arge leaks Check seal in an indicator liquid D!easurement of elec- Monitor IC pa,rameters according to specifications at nor- trical paxameter mal temperature Electrical thermal IC test at cons+ant electrical load and maximum allowable agiag tests for temperature higher reliability IC Measurement of elec- Check of ineeting electrical pa,rameters of IC in accordance trical parameters with specification Static paxameters Check at the lower and upper values of ambient temperature in specification Dynamic parameters Check at normal ambient temperature ~cterior visual in- Check of structural elements (welded and soldered seams spection and ~oints between glass and metal) under a microscope with ma~ification not less than 16. Visua.l inspection of coatings and labeling - 32fl - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 Defects in chip connection (chip orientation not according to design drawing~ leadout crosses~ the eutectic covers less than the allowable part of the chip perimeters~ too much paste and glass, defects of the housing base (deformation of the housing~ peeling of the gold coating, shifts of the coating and eutectic~, defects of the housing (absence of leadouts~ corrosions, resence of drops of glue~ �in on the flangeoof the housing on the side of the cover~, as well as defects in assembly (chip on boaxd. glued too high~ boa.rd bent) that originate in inaccurate assembling of IC. After annealing to stabilize, parameters and ssa,iing~ IC are subjected, in turn~ to the effects of thefr high and low valuea of ambient temperatures to deteot a mismatch between thermal expansion coefficients of individual IC parts. After these tests~ the IC must preserve their external appearance and the electrical paxameters. The mechanical integrity of the design is checked by testing on a centrifuge. The - microcircuits axe attached to the housing in a special device and are subjected to the effect of lineax loads which produce forces along the vertical IC axis corre- sponding to accelerations of 10,000 g for hybrid~ and 20,000 g for semiconductor microcircircuits. These forces are usually sufficient to de~ect defects of xelded connections of internal leadouts and poorly attached chips. ~ In testing IC~ devices xith improper seals are re~ected.The widest failure mechanism in such IC is due to the moist air penetrating the housing and water vapor con- densing causing corrosion of the metal coating. Flirther electrical tests are made in which IC not corresponding to technical norm documentation (INTD) are rejected.. After that~ IC which axe to meet higher reliability requirements axe subjected to special electrical thermal tests which are tested until they fail. This type of testing shows defects not detected in visual inspection very effectively. Typical defects which may be overlooked in visual inspection (but may be detected in ther- mal current tests) are scratches on the metal coating~ thinner metal coating on the oxidation treads and microholea in the oxide under the metal-coated tracks. These defects ma.y also include poor electrical contacts and surface contaminations that cause instabi.lity of IC parameters The final type of test is an all-around investigation of basic IC electricl param- eters under normal climatic conditions, as xell as at the upper and lower ualues of the temperature in the specification. Electricaltests are also made at a com- bination of electrical modes (input ai~als~ loads~ feed voltages) which are the worst for the given type of test within the limits of specifications. Rejection tests axe completed by checking commercial type IC~ with special attention being given to inspecting the qua,lity of xelded and soldered 3oints~ glass in the metal joints~ the labeling and integrity of the coatings of the lead.outs and the housings. By analyzing typical experimetal data that characterize the effectiveness of rejec- tlon tests in the process of production (Table 5.5), it is possible to conclude that the complex of rejection testa makea it possible to detect a considerable num- ~ ber (including 43.296 of the number tested) of potentially unreliable IC and thus raise considerably the quality of IC lots supplied for use in the RFA. - 321 - FOR uFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 . � ~ ~ Table 5.5 Effectiveness of re3ection testa . Type of test Share of Basic types of defects and their defective IC share. 96 Visual inspection of 5 Absence (unwelded) connection 26.4 quality of connecting Repeated thermocomgression 17.0 leadouts . Shift of leadout.beyond area of contact pad 13.6 Pinched leadout 10.6 Shift of xelded joints on the crosspieces 8.0 Others 24.4 Visual inspection of 3.7 Splits 10.7 chips Photolithography defects 10.7 Others 29 Annealing for stabilizing paxameters~ before sealing 0.0 - after sealing 0.0 - Cyclic effect 0.0 - of temperature Linear loads 0.0 - Leak tests~ ~ small leaks 7.0 Not in accordance with norm - medium and large 1.9 ~ same leaks Monitoring electrical ~.4 - ~ parameters at normal conditions Electrical thermal 0.~ � - aging Electrical tests~ check of static param- 0.6 - - eters at higher temper- ature Check of static paxam- 4.7 - eters at lower tempera- tures Check of dynamic 1.6 ~ - parameters 10.6 Splits and cracks in housing ~+.4 Inspection of exterior Twisted leadouts 16.0 of IC La,beling defects 9.4 Dia,maged coatings 20.2 -322- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 . b 50 . ~ . , 0 40 ~ � � ~ ,i0 � _ . ~ 20 ~ 010 � . ~5) ~ ' 2 . e - A B A B A ~ /Inama 6~a+-a do 6 ~7) ~ (e) ~ . Fig. 5.2. Distribution of IC failures in production and testing of apparatus~ l. failures of printed boards B. stage xhen product is released to quality control department 2. failures in units 3. failures in devices 5. ~6 of total number of failures 4. total number of failures A. shop test stage 6. circuit boarda 7. unita 8. devices Inasmuch as re3ection testa uaing above-cited methods are compulsory for all manufccturing plants~ the IC quality of various suppliera is equalized to a consid- erable exten~. Now IC that have passed through ~e and the eame "re3ection bax- rier" at various plants have a similar quality level. 5.4 Effect of External Factors on Apparatus Production A typical technological process of apparatus manufacture using emall-acale mecha,- niza,tion tools is shoxn in Fig. 5�3� -323- FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 ruK uh~N~~:lnl. ~~SM: ()NI.Y 2 % F Z 9 1 ~D 7 t~.fa 14 4,~ ,s6, 7 ! 5 1>, 5~ 15, f6 ? 9 Z ,3 ? lp ? 8 2 f2,f f4 _ S 19,~ f;,5 ~ 5,6,7 1B,20,2f,12 1J >4 ?4 7.7 '4 ,~0 14' 34 35 f6,13 ?5,2~ ~28,?� J 3Z,33?21 18,19 t � a! . . . 1 9 z a z e z n w n 5 4,5 5,6~7 5 1B,10,11~11 - ~ . fo 16,f ~a ?4 w 17 fa 30 14 34 35 15,16,13 ?5.16 ?8 ?.9 3f,T5 1B 19 ~ ' 37,33,12 ' � Ifl Fig. 5.3. Technological route of passage of IC circuit in manufacturing apparatus in housings types 1 and 3(a) and housings type 4(b)i 1., IC ~9. die forming and trimming to size 2. technological packing 20. spatula 3. forming and trimming leadouts 21. device for gluing 4. die for forming and trimming the 22. thermostat size . . 5. magnetic vacuum or optic tWeezers 23. semiautomatic soldering device 6. crucible with thermal regulator 24. cleaning flux from boards 7. device for tinning 25. brush 8. tinning leadouts 26. vat ~ 27. regulation 9. making up sets 28. control panels, devices 10. trimming inactive leadouts 29. hot-cold chamber 11. die with keying device 30. protection against moisture 12. installation 31. paint and varnish 13. soldering 32. centrifuge 14. board 33. pulverizer - 32 4 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 ' K~y ta b'lg. ~,3, contlnue~i 15. device for soldering IC without 34. functioning and control check gluing 16. electric soldering device single-core 35. assembly unit 17. gluing 36. fluxing 18. injector . The sequence of operations and transfers indicated in the technol~agical routes of circuits may change depending on the special design features of the assembly units and the specifics of production. In passing over these routes~ the IC are subjected to the effects of various external factors~ mechanical, temperature, chemical and electrical (Table 5.6~. Mechanical forces are applied to IC in assembly operations, forming and trimming leadouts, and mounting and gluing the IC to the printed circuit boaxd. Forces acting on leadouts and their insulation may dama,ge the sealing of the housing. Temperature effects axe related to the operations of tinning, soldering and dis- mantling. In these operations~ heat pa,sses through the leadouts to the chip or substrate and produces heating of the structural elements of the IC. Chemicals affect the plating material of the housings and the IC labeling when fluxin~, cleaning the flux off the printed circuit boarda~ applying moisture protection and dismantling. And, finally, electrical effects are related to dischaxges of static electricity through the IC. This effect also takes place at all technological operations if no special measures are taken to reduce and remove static electricity charges from production areas. . As may be seen from Table 5.6, IC axe sub~ected many times, although to a different degree, to effects of external factors in the environment. The most dangerous of them are the actions of the operator because they depend to the greatest degree on the individual prepaxation of the operator and they axe the most difficult to con- trol. In the process of apparatus production~ if the modes and equipment qua.lity do not correspond to the problem of producing highly reliable apparatus, vaxious kinds of IC defects and failutes may originate (Table 5.7). 5�5 Forming and Trimming Leadouts (~e basic requirement that the IC housing must satisfy is the presexvation within it of compaxatively dxy air during its entire service life. The presence within the housing of moisture, chemically active and electrically incompatible with semi- conductor~ substances facilitate the origination of sudden, as well as gradual, failures. They happen due to the corrosion of inetals and their alloys and inter- contact connections, and the deterioration of electrical chaxacteristics caused by changes in the surface and volumetric conductivities and ionic contamination. Under normal conditions, any surface of a substance is covered by a thin moisture of from 0.01 to 0.001 micrometers. Due to the small values of a molecule of - 32.5 FOR OFFiC1AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 rvn vr~1~.~H1, u,~. UNLY Table 5.6 Dcternal factars acting on IC in the process of apparatus assembly Source of action Assemblv Forming an~l Fluxing and Mounting Fluxing trimming tinning ~d gZuing and leadouta 1~ on cir- golderinu cui~ bo~rd Operator E, M E E E,M E Material covers of E - - E E ~ working positions and rooms Packing E,M L,M E,M E.M - ~ Assembly tools E,M E,M E,M,T E,M E,M,T Technological - M~E E M - D~uipment � Flux - - Kh - Kh Solder - - T - T , Washing liquid - - - � _ _ Varnish solvent - - - _ _ D~uipment and materials for moisture protection - - - - _ Cleaning Regula- Moisture Flxnction- Disassemblv off flux tion Qrotection in~ test . Operator E E E E E,M Material covers of - - - - E working positions and rooms - Packing - - - - E,M Assembly tools - - - - E~M,T Technological M,E E E E - t~uipment Flux - - - - Kh Solder - _ _ _ T - 326 - FUR OFFIC(AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R400540080030-5 Table 5.6 continued ~cternal factors acting on IC ir~ the p~rocess of apparatus assembly - Source of action Cleaning Regula- Moisture ~luiction- IJisassemblv - off f ux ti,~_ Protection in~ test - Washing liquid Kh - - - - Varnish solvent - - - - ~ D~uipment and ma.terials for moisture protection - - ~,M - - Notei designations of actionai E--~electricali Kh chemical; T-- temperaturef M mechanical. 2.7x10-10 meters and the lox viscosity of water, moiature is able to penetrate even the intermolecular spaces of complex inorganic compounds. In thia case, ~ mechanical destr.uction of materials occurs, along xith a change in the electrical properties of the surfaces~ corrosion of inetals and their alloys. To avoid this, the sealing of microcirCUit h~usings is usually done in an atmosphere of dry nitrogen in which the .xater content does not exceed 10 parts per million. Metals, glass and ceramics used in manufacturing IC housings axe practically im- penetrable to gas and moisture. Most plastics axe hygroscopic to some degree. To preserve a dry inert atmosphere within the housing, the seams between unlike metals should be ma~cimally sealed. According to the adopted norms, a good. soldered seal passes not over 1 cm3 of ga,seous helium at a pressure difference of 1 atmosphere in 30 years (practically, this means absolute air impenetrability). Metals are joined to metals by soldering with soft ar brazing solders, hot or cold weldin~ or their combination. 5oldering of glass to glass or ceramics is done by melting them at high temperatures~ or gluing with lox-meltin~ glass. Sealing a _ metal-glass seam which insulates the leadouts electrically from the IC housing is a complex technical problem. This is becauae mo$t of the common gla,ss has low coefficients of linear expa,nsion and heat conductivity~ while most metals conduct heat xell and have high lineax expansion coefficient. The difference in the speeds of the heating and cooling of glass and metal par~ta og soldered joints~ and the _ difference in the lineax expansion coefficienta leads to mechanical stresses and damage to the joints. As far as IC operatng conditions are concerned, glass and metal are considered compa,tible if the difference in their lineax expansion coeffi- cients do not exceed 4x10'7 per centigrade degrees ~4]. Usually, in sealing IC leadouts where they come out from the housing~ crystalliza.- ble glasa solders (for exa,mple, of the "Piroceram" type) axe used. The technology of obtaining such a sealed 3oint by soldering is based on the formation of a glass- ceramic joint Nith the crystalliza,tion of boron lead-$inc glass. In this method, -327- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 ~.~1~ ~ rl r n~\ 1 t �~1� 1 f'~'1 \ the glass is melted by the hea,t and sgreads thoroughly, wetting the ~oined sur- faces of the ceramics, glass and metal~ li~ke the metallic solder wets and joins metal parts in common soldering). When the soldered glass is heate~d furthE~r "devi~rification" occurs and centers and crystallization of the seam materi^'. are groduced. The sizes of the crystals formed are.proportional to the time and temperature of the grocess. The strength .~f such a sealing seam is determined by ite crystalline structure and is twice that of a seam from amorphous glass. Moreover~ at mechanical loads, microscopic cracks are formed in joints with noncrystallized glass which create paths for mois- ture penetration into the housing through the glass. In crystallizable glass, how- ever, the microscopic cracks end at the crystals and do not pass through the joint. By regulating the content of the crystalline pha.se of the seam material, it is pos- sible to~change its temperature linear expa,nsion coefficient (TKR) from 40x10-7 to 120x10-7 per degree centigrade which agrees well with the TKR values for a great number of glass~ ceramics and metals used to make housing parts. The Kovar alloy (iron, nickel, and cobalt) or the S~.lmet alloy (iron, nickel and chromium) are most frequently used for IC leadouts. These alloys have low TKR values that agree Well in the working and technological temperature range with the expansion coefficients of most glass (the TKR for Kovar is 47x10-7 per degree centigrade and for glass 46x10-7 per degree centigrade). An essential special feature of most types of IC housings is tha,t part of the lead- out length is under the cover of glass (or ceramics). This cover should not be dama.ged in fcrming the lea,douts. - Contradictory demands are ma,de on the IC housing. Thus, the housing must be suffi- ciently strong mechanically to withstand loads originating in the appaxatus pro- duction and operation and, at the same time, it must be as small as possible with a shape permitting the greatest density of R~A assembly. This contradiction must be taken into account~ providing a complex of technical mea,sures for preserving the reliability of the microcircuits in designing and producing the appara- tus. In implementing the technological operations on prepaxing the IC for assembling on the printed circuit boaxd (straightening~ forming and trimming leadouts), the lead- outs are subjected to stretching, bending and compression. In this case, the stretching force P1 is applied to the most sensitive mechanical forces zone of the housing the seal , inlet (Fig. 5.4). If the stretching force is excessive, cracks may originate in the glass or ceramics of the housing where the leadouts pass the housing leading to an immediate~ or what is worse, a subsequent loss of housing seal. The die design for forming and trimming leadouts (Fig. 5.5) must insure the produc- tion of independent and sequential forces for clamping P2, forming P3 and trimming P4. '?he values of these forces are selected so that they insure the integrity of leadout plating, apply the minimal stretching force along the leadout axis and obtain a given configuration. In forming and trimming the IC leadouts, it is - 32 8 - FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 Table 5.7 Possible types of IC failures under various effects Oject of Technological Effect factor Type of possible vio].ation ef,f~ct operation , parameter and failures Mechanical IC leadouts Straighten, Pulling force Inaulator cracking~ causing forming a.nd Clamping force loss of housing sealj leadout tr~.mming deformation (pinching, twisting, breakage) ' Insulator, Mounting Static Insulator cracking, causing ~ housing base, and gluing IC force of los~ ef hausing seal. Deforma- flexible con- to the board, clamping tion of housing bottom causing nections, chip dismantling housing to cracking and sepaxation of chip~ or substrate ~ board substrate and breakage of flex- ible conductora. Destruction of housing - . Temperature Lea.dout coating Input control Force of Dents and scratches on leadouts ~ straightening~ clamping lead- leading to corrosion forming and out trimming Lea,dout insula- Tinning, sol- Overheating Insulation cracking~ causing tor, chip~ sug- dering, dis- the leadout loss of housing seal. Peeling strate~ active mantling, or solder ~ of substrate or chip ( in case elements and drying they are glued) from the mount- flexible lea~d- ing surface of the housing~ outs causing breakage of leadouts Increased Theamal defarmation of protective operating coa.tings of chipa, causing temperature breakage of flexible leadouts Chemical Coating and Fluxing, Chemical Corrosion of coating or basic labeling cleaning~ activity material of leadouts and hous- moisture-proof- ing, and destruction of labeling ing~ disma.n- deaignations and paint-varnish tling coating8 - 32 9 - FUR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 . . . ~ Table 5.7 continued Possible types of IC failures under various effects Object of Technological Effect factor Type of possible violation and effect operation paramet failures IIectrical Passive and All tech- , E'lectrical Puncture of oxide, degrada,tion active IC nological charge of IC parameters due to punc- elements, metal operations (number of ture in.the semiconductor coating, p-n effects junctions, ~ structure capacitance protective oxide and resist- ance in the discharge circuit,voltage difference) permitted to leave tool traces (prints) on the IC leadouts, tha,t do not damage the plating on the leadouts. Table 5.8 sho~rs allowable values of clamping and forming forces at which damage of plating does not lead to corrosion. Depending upon the cross section of the IC leadouts, the value of stretching force P1 should not ex- ceed the values shown in Table 5�9� Table 5.8 Allowable forces of forming and clamping Sequence of force Cross section of _Cl__a_m~ pi~n~ Formin~ actions housing leadouts, . N microPa N MicroPa ~ ~ Weak traces of working O.1x0.3 i3~7 30�~ 18.6 29.4 pa.rts of the die on the 0.15x0.45 19.6 30.4 27,4 29,4 surface of leadouts in the form of compacting the coating Maximum allowable traces O.1x0.3 17.6 39.2 2~+.5 39�2 of die parts on leadout 0.15x0.45 27.~ 39�2 coating 37�2 39�2 Impermissible damage of 0.1 x 0.3 21.6 48.0 31.3 49.0 leadout coating 0.15x0.45 32�3 48.0 46.0 49.0 in the form of dents - 330 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 The die design should prof'ice rigid fastening of each IC leadout outside the glass or cerma.ics buildup. A leadout section of 1 mm from the body of the housing should not be subjected to bending or twisting deforma.tions. Allowable bending radii shc~uld be maintained in forming. Forming IC leadouts of a rectangulax cross section should be done with a bend radius of not less tha,n tWO lea.dout thi.cIu~essQS, while lea,douts with a round cross section with a radius not less than txo dia.meters. Table 5�9 Maximum values of stretching forces Leadout cross section, mm Stretching force per one leadout, Ne~an ~ Up to O1 0.245 Above 0.1 to 0.2 0.49 Above 0.2 to 0.5 ~ 9�8 Above 05 to 2.0 19.6 The IC leadouts inside the housing or leadouts not used in the circuit of its ap- plication and not affecting the working capacity of the IC, may be trimmed 1.0 mm from the housing body; however, it ahould be taken into account that a considerable paxt of the heat is removed over IC lea,douts (eapecially of amall sizes). In a typically improper design of a technological device, the formation of lea.d- outs of type 4 housings (Fig. 5.6b), a gap (not less than 0.5 mm from the body of the housing), necessary to preserve the integrity of the ceramics was not left. A die of such design may damage the housing seal of the IC. Fig. 5.7 shows another typical assembly error. We will assume that the forming of IC leadouts, intended for installation on a multilayer printed circuit board with open contact pa,ds, was done at the depth of the second-third layer (Fig. 5.7a). Actually~ however~ it ~as necessary to salder them to other layers. In assembly, the leadouts were bent ma.nually at the inlet of the seal (the bend angle in the vertical plane ma,y reach + 6096). Straightening the leadouts made without rigid fastening of the leadout zone on a section 1 mm from the body of the housing (i.e., without using the technological device) may lead to damage of the leadout at the housing. With such a method of assembly, the IC ma,y lose it~ seal duri~g the con- sequent ne~hs~ieal forces when operating the apparatus because the deformed lead- outs axe in a stressed condition (Fig. 5.?b). 5.6 Tinning and Soldering In the production of radio electronic appaxatus, group methods axe widely used to implement individual technological operations, for example, tinning IC leadouts by "dipping into melted solder" or aoldering by mea,ns of a"wave of solder." These modes of operations (temperature of the melted solder, contact time between the solder and the housing leadouts, axea, of the contact zone of the leadout with the solder), selected without taking inta account the hea.t transfer characteristics of - concrete types of IC housings may lead to a destructive effect of heat shocks on IC. -331- . FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 ~�a~n .~~~r~t ~~11~. I?IVI.Y , ~1~ . .x ~ p~aQlN ~ 0,5max~ Fig. 5.4. Direction of stretching force in forming and trimming leadouts 1. P1 ~ 0.1 Newton .+ii ~ / P~ r- ~ - ~ +f.~ +~~1 ~ ' r ~ ~~J i � j~ ---t-- / i~~ i~~~ oi ~ ...~..I~.. - i . . ~ I . " n, . ~ ,,i , ....L .1( . _ - Fig. 5.5. Forming and trimming IC leadoutsi a-- clamping the leadouts; b-- forming the lea.douts; c-- trimming the leadouts. -332- � FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 , - / ` i ~ ~ y . i � ~01 ~ / ' i ~ %.i / / ~ ~ 6j !j .J _ / ~i Fig. 5.6. Correct (a) and incorrect (b) forming leadouts of a planar housing ~1~ . s s ~ r~ ~ . Cnew � :a . ~i ~ ~ ~ Z . ~ 3 4 S ' 6 7 8 60' ' � / ` ' i :,s ~i+ ' . 60 , Ol Fig. 5.7. Correct (a) and incorrect (b) assembly of planar housings on a multi- layer printed circuit board with open contact pads. � 1. Layers ~ - 333 - FOR OFFICIAL ,~3E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 ~.?u ~~i r~~ ~ ~i ~ ~~;`i ~ Fi~;. 5.8 shows schematically individual elements of IC design which axe subject~d to thermal effects and participate in heat transfer. A temperature gradient is produced along the IC leadout in contact with the melted 3older causing the trans- fer of heat. The heat exchange is implemented from the soldering zone (zone A) through the leadout metal to the ceramic base of the housing body (2) and further to the IC chip (4). The heat flow is also transmitted to the chip from the inner part of the leadout (zone B) through the internal connecting conductor (3). The speed of heat transmission depends on the temperature difference, on the heat conductivity of the ,na,terial and the configuration of the IC structure elements. The heat conductivity coefficient is calculated by formula 7l ( w/(M��C)1 = Q/e!�S�AT/A/, (5.1) where Q is the amount of heat,joulesi pT temperature gradient, �C; 1-- distance from heat source; S= /S Q,~T system entropy, joules~degree. Formula (5.1) contains the specific heat of the system c= Q~ ~ t and the temperature gradient grad T= t1T~ L~ 1. Values of heat conductance coefficients of several materials used in the IC structure are shown below. Material ~ , watts~(meters. �C Silver 460 Copper 39~, Beryllium oxide . 208 Aluminum ' 203 Silicon 83�5 Aluminum 19,6 xovax ~9~7 Glass (borosilicate) 1.1 Laminated epoxy plasti.c 0.28 � To evalua.te the degree of the heat effect in tinning and soldering~ it is neces- sary to know the material heat transfer coefficient of IC structure elements n � - )./c�~~, � (5.2) where coefficient of heat conductivity, c-- specific heat, joules (kg.�C); density~ kg~in3. This coefficient is determined experimentally for each type of IC housing and a given ma~cimum temperature of elements in individual structures. Fig. 5.9 shows diagrams of heat distribution for five housing designs. Isotherms are shown on these figures that chaxacterize the degree of heating of IC elements . when tinning leadouts. This data was obtained by thermal melting indicators whose action is based on the irreversible and sharp change in color when a certain - 334 - NOR OFFiCiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 ~ ~ Z~ J 4 ~ % / , , . ' . - , , i Fig. 5.8. Heat exchange circuit in tinning and soldering external IC leadoutsi 1. contact pad 3. internal connecting canductor . 2. housing 4. IC chip~ critical temperature is reached. In the experiment, thermal melting indicators with vaxious critical temperatures xere coated on the aubatrate or bottom of the IC. Then the IC was enclosed by covers, and fastened in a special holder made of textolite~ and the tinning operation was done by dip ing the leadouts in melted solder (temperature of the melted solder was 260o j S~C~~ distance from housing to solder surface was 1 mm~ the contact time betxeen the leadouts and solder wa,s 3 seconds. The devices ~used. in the experiment provided a minimal removal of r~ea,t from the IC housingi in this case, the linear shifts perpendicular to the surface of the sol- der were held to an accuracy of � 0.2 mm. ~ To determine the precise temperature values (the thermal melting indicators gave only limits of temperature changes), and to evaluate the changes of this tempera- ture with time, temperature mea,surements were made on the most ~ypical IC elements (leadouts, substrate, chip) by a thermal electric method for different modes of tinning and soldering. The temperature was measured by a low-inertia copper- constantan thermocouple xith an 0.06 mm electrode diameter which made it possible to reduce the meASUrement error and the thermocouple effect on the true value of the temperature. In the experiment~ the thermocouple was attached to the mea.sure- ment point~ then the housing cover was closed an d sealed by "cyacrin" glue. The thermocouple indications were recorded by a high-speed self-recording device. - The relationships betKeen the temperatures of the IC elements of various types in the process of tinning and the tinning time and the distance to the aolder sur- face axe shown in Fig. 5.10. - 335 - FOR OFF'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 i.~K urr~~ i:~i ~~,r uti~ ~ _ t~' ~c9' ~:.o.' ~ ' ) � ss' i,~~ e a0, � : . ~W p0~ ' , ~ O �St' l09~ , S3� ny ' n n' ~ . : . ~ B 6' J(n p !S � . ,n/~~ J20' ' ~ ~ ~ ' ~;9' /:0 /10' , a, ~ ~ fi~ ao'p UU ~ oO~ . . ~d~ - - - - ~ ~ ~ (e). ~s' er' a~` ~s� ee� ) I ~ I o ~ o(~ L ~ s 6~~ Fig. 5.9. Temperature diatribution of IC houeing heating when tinning leadouts~ a-- type "Tropa" housing= b--planar houaing 401.14-1; c-- housing 151.15-1; d-- type "Po:ol" housings 3-- round ho~sing 301.12-1. In this figure temperature zones obtained by thermal indicators of inelting~ are shown for comparison. The test results show tha,t temperature values obtained by the thermoelectrical method are in the temperature zone determined by the therma.l indicators of inelting. An analysis of the experimental data indicatea that the temperature difference of heating IC elements when tinning and soldering reaches 10...20�C and for all housing types 301.12-1~ the tinning mode is more "rigid." - Tinning parameters are shown below. Parameters of tinnina mode Norm Max. soldering temperature, �C z5~ Max. ti me the leadouts are in the melted solder, seconds 2.0 Min. distance from housing "body" to boundary of solder along the 1�3 leadout length~ mm Max. allowable number of dippings of the same leadouts into the 2 solder Minimum interval of time between two dippings of the same 5.0 leadouts into the solder, minutes - 3 36 - FOR OFFICIAI ~.1SE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 jJ~ 1-1nn Z r~~ t-1c ~ . f00 - 4 i00 0 0 0' J 2 0. . ~ � 4 ~ 80_ ! BO 1 0000 . . ~ d'0 ' ~ 60 ~ ~b~~ T _ r ~ ~ 3 49- o o k 40- f a I ~ J ~ i i 2 3 4 S 6 t,c > 2 3 , 4 5~~1? ~ l m fnn S t, G t-2c � ~fm I � 7U0 ~ , , ~ i s - ' ~ ' 2 y;ll Z 80 3 4 I - ~J ~ - ,1~ ~v - . ~ p 7 : 2 50 - 1 _ 3'" % ~ ' ._f ~ .3 ,f0 - Z 3~ 4 S 6 t, C ~1 1 2 3 4 S~'~? ~~-1n~ 3 : t-Zc . r,'c - ~ �c , ~ ~ ~ov � ~c~ ~ ' ~ -3~~' ~ ` P1 r---- . ~ . ~ ? o% o o~' 4 6p ~ 4 ~ ' . 3~j . 60 - p ~ ~~~~~~~~1/~ f~j~ . . 1 _ 3 f "~G~'(l/!l, _ . 40 - 4 40 y . ~ ~ i ~ ~ ~ 2 J 4 5 6 t,C f ? 3 4 5l,yi~? ~ Fig. 5.10. also continued on the next sheet - 33~ - FOR OFFI~rAL l1SE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 NOR OFNICIAL USF: ONLY r,�~ ~ T'~ o,t-~5) . ~?0 ~ ~_!yy i t~2c x~t-dG ~ !00 0 1 ~ >00 ' ~ J o o ~ . d0 z 80 " . 2 , � ,;.a~ 60 - ~ , K Z P'p ~6~ . 2 3 4 S 6 t,0 d1 2 ~ 6 l,a~Y Fig. 5.10. (continued from previous sheet) Relationship between temperature of IC elements in the process of tinning and tinning time (t) and the distance (1) between the level of solder for housings series 217 (a)~ 106 (b)~ 218 (c) and 122 (d). The numbers on the curves correspond to the points of the IC elements at which the measurement is ma.de; solder temperature is 260 � SoC. - 5. t= 2 seconds 6. t~ seconds In tinning, the solder should not touch the seal inlets of the houaing. The sol- der should not fall on glass or ceramic parts of the IC housing. The boundaxy of solder flowing on lea.douts should be no closer than 1 mm to the body of the hous- ing (Fig. 5.lla); however~ some nonuniformity of tinning along the length of the leadout is allowed. The minimun( length of the tinning section along the leadout . length from its end must be no less than 0.6 mm (Fig. 5.llb), but "icicles" on ' the ends of IC leadouts are permitted (Fig. 5.llc). It is necessary to make sure that connections are not formed between the leadouts and the soldering surface should be continuous without cracks~ pores and untinned sections (Fig. 5.lld). D~uipment used for tinning must insure the setting and measuring of the tempera- ture with an error no greater than y SoC. The quality of soldered connections should be determined by the following criteria~ the soldered surface should ha.ve a light or ma.t finish without dark spots and foreign inclusions. The shape of the soldered connections must have concave fil- lets of solder along the seam (without an excess of solder). The contours of the leadouts should come through the solder. In soldering IC housings with planar leadouts the following is permittedi a flooding form of soldering in which con- tours of individual IC leadouts axe fully hidden under the solder on the soldered side of a connection (Fig. 5.lle~ f), partially covering the surface of the con- tact pa.d with solder along the soldering perimeter~ but in no more than two places, - - 338 - FOR OFFiC1AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 not exceeding 159b of the total area (Fig. 5�llg), solder bits of conical shape (Fig. 5.llh) and rounded shape (Fig. 5.lli) where the soldering tool is removed~ a sma.ll shift of the leadout within the contact pad (Fig. 5�11~) and the spread of solder (only within the boundaries of the lea,dout length~ suitable for wiring). ~ ~ ~ n . Z ~ Z r Q ~n ' r b ~ ~ ) ~7) ~ lJ~eaa+~ra ~ ' I /kro~nywe~i3 , yvacmoK . ~ ; 6~ c) . ~d~ . ~ � ~ ~ , . 5 5 . ~3 3 3 � A 4 f ~ 6) ' ~ . . ~ � � 5 . ~ 5 3 . 3 4 . 4 . . h i J~ . Fig. 5.11. Examples of tinning and soldering lea,douts of a planar housing~ a-- zone of solder flow; b-- allowable nonuniformity of tinning; c-- presence of "icicles"; d-- nonuniform tinning and false connec- tions; e~ f-- flooding form of soldering; g-- par'tial tinn~ng of con- tact pad; h~ i-- con~cal sha.pe solder beads; j-- small shift of leadouts; 1-- leadout; 2-- housing; 3-- contact pad; 4--printed circuit board; 5-- solder; 6-- connectioni 7-- ~tinned section When soldering IC leadouts into metal-coated holes, the soldered connections must be according to the sketches shown in Fig. 5.12a-d. The solder on the side of the housings should not spread beyond the boundaries of the contact pads. The leadout . end may be untinned. The metal-coa.ted wiring holes must be filled with solder to a height of not less than 2~3 of the thiclmess of the board. The correction of defective connections from the aide of the IC mounting on the board is not per- . mitted. - 339 - FOR OFF:.:1f:i~ USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000500480030-5 . . . . 1 1 3 , , ~ ~ ~ , I ~ ~ ~ , ~ Tope~f ,s'~ ~4 61 d~ . a~ . , , . . I . ~ ~ : J � ~ ~ - . ~ 4 1 3 4' 1 ~ g~ e~ f) . Fig. 5.12. Examples of soldering housings with plug-coupler leadouts~ a~ b, c, d-- soldering in metal-coated holes; e, f, g-- soldering in nonmetal-coated holes; 1-- leadout; 2-- metal-coated hole; 3-- printed circuit board; 4-- solder; 5-- cavity in solder; 6-- contact pad; 7-- end not tinned. When soldering IC leadouts to contact pads of printed circuit boaxds with holes not coated with metal, the soldered connection must be made according to the sketch (Fig. 5.12e-g). The spreading of the solder along the IC leadouts shou~.d not re- duce the minimum distance from the housing to the soldering point~ i.e., it should be within the zone suitable for the wiring shoHn in the specification. There need be no solder at the ends of the leadouts. The equipment and fixtures used. in soldering must provide the following; automatic ma.intenance and control of the melted solder temperature with an accuracy of t 5�C when implementing the "soldering wave" operation; maintenance and periodic control (every 1 to 2 hours) of the temperature of the soldering bit with an accuracy of � 5�C in the individual method of soldering; control of the time the IC leadouts are in contact with the soldering bit or with the molten solder in group soldering; also control of the distance from the housing body to the boundary of the solder along the length of the leadout. The soldering bit must be gounded (the ground re- sistance should be no greater than 5 ohms). Table 5.10 shows the recommended modes of IC soldering using single-bit and group methods. ~ - 340 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 Table 5.10 Recommended IC soldering mode Paxameter 3older~ng IC xith Soldering IC with planar ~leadoutr s plurr-coupler leadout~ 1-bit group method 1-bit group method me~ method Max. temperature of solder- 265 - 280 - ing iron core, ~C Max, contact time 3.0 - 3.0 - of each leadout, sec- onds Min. time interval 3.0 - 3.0 - betxeen soldering of adjacent leadouts~ seconds . Max. temperature of molten - 265 - 265 - solder, oC Max. contact time - 2.0 - 3�~ of each lea.dout Hith solder Min. distance from 1.0 1.0 1.0 1.0 housing to solder along leadout, mm Min. time between 5�0 5�0 5�~ 5�~ two repeated solderings ~ of same leadouts, min. 5�7� IC Assembly on Printed Circuit Boards The folloxing axe the design features of IC housings~ the presence of seal inlets and sealing sea.ms, and a relatively "thin" housing base (0.1...0.2 thick)~ to which are fastened the substrates or the chip, determine a whole number of specific re- quirements xhich must be implemented in assembling IC on printed circuit boaxds. All precautionary measures, in this case, are reduced to protecting the IC housing from impermissible deformations. -341- ~ FOR OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040500080030-5 On one hand, the assembly method must provide mechanical strength that would guar- antee resistance to mechanical loads expected in operation but, on the other hand, "rigid" attachment of the housing ia impermissible because the de�ormation of the printed circuit board (if its deflection is even several tenths of a millimeter) ma,y result either in the cracking of the sealing joints of the housing, or in the deforma.tion of the bottom and the rupture of the substrate or chip. In most cases of IC application~ mechanical stability is insured only by soldering all leadouts to contact pads. The neceasity and methods for additional fastening of the IC to the boaxd are determined by the rigidity of the operating conditions of the apparatus, as Kel]. as the' weight and size of the IC housings. T}ie design of the appaxatus must insure efficient removal of heat by air convection and heat-removing metal buses. The convection is provided by using housings with the maximum permissible gaps between the plane of the board and the bottom of the hous- ing. The housing arrangement on the printed circuit buaxd must provide the possi- bility of coating it with moistwce-protective varnish without having it fall into places tha.t should not be coated, and have free access for dismantling any IC. Taking int o account the necessity of preserving the integrity of the housing and to provide for heat removal, recommendations are given below for using vaxious types of I C. ' np~rnad~~ ul ~ 6l ~O~ , . ~ ~ n~~ua~ . d~ e f~ g~ Fig. 5.13. Vaxiations of mounting vaxious housings on the print circuit board with metal-coated holes: a,b housings with plug-coupler pins without additional fastening; c,d housing with plug-coupler~pins with additional gastening; e-- plastic housing; f-- cylindrical housing without additional fastening; g-- cylindrical housing with an electric insulation spacer 1. Spa.ce r - 342 - FOR OFFIC(AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 1~'1~,. ~.lju,b JI~ONJ varLations of mounting housings with plug-coupler pin leaciouts (housings 151.15-4 and 151.15-6). These housings are mounted in metal-coated holes. The IC do not have leadouts. The gap, equal to 1- 0.5 mm, is chosen to insure IC stability in the entire range of inechanical loads and the preservation of the integrity of the housing (at smaller gaps, it is possible to da.mage the seal inlet of inetal-glass housings due to the thermal effect of soldering). IC in housings 151.15-2~ 151.15-3 (~'1'-~� 5~13c) and "Aktsiya" (Fig. 5.13d) require additional fastenii~gs. IC in housings 151.15-2 and 151.~5-3 are glued to insula- tion spacers, fnr example, ma.de of D6V-2-R-2M (G(~T 17478-72) or AG-4 (GCBT 10087-62). The spacers must be fastened rigidly to the printed circuit boaxd. In choosing the dimensions of the insulation spacers, it is necessaxy tha.t they be as cloae as possi- ble to the axea of the IC housing base and that the integrity of the seal inlet be preserved. The IC in the "Aktsiya" housing (,Fig. 5.13d) is mounted against an LN cement~ placed along the perimeter. Cover should be provided with a two-sided arrangement of conductors in the board under the electric insulation of the IC housings. IC in housings 201.14-1 are mounted on boaxds with a single-side or a two-sided arrangement of printed conductors into metal-coated holes with a gap insured by the design of the leadout (Fig. 5.13e). Fir. 5.13f,g shows vaxiations of mounting IC with housings 301.8-1, 301.8-2 and 301.12-1 with formed leadouts. They are mounted with a gap of 3* 0.5 mm (Fig. 5.13f). If the appaxatus is subjected to - higher mechanical forces in operation, rigid spacers of electrical insulation mate- rial must be used. The sgacer should be glued to the boaxd and the base (to the bottom) of the IC (Fig. 5.13g). The design of the spacer must also insure the integrity of the seal inlets of the microcircuit. IC with cylindrical housings without leadouts are mounted onto metal-coated holes with a 1~ 0.5 mm ga,p. ~ u~ 6J a~ - Fig. 5.14. Vaxiations of mounting planar housingsi a-- against the .printed board; b-- with gap~ c-- against a spacer IC in housings 401.14-1 and 401.14-2 with sha.ped leadouts may be mounted on the bo~,rds with a single-aide or a two-sided arrangement of printed conductors by the following methods~ against the printed. boaxd ar on a spacer (Fig. 15.14a~c) or with a gap of up to 0.3 mm(Fig.15.14b). In this case~ the additional fastening is provided by coating with varniah. The gap may be increased to 0.7 mm~ but then the IC housing must be fastened additionally to the boaxd by glue. Planax housings must be glued to the entire plane of the housing base. The thick- ness of the seam is determined by the chosen variation of forming the leadouts (the distance from the plane of the IC base to the board), but the gaps between the IC and the boaxd must all be filled with g1ue. Yhen IC are mounted on planar - 343 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400540080030-5 N'OR OFh1Y'IA1, I,ISE l)NI.Y ~l~ /~l yP-?3f ~2~ ' . ~~~t, f w Q1 /IH yP-Z~i> N v~~ . Fig. 5.15. bcample of proper (a) and improper (b) mounting of a planax housing on a printed circuit 1. IN 2. UR-231 housings a shift of the free ends of the leadouts in the horizontal plane is per- mitted within � 0.2 mm for matching xith the contact pa,ds. FS~ee ends of leadouts may be shifted within � 0.4 mm in the vertical plane from the leadout position af- ter forming. ~ ~ The use of glues VK-9(3hehI0.026.400TU) or AK-20 (TU 6-10-1293-72), as well as ~ cement LN (TU NIICP. 3o52-55) to glus IC to printed boards is recommended. The dry- ing temperature of ma,terials used for fastening IC to the board should not exceed the permissible temperature for operating IC. The recommended drying temperature - is 65 f 5oC. In gluing IC to the printed board, the squeezing force should not exceed 0.08 microPa. ~It is not permissible to glue IC with glue or cement applied at individual points on bases� or at the ends of the housings. Fig. 15b shows an impermissible variation of IC mounting which is glued to the end of the housing (this may be done for simplifying the disma,ntling of IC). In this method, the gap between the bottom of the IC and the board is partially filled with cement. In implementing the moisture protection operation, UR-231 varnish may get into the ga,p which, by polymerization, raay be able to cause the deformation of the bottom of the housing (0.1...0.15 mm thick), the ungluing of the chip or break- age of the internal connectiona of the IC. In all cases of installation of IC on printed circuit boards, no force should be applied that leads to the deformation of the housing of the IC. -344- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 _ ~.8. LC protection Against Eleotriasl Effecte The degree of integration of the IC (i.e., the density of the grouping of elements on one wafer) is increasing with time because of the development of a teahnology tha.t makes it possible to reduce the dimensi~s of the elements, as xe~l as those areas by means of which the elementa are electrically insulated from each other on the IC Wafer. Such an increase in the density of the elements on the surface of the wafer makes it possible to improve the electrica,l and functional parameters of the IC~ but is accompanied by a reduction in allowa,ble electrical loads, and in- crea.ses the sensitivity of the microcircuits to static electricity discharges. Table 5.11 shows comparative typical chara,cterist~ics of transistors n~nufaetured by different technological procesaes. Table 5.11 Some parameters of vaxious designs of transistors Technical characteristics P'lanar epitaxial "Izoplanar-1" "Izoplanax3I" tec_, h~nolo~v technolo~? technolo~.v Dimensions of emitter 25x38 ~,x25 2.sac12.5 area, micrometer - Breakdown voltage 23 7 5 emitter-collector~ volts Breakdown voltage 55 22 14 collector-base, volts , Actually, an analysis of IC that failed in the p~rocess of praiuction indicatea that the cause of failures of up to 40 to ~Oy6 of such IC is electrical overload. In damaged IC there is detected a deterioration of the steepness of the volt-ampere slope or a complete breakdown of the p-n junction although there are no changes in the metal coating visible under a microscope. ~nitter ~unctions are damaged m~re frequently than others. E~cternally the defect is manifested in that the value of the reverse current increa,ses by several orders of ma~itude, xhile the current amplification coefficient decreases essentially (by 7096). In this case~ the elec- trical overloads cause irreversible changes in the p-n 3unction structures leading to the deterioration of~the efficiency of the emitter. A typical volt-ampere char- acteristic of the junetion for a reverse bias is shown in Fig. 5.~6. The emitter current (curve 2) is almost linear xhich may be due to the appearance of an ohmic shunt on the surface, or in the volume of the p-n 3unction. A partial or complete burn-out of the metal coating and ttre formation of juiqpers between adjacent tracks may occur~ along xith highly visible traces of p-n junetions breakdowns on the surface or under the passivating layer. - 345 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 r~rK �r~~~~ ~ni. ~ ~til~: ()NI.Y ~ ~3eo,M~S) 4 a> 3 . Qp1 - OA?J 1 / ~ ~ Z u,,e (6~ Fig. 5.16. Volt-ampere characteriatics of�emitter ~unctions of two transistors without housingsi 1,2 transistors in working order; 3,4 transistors after a 600-volt discharge through the emitter ~unction in the reverse direction; 5 microamperesf 6 volts IC~tha.t failed due to electrical overloads are characterized by the melting and spattering of aluminum (when boiling) and the formation of short-circuited adjacent sections of the meta:~ coating. The burn-outs occur most frequently at the "weak- est" points of the current-carrying tracks that have loca,l thinning (at the "steps" of the oxide). ~ Che cause of IC failures of the above-indicated types ma.y be the effect of dis- charges of static electricity originatirig during various technological operations due to the wide use~ under production conditions, of strongly electrifiable syn- thetic and other insulation materials. Moreover, due to poor grounding of device housings and technological tools, considerable network noise inductions may occur. The origination of static charges is due to aeveral generating mechanisms and the value of ~these charges dependa on maxiy factors. The values of static voltages (U~,) on the surface of the dielectric, independently of the mechanism of their generation axe alxays proportional to the apecific aurface resistance of the (PS This can easily be seen by ansly8ing the experimental data on the value of static voltages originating on the surfaae of several materials at a relative humidity of 5096 (Table 5.12) � -346- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000500080030-5 Fig. 5.17 showa the relationship between the atatic voltages and the relatiye air humidity of two types of material used widely for the apecial working clothes of production personr~~el Lavsan and cotton cloth. The relative humidity of the air is used as the parameter when measuring the voltages. In analyzing these relation- ahips, it should be noted that static potentials at low relative humidit~ of.the ~ air (40 to 5096) reach 3 to ~0 kilovolts. The static voltage on Lavsan ~.r higher than on cotton cloth and depends stro~gly on the reiat~ve himidity of the ~ir (at 659~ humidity the voltage on cotton is zero, while on Lavsan, it exceeds 3 kil- ~ volts). � In developing measures to protect IC from the effe~ct of static electricity dis- cha.rges, it is necessary to take into account a~s;o the ability of insula.ting wate- rials to retain charges accumulated on their surfaces for a certain time. As the charge retention time is assumed the time (~C y) during which the accumulated static voltage reduces to a half or a third. 2'y may be measured as folloksi the aurface of the tested material is charged (for example~ by rubbing) to a certain voltage and a fla,t metallic contact. electrod.e is applied to the surface of the me,terial. The electrode is connected to a type 5-95 static voltmeter and then the time it takes for the voltage to drop to half or a third is recorded. The charge rstention time is proportional to the specific sur- face resistance of the materia3.s exactly the sa.me as the values of the static volt- ages. Table 5.12. Static voltages and surface resistance of various materials Material U~Kvolts ohms Polyvinyl chloride 1.3 - 2.8 1x1014 wood o.? 1.4x1413 Glass 0.6 - 0.8 9.6x1012 Getinaka 0.45 ~ 4.3x1012 Table 5.13 Charge retention time on vaxioua surfaces Material 'r,~ . sec~ : ohms Paper 25 (3.3 -9i~)1011 Varnished wood 1200 1.4x10 Polyvinyl chloride 7800 1.Ox101~ Glass ~ 9000 2.2x1015 Synthetic linoleum 1~000 4.Ox1014 - ~347 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 , FOR OF6'ICIAL USE ONLY , . ~ !'a~?,~~- ~ ~ - . . . . ~ _ _ o . . : . . , ~ ~ ~1~ ~oooo . . ; .f ~ � , ~ , ' ~ . ~ � ~ ~n~~ I u � x - - . I: . . . . . y~~: ' x ' . , ~ . Z f0� ~ . ~ . SO ' ~10 . O~xr.ia~oaia,% : y . � . , i . ~li . ' o 5:17. Relationehip betxeen the value of static ! o and relative humidity of air for cotton ~ cloth (1) and Lavsan cloth (2) . ~ ~ 3. Yolte 4. Rumidity ~ , s ~ SO 70 ,t}7 ! (2) o~o,mra~ve avaayxa, ~ _ Fig. 5.18. Relationahip between ~ apeoifio aurface re- . , aiatance ( (~S ) of poly- . , vinyl chloride and the level of the relative humidity of the air, 1. ~ms 2. Air Hu- midity.~ 9~ Table 5.13 shox$ experimental data on charge retention tine at the relative huraidi- ty of the air of 6~6. The time retsntion time c~ the eurface of aynthetic linoleum xas measured at a loxer humidity (60~). It may be concluded ~om Fig. 5.18 that an increasa in humidity from 4~0 to 8396 re- duces the specifio eurfacs realatanos of polyvinyl ohlaride by five arciera of mag- nitude. In organizing apparatua production uea.ng IC, it must be remembered that considerable static voltagea, from hundreda to ssveral thoueands of volts~ are produced on the hands of the xorkers when doing varioue tachnological operations. The value and polarity of theae voltagee depend ou maay varioua factora~ including the humidity - 34-8 - ROtt OF'FIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R400504080030-5 of the air in tha room, the adterial of the clothing xorn, the materials used to cover the table and chnirs, the technological and tset aquipment and the degree - of insulation of the xarker From ths "ground" (m~teriale of ehoes and floor) ~'sa. 5. i9) . An analysis of the data in Fig. 5.19 ahoxs that ~th xatking shoes xith rubbar soles (curves 2)~ the static voltage an the har~ds of tha xorkers is 2 to 2.5 time~ ~ higher than when xorking in leather ehoe~ (curves 1). This is due to the fact that the leakage resistance of shoes With rubber and lea,ther solee differs ~y a1= most txo orders of m~gnitude (leskage resistanae of shoes xith rubber soles is 1.8x108-2.8x109 ohma~ xhile on leathe~ solea 3t ia 5.6~c106 to 1.9x1A7). It should also be noted that high valuea of ata~lc .voltages on the xorker8' hancLa correspond to the case xhere dielectrics xith hi~ apecific aurfaoe resi$tance are used at the xorking paaitian. . . . _ ~ . ~ . a~,e ~3) ~ o~~c ' ' ~ ' ~&;~,Q ~,,a . o~ , , ~ ~ ~ ~ , ~e~v ~ � ~ ~ ~ ' t~ " A617 . Z ~ " ~ ~ ~ x t ~ ~ . 2 . x~ ~ ,f~ 7G . a7 ~ ' d0 3i? 7D ~ ~ 3i~ R7 AD ~ ~i7 707 , ~ ~ al . g~o~!~ x ~ o ~ : Q~r.~m.% . ~ , Fig. 5.19. ~lationship betxeen the static voltag~e ariginating on the xorkere' hands ~hen rubbing different materials ar~d the relative level of the humidity of the air far the table surfaoe bein oP polyviayl chloride (a)~ varniahed ~rood (b), textolite (c), covered xith glass ~d). Korkere' ehoes with leatMer (1) and rubber soles (2). 3. volta ~ 4. Humidity, 96 i~lhen the workera xalk on a floar oovered xith eynthetic linolsum~ charg~ee are also accumulated on them (Fig. 5.20). The p~aventio~ of static electricity chargea in the productian p~ocess ahould p~ooeed in txo dirsctione~ firat reductiaal of the posaibility of static eleatri+~ity aharg~e generatio~ aad, eecaudly~ ineurance of the removal of acoumulated ohargea f~om the p~roducticn end technological equipmer?t and workers. - 349 - FOR OFF[CIAL USE O1VI " APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400540080030-5 . FOR OFFICIAL USE ONLY In organi~ing apgeratue production aectiona where IC are used the wse of finishing materials xith high specific $urfaca resiatance ie not recomme~ded. The use of finiehing materials for p~oduction t~rniture, floors testing and technological' equipment ma,teriala xi,th lox not over (1 to ~)10~ ohms,insures the necessary conditione for the rapid draining of the etatic electricity charges. ~ G~7t~'I~J.' ' . _ ~ o .x. , ~ � ~ � . 1A7 . 1G17 % ~ ; !0 ~ � . � ~ , � ~.�~+,x - : ~8� 5�20� Relationship betxeen etatic voltage on the worker at various values of the ralative humidity and degree of insulation from the floor, if tha xorkere' shoes he~ve leather (1) or rubber (2) eolea. 3. Yolta 4. Humidity, 96 Table 5.1~ Relative characteristiae of txo types of linoleum Type of synthetic Pg , ohms ohm. cm Z'y . secands linoleum - Common 4x1014 ~ 5.9x1017 12000 Antfstatic Sx109 2.4x1o9 0.5 A special antiatatic linoleum is reaommended to cover surfacea. The comparative electrical parameters 8pecific surfaoe (4~ ) and volumetric ( P~ ) resistances and the time of charge retention (~Cy ) of common and antistatic linoleums axe shoHn in Table 5.14. The use of antiatatic linoleum eliminatea the poasibility of charge accumulation on the warker~ a contact by the xarker'e hand xith a eurface covered by the anti- etatic linoleum bafare doing tha neat technological operation insures draining of the charge in 1 aecond. Synthetio oover P-2-B-S-S.haa tk~e best antiatatic proper- ties~ specific aurface resiatana� of the material ie 10 ohms. The use of auch material inaures the complata deetruction of tha atstic charges becauae the drain- ing time of a charge f5rom s persori ie only 2x10'~ $~onds. ~ - 350 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 - . . . .~.-'R~`{~~: ~ ~'~J~:'". . . . . . in" ~ : '~f~ . ~ ~ ~ . - . . . . . . . ~n � . ' ' � . . . , . : . . . , ~ � . . ~ ,~p~ ~~.re ' . Zs-'~ . . . ~ 5) _ ~ f ? 3 i 9 7~ t,el~r. Fig. 5.21. Relatia~ship betxeer? apeci~ic eurfsae resiataace ) of various me~terials and time befare and aF~er their trestment by "Oharodey~s" pdets~ ~ 1. syrithetic liuo~eum 3. cardbo~rd 2. teatolite 4. ohms 5. days Che of the methods recommended to redu,cs the speaific et~face redie~ance of covere is to use aurfacs=activs subatanoes (PAY)~ fa~ saa~pls~ "@~s~codeyks" paste (TU-6-15-604-?1)~ ~hich is applied in 8 thin laye~ on the xo~king di~lectric sur- facee of tablss, test arid teohnologioal equip~ent~ psokin6 for atariug IC atid aeasmbly unite~ and is ueed to mop floora atid xesh pspst aovers fos p~oduatiaaz furnitwce. The antiatatic p~operti~s of ths pe~ste xith rsspeot to tiae are ohar- acterised by e~cperim~e~~al data (Fig. 5.21) . The incre8as in eurfacs rsaietancs xith tims of ths p~oced~sed aurface~i~e dus to~the natursl drying arid aging of the pssts aad also to its bsina rubbed off in opera- tion. The rasistauce increaeea by an az~der oP a~ituds in 10 to 15 dayet there- � fore, the intervsl batxeeu applying ths paate should bs detes~ed on tha basi8 of aaocre~ts p~oduatians. In ths oas~ of uaing antietstic linoleun~ aa ~ell ss . _ ssi - P'OR OFF7CiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R400540080030-5 ~ FOR nF1~1C'IAI, t.1.5M: nNLY ~ in using PAV to drain charges~ it ia necessary to insure good eleotrical contact of one-txo points of the groceased surface (contact area not less than 1 cm2) with the "ground." To reduce the surface resistance of covers at working positions, it is recommended. to insure the maximum rela.tive humtdityr in the production axeas (a satisfactory re- sult may be achieved. at 65 to 7096 humidity) . Materials with surface resistances of 106 and 108 ohms are recommended for inter- operation packing. The packing material may be coated with aluminum current- ' conducting paint. The paint layer does not prevent charge draining becauae it has a low Ps � ~ The continuous oontact betxeen the xorker and the "ground" should be provided by a special antistatic bracelet, connected through a high-voltage~rasistor (for example, the KLV type 10 kilovolt resistor). Rowever~ it should be taken into account that the use of an antistatic bracelet ia effective only when the working position, packing and fixtures are made of materials with low surface resistances tha,t prevent the accumulation of static electricity chargea. Otherwise the possi- bility of IC damage ia high. Actua,lly, charges of static electricity on a high resistance surface, for example, on interoperation gacking,�may produce a voltage of up to several thousand volts on the packing itself~ as well as on the IC in it. At the moment of contact between the worker and the IC: when there is a current circuit "IC-xorker-ground" the pulae of the dischaxge current ma,y cause the failure of the IC E2]. The workers' clothes should be ma,de of cotton cloth, be laundered with antistatic '~Charod.eyka" paste or other surface-active substance. The workers shauld wear leather or semiconducting rubber soles. ~ 5�9� Dismantling In manufacturing apparatus, it frequently becomes necessary to dismantle IC. The following are reconuaended for this operation. If IC with planar leadouts axe to be disassembled~ it is necessary toi. remove the varnish at points of leadout solder- ing (if needed); unaolder the IC leadouts using a mode tha.t does not exceed the soldering mode specified in the IC certificate; lift the ends of the leadouts from where they wate fixed in the seal inlet; remove the IC from the boards thermome~ chanically by means of a apecial device. (This device is heated to a temperature that prevents the IC housing from overheating above the temperature indicated in the certificate. The heating time should be sufficient to remove the IC and not permit cracks, chipping and damage to the housing). _ When removing an IC with pin leadouts~ it is necessaxy toi remove varnish at the points of soldering of the lea,d.outsi unsolder the leadouts with a special soldering tool (the solder should be drawn off according to a mode not exceeding the aolder- ing mode, specified in the IC certificate~ until all IC leadouts are freed from connection with the metal-coated printed circuit board)f remove IC from the board (not permitting cracks~ chipping of glass or deforming of the housing and the lead- outs). In this case also,if neceseary~ it is permitted (if the housing is fastened = 352` - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 to the board xith varniah ar 6lue) to uee a thormo~schatiical method to remove the IC that prevents averhea,ting of the tioueing~ or chemical solveaita that have no effect on the coating, labeling a~d naterial of the houaiag. BIffi,IOGRAP~ 3 1. Inte~ated Circuita. Prfnciplea of Desi~t aad Production. Trarislated. ~om the ffi~glish. ~dited by A. A. Kolosov. l~oecox. 9ove~akoye radio~ 1967~ 2. Kaver$nev~ Y. A.s Zaytaev~ A. A.~ Ovschlcia. Yu. A. "S`tatic SLeotricity i.n the 3emiconductor Induatry." Moacox. ~ergi~ra~ 1'9'J~. C(~'YEIGIiP ~ I~datel' etvo "8ovetakoya radio", � 1979 2291 cso, 1863/209 - 353 - ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 ' FQR OwFt('IA1, 11~F; ONLY ~ Table of Contents Foreword ~ . Chapter 1 Page Terminology in microelectronics and clasaification of integrated circuits ( i.i. Introduction ( 1.2. Terminology in microelectronics 7 1.2.1 Integrated circuits, elements of coraponents (7). 1.2.2 IIements of design (7). 1.2.3. Simple and complex IC (9). 1.2.4. Microa.ssemblies and microunita (10). ~ 1.3. IC classification li 1.4. System for conventional designations of IC 12 Chapter 2 Integrated circuit ma,nufacturi,ng methods i$ . 2.1.~Film and hybrid technology i$ 2.1.1. Materials for hybrid IC (19)� 2.1.2. Manufacturing of hybrid IC elements (22).. 2.1.3. iiiring of electrical connections in hybrid IC (2k). 2.2. Semiconductor technology z4 2.2.1. Materials for elements of semiconductar IC and their manufacture (36). 2.2.2. Manufacture of integrated circuits (29). 2.2.3. Division of wafers into ehips, wiring of IC (35). 2.2.4. Sealing IC chips (36). 2.2.5. Manufacture of IC housings (37). 2.3� Special features of high degree of integration of IC technology 40 Chapter 3 ~ Digital integrated circuits 46 3.1. Purpose and application 46 3.2. Logic funetions obtained by digital IC- 46 3�3� Classification of digital IC and their basic electrical paxamet ers 51 3.4. Transistor-transiator logic circuits 56 3.4.1. Basic electrical parameters of type TTI, IC (70). 3.4.2. F~.inctional oomposition of TTL jeriea (72). 3�4�3� Some ~features of using TTL type IC ~78 J , 3�5� Emitter-connected transistar logic F~TL 8~ ~ - 3�5�1. F~anctional composition of the FSTL aeries (80). 3�5�2� Basic electrical parameters and typical cha~acteristics of type E5T'1, IC (99). 3�5�3� Some features of applying type ~ ic (io3). - 354 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000500080030-5 3.6. Digital IC ma,de of M1)6 109 3.6.1. Principle of IC operation with p-chaxinel M(~ ~ transistors (111). 3�6.2. Static circuits Kith p-channel MD6 transiators (113). 3.6.3. Quasiatatic and dynamic circuits (116). 3.6.4. Principle of IC operation Nith complementary MiS transistors (119)� 3�6�5� ~ic IC series xith M06 transiatars (123). 3~7� Inte~ated circuits of inemo~y units 130 3. 7. i. Me~mory elements fri.th bipolar transistara (131) . � 3.7.2. Memory elements xith MC~ transistars (134). 3�7.3� Memory elements ~ith complementary Hi~ transistors (135)� 3.7.4. Memory elements xith 1~'Q~1t~ tran~istors (136). 3�7�5� Memory elements wi.~h "silicon on sap ire (138). 3.7.6. Memory elementa uaing new materials ~138) 3�7�7� Basic IC memory units and their functional composition (141). 3.8. Perspectives of digital IC development 142 3�8�1. Integrated injection logic (143). 3.8.2. M+OB circuits with n-channels (i41+). 3�9� Microcalculators 146 3.10 Microprocessors 149 3.10.1. Microprocessor characteristics (150) 3.10.2. Medium speed microp~oceasor set (1 3). ~ 3�10.3. High speed microp~ocessor aet�(159~� Chapter 4 Analog integrated circuits 200 ~ 4.1. Purpose and application 4.2. Operational amplifiers ~ 4.2.1. Operational amplifier xith a two-stage circuit 207). 4.2.2. Amplifiers with field transistors at the input 214). 4.2.3. Amplifiers Kith auper-beta transiatoza (215)� 4.2.4. High current operational a.mplifier of the 153UD5 type (219)� 4.2.5. Quick-acting operational amplifiers (221~. 4.2.6. Micropoxer operational amplifiers (223 . 4.3. Integrated comparatora ~7 4.4. Integrated analog multipliers 231 4.5. Analog IC for radio receivers ~1 4.5.1. Differential amplifiera (243). 4.5.2. Low frequency amplifiers (UNCh) (244). 4.5.3. 3peciali~ed IC (248). 4.5.4. IC for deaigning selective devices (255)� 4.6. IC for mutual conversion of digital and analog data 273 4.7. Analog sxitches 4.8. Integrated voltage stabili$ers 2?'8 . - 355 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500084430-5 NnR ()I~FI('IA1. tltiN: ()NI.'Y ~:hs~}~t~~r ; Page Providing IC reliability when they are manufactured and installed in appaxatus 293 5�1� Design-technological principles for high IC reliability 293 5.2. aperational monitoring 295 5�3� Rejection tests 295 5.4. Effeci of external factors in apparatus manufacture 305 5.5� Forming and trimmfng leads 307 5.6. Tinning and soldering ' 313 5�7� Mounting IC on circuit boasds 320 5.8. Protecting IC from electrical effects 323 5�9. Diamas~tling ~ 329 Conclusion 331 CQPYRIGHTt Izdatel'atvo "Sovetskoye radio", 1979 2291 ~ cSn: 1863/209 - END - -356- FOR OFFIC'IAL USF ONI.Y APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500080030-5
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