JPRS ID: 10272 TRANSLATION RELIABILITY OF SOLID STATE INTEGRATED CIRCUTS ED. BY I. YE. YEFIMOV, I.G. KAL'MAN AND V.I. MARTYNOV

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_ JPRS L/10272
22 January 1982
Translation
RELIABILITY OF SOLiD STATE IIdTEQRATED CIRCUITS
Ed. by
I.Ye. Yefimov, I.G. Ka!'man and V.1. Martynov
FOREIGN BROADCAST INFORMATION SERVICE
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NOTE
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JPRS L/10272
22 January 1982
RE!IABILITY OF SOLID STATE INTEGRATED CIRCUITS
Moscow NADEZHNOST' TVERDYKH IPdTEGRAL'NYKH SKHEM in Russian 1979 (signed
to press 7 Sep 79) pp 1-216 '
[Book by Ivan Yefimovich YefimoW, Tgor' Georgiyevich Kal'man and
Vladimir Ivanavich Martynov: "Hard Integrated Circuit I:eliability;
Second Edition, revised and supplemented", Izdatel'stvo Standartov,
15,000 copies, 216 pages]
CONTENTS
Anr.e-cat ion 1
Chapter I. Basic Concepts of Semiconductor Integrated Circuits 3
~ Chapter II. The Reliability of Semiconductor Integrated Circuits 16
Chapter III. The M"ajor Kinds, Causes and Mechanisms of Semiconductar
Integrated Microci.rcuit Failures 30
I Failures related to pher_omena in the volume of the semicondtictor chi.p 33
2. Failures which depend on the state of contact bonds 34
3. Failures due to phenomena itt the chip suriace 52
= 4. Other kinds of microcircuit failures 55
Chapter IV. Methode of Monitoring and Estimating the Reliability
of Semic:onductor Microcircuits 59
5.
General principles
59
6.
The classification of tests
73
7.
Rules �or series production
product acceptance
112
~ Chapter V. Ways of Assu..ing
Semiconductor Integrated Microcircuit
Reliabilit,;
122
8.
Assuring integrated circuit
reliability during design
153
_ 9.
Assuring integrated circuit
reliability during the
fabrication st,age
157
, 10.
Assuring integrated circuit
reliability in the applications
stage
175
a - [I - USSR - N FOUO]
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Cha.pter VI. Metrologi_cal Support for Integrated Circuit Quality
~ Control and Reliability Testing 178
- 11. The role and p1acEt of inetrological support in the quality
control system 178
12. Basic principles of inetrological support for integrated
circuit quality control and reliability testing 179
13. The state inspection and departmental monitoring of
metrological suppo~-t 18E
14. Centralization of t:ests: a way of improving the level
y
oi metrological support for quality control 18$
Bibliography 190
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Annotation
The major aspects of semicanductor integrated circuit (IC) reliability are
treated in the book. The kinds and main reasons for IC failures during the
production pracess and in operation are cited. Methods of quality control
as well as the estimation and prediction of IC reliaUility are analyzed.
The book is intended for engineering and tec:hnical workers engaged in the
producti.on and utilization of semiconductor IC's, and will also be useful
t4 students in the VUZes and technical schools for the appropriata special-
ties. There are 31 figures, 26 tables and 186 bibliographical citations.
Table of Contents LOriginal pagination]
Chapter I. Basic Concepts of Semiconductor Integrated Circuits 3
� Chapter II. The P.eliability of Semiconductor Integrated Circuits- 17
Chapter III, The Major Kinds, Causes and Meeiianisms of Semiconductor
Integrated Microcircuit Failures 31
1. Failures related to phenomene in the volume of the semiconductor chip 34
Failures which depend on the state of contact bonds 35
3. Failures due tu phenomena at the chip surface 54
4.. Other kinds of mjcrocircuit failures 58
Chapter IV,. Methods of Monitoring and Estimating the Reliability
of Semiconductor I4icrocircuits 62
5. General princ iples
6. The classification of tests
7. Rules for series production product acce.ptance
62
77
120
Chs.pter V. Ways of Assuring Semicondur_tor Integrated Microcircuit
Reliability 129
- E. Assuring integrated circuit reliability during design
9. Assuring integrated circuit reliability during the
fabrication stage
10. Assuring integrated circuit reliability in the applications
, stage
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169
174
194
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- Chapter VI. Metrological Support for Integrated Circuit'Quality 196
~ Control and Reliability Testing
11. The role and place of inetrological support in the quality 196
control syste*.n
12. Basic principles of inetrological support for integrated 197
circuit quality control and reliability testing
13. The state inspection and departmental monitoring of 206
metrological support
14. Centralization of tests: a way of improving the l.evel 208
of inetrological support for quality control
Bibliography ' 210
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Chapter I. Basic Concepts of Semiconductor Integrated Microcircuits
A seiiiconductor integrated microcircuit takes the form of an electronic cir_cuit
produced in a monolithic semiconductor chip. The various regions of the chip func-
tion as independent active or passive circuit components, which are coupled to-.
gether by a system of thin film conductors. Such a monolithic circuit, as a rule,
is enclosed in a hermetically sealed package, where the electrical connections
between the contact areas of the circuit on the_chip and the package leads are
_ usually made with gold or alaminum conductors.
Modern technological methods, used for the construction of-IC's, mak.e it possible
chrough the use of the properties of semiconductar materials to fabricate both the
active components (trar.sistors, dipoles) and the passive components (resistors,
capacitors) of the circuit in the volume and on the surface of a single chip. The
techniques of ep{taxial build-up-of semiconductor material layers, photolithographic
etchings, dopant impurity diffusion, oxidation, thin film deposition and other
technologies are employed for these purposes.
~ Certain IC components are lepicted sche;uatically in Table 1 which are produr_ed by
planar epitaxy with insulatior. using p-n junctions. Various combinations of active
and passive components are used to realize monolithic IC's for various functional
purposes.
From a structural standpoint, IC's have come to be converitionally broken down into
two classes. The first class is logic or digital'circuits, which are used basic=
- ally in digital computers and controllers [1, 2, 41. In an integrated circuit.
- design, the circuits of this class are realized both in�the form of individual
logic elements (gates) of the following types: "NAND", "NOR","NAND/NOR", etc., as
well as in th e form of more complex elements (flip-flop, buffer circuits, half-
adders, counters, etc.).
- The second class IC's is comprised of linear or analog circuits. These include
primarily difrerent kinds of amplifiers (multistage, differential, operational,`
video amplifiers, read amplifiers, analog switches, etc.). It is more difficult
to make such microcircuits in integrated circuit form. The reason for this con-
sists in the lack of integrated circuit inductive components and in the high
requirements placed on the precision of IC resistors.
The major advantages of linear integrated circuits.as compared to analog circuits
using discrete components are the improved temperature stability (related, in par-
ticular, to the identical nature of the charac*_eristics of planar transistors), as
well as the favorable capability of realizing negative feedback. This is respons-
ible for the high operational reliability of linear IC's.
Theie is yet another class of integrated circuits which takes the form of a unique
"hybrid" of integrated circuits of the first two classes. These are li.near
pulse IC's, which usually include various cc:rrant drivers. Logic gates are in-
serted at the input to these IC's (for example, TTL circuitry), while analog
current pulse drivers with a high power dissipation level are inserted at the
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TABLE 1.
llesignation of the
Circuit Component
1. Resistor:
a) Simple;
bl Diffusion
"pinch";
2. Capacitor
3. Diode using
emitter and
collector p-n
junctions
4. Transistor:
a) Simple n-p-n
bipolar
b) Multiple
emitter
bipolar;
c) g-channel
MOS
d) n-channel
MdS (comple-
mentary)
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Conventional
Svmbol
A
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Schematic Depiction of the Component
Fabricated with Solid State Technology
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output. The production technology for linear pulse IC's does not differ from
the technology used in the fabrication of logic and linear IC's.
We shall treat in somewhat more detail the first class of microcircuits. The
following logic gates have become the most widespread at the present time [1, 3-6]t
--Resistor transistor or current switching circuits (PTTL), and MOS transistors
of the same type of `conductivity.
The increase in the functional complexity and level of integration cf integrated
semiconductor circuits required the modification of existing circuit designs
- and the creation of new ones which make it possible to substantially improve the
characteristics of the basic logic elements and large scale integrated circuits
(LSI's), designed around them (reduction in the power dissipation, increase in
the circuit speed, reduction in the area of the basic logic gates, etc.). As
a result, such logic circuits as the following are being developed and placed
in production [10-15J:
- --Modified transistor logic (with a supplemental transistor in the output circuit):
T3L;
- --Integrated injection logic: I2L;
--Emitter follower logic: EFL;
--Logic using complementary MOS transistors: CMOS;
--Logic using charge coupled devices: CCD's, etc.
Logic circuits are most easily realized in integrated circuit f orm. Because of
the fact that the logic devices (modules, assemblies) of electronic digital
, computers (ETsVM) can be put togeiher from identical functional componEnts, the
' finite series of logic IC's needed for computer construction consists,of a
comparatively small number (5 to 20) of standardized circuits. The use of IC's
as digital computer components which, as a rule, operate in the mil:.iwatt and
- microwatt power ranges, improves their operational reliability. This, in parti-
cular, has been responsible for the predominant development of logic IC's as
~ compared to linear ones.
The constant striving towards mi.crominiaturization of integrated circuits led to
the fact that the component layou,. 3ensity on a microcircuit chip increased by
more than three orders of magnitude over a decade (from 1962 through 1972). In
this case, the increased level of integration of IC's was achieved by increasing
the chip dimensions (from 1 mm2 in 1962 to approximately 6 mm~ in
1973), reducing the average size of the components and the spacings between them
on the chip (from 2- 10-2 mm2 in 1962 to 1- 10'3 mmz in 1973) and
using multilevel interconnections, which made it possible to approximately quad-
rupte the ratio of the actually utilized area to the overall area of the IC chip
[17].
Component miniaturization becaine possible only because of the refinement of the
fabrication technology processes for IC's and optical production process equip-
ment which makes it possible to use precision photographic templates for quite
sizeable areas. .
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As a result of working out the engineering design solutions and the fabrication
technologies for logic integrated circuits, considerable progress was achieved
in the fie11 of microminiaturization of electronic systems. Individual printed
circuit boards with logic IC's, combined in the modules and assemblies of digi-
tal computers, are being replaced at the present time by series and random
access memories (ZU), iogic gates with an arbitrary structure and microprocessors,
made on individual chips, i.e., realized in the form of LSI's [10].
The basis for the achievements in the field of systems engineering is the exten-
sive set of technologies, which are distinguished by their diversity and capa-
bilities of improving the qualitative characteristics of IC components.
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Figure 1. (a-e). Transver5e sections through planar transistor structures,
fabricated using various technologies.
Key: 1. Silicon;
2. Silicon dioxide;
a. Triple diffusion (3 D technology);
b. Epitaxial collector (planar epitaxial technology with insulation
Of the elements by p-n junctions);
c. With dielectric insulation;
d. Insulation created during collector diffusion (CID technology);
e. Isoplanar technology (with insulation of the elements by a
_ dielectric).
The topological drawings and technological characteris~ics of various four-input
basic logic gates, realized in the form of TTL, ECL, I L and MOS structures are
shown in Tab1e 2 to compare the capabilities of the various technologies [11,12].
The maximum functional 3ensity (number of circuit functions per unit of chip
_ area) is limited by the amount of power dissipation or the area occupied by the
transistors, interconnections and passive elements [9]. Thus, the maximum pack-
aging density of an IC is obtained with a minimization of the supply voltage and
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the geometric dimensions of its components. Since the minimum size of the major
IC element (transistor) is governed by thE "closure" effect (the mutual overlap-
ping of depleted layers when the supply voltage is raised), to further reduce
IC dimensions, it is necessary to increase the doping concentration of the
diffusion regions of the structures with fine layers.
Cross-sections through planar transistor structures fabricated using various
technologies are shown schematically as an illustration in Figure 1(a-e):
--Triple diffusion (3 D technology) (Figure 1 a);
--Insulation created during collector diffusion (CID technology) (Figure 1 d);
--Isoplanar technology (with the insulation of the elements by a dielectric)
(Figure 1 e).
The technologies for fahricating integrated semiconductor circuits have been
treated in detsil in domestic and foreign literature [7, 2, 4, 5, 8]. For this
reason, in this section we will deal with questions of IC iabrication technology
only in order to discuss the major factors governing their reliability.
Planar technology methods are used to construct IC's (doping impurity diffusion,
plate axidation and photolithographic etching of an oxide film, thin film
deposition, etc.), which make it possible to obtain individual circuit compo-
nents and make electrical.connections between the components by means of thin
Film conductors ("meta"Llization"). A combined technology is used when fabrica-
ting resistors with high nominal values and having a small scatter in their
characteristics. P. distinctive feature of combined technology is the fabrication
of resistors by means of deposition on the surface of the semiconductor structure,
created by planar epitaxy, of a thin film of material with a high specific
resistance.
Silicon usually serves as the main semiconductor material used in the fabrication
of IC's. The use of silicon assures good producibility of the devices in the
fabrication process using planar technology methods. In this case, the execu-
tion of the oxidation and photolithography operations on silicon is substantially
simpler than when other semiconductor materials are used. Moreover, the opera-
tional temperature range of semiconductor devices made from silicon is signifi-
cantly wider tran for germanium devices. However, the merits of silicon do not
preclude the possibility of using other raw materials in some cases.
We shall consider one of the basic technological processes in the fabrication
of IC's using planar epitaxy with insulation of the elements by p-n junctions
and one-level metallization. ,
A chip of p-type silicon with an epitaxially grown layer of n-type silicon on
it and locally formed hidden n+ type layers, locate3 at the "epitaxial film--
substrate" separation boundary in~the regions of the future transistors of the
IC's for the purpose of improving their electrical parameters serves as the
starting material in this case.
Using group techiques, by means of alternate oxidation, photolithogxaphy, diffus-
sion and deposition operations, several hundreds of chips are produced simultan-
- eously on this plate, where each of the chips takes the form of a complete
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microcircuit. After this, the plate is cut into individual chips and each chip
is mounted in a package. Then the packages are hermetically sealed and the
quality contro 1 and sorting of the finished IC's are carried out.
Cross-sections through such an IC in various stages of tne technological process
of its fabrication are shown schema.tically in. Figure 2(a-f) . For the sdke of
simplicity, on ly the transistor stYUCture and diffusion resistor are shown.
Diodes, as has been noted, are realized on the basis of the transistor structure
by using its individual junctions ("emitter-base" or "collector-base"). The
typical production process consists of the following main operations:
--Oxidation of the plates of the starting material (Figure 2a);
--Photolithogr aphic etching of the oxide film to produce the configuration of
the insulated regions:
--Stage I of b oron diffusion (infusion - the application of the boron);
--Stage II boron diffusion (dispersal - the insulating diffusioa of the boron
through the entire thickness of the epitaxial layer) and oxidation of the
silicon (Figure 2b) ;
_ --Photolithographic etching of the oxide film to c*:eate "windows" underneath
- the base re gions of the transistors and underneath the diffusion resistors;
--Stage I boron diffusion (application of the boron to the surf ace of the bases
and resistors) ;
--Stage II boron diffusion (dispersal of the dopant to the requisite doping
depth of the base--collector junction) and the oxidation of the silicon in the
"windows" (Figure 2c) ;
--Photolithographic etching of the oxide film to create "windows" underneath the
emitter regions and the contact areas of the collector;
--Stage I phosphorus diffusion (application of the phosphorus to the surface of
the emitter areas and the collector contacts);
--Stage II ph osphorus diffusion (dispersal of the dopant to the requisite doping
depth of the emitter--base junction) and the oxidation of the silicon in the
"windows" (Figure 2d)*;
- --Photolithographic etching of the oxide film to create "windows" underneath the
contacts (Figure 2e) ;
--Deposition of a thin aluminum film;
--Photolithographic etching of the aluminum to shape the requisite configuration
of the internal circuit wiring between the components (Figure 2f);
--The melting- in of the aluminum;
--The cutting of the plates into chips;
--Sorting and rejection of the chips (finished IC structures) with respect to
the electri cal characteristics as well as visually;
--Mounting of the chip on the package base;
--Heat compression or ultrasonic welding of wire leads to the contact areas on
the chip;
--The welding of the wire leads to the external package leads;
--The hermetic sealing of the IC;
- --Technological testing of the IC;
--Sorting and rejection of the IC's with respect to the parameters.
*The stage I and II phosphorus diffusion operations can be combined in a single
process.
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a (a) (b)6
d (c) (d) s
(e) g
(f) e
Figure 2(a-f). Schematic depiction of the cross-sections of an integrated
circuit at various stages in the fabrication.
The oxidation of the plate is accc::;.llic:-.ed in an oxidizing atmosphere at high
- temperature. The thickness of ttie layer should be sufficient so that with
subsequent diffusion operations, the penetration of the diff usant into the
oxidized regions of the silicon plate is prevented and reliab le protection of
the surface of the already fabricated structure is assured.
The photolithographic etching of the oxide film as we11 as the diffusion of the
doping impurity and the oxidation of the silicon must be handled separately,
since the sequential alternation of these main processes makes it possible to
essentially obtain the entire structure of the circuit and assure the requisite
internal circuit layout separation.
The function of the photolithography process consists in shaping the "windows"
in the oxide film, which are intended for the diffusion of the doping imp urities
- or for the fabrication of contacts to the silicon in regions of the plate
cleaned of oxide, as well as for making internal circuit connections (intercon-
nections) of a definite configuration between the individual components of the
integrated circuit.
For this purpose, a thin layer of photosensitive varnish, the photoresist, is
applied to the oxidized surface of the plate, after whi_ch the figure is
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transferred from the photographic template to the photoresist layer by means of
contact or projection photographic printing. Ultraviolet irradiation of the
- photographic layer increases the speed of photoresist dissolution in the
developer. During the developing process, the exposed portions of the photo-
resist are dissolved in the developing solution. After thermal hardening - the
polymerization of the remaining photoresist - an acid resistant mask is obtained,
which makes it possible to etch the oxide (or metal) film in the areas not pro-
tected by the photoresist, and thereby obtain in the oxide (or metal) film the
figure corresponding to the photographic template. When the oxide etching
process is completed, the plate is cleaned of the photoresist, after which the
plate with the corresponding figure in the oxide is sent on for the doping
impurity diffusion operation (or the operation of inelting in metal). The dif-
fusion of doping impurities is intended to create regions of p or n conductivYty
at the appropriate points in the chi.p. The doping impurities diffused into the
chip at points free of the oxide, which makes it possible to localize the impur-
ities in the corresponding regions of the semiconductor material and thereby
create the requisite circuit components.
For the purpose of having better control of the diffusion process, it is usually
accomplished in two stages. The impurity is initially applied to the surface of
the plates, which then goes into the shallow surface layer of the silicon
through the "windows" in the oxide (Figure 3). After this, the plates are
annealed at high temperature in an oxidizing gas medium, the so-called dispersal
of the impurity. In this case, the impurity diffuses down to a specified depth,
producing the requisite diffusion prcfile, while the oxide film which appears
protects the surface of ttie plate and the p-n junction being created against
exposure to the environment.
We shall now analyze the, process of fabricating a silicon IC step by step.
After the oxide film is appl.ied to the plate of the original silicon, it is
photolithographically etched to produce the configuration of the insulating
regions. As as result, grooves are created in the oxide film which expose the
- silicon for the diffusion of tke p-type doping impurity in these regions, some-
thing which is essential for the creation of electrically insulated n-type
"pockets", in which the individual integrated circuit components will be fabric-
ated in subsequent stages (Figures 3a, b).
Windows underneath the base regions and underneath the diffusion resistors are
created in the second photolithographic stage in the corresponding insulated
portions of the structure. The resulting figure on the oxide film should pre-
cisely match the relief obtained as a result of the first photolithography.
The next diffusion of the p-type doping impurity is necessary to produce the
base collector junctions and the regions of the diffusion resistors. The holes
created in the oxide by the preceding photolithographic etching are covered
with an oxide layer, which is grown thermally during the second stage of boron
diffusion (Figure 3c).
In the subsequent step, the third photolithographic etching is accomplished for
the purpose of creating "windows" underneath the emitter regions and the
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contact areas of tlie collectors. It is absolutely necessary in this case that
- the new pattern of the photographic template completely match the already
existingpattern on the oxide layer.
6 7 5 7
" 4
3
n ~ 2
n
R# - - ~
P
a (a)
Figure 3.
Key:
2
-6 (b )
2
" P. ---n
P /
e (c)
7 5
y
3
n n 2
n# P !
Z (d).
n� n' � t
n~,---- I
a (e)
9 f0 fI 1? B 2

f
e (f)
Defects in integrated circuits related to photolithography
defects.
1. Silicon;
2. Silicon dioxide;
3. Photoresist; .
4. Photographic template;
5. Ultraviolet radiation;
6. Scratch on the photographic template;
7. Dust particle;
8. Aluminum;
9. "Base-emitter" short circuit;
10. p-n junction with low breakdown voltage;
11. "Emitter-collector" short circuit;
12. Diffusion tube, diffusion-resistor break.
The next phosphorus diffusion produces n-type regions needed for making the
emitters of planar rransistors and the regions of contacts to the collectors,
which makes it possible to improve the characteristics of the corresponding
ohmic contacts (Figures 3d, e).
Then the fourth photolithographic etching is carried out, during which "windows"
aze created in the oxide underneath the contacts to all elements of the planar
structure formed during the preceding operations in the production process cycle.
After this, the internal circuit connections are made between the individual
components (Figure 3f). For this purpose, an aluminum layer is initially
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- deposited on the entire surface of the plate, and then by means of photolitho-
; graphy the unnecessary aluminum is removed, as a result of which, the requisite
pattern of connections between components is produced. The operation of inelting
in the aluminum promotes an improvement in the adhesion (sticktng) of the metal
film to the surface of the substrate, as well as an improvement in the character-
istics of the ohmic contacts. At this stage, the production process for produc-
- ing the structure of the integrated microcircuit is essentially completed. Sub-
sequent operations, as has already been noted, are carried out to break the
plate up into chips, mount the chips in packages, hermetically seal the packages
and check the characteristics of the finished IC's.
To realize all of the advantages of semiconductor microelectronics which assure
a high level of IC quality and reliability while maintaining a high percentage
of good product output, careful handling of all of the technological operations
and the assurance of effective monitoring of the IC production process are
essential. This is especially important in the production of integrated circuits
with an increased level of integration. The task is facilitated significantly
by the fact that the technological operations and the equipment used are of
the same type, which makes it possible, first of all, to standardize the produc-
tion process using a limited number of basic technological pr.ocesses for IC
fabrication, and secondly, to provide for effective control of the production
process and thereby achieve high IC quality and reliability.
The following play a large role in IC production: the purity and perfection of
the crystalline structure of the semiconductor materials; the careful proces-
sing of the plates, which provides for high purity of their surface; the use
of ultrapure chemicals, water and gases; high photographic template quality
(strict tolerances for the geometric dimensiQns, no damage to the pattern of the photogra.phic layer and "compatibility" of the set); and precision in the
combining operations. All of these requirements follow from the major feature of the production of
integrated circuits with a high layout density of the circuit components on a
single chip. If only one dust particle of micron size or diffusant particle
gets on the surface of a planar structure during the diffusion (Figure 4a),
oxidation (Figure 4b) or photolithography, it can lead to the disruption of the
requisite diffusion profile and the appearance of so-called "diffusion tubes"
or to a degradation of the oxide film quality (punctures, holes), which serve as
the cause of short circuits, elevated leakage currents and a reduction in
breakdown voltages.
The presence of dirt and moisture in the energy -vehicles, for example, in the
oxidizing or inert gases, has a negative impact on IC quality, since the masking
and passivating properties of the oxide fiJ_m are sharply degraded in this case,
something which, in the first place, significantly reduces the output percentage
of good circuits, and secondly, can lead to the most diverse IC failures during
their testing and operation.
Dislocations, microcracks, sections with a nonuniform doping impurity distribu-
_ tion and other microdefects in the crystal lattice of the initial semiconductor
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r
(a)
Figure 4. De
Key: 1.
2.
3.
4.
5.
(b)6
fects in integrated circuits related to diifusion defects.
Silicon;
Silicon dioxide;
Dust particle;
Diffusant (donor) particle;
Diffusion tube, diffusion resistor break.
material are causes of the appearance of potentially unreliable integrated cir-
cuits, especially in the case where the indicated defects occur in the region
of the active components of IC's or prove to be close to the p-n junctions.
The precision in combining the templates in the photolithography process, which
is due to the great layout density, is of exceptional importance in the produc-
tion of IC's. If a useful output of 0.85 to 0.9 is obtained after each super-
imposition operation, then following the fourth combination photolithography
process, the quantity vi rejects because of just one unsatisfactory combining
operation will amount to 35 to 50 percent (in practice, this quantity will be
less since several defects occur in the same structure).
IL- should be noted that when fab r icating the contact connections, a whole series
of difficulties come up, wliich are related, first of all, to the complexity of
producing intersecting connections, and secondly, to the appearance of parasitic
capacitances between thin film conductors positioned. close together, the length
of which can reach a significant value in complex circuits.
One of the most important problems which occur in IC production is the problem
of insulating circuit components. The choice of the method of insulation plays
a substantial part from the viewpoint of both the fabrication technology and
the quality and reliability of the finished IC's, since the insulation determines
the parasitic feedback loops (leakages, parasitic capacitances, etc.) between
the circuit elements. The method of insulating elements with isolating p-n
junctions was described above. O ther techniques of element insulation are
- also possible, for example, using a layer of silicon dioxide.
The design of high quality and high reliability IC's is a complex problem. The
fabrication technolo_gy for IC's gives them advantages over semiconductor devices
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and other electronic technology products. However, these advantages can be
realized unly given the condition that all of the specific features of IC pro-
- dsction are carefully taken into account and with the comprehensive resolution
of several structural design and technological problems.
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Ctiapter II. The Reliability of Semiconductor Integrated Circuits
- In integrated semiconductor circuits, the active and passive components are com-
Uined in a monolithic chip and manufactured in a single technological proces5.
This is responsible for their high liability [1, 2, 4, 18, 191.
Planar technology is employed in the fabrication of IC's, which provides for
goocl protection of the p-n junctions against the impact of the environment.
Microcircuits, as was noted in Chapter I, are fabricated using a group technique,
in which several hundreds of semiconductor IC chips are produced on one plate of
semiconductor material under identical conditions and production modes. The
hermetic sealing of the finished functional unit, which is the integrated cir-
cuit, in a single package makes it possible to simultaneously protect the
entire set of circuit components against exposure to the environment. It is
anticipated in this case that the reliability of a circuit enclosed in a single
package will increase with increasing circuit complexity and number of cbmpo-
nents, figured on a per function basis.
The comparatively small quantity of standard technological operations, the con-
tinuity and closed nature of the fabrication process for integrated circuits,
within the bounds of a single production line, allow for the maximum automation
of the fabrication and quality control processes, a reduction in the probability
of allowing errors and the achieving of uniformity in product quality. As com-
_ pared to semiconductor production, well organized integrated circuit production
is characterized by a smaller scatter in the parameters and characteristics of
the finished product.
The relatively small number of contact connections in integrated circuits as
compared to circuits designed around discrete semiconductor devices and other
electronic hardware components, and the more sophisticated fabrication tech-
- nology for integrated circuits are also responsible for the high reliability
of the solid state devices.
Thus, integrated circuit reliability proves to be approximately equal ro the
reliability of a single transistor, meeting the most modern requirements, while
the application of IC's opens up broad possibilities for further improving
equipment reliability. Comparative data on the reliability of several radio-
_ electronic assemblies, constructed using various components, are given in Table
3[20]. An analysis of these and other data makes it possible to draw the con-
clusion that in the integrated circuit variant, the radioelectronic assemblies
have a reliability which is two to three orders of magnitude greater than the
reliability of similar devices designed around vacuum tube and semiconductor
devices.
It should also be noted that the increase in the functional complexity and
level of integration of IC's, related to the increase in the number of compon-
ents in one device, up to a known limit (up to the level characteristic of
circuits using discrete components) does not reduce its reliability. Thus, for
example, if the failure rate at normal temperature is 10-7 hr-1, and at a
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TABLE 3. Comparative Data on the Reliability of Radioelectronic Equipment
Assemblies Constructed Using Various Components (Failure Rate in
hr' 1)
Radioelectronic
Equipment .
Unit (or Device)
Flip-flop
Half-adder
"NAND" gate
J-K Flip-flop
Vacuum
Tubes
5.1�10'4
4.7�10-4
4.4�10-4
9.2'10-4
Discrete Semiconductor Device
Comvonents _
Ordinary Accep- Following Special
tance Testing Selection
5.3�10-5 3.7�10-6
3.9�10-5
3.9�10-5
9.5'10-5
1.7�10-6
2.4'10-6
4.1'10 6
Integrated
Circuit~
8.5�10-7
8.5�10-7
8.5�10 7
8.5�10 7
- temperature of +85� C is equal to 6- 10-7 hr 1(which corresponds to the relia-
bility of a series produced plan-r siZicon transistor) for a microcircuit,
equivalent to a radioelectronic circuit consisting of 20 discrete components,
then a radioelectrunic circuit incorporating 10 such transistors and other
components will have a failure rate a of (1--6) � 10-6 hr'1. This clearly
illus�trates the advantages of semiconductor IC's as components for equipment.
Besides the considerable reduction in the number of components, with tre use'of
IC:'s in equipment there is a substantial reduction in the number of different
kinds of connections, something which also leads to a reduction in its failure
rate.' As is well known, contact connections have an impact on the reliability of any
device. This is explained by the fact that device or equipment reliability is
composed of the reliability of the elements comprising the device or equipment,
as well as their connections. For the case of independent failures, this func-
tion is written in the following expression:
k Z
atotal' - iE1Nei~ei +'JE1Ncjacj
where atotal is the integrated circuit (radioelectronic equipment unit) fai.lure
rate;
Xei., xcj is the failure rate of the i-th integrated circuit (or,device)
component and that of the J-th contact connection between the
components;
Nei, Ncj is the number of components incorporated in the integrated cir-
cuit (or the electronic equipment unit), and the number of connect-
ions between them.
_ It is apparent that the use of IC's leads to a sharp reduction in tlie number of
welded and soldqred connections between various components, figured on the
basis of the function performed. It is specifically for this reason, that despite the fact that welded contact
connection reliability is usually less than the reliability of other structural
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elements of monolithic IC's, by vircue of the smaller number of contact connec-
tions per unit function which is performed, the reliability of IC's as a whole
is better than the reliability of similar electronic products for a similar
ftnctional purpose, desigr_ed around other components.
For the same reason, the reliability of radioelectronic equipment units designed
around IC's is several orders of magnitude higher than the reliability of equip-
ment designed around discrete semiconductor devices, and the "gain" from the
use of IC's increases with their increasing level of integration and functional
complexity.
An important factor which has a favorable influence on the operational charac-
teristics and reliability of IC's is their low weight. This is.due, on one
hand, to the good mechanical qualities of both the IC's themselves and the
equipment designed around IC's (strength and immunity to the impact of vibration,
shock and linear loads). On the other hand, the miniature dimensions (and low
power consumption) create the prerequisites for improving radioelectronic equip-
ment reliability by virtue of providing for redundancy.
_ An finally, the use of IC's as the component base for radioelectronic equipment
reduces by many times the possibility of decreasing equipment reliability,
related to the incorrect use of the components. This possibility is due pri-
marily to just the technical clarity of the use of integrated circuits. The
more discrete electronic products are replaced by IC's, the lower the probability
of making mistakes when installing and aligning equipment.
In step with the refinement of the structural design of IC's, their fabrication
technology at~ well as the accumulation of experience with the manufacture and
_ operation of rac;~.oelectronic equipment designed around IC's, a substantial
improvement is being observed in the quantitative indicators for the production
and operational reliability of IC's.
The IC reliability level achieved at the present stage of integrated circuit
electronics development is characterized in different cases of IC applications
by a nonfailure operating probability of 0.999 - 0.9999 in 10,000 hours.
According to some data obtained from the sphere of radioelectronic equipment
opeLation, the failure rate of IC's is 7� 10-9 hr 1 at a confidence level of
0.6 [21, 27, 281.
The service life of solid state semiconductor devices is significantly greater
- than the service life of other electronic equipment products. At the present
time, accepted practice is to guarantee a service life for IC's of 10,000 to
15,000 hr. An improvement in the quality of the package protection for IC's,
an increasa in the reliability of their contact connections up to the level of
the reliability of the semiconductor structures, a iurther increase in the
quality of the active.elements and the stability of the surface properties of
planar structures as well as the absolute observance of the requirements of
the technical specifications and standard setting documentation during opera-
tion will make it possible to achieve the ultimately possible service life
and reliability of IC's.
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.
TABLE 4. Generalized Data on U.S. Integrated Circuit Reliability
Maximum value of
the failure rate for
Volume of the a confidence leVe1
Tempera- tests, x 107 of 0.6 and higher,
Conditions ture �C circuit-hr hr-1
IC operation as part of
radioelectronic equipment More than 35 (0.7--90) � 10-8
Service life tests uf IC's 25 More than 1 (0.6--6.7) � 10-7
Operation of minicomputers
using MOS LSI 55 About 5 0.8 ' 10-7
Service life tests of IC's 85--125 More than 7 (0.16--18.0) � 10�6
The same 125 More than 1.3 8.4 � 10-8
The same 125 About 4.3 2.2 � 10-8
The same 150--200 More than 0.6 (0.02--5.0) � 10-5
Field tests More than 0.5 1.8 � 10-6
Accelerated stepped tests 125--200 More than 0.9 6- 10-6
Storage 25 More than 1.7 5.6 � 10'8
The same 150 More than 9 0.63 � 10'7
The same 150--175 More than 3 (2.2--2.9) � 10-6
The same 200--300 More than 1 (0.9--2.4) � 10-5
Generalized data on IC reliability, obtained from tests of IC's and during opera-
tion of radioelectronic and other equipment and instruments using these compon-
ents, are given in Table 4[20-28, 30]. And the curves shown in Figure 5 demon-
- strate the reduction in the failure rate of semiconductor IC's made by Texas
Instruments Inc. during 1961--1973. The reliability of series produced products
has grown by several orders of magnitude over the past decade. As far as micro-
circuits produced in accordance with special programs for particularly important
facilities are concerned, the growth in their reliability is characterized by
even more impressive figures [27].
The convincing success in achieving the high "natural" reliability inherent in
solid state components gave the specialists of the above mentioned company the
incentive to intoduce a new measurement unit for the integrated circuit failure
- rate into everyday practice. Since in operating with the measurement unit
adopted in the U.S. for the failure rate - percent per 1,000 hr - with a low
- failure rate (hundredths and thousandths.of a percent), there is a high pro-
bability of erroneously estimating the reliatiility, a new measurement unit was
- introduced into pr.actice: the FIT. One FIT is equal to one IC failure per 109
device hours [28].
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i~ -
In analyzing the data of the table, the
conclusion can be drawn that the.reliability
of IC's incarporated in electronic equipment
1.~ E 1U4
when it is in operation is considerably
Cd o
~ ~s ,
higher than their reliability determined
during testing.
~~ro�'
~ E~v'� Z
This is explained by the fact that during
3
~ 1961 /963 1965 1967 1969 197f 1973G
operation, IC 'S t18tlSlly operate in ZeSS
severe modes than during the testing pro-
cess. A properly c?esigned radioelectronic
Figure 5. The decrease in the
'
syste-m provides for its components to be
s
failure rate of IC
used in alleviated operating modes and in
Key� l.Series production;
.
the majority of cases, under conditions
2,3.Integrated circuits
close to normal. The electrical circuits
fabricated in accor-
of such systems are designed taking into
dance with various
account the permissible variations in the
reliability programs.
values of the major parameters. A circum-
stance of'no small importance is also the
nassive numbers of IC's in service
and the long operating time, which. are respon-
sible for the accumulation of an enormoua amount of experimen~.al material, and
consequently, the high statistical
significance of the estimate.
When testing IC's though, everything is reversed. In striving for production
profitability, reduction in the product manufacturing time and an increased percentage output of good products, the manufacturer directs his ef;orts pri-
marily towards the timeliness of obtaining data on the quality and reliability
of the output product. For this purpose, he knowingly limits the scope of the
tests, compensating for this by increasing the severity of the test modes, con-
ditions and evaluation criteria for the test results.
The accumulated operational and testing experience makes it possible to state
that inherent in IC's fabricated using planar epitaxial technology is a lack of
an explicitly pronaunced burn-in period and in practice, a minor and timewise
uniform failure of IC's is observed in the process of their long term operation
under normal conditions (Figure 6).
At the same time, during tests o:f IC's under conditions of severe loads (espe-
cially with the loads applied in combination), an elevated failure rate of the
IC's is observed in their initial period of operation. The potentially unreli-
able samples, having hidden production defects (and�by virtue of this�, a short
service life), generally fail in a period of 1,000 hours of operation. The
majority of them fail in the first 200 to 500 hours. Incorporating special kinds
of tests in the production process cycle for IC fabrication provides for the
timely rejection of such circuits [4, 20, 27-30] and increases the reliability
of the manufactured batches of devices.
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;
0-1
v~J x-i
�-J
~0 1 HT x
(A)
>�c o
D
f000 10000
BpeMx,m Ti~m00e, hours
Figure 6. The failure distribution
of IC's fabricated using
planar epitaxial technology
as a function of time for
reliability testing at an
ambient temperature of
_ +125� C
Key: 1. IC chopper;
2. Micropow.er "OR--NAND--
NOT" IC;
3. Logic IC
A. Numb er of f ailures,
. units.
formation of electrical fields which act on the device s m a
a mechanical load, localized at one point.
The criticality of IC's to electrical overloads is responsible for the special
requirements placed on the use of these devices. The operational modes of radio-
~ electronic equipment and systems using IC's should also preclude the appearance
of electromagnetic pulses as well as those transient processes when switching
- circuits and when defects occur which would cause the IC to fail.
An analysis of the operational data and the results of all possible IC tests
shows that the IC failure rate during operation and storage differ substantiaTly
and depends greatly on the ambient ~temperature (Figure 7).
The ambient temperature, along with IC overheating caused by internal power dis-
sipation, leads to a-change in device parameters. The transistors of IC's are
especially 'sensitive to a temperature change. Just as significant as the tem-
perature dependence is the temperature coefficient of resistance (TKS). Plotted
in Figure 8 are graphs which illustrate some of the major parameters, the pro-
perties of IC quality, as a function of temperature [4], and Table 5, the mean
time betwesn failures as a function of the junction temperature.
Because of the structural design and production.process features of silicon IC's,
the impact of temperature on their reliability is a great deal less than on
certain other semiconduc*or devices, in particular, germanium ones, nonetheless
it is significant, and this phenomenon cannot be disregarded.
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The electrical load has a substantial
impact on IC reliability. With the
action of the current flowing through
an TC, because of local overheating at
defective points in the metalized inter-
connections (scratches, local thin
places.in the aluminum film at stepped
points in the oxide down to values lower
than the permissible) melting of the
interconnection material takes place,
while in the presence of moisture and
dirt, corrosion of the aluminum wires
and other thin film components of the
IC is observed. .
A voltage applied to a device causes
the formation of surface channels with
the opposite type of conductivity and
breakdown of the oxide in samples with
a contaminated surface or with an ele-
vated content of inetal impurities in the
oxide layers.
Under certain conditions, the electrical
voltage applied to an IC can lead to the
i il r to the action of
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~
0
~
0
0
0
0
(A~
~
S
a la)
:3.
0
~
0
&
0
0
F
(A~
4
Z
,t - 0
4,6
ical function X= f(T) for IC's during operation (a)
_ Figure 7. Typ
= and in storage (b). _1
Key: A. Failure rate, hr
Numerous studies have made it possible to parameter
of a semiconductor structure in IC s occurs a
elevated temperature at temperatures above 300� C. It can be seen from~egise
g, where the major e~ectrical parameters of a three-input "NOR" logic ga
- plotted as a function of the ambient temperature that up to a temperature of
- +300� C, no substantial changes are observed in the values of the parameters.
Only at temperatures above +300� C is a significant deviation noted in the
majority of devices in the values of the parameters froleaka enchannelslappear
g
It is supposed that with exposure to high temp~eliability tests ~f these cir-
close to the p-n junctions. Along with this,
cuits at a temperature of up to +300� C have demonstrated the high stability
of the major electrical parameters (Figure 10).
7'ABLE S. The following are numbered among the
defects which occur wi.th combined
Junction Operat- Mean Time Between exposure to high temperature and
ing Temperature, Failures, 24-hr electrical loads: the formation of
o~ Days transition metal compounds with
80 6,944 increased brittleness and high elec-
- 100 1,191 trical resistance, the formation of
120 243 electrical insulating layers at the
140 58.5 "aluminum--silicon" separation
boun3ary, corrosion of the aluminum
- in cracks and at oxide steps, etc.
Among IC failures which occur when they are tested for reliability under con-
ditions of normal and elevated
predominate. The bulk o
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f,2
1,0 - O6
B
0,6 _75 .?S 25 75 t,'C
a (a)
ICOUI, MA
JO .757
24 � 11
18
12
6 �
0
QI 0,4 0,6 QQ U~p~, 8
(c) Q
R,ON
ann - Ohms
i
.
`uoul,B voll;s
4
f
0,9
0,6
0,4 .rt
0,2 :YS�cc
�
0.1
U,2 44 O,ff 1 2 4 U1,7, 8
6 (b) volts
YlP NA
l,2
D,B
04
0
9
(d) ` volts `
y~~ RS.~OO~~K~� s~~.,
m:iNC'~.9'td
300 af�rcco~l~aaBVo
200 Rs�100IN/K/ol0om: tKC-~5�r0'~rPad'
~VL7 R9�500n/KEOdOOm: TKC~4~'l~
40
-BO -40 0 40a BO ~fe?Q 16040C 0 20 40 80 B80 f1n8 1?0 f40e~'e
Figure 8. The temperature dependence of the current gain of a
silicon transistor (a), the transfer function of a
typicalDTL circuit (b), the collector saturation voltage
(c), the input characteristic of a typical DTL circuit (d),
the resistance of a resistor (e), and the inverse current
of a silicon p-n Junction (f) is the theoretical curve.
Key: A. RS = 300 ohms/square unit; t mperature coefficient of
resistance = 2.8 � 10-3 deg-~.
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U , volts z Nc nsec
Ua6~x,~B out sod~ 93y.
_ 509'0
'r 7%
50~+ 4 0 ~
D,B 7,~~ .
0,7 p 100 300 t,�C 3'D 200 300 t,�C
Is,MO IP, ma
9J9'.
50% 9370
soy.
1,4 s,o 7~r
9%
U Z00 30U l,''C 51 0 200 duu c,~C
Figure 9. The major electrical parameters of a three-input
"NOR" logic gate as a function of the ambient
temperature.
/ewx ~ 0
1,60 -
1,55
ina~ ^,S
7
5
;SI-
I
~
SDO I0007,y
A
a soo 1DODIv soo /onoT. 4
Figure 10. The change in the main electrical parameters of
a three-input "NOR" logic gate during reliability
testing.
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c'
f
S,
500 10001 q
, I

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FOR OFFiC1AL USE ONLY
~
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Q2 L
0,! `~-~--7 ~ ~ `7 f
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n
04
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03
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~ L
Of

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!-_-j
U
n z50 son 7sn fnon ~snn sooo
f n, 0
0,1
U
e
Figure 11. Histograms for the change in the voltage of three-input
logic IC's during service life tests at +125� C(a) and
storage life tests at +150� C(b) and +300� C(c).
Gradual failures comprise only an insignificant portion, thereby attesting to
the high "inherent" (inherent in semiconductor IC's) reliability of these elec-
tronic products. The results of IC reliability tests at an ambient temperature
of +125� C in a volume of about 13 million circuit-hours are given in [22].
Only in 0.68 percent of the IG's did the amount of parameter drift exceed the
set norm. In the example cited in [4], the lack of any failures at all in IC's
is indicated which were tested in an amount of 3, 626 units in an "ring oscil-
- lator" circuit at En = 3 volts and an ambient temperature of +125� C for
11, 845 hr.
The typical distribution of the parameters and the change in them during the
testing process can be seen from Figure 11, in which the results of shelf-life
and service life tests of MECL three-input IC's are shown. The high stability
of the parameters is noted. At an ambient temperature of +300� C, the rate of
drift in the mal.n parameters did not exceed a value of 0.00001 [23].
As is well known, temperature cycles and shocks, humidity, a gas contaminated
environment, mechanical loads, radiation and other factors have an impact on
IC reliability during operation in addition to the factors considered here.
Devices manufactured with high quality easily sustain all of these loads within
the limits of Che norms specified in the technical specifications, testing
-25-
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programs and other standard setting engineering documentation. The IC failure
distribution during climatic and mechanical tests shown in Table 6 clearly illus-
trate the assertion concerning the capability of IC's of successfully standing
up to exposure to such loads [23]. As follows from Table 7, burned-in IC's
- stand up to more than 100 thermal sho cks. A cyclical change in the ambient
temperature has a negative influence on poorly mounted microcircuits, as well as
on microcircuits in which materials with substantially different thermal coeffi-
cients of expansion are used. For example, the use of an unsuccessfully selected
molding composition used to hermetic ally seal the IC's in plastic packages can
cause the welded contacts to break or short circuits in the wire ].eads at the
surface of the chip. The voTtages wh ich occur when the temperature changes and
which are due to the differing therma 1 coefficients of expansion of the materials,
is the reason for this. Thermal sho ck can accelerate the breaking of poorly made
connections, etc. [4, 18, 27, 32].
Studies of the resistance of IC's to sea fog and tropical climate have made it
possible to establish the fact that the packages of the devices limit the
operational possibilities for IC's.
The mechanical strength of integrated semiconductor circuits exceeds the tech-
nical capabilities of the test equipment in the overwhelming majority of cases.
The greatest number of IC failures during shock strength tests and tests for
resistance to linear acceleration ar e observed at loads which are either never
or extremely rarely encountered in operation. The most vulnerable section in
IC's are-the. internal leads which connect the chip to the external leads. They
usually break during centrifuging. However, this occurs at an acceleration many
times greater than the, level encount ered in equipment operational practice. For
this reason, by setting strict re.quirements on the level of the test load (up to
30,000 g), the requisite strength s afety margin can be assured.
The radiation immunity of IC's falls at the level of the radiation resistance of
silicon planar transistors and is 1 imited by the latter.
According to [27-30, 32], modern semiconductor IC's stand up to operational
loads in the following ranges: line ar acceleration of from 50 to 50,000 g for
standard products and up to 100,000 g for samples fabricated in accordance
with special programs; in a tempera ture range of from -196 up to +200� C in
the case of thermal shock; up to 280� C for soldering and up to 1,100� C in an
inflammability test; from -185 to +300� C in a thermal cycling test; in terms
of moisture immunity and moisture resistance at about 100 percent humidity, in
a temperature range of 2 to 96� C; in terms of resistance and immunity to a
salt fog, at 71� C and 20 in a s alt solution, up to 10,000 g shock accelera-
tion for a shock pulse width of f rom 0.2 msec to 6 msec; in terms of vibrational
strength and vibration immunity at accelerations of from 5 to 2,000 Hz, and a
displacement amplitude of no more tYian 2.5 cm and a vibrational acceleration of
up to 100 g.
We will note in conclusion that the predominance of IC catastrophic failures,
among which the greatest specific weight belongs to failures due to poor quality
connections, makes it possible to s uppose there is a real possibility of a
-26-
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TABLE 6. Failure Distribution as a Function of the Kind and Magnitude of
Test Load
Kind of Load
Thermal shock
Thermal cycling
Tropical humidity
Mechanical shock
Vibration:
At one frequency
In a range of frequencies
Constant acceleration
Maximum Number
Test Conditions of Failures,
0--100�C; 5 to 270 shocks 0.71
-60 + 175�C; 5 to 160 cycles 0.30
-10 + 60�C; 90 to 98
1,200 hr
Period from 0--500 hr 0
Period from 500--1,200 hr 1.40
3,000--10,000 g; 5 to 125 1.40
shocks
60 Hz, 20--50 g; 96 hr 0
5 to 500 Hz; 20--50 g; 1 hr 0.4
150--50,000 g;
iricluding 150--20,000 g 0
above 20,000 g 1.3
TABLE 7. The Results
of IC Tests for Exposure to Thermal Shocks
flpenen w H3xexeNxR TemnepaTypa e pamKax oAxoro repMOyaapa
Number oi
OT O AO 1QO� G
OT -GS AO + I75P C
OT, -ROO AO '}'ZOUr C
Ko.1u4ecreo
~'3apoe
cks
Sh
=760PK...
ucno
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TK8
30H,
ea6opxa,
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0
100
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0
12
0
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0
- 500
33
2
1000
24
3
1500
14
I 5
Note: Exposure time is 30 minutes.
Key: l. Range of temperature change within 1 thermal shock;
2. Sample, number of units;
3. Number of failures, units.
further in^rease in IC reliability in the immediate future. As was noted above,
working out individual production process operations, refining the package pro-
tection, automating production processes, improving the metrological production
support and refining the quality control system for the output product as a
whole wiil assure the elimination of substantial sources of failures and the
attaining of the reliability inherent in solid stats components.
-27-
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TABLE 8.
JPoerub naacMtuocnI r t1
- IQ-s 5.10-5 I 10-e I IU-t I 5.10-8
I
BNAN XCt1MT8HNA MBKCNMAJIHYt 3i7QiTN ,IIa OAH)' lINKPOC7(!M)'.
(2) AOlIA.
Kinds of Test_s
p I 3 I 5 I 10 ~ 100
3neKrpxqeacAe
(~Ymcuecaa~xde)
(3)
:TTepK04XKAHP0-
~4)
n
s1.leN'rp14Yr+P0-
saaae (5)
i
Ilpoeepxa rep-
weTxveoCTx ( 6 )
3nacTparepmo-
rpeHxpoeXa (7)
CneuWaaaxue
NCR6iT8FtA! (8)
PCNTI'CHOAet0eK'
TocxonaA (9)

Kea.lx#:aueoe-
HHC NCOdT88AA
NCOdTBHHC H8
JiOdifO9C9HOCTb
I(JI N M BTNVCMC
NCt1dT8HHA (a non�
uom o6beme) (12)
flposepxa npov-
[Iocrii ceapHUx cce-
Annexlf~~ (13)
Key: 1. Reliability level (aav ~
3. Electrical (functiona
6. Checking the hermetic se,
8. Special tests; 9.. X-ray
11. Operating life testing:
13. Cliecking the strength of
r-l); 2. Maximum expenditures per IC, dollars;
4. Thermal Cycling; S. Centrifuging
31; 7. Electrical & thermal conditioning;
flaw detection; 10. Qualification tests;
12. Climatic tests (in the full volume);
the welded connections.
-28-
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A consequenc of the substantial improvement in IC quality is a perceptible
decrease in the number of complaints of substandard products, a reduction in
the volume of periodic tests and tests of the nonfailure operating time as well
- as increased consumer confidence in the product manufacturer.
Reliability studies of domestic semiconductor IC's which have been conducted in
recent years attest to the fact that the reliability which has been achieved
comes up to the world state of the art and further efforts in this field should
be made circumspectly, carefully weighing the economic expediency. The imple-
mentation of those measures to improve IC reliability and quality should be
avoided which can be classified as superfluous and related to excess expenditures
on quality control.
Quality improvement programs should be worked out on the basis of several relia-
� bility levels for the output product. Naturally, each of the levels should have
- its own corresponding cost expression. General and special technical specifi-
cations on IC's should provide for the possibility of the coordinated delivery
of products to a consumer having permissible deviations from the specified
requirements. Generalized data which illustrate these kinds of programs, which
are widely used in the U.S. and other developed capitalist nations, are shown
in Table 8.
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Chapter III. The Main Kinds, Reasons for and Mechanisms of Semiconductor
Integrated Circuit Failures
An analysis of the reasons for the failure of IC's during operation and testing
makes it possible to establish the fact that at the present stage of micro-
electronics development, a characteristic feature is the predomipance of failures,
as a rule, due to the destruction of some of the structural components as a con-
sequence of the imperfection of individual production process operations in IC
fabrication and various violations of the standard setting engineering documen-
tation in their application stage. This is clearly seen from Table 9, in which
the generalized distributions according to kinds and causes of IC failures are
presented [27, 28, 31-38]. Improving the structural design and fabrication
technology of IC's will lead to a substantial increase in their reliability,
- which is evidenced by Figure 5, in which the averaged curve for the reduction in
- the failure rate of semiconductor integrated circuits over the period from 1961
through 1972 is shown based on generalized data (from various foreign sources)
[27, 32, 33, 30, 39, 40]. The curve for the reduction in the failure rate after
1968 becomes flatter. This is explained, first of all, by the fast process of
refinements in the structural design and working out the technology for bipolar
IC's in the initial period of the introduction of this technology, and secondly,
by the increase in the complexity of the technology and the rise in the level
of integration, characteristic of the later developmental period of microelectro-
nics [27].
A major source of total failures of IC's, as can be seen from Table 9, is the
destruction of the electrical circuit. Reasons for breaks in the electrical
circuits of IC's are inadequate strength of the welded connections, the occur-
rence of undesirable transition metal compounds in the contacts of materials of
different kinds, as well as mechanical, electrical and chemical destruction of
thin film metal conductors and assembly defects in the IC's.
The main causes of short circuits in the electrical circuits of IC's are defects
in the photolithography and dielectric films, the occurrence of channels with
the opposite type of conductivity, body defects in the crystal lattice of the
semiconductor material as well as defects in the assembly of the IC's.
Gradual failures manifest primarily as an increase in the leakage currents and
are caused by such factors as the appearance of channels with the opposite type
of conductivity due to the migration of the mobile charge in the oxide film and
the contamination of the surface of the semiconductor chip and the IC package.
Where such defects are present, as well as in the case of a failure to seal by
the package with the exposure to the ambient atmosphere, individual electrical
parameters of an IC can gradually change their values ("drift"), something which
in turn can lead to equipment failure.
We shall treat the physical and chemical processes which lead to IC failures.
Microcircuit failures encountered in practice are shown schematically in Figure
12; they can be conventionally broken down into three categories:
--Failures related to phenomena in the body of the semiconductor chip;
-30-
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- 31 -
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--Failures which depend on the state of contact connections;
--Failures due to phenomena at the surface of a chip.
1. Failures Related to Phenomena in the Body of a'Semiconductor Chip
The appearance of failures related to body defects is explained either by the
redistribution of the doping impurities in the body of the crystal chip or by
structural defects in the semiconductor cryatal (dislocations, etacking faulta,
microcracks, etc.), which occur or develop during the process of operating a
defective IC.
The redistribution of impurities is theoretically poasible because of the con-
tinuously ongoing thermal diffusion of doping impurities used to create the IC
structure in a monocrystalline sample of a aemiconductor material. However,
there is little probability that this process plays a subatantial role in prac-
tice, since the diffusion coefficients of the doping materials (boron, phosphorus,
- arsenic, antimony, etc.) in a silicon monocrystal are insignificantly small in
that temperature range where IC's are used (from -60 to +125� C).
The most probable cause of failures related to ptienomena in the body of a chip
are defects in the semiconductor material. Dislocations and other defects of the
crystalline structure, as well as cracks, deformations and mechanical stresses in
a silicon crystal, developing during operation of the IC when expoaed to thermal
and mechanical loads, can have a substantial impact on changing the electrical
characteristics of integrated circuits, leading primarily to gradual failures.
With an increase in the level of integration, which is characteristic of the
state of the art in microelectroaics, a trend is observed towarda an increase in
the "stacking density", a reduction in the geometric dimeneions of active and
passive IC components and a reduction in the doping depth of the p-n Junctions
related to this, as well as in increase in the level of doping of the diffusion
regions of the semiconductor crystal and the electric field intensity in the
IC elements.
- Because of this, the degree of influence of local defecta of the semiconductor
structure on IC reliability increases. The major mechanisms for the degradation
of the properties of epitaxial and diffusion layers of IC's with "small" p-n
junctions are the motion of dislocations, a change in the internal stresses of
the crystal lattice, recrystallization and breakdown of solid solutions, etc.
[41-43]. The indicated processes lead to a change in such important character-
istics as the concentration, mobility and lifetime of the current carriers in
the semiconductor, and as a rule, to an increase in the leakage currents, a
reduction in the breakdown voltage values for the junctions and a degradation,of
= IC speed. We shall now move on to a consideration of failures related to contact joints.
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2. Failures which Depend on the State of Contact Bonds
Two types of contact connections are usually employed to connect an IC chip to
eXt2Yria1 power supplies, as well as to provide for electrical connections between
the circuit components. The first type is a connection of the thin film metal
contact areas on the silicon chip to external leads which pass through the wall
of the package (traverses). Such connections are made using gold or aluminum
_ conductors, which are welded to contact areas of the chip and the package trav-
erses. The second type of connection is thin film metal conductors, which play
the part o� the intracir.cuit wiring between the individual components on the IC chip. _ When producing the contact connections in IC's, a considerable amount of different
kinds of materials is used (gold, aluminum, silicon, cermet and silicide connect-
ions, sub layers of molybdenum, vanadium, platinum, titanium and other difficultly
fusible metals, etc.), the interaction between which promotes the formation of
transition metals, frequently with undesirable properties.
Failures related to contact connections, as a rule, take the form of an increase
in the contact resistances or breaks in the electrical circuits due to two
mechanisms:
--The clustering of vacancies in different regions of the wiring layout intexrial
to the circuit; --The formation of regions with electrical insulating properties, which occur at
the separation boundaries of the various materials used in the construction
- of the IC's [31, 44-46]. (1
Clgure 13.. Regions oE'possible cavity formation in an IC with
- one level of inetallization.
Key: 1. The metal to metal welded contact at the package feed-
, through;
2. Flexibie (wire, lug) lead; 3. Welded metal to metal contact at the chip;
4. Contact between the deposited resistor and a thin film
metal conductor;
5. Thin film resistor;
6. Tliin film metal conductor;
7. Metal to semiconductor ohmic contact; .
8. Contact between the chip and the chip holder of the
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package (fused, giued) ;
~ 9. Si chip;
10. Chip holder (package).
A cross-section through the components of the internal wiring layout of IC's is
shown schematically in Figure 13, where this layout is based on single level
metallization and regions are indicated in which cavity formation and breaks
are usually observed because of the clustering of vacancies (regions 1, 3, 4, 6,
7 and 8).
Welded Contacts. One of the most well studied regions of the intracircuit wiring
of IC's in this regard is, apparertly, the region of the welded metal to metal
contact, in particular, the gold to aluminum connection.
~
s 1
a
a (a)
9 (a)
e (b)
Figure 14. Cross-section through a Au--Al connection after 5 to 10
minutes exposure to a temperature of about 300� C(a)
and after 10 to 1,000 hours of high temperature storage
at a temperature of 200 to 300� C(b). Mechan ical stresses
in the welded joint which lead to contact breaking are
shown schematically in the figure (c).
Key: 1. Au;
2. A1;
3. Si02;
4. Si;
5. Au2A1;
6. AuA12;
7. Au4A1;
8. Au5A12;
9. Cracks;
10, Cavities.
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- The composition of transition metal compounds (phases) in gold to aluminum contacts
is complicated and changes, depending on the conditions under which the composition
= is produced (the concentrations of gold and aluminum, the presence of free sili-
con, the temperature and pressure during the welding process, the ambient temper-
_ ature and the operational time of the finished IC) as well as many other factors.
- The formation of transition metal compounds and the change in their composition
during operation lead to cavity formation because of the accumulation of vacancies
due to the Kirkendall effect, the occurrence of inechanical stresses at the surface
of the gold--aluminum separation boundary, and in the final analysis, to breaks
in the welded connections.
The mechanism for the failure of welded contacts produced by thermal compression
is usually as follows [47-52]. During the process of thermal compression welding,
which is accomplished at a substrate temperature of 300� C, the mutual diffusion
of the gold and aluminum takes place, which leads to the formation of transition
metal phases of the Au2A1 type at the gold--aluminum separation boundary (close
to the gold wire) and AuA12 type (close to the aluminum contact area on the
oxidized sLrface of the chip). In this case, because of local heating in the
contact region, the temperature rises up to the minimal melting temperature of
the gold--aluminum system, and the fusion occurs only in a small amount at the
separation boundary of these metals.
During the fabrication of the remaining thermal compression contacts for the
same IC, the substrate is at a temperature of about 300� C, which leads to rapid
thermal diffusion of the gold and the formation of transition metal phases of
the Au4A1 and Au5A12 types in the region of gold--aluminum bonding (Figure 14a).
Immediately following the welding, the contact connections usually have good
mechanical and electrical properties. However, in the process of subsequent
operation or when the IC is stored at an elevated temperature, irreversible
phenomena occur which cause the electrical resistance to increase and the thermal
compression contacts of the IC's to break. The concentration gradient of the
metals and the difference in the diffusion coefficients of the individual com-
ponents in this metallurgical system are those conditions under which a mass
transport effect is Qbserved (the Kirkendall effect) in accordance with the
equation: .
X =1`0,51 � exp 236M) f(1)
~ RT
where X is the displacement of the separation boundary between the transition
metal phases relative to its initial position, cm;
R is the universal gas consfant;
T is the absolute temperature, �K;
t is the exposure time to the given temperature, �C.
It follows from this that failures related to the formation of transition metal
phases in gold--aluminum contacts of IC's should be manifest extremely rarely
under normal operating conditions. This conclusion is confirmed by extensive
experimental data obtained during IC testing and operation. Nonetheless, since
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the gold diffusion rate greatly exceeds the aluminum diffusion rate in the model
described here for thermal compression contact degradation, with longterm opera-
tion of a finished IC at the maximum permissible temperatures according to the
technical specifications, uncompensated diffusion of the gold into the aluminum
track is altogether possible, in which case, the AuA12 transition metal phase
with a red shading (the "purple plague") is formed at the peripheral areas of the
gold--alumir.um contact. In this case, cavities and cracks remain in the region
of the weld which reduce the mechanical strength of the contacts (Figure 14b).
The indicated process of gold diffusion into aluminum can be supplementally
accelerated by the electromigration of the gold when DC or AC flows through the
contact. Electromigration processes in integrated circuits will be treated
below. The formation of transition metal phases and the changing of their composition
_ during operation of integrated circuits also leads to the occurrence of consider-
able mechanical stresses at the surf ace of the gold--aluminum separation boundary,
because of the variation in the body and the mismatching of the crystalline lattice
of the various transition metal compounds. The stresses occurring in this case
, can be amplified by the presence of additional mechanical stresses at the peri-
phery of the thermal compression contact, as well as by the difference in the
temgerature coefficients of expansion of the individual transiCion metal phases
" (Figure 14c). All of, tilese factors, in conjunction with the increased brittleness
of many transition metal phases, can lead to breaks of the gold conductors away
- from the aluminum areas.
The proposed mechanism is confirmed in many respects by experimental results and
has made it possible to provide a reasonable explanation for the given phenomenon.
- However, the latest studies [44, 53-55] have necessitated corrections in this
mechanism, since the newly obtained results could not, at first glance, be
explained by the Kirkendall effect.
It was foLnd, in the first pTace, that the clusters of vacancies which lead to
the appearance of cavities, occur under definite conditions in aluIIiinum, and
this is evidence that aluminum is a faster diffusant. Secondly, it was established
that the process of aluminum diffusion into the weld regian is substantially
accelerated in the absence of oxygen in the internal atmosphere of the IC package.
However, it was successfully determined as a result of additional experiments
[44] tl-iat the observed phenamenon is also explained by the Kirkendall effect if
one takes into account the fart that the transition metal compounds formed in the
region of the weld act as a barrier for the mutual diffusion of the gold directly
into the aluminum, while they also serve as an effective drain for both the gold
and the aluminum. It is specifically for this reason that cavities (breaks) can
be formed both in the gold and in the aluminum in welded Au-Al connectiois.
The influence of the gas environment in the IC package on the process of mutual
diffusion in "gold�--aluminum" contacts [54] is explained in the following mannFr.
When oxygen and water vapors are absent (the hermetic sealing is carried out in
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a dried nitrogen atmosphere) with subsequent high temperature storage, the pre-
dominant mechanism is the diffusion of the aluminum into the region of weld. In
this case, the diffusion takes place primarily along the surface of the aluminum
film and along the grain b oundaries. In the case where oxygen is present inside
the package in a minimal amount, but nonetheless sufficient (no less than 0.1%)
(or water vapor also), when the IC is heated, oxidation of the aluminum surface
occurs, and the rate of its diffusion is substantially retarded, since under these
conditions, the predominant mechanism is bulk diffusion.
Aluminum wire is used in p lace of gold to completely eliminate failures related to
the formation of transition metal compounds at Au--Al contacts on a chip. However,
_ conditions appear in this case for the phase transformation of AuXAly on the gold
: traverse.
An additional factor which has a negative impact on the mechanical strength of
welded connections is mechanical damage anci undercutting etching of the contact
areas during photoiithography, during the checking of the functioning of the IC's
on the plates, and the welding, which lead to a reduction in the contact surface
area and should be rejected in a timely manner during IC fabrication.
For integrated circuits, especially the early designs which were hermetically
sealed in plastic packages, the specific kinds of failures related to the welded
connectious are intermittent breaks and short circuits of the wire leads at the
edge of the IC chip [27, 30, 56, 57]. The intermittent nature of the failures is
explained by displacements of the wire leads relative to the chip due to mechanical
stresses occurring in the IC structure when subjected to temperature exposures
because of the difference in the temperature coefficients of expansion of the
materials P-mployed.
Many other kinds of contact connections are also used in IC's besides welded ones.
Vacuum Deposited Resistors. The most vulnerable component of integrated circuits
fabricated using a combined technology is the thin film deposited resistor.
- Compositions whlch take the form of a mixture of two or more metal and ceramic
- components, for example, a mixture chromium and silicon monoxide, Cr-SiO, or the
- silicides CrSi2, MoS12, etc., as was noted above, are usually employed as the
material for a resistive film. The electrical connection of deposited resistors
to other IC components is made by means of inetallic thin film conductors (A1),
where aluminum, as a rule, is deposited on a layer of a chemically neutral metal,
which separates the metal and resistive films. This is done for the purpose of
preventing a possible chemical reaction between the individual Components of the
resulting system. In the case of damage or too small a thickness of the separat-
ing f ilm, a reaction between the aluminum and the material of the deposited
resistor can lead to the formation of a transition metal compound, Yaving dielec-
tric properties, and as a result, can be responsible for a break in the electric-
al circuit in the region of the metal to CP,;.:L~Ot contact [871.
Electrolytic corrosion is of the greatest danger to integrated circuits with
deposited resistors, the chips of which do n.ot have additional protection with
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dielectric films, to prevent the intrusion of moisture and ionic contaminants to
the surface of the resistors [64, 31].
The Corrosion of a resistive film takes place in several stages in accordance with
the following scheme: the electrolyte initially interacts with the metallization
at the.positive contact (the anode), and then the products of this reaction inter-
act with the cermet, leading to the formation of an electrically inaulating film
at the point of contact:
6A1-}- 6H2O 6A( (OH)s 3H9
6A1(OH)s = 6H3A103 ~ 6H+ 6Al02- -}-CH,O; (2)
2Cr 6Al02--}- 6H+ 2Cr (A10s)s + 3H2 T.
In properly designed integrated circuits (the chips protected with a S102 film,
hermetically sealed packages), the occurrence of failures because of this factor
is practically eliminated.
Thin film metal conductors ("tracks") which provide for electrical contacts
between the individual active and passive components of IC's through contact
openings in the oxide film and which are produced in the corresponding regions
of the chig by means of photolithography, are usually employed as the intercom-
ponent wiring for integrated circuits. To obtain the indicated contact connect-
ions, as a rule, the method of aluminum deposition on the surface of an oxidized
silicon substrate is employed with subsequent photolithographic generation of
the "pattern" of intracircuit wiring and the melting of the aluminum to increase
its adhesion (bonding) to the substrate material and improve the characteristics
of the ohmic contacts to the silicon.
We shall deal with the kinds and mechanisms of failures of the ohmic metal to
semiconductor contacts. .
Metal to Semiconductor Ohmic Bonds. The metal to semiconductor ohmic contacts
used for making electrical connections to the active and passive components of
a semiconductor structure on a chip are one of the important components of con-
tact connections of IC's which have an impact on their reliability. Requirements
are placed on them as regards the ohmic nature of the contact and low electrical
resistance, as well as the stability of the properties and the absence of pro-
cecses which lead to the degradation of the properties lying below the diffusion
regions and the p-n junctions [48, 53, 58-61].
The latter is especially important from the viewpoint of assuring reliability
of structures with small junctions and with "full" emitters.
- Some three failure mechanisms are basically characteristic of the ohmic contacts
of integrated circuits [48, 53, 58, 60, 611:
--The formation of short circuits in the region of etching holes or the appearance
of "nodules", which lead to pinholes in the protective dielectric film above
the contact windows to the silicon, because of electromigration processes in
the IC conductors (the danger of failures because of this mechanism rises sub-
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stantially for IC's with small p-n junctions and multilevel metallization); the
_ formation of films with electrical insulating properties at the metal--semicon-
ductor separation boundary, which lead to an increase in the contact resistances
or complete electrical breaks in the ohmic contacts; �
--Thermal diffusion of the aluminum into the silicon and short circuits at elevazed
ambient temperatures and with local overheating of the diffusion regions on the
- chips.
Failures of ohmic contacts related to electromigration effects will be treated in
more detail in the next section. We shall deal with failures due to the formation
of electrical insulating films and the thermal diffusion of.aluminum into silicon,
which are observed during operation or storage of integrated circuits at an ele-
vated temperature.
The probability of breaks is increased where photolithography defects are present
(insufficient opening of the windows) and in the case of an inadequate tempera-
ture when fusing in the ohmic contacts [48]. It should be noted that an excessive-
ly high fusing temperature can also lead to a break in the aluminum film at the
oxide steps at the boundaries of contact windows.
In structures with a"full" emitter, which have found widespread application in
integrated circuits with an increased level of integration [VLSI], the interaction
reaction of aluminum with silicon dioxide represents a particular danger, which
takes place rapidly at temperatures above 500� C[48, 53]:
4A1 + 3Si02 2A1203 + 3Si
(3)
In this case, the S102 is reduced to silicon, and the aluminum at the boundaries
of the contact window for the "full" emitter approaches an impermissibly close
distance, x, to the emitter junction (Figure 15), which can lead to ajunction
short circuit.
3 Q (A)OnocNra yvocmxu cmOyKm 061 4
~ 4
Q (a) 0
Z i
P ~ p ~1

6(b) q p before fusing in
- 5 Oa On~OeeNUn
t axne Oar010e,v16
, X after fusing in
c (d)
Figure 15. Schematic cross-section through a"full" emitter at
varioua stages in producing'the IC structure.
Key: A. Dangerous regions of the structure.
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To prevent this undesirable phenomenon in integrated circuits with "full" emitters,
multilayer films with sublayers of difficultly fusible metals (for example, Mo-Au,
Mo-Al, Ti-Pt-Au, etc.) are used instead of "pure" aluminum when producing the thin
film wiring layout.
Thin Film Tnterconnection Wiring. The increase in the level of integration of
integrated circuits, and as a consequence, the packaging density of the components
on a semiconductor chip, the increase in the speed and maximum frequency of inte-
grated circuits, as well as the density of the currents flowing in thin film con-
ductors have brought about an-increase in the role of the intracircuit wiring
layout and its contribution to IC reliability [31, 48, 58, 59, 62, 63].
Aluminum is used as the basic material for thin film conductors in'integrated cir-
cuits. From a reliability standpoint, the major drawbacks of aluminum as a
material for conductors are its following properties [48, 59]:
--The ability of aluminum to form large transition metal compounds in contact with
gold;
--The ability of aluminum to corrode in electrolytes because of its own electro-
negativity [64-67];
--The possibility of the corrosion of aluminum in contact with other metals
because of the galvanic effect [57, 68, 66, 69];
--The softness of aluminum and consequently, the ease of damaging an aluminum
film;
--The possibility of the appearance of cavities and projections on an aluminum
film because of electromigration at current densities somewhat less than for
other metals [31, 34, 44-46, 58, 59, 70];
--The possibility of liberating silicon dissolved in aluminum during the proceas
of fusing in the contacts at the boundaries of aluminum grains [44,46, 59];
--The rather intense reactian of aluminum with S102 with the reduction of the .
silicon at temperatures on the order of 500� C[44, 53, 59].
Despite the indicated drawbacks, aluminum has a whole series of substantial advan-
tages over other metals, which make it practically the only naterial suitable for
producing single layer metallization of IC's, and for this zeason, is widely used
in modern microcircuit engineering [48, 58, 59].
One of the reasons for the failures of thin fi]m conductors is the inadequate
corrosion immunity of aluminum. The intrusion of moisture inside a package prior
to its hermetic sealing or as a consequence of an inadequate hermetic seal of
the package during the testing (or operating) p�:ocess of an IC can lead to the
destruction of the metallization. Only a thin film of A1203 (2 to 10 nm) on the
aluminum surface serves to protect it against the chemical reaction o� aluminum
with water. However, a rather small amount of chlorine, ammonia or copper ions
or those of certain other elements suffice for the passivating film of aluminum
oxide to be reduced azd the direct interaction of aluminum and water to begin,
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in which aluminum hydroxide is formed [65]:
- 2A1 + 6H20 2A1(OH)3 -I- 3H: j. (4)
Aluminum hydroxide does not protect aluminum against exposure to harmful reagents
and possesses electrical insulating properties. As a result, breakage of the
electrical circuits of the IC's occurs.
Other aluminum reactions are also known in which the substances indicated above
- play the part of catalysts [67], for example, the following cyclical reaction:
6HCl + 2A1 2A1C1, 3H: t
A1C13 3H=O Al (OH)3 3HC1 } (5)
2A1(OH)9MplNNyAI=08 3H,0, ~
ageing
- which leads to the oxidation of the aluminum. The process of aluminum corrosion
is accelerated substantially by electrochemical reactions:
--Where a voltaic couple of inetals is present (for example, in the region of the
gold--aluminum welded contact, a voltaic couple with a 3 V e.m.f. appears);
- --When an external electrical bias is applied to the IC [28, 57, 64, 66, 681.
Anode dissolution of the aluminum at the "positiv.e" contact is observed in these
cases.
The processes of electrolytic corrosion of thin film conductors represent yet
another danger, since disintegration products are formed during corrosion and
electrical transfer of inetal ions (for example, gold, silver) to the cathode is
observed, which can lead to the appearance of shunting leaks and even to short
circuits because of the formation of current conducting "bridges" between adjacent
tracks (57, 65, 69]. The failure mechanisms described schematically above, relat-
= ed to the corrosion of the material of thin film conductors, are shown in Figure
16. Dielectrics (Si02, A1203 glass, etc.) are used to attenuate the effect of
the indicated processes in integrated circuits. However, since windows should
, be formed ir: this insulating layer in the contact areas underneath the welded
_ contacts, there exists the problem of circuit breakage because of inetallization
corrosion in the indicated regions.
Protecting the entire assembly with glass after laying out the leads unfortun-
ately also cannot completely solve the corrosion problem, because mechanical
stresses and cracks, which are formed in the glass during the process of assembly
and hermetic sealing and with subsequent temperature loads on the IC, lead to
local exposed places on the wire (lug, tab) conductors [57, 65, 66].
Electromigration (electrodiffusion) processes represent a definite danger for thin
film conductors in IC`s: mass transport as a result of the flow of an increased
density dire.ct current through a conductor [27, 31, 34, 45, 46, 59, 60, 70, 71].
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� B
(uaonaqv~i~ np Oy (A) KmoNU 06natme oMOONOtoC , (C)
Q Koop~uu) O Q pocmOopeNU~ ymevirp � ~ O. .
Z Nemonna 1909 Ka j
2
i
. ! 3
4 � 4
S P 5 P u (a) (b) 6 .
- Figure 16. Schematic illustrating the mechanism of the
occurrence of an electrical break (a) and a
shunting leak (b) in IC circuite as a conse-
quence of corrosion of'the material of thin
film semiconductors.
Key: 1. A1;
- 2. Au;
3. Mo; '
4. Si02;
5. Si;
A. Break (insulation by corrosion products);
B. Region of anode dissolution of the metal;
C. Leak (or ahort circuit). .
Electromigration in thin film aluminum conductors can lead to two different kinds
~ of failures:
--The violation of the electrical integrity of aluminum conductors as a result of
the formation, directional motion aud clustering of vacancies, which leads to-
- the formation of cavities comm.ensurate with width of the thin film conductor
(circuit breaks);
--The formation of "nodules" and "whiskers" because of a local accumulation of
aluminum which is manifest in the form of short circuita between the thin fiTm
conductors of single and multiple level metalization and in the appearance of
pinholes in the protective S102 and glasa films, which can aubsequently serve
as a cause of corrosion.
The electrical.force acting on metal ions when an electrical current flows is
composed of two components:--The force of the interaction of an ionized metal atom with the electrical field
(it is proportional to the electrical field inrensity and the valence of the
metal, and is directed towards the negative-electrode) and the force of the
- "electron wind", which is governed by the impulse exchange between the charge
carriers and the metal atoms (it is proportional to the specific resistance of
the film and the current density, and is directed towards the positive electrode).
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T D
rt
. Dz 141_ MI MJ
Tt D~ - - - -
~ D~ � ~ 1
Au I
T ~ I Tt I' Tt 0 p~ ~ I A~ Si
- reF.;':~.~:�: � 1-;lI Si0
~ �E: : ' ~ ~ ropKU +
~ 1 ycmomr~~ 4�;:: : ~~T ~ ~ p +
ena,NEdrawp' .Towa,xoKannoMUa� ' (b) a
(a) a (5)
(6) NJMlNCNUI HmeNeNUt (7)
~ p931"pod septH opueNmoquu nneNKU
Figure 17. Schematic illustrating the mechanism for the occurrence
of IC structural component failures because of electro=
migration.
Key: 1. Cavities;
2. Depletion zone;
3. Whi$kers;
4. Nodules;
5. Accumulation zone;
6. Change in grain size;
7. Change in film orientation.
The second component prevails in metals because of the shielding effect of the
electrons, and as a result, the drift of inetal ions is observed from the cathode
to the anode.
In the absence of a temperature gradient, electromigration is not able in and of
itself to bring about the failure of a conductor made of a pure homogeneous mater-
ial, leading only to the continuous compensated motion of the metal in the direc-
tion of electron travel (towards the anode). In order for a break to accur in a
conductor as a result of the electrical current f3owing throt~gh it, the continuity
of the flow of atoms over its length must be disrupted. This can occur where
various gradients are present:
--Temperature gradients (Figure 17a);
--Gradients in the material composition (contacts of thin
silicon and aluminum wire, which have smaller diffueion
aluminum film) (Figure 17b);
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film conductors to gold,
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--Film structure gradients: a change in the size and orientation of the grains
(Figure 17c).
Electromigration in thin film conductors is usually estimated quantitatively in
terms of the failure free operating time. The value of the mean time before fgilUrej
tu, of a thin film metal conductor is related to the transport speed for the
material, R, and the cross-sectional area of the conductor, S, by the expression:
t� ~ � R . (6)
It is apparent that such defects in conductors as mechanical damage, undercutting of
the film and local thin places lead to a reduction in the cross-sectional area of
thin film conductors because of the unsatisfactory coverage of the steps with oxide
and a reduction in their reliability b2cause of the rapid development of the cavi-
ties which are formed prior to the stage of complete breakage.
The electromigration rate is described by the following expression [34, 46, 59, 60,
71, 72]:
R - A - Jn- eXp[r`k + LI1' (7)
where A and a are coefficients which depend on the structure of the metallic
film (grain size, the presence of additional protective films, the density of
structural defects, etc.), (A/cm2)-n � hr-1 and centimeters;
J is the electrical current density through the conductor, A/cm2;
n is the exponent which depends on the electromigration mechanism;
4~ is the activation energy for the electromigration process, which depend sub-
stantially on the composition of the film material, grain size and structural
perfection of the metal films, as well as on the presence of protective dielectric
films on their surface, electron-volts;
L is the length of the thin film conductor, centimeters;
k is Boltzmann's constant (k = 8.62 � 10-5 eV/�K);
I T is the absolute temperature, in �K.
,
I~ The exponential dependence of the electromigration rate on conductor length, L,
was derived in [72J assuming a random nature for the localization and a constant
distribution density of structural defects over the length of the thin film ccn-
ductor.
It should be noted that different researchers obtain considerably different
quantitative values for the "parameters" (A, n, (D) in equation (7). These differ-
ences, as was noted above, are apparently explained by the substantial differences
in the aluminum films themselves (grain size, crystallographic orientation of the
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= film, the presence of impurities in the material of the thin film (copper, silicon,
aluminum oxide, etc.), unavoidable changes in the conditions on the substrate, the
difference in the materials and methods of applying the dielectric coatings, the
range of temperature and currents with which the experiments were performed and an
entire series of other factors. Thus, for example, with an increase in the temper-
ature of the conductor, the value of the exponent n varies from 1 to 3[45] and
more (especially in the case of the combined action of various gradients in the same
conductor).
For the reasons noted previously, fundamental divergences are also observed in the
treatment of the experimental results [45, 62]. Thus, the majority of researchers
[46, 71-73] feels that the grain size and the coating of the films with glass has
an influence on the activation energy 4~ because of the change in the predominant
diffusion mechanism:
--0.48 eV because of the combined action of diffusion via grain boundaries and
surface diffusion in fine grained thin films;
--0.84 eV because of surface diffusion in ]arge grained films;
--1.2 eV in large grained thick films, covered with glass, because of the dominant
mechanism of bulk diffusion (with a reduction in the zole of surface diffusion
af the film material).
Jther researchers assert that the grain size has no influence at.all on the level of
the activation energy [87] or feel that the increase in the activation energy
observed in this case is a consequence only of a more ordered orientation of large
grained films [45, 73].
- Al1 of this is evidence of the inadequate extent to which the process of electro-
migration has been studied and the necessity of determining the quantity A, n
and ~ in equation (7) for specific conditions of the formation of thin film con-
ductors and the application of dielectric films whinc coat metal tracks.
Despite such substantial disparaties in the quantitative characteristics of the pro-
cesses, the understanding of the basic laws governing the mechanism of electro-
migration occurring in thin film conductors is useful both in the development of
more reliable IC's and for the accelerated evaluation of their reliability
(especially the durability indicators).
Short circuits of the p-n junctions due to the formation of etching holes in the
silicon in the region of the contact windows represent yet another variant of
failures related to electromigration in the thin film wiring layout for IC's
[46, 60, 61]. This phenomenon is explained by the transport of silicon in the
direction of electron travel through a thin film conductor (in the region of posi-
tively biased ohmic contacts) and the subsequent filling of the etching holes,
which propagate at the depth of the p-n junction, with a layer of inetal.
The electromigration process represents a special danger in very large scale inte-
grated circuits [63, 711, since the substantial reduction in the width of thin
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film conductors, the presence of a large number of relief steps at intersections,
the rise in the current density at critical points and the occurrence of local
overheating because of the increased levels of power dissipation - all of this
leads to the fact that the electromigration process which occurs in the thin film
conductors of LSI circuits can become the major mechanism for failures which
governs the durability of the IC's.
Numerous studies of the electromigration mechanism in IC thin film conductors make
it possible to determine ways of minimizing this process both in the design stages
and in the process of fabricating the IC's [27, 31, 32, 45, 58, 59, 71]. These
include primarily:
--Limiting the maximum permissible current density through an aluminium conductor
to a value of 2- 105 A/cm2;
--Optimizing the conditions for applying and fusing-in the aluminum for the
purpose of assuring a large grained structure for the thin film conductors;
--Optimizing the geometric dimensions and configuration of thin film conductors
(if there are no other limitations, it is more expedient to increase the width
of the conductors rather than the thickness in increasing the cross-sectional,
area, since this does not degrade the quality of the application of insulating
and passivating Si02 films in a multilevel layout or the structure of the metal
film itself; long conductors are to be avoided, as well as sharp changes in the
width of conductors, etc.); --The selection of difficultly fusible metals with a loi,r electromigration rate for
' the thin film conductors (for example, gold, molybd:.num, etc.);
--Alloying the aluminum with copper, magnesium, rhromium and other metals which re-
duce its electromigration rate, as well as �ri_~~ silicon, for the purpose of pre-
venting the appearance of etching holes ir, the contact windows with the semicond-
uctor structure when electrical current f;lows through it; --Applying protective dielectric coatings of S102, A1203, etc. to the surface of
the thin metal films, which make it difficult for "nodules" to grow (and conse-
quently also cavities) in the conducting films;
--Monitoring the thickness of thin metal films (especially the degree of coverage
of relief steps) using a scanning electron microscope; -
--Visually monitoring the quality of the thin film wiring layout under a microscope
for the purpose of rejecting IC's with defective current conducting tracks.
Multilevel Interconnection Layout. Because of the increase in the component place-
ment density on chips in the production of very large scale integrated circuits,
there has been a great growth in the role of multilevel metallization at the present
time [28, 59, 62, 71, 74, 75]. When a transition is made to LSI circuits, as prac-
tice has shown, the prevalent types of failures become thase related to the multi-
level metallization [27, 63].
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We shall consider problems of reliability related to the occurrence of new
failure mechanisms which are characteristic of multilevel metallization, a
schematic cross-section of which is shown in Figure 18.
There are three specific kinds of failures inherent in this structural component
of IC's [62, 74, 751:
--Disruption of the electrical contacts between the thin film conductors of the
different levels;
--Short circuits between the thin film conductors of the different lavel.:; because
of the presence of defects in the interlevel insulation;
--Breaks in the thin film conductors of the upper levels at relief steps in the
lower metallization levels.
Strictly speaking, the latter type of failures is also observed in IC's with a
- single level of inetallization, but with the transition to structures with multiple
level metallization, ita role increases significantly.
Contacts between the tracks of the different levels should have a low electrical
contact resistance and a high current carrying capacity.
Failures of the first kind occur because of contact window opening defects in the
interlevel insulation. Undercutting etching and complete overetching of lower
level thin film conductors are observed, since the aluminum used at the present
time as the basic material for thin film IC conductors actively interacts with
a broad range of the etchants which are used. Moreover, it is difficult to assure
a high quality coating of the lower layer of inetal when depositing the upper
metallization level in these regions because of the "shading" of the lower sur-
face (bottom) of the contact window by its walls [75]. The electrical contact
can be preserved in this case, however, increased resistance in this region can
lead to IC failure during its operation.
Failures of the second kind are due to defects in the oxide film used as the
interlevel insulation. Usually, the oxide layer is obtained by precipitation
from the gas phase and is extremely inhomogeneous, in which case, the material
of the lower layer as well as the geometry and thickness of the oxide can have
an influence on its profile [62; 74]. If the edges of the thin film conductors
are not smoothed off in this case, then microholes can be formed at the steep
steps in the metallization, where these holes are potential sources ofshort
circuits (see region 9 in Figure 18). Insufficiently careful cleaning of the
surface prior to the application of the oxide, as well as unsatifactory monitor-
ing of the composition and thickness of the deposited oxide film exacerbate this
phenomenon. Effective techniques for solving this problem are smoothing off the
edges of the thin film conductors and providing for an optimal ratio of the thick-
ness of the metal layers and the oxide covering it (increasing the oxide thick-
ness).
Shorts between the conductors of the different levels can also appear because of
the growth of nodules ("little bumps") on the surfaca of the metal film during
subsequent heat treatment [74].
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The height.of such bumps can reach a few microns, and the passivating layers of
oxide or photoresist film cannot cover them, something which leads to undercut
etching of the oxide and the metal. As a result, shorts appear between the con-
ductors of the various levels when subsequent metallization levels are applied or
during operation of the IC's with temperature and electrical loads.
Figure 18.
Key: 1.
2.
3.
4.
5.
6.
7.
8.
9.
Cross-section through the structure of an integrated
circuit made with two-level metallization (levels I
and II) with a passivating protective glass surface.
"Thermal" Si02;
Precipitated S102;
Passivating glass;
Si;
Lower metallization level;
Upper metallization level;
Contact between the conductors of the different levels;
Thinning of the upper level conductor at a relief step in
the lower level;
Insulated crossing of the conductors of the different levels.
An effective means of preventing the formation of nodules and cracks in the oxide
film is the use of a low temperature 400� C) passivating coating of Si02 of
sufficient thickness (up to 100 nm). It is also recommended [75] that a combina-
tion af two technological processes be used for the application of the Si02 films
(P.F vaporization coating at a temperature of about 100� C with subsequent chemical
precipitation of Si02 from the gaseous phase). In this case, the bottom (main)
Si02 layer provides for good insulation, while the upper layer covers possible
holes and smoothes the surface of the oxide film.
The third type of failure is breaks in the thin film conductors of the upper levels
at steps in the lower levels and is the most probable kind, where rather high and
steep relief steps are formed on which it is very difficult to apply a layer of
_ metal in the process of producing the third and subsequent levels of inetallization
(Figure 19). The most effective means of eliminating this cause of failures is
- the technique of "smoothing off" the edges of the thin fllm conductors when pro-
ducing the bottom (first) metallization level. However, it must be noted that the
cross-sectional area of the thin-film conductors of the first level is approxi-
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mately cut in half in tt+is case (as compared to the initial value), which can
lead to failures due to electromigration, if the reduction in the cross-section
is not compensated beforehand [74].
ypuBNU Me
I 1l pl PoaDe+O Mt-0
Sc
Figure 19. Break in a third level
thin film conductor at
the matching boundaries
of conductors of inetalli-
zation levels I and II.
Key: l. Metallization levels;
2. Break in level 3.
Scientific research and design work are
constantly under way to seek out new com-
binations of inetals to produce reliable
current carrying conductors and materials
as weZl as a more refined technology for
applying insulating films in structures
with multilevel metallization so as to
more fully utilize all of the advantages
of multilevel metallization.
The most promising trends in this case
are:
--Replacing aluminum as the main material
of the conductors with multilayer thin
metal films based on difficultly fusi-
ble metals [59, 58, 761;
--UsirLg aluminum dioxide for the inter-
level insulation of the films, where
this oxide is obtained by means of ano-
dizing, or using polyimide films [77,
78].
Thin multilayer metal films (Ti-Pd-Au, No-Au-No, Ta-Au-Ta, etc.) make it possible
to:
--Increase the mean time before failure by one to two orders of magnitude (under
similar operational conditions);
--Reduce the geometric dimensions of the current carrying conductors as compared
to single layer ones with the same current density levels;
--Assure high adhesion and substantially reduce the probability of undesirable
chemical interactions of ineta'L films with silicon dioxide, silicon, moisture
and surface contaminants of the chip;
--Markedly reduce the mutual diffusion rate of the metals (the Au-Au welded con-
tacts).
All of these advantages completely justify increased complexity of the metalliza-
tion system, especially for very large scale integrated circuits.
The use of new insulating materials as the interlevel insulation instead of tradi-
tional silicon dioxide makes it possible to:
--Substantially reduce the probability of failures due to short circuits between
the conductors of the various levels as a consequence of the better electrical
insulating properties and the smaller number of defects in the "barrier" A1303
oxide films and the polyimide films (as compared to S102);
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--Reduce to a minimum (in structures with A1203 dielectric insulation) or complete-
ly eliminate (in structures with polyimide insulating films) relief steps, which
makes it possible to eliminate local thinning of the thin film conductors at
relief steps of the lower levels of the wiring layout and to realize three to
five level metallization for very large scale integrated circuits while pre-
serving acceptable indicators for their reliability;
--Increase the resistance of multilevel metallization to thermal shocks because of
the high elasticity of the polyimide.
In conclusion, we shall consider yet another kind of contact connecticn used in
integrated circuits. .
- The Chip to Chip Holder Contact. In the process of mounting the chip in a package,
it is fastened ("seated") in the chip holdex by means of brazing using a gold-
silicon eutectic or by gluing with a heat resistant glue (compound). It should be
noted that "seating" the chip on a eutectic is more to be preferred bPCause of the
better mechanical properties and lower thermal resistance as compared to glued con-
tacts.
= As a result of contamination of the chip surfaces and the chip holder, or inade-
quately wQrked out conditions for the " seating" operation, nonuniform wetting of
~ the surfaces being joined together with the gold (or glue) is sometimes observed,
misalignment of the chip and other defects occur which lead to a degradation in
the characteristics of the contact connection.
Nonuniform brazing or gluing (in particular, because of nonuniform wetting of the
surf.aces) in the region of the chip--chip holder contact connection (region 8 in
Figure 13) can lead to the fact the IC's will contain cavities underneath the
chips, although they pass all of the electrical tests. This defect can manifest
both in an overall increase in the thermal resistance of the IC, and in nonuni-
formity of the temperature field in the chip, something which is the most dariger-
ous for high power and linear IC's. The mechanical strength of such a contact is
naturally reduced. It is specifically IC's with such weakened contacts which are
= the most inclined towards failures because of the difference in the temperature
coefficients of expansion of the materials employed. This eff ect is especially
pronounced in the accumulation of inechanical fatigue damage due to variable mech-
anical stresses which occur in the structural components with long term exposure
of the integrated circuit to temperature gra3ients: thermal shocks, thermal
cycling, and a cyclical variation in the dissipated power.
In this case, it is specifically a degradation of the contact connections which is
observed first of all, and which leads in the final analysis to a gradual failure
of the IC, especially in the case where it is hermetically sealed in a plastic
package.
We shall now move on to a discussion of third category: failures related to the
state of the integrated circuit surface.
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3. Failures Due to Phenomena on the Chip Surface
Gradual failures due to surface instability of IC's and the ir.fluence of the
environment comprise an important category of IC failures, especially in the case
of an increased level of IC integration. The difficulty of achieving the high
level of purity needed to preclude undesirable surface effects, the reduction in
the dimensions of the r.omponents and the spacings between them, which leads to
an increased electrical field intensity in IC's, as well as the wide scale applz-
cation of an increased level of integration of MOS transistors with a thin layer
cf oxide under the gates in integrated circuits - all of these factors make the
study of the influence of the surface migration of ions on MOS and bipolar IC
_ reliability an extremely urgent problem.
The application of dielectric films to the surface of a chip for the purpose of
passivating it or to form interlevr.l insulation in the multilevel metallization
of very large scale integrated circuits can have a substantial impact on IC relia-
_ bility because of the change in the following characteristics of the Si--Si02
- system [30, 31, 47, 62, 79-81]:
--The amount of the mobile and stationary charge in the oxide;
--The stability of the charge in the oxide when exposed to an electrical field
under elevated temperature conditions;
--The surface recombination rate.
We shall consider the possible reasons for these failures. As is well known, when
using planar technology, the electron--hole junctions are formed by the diffusion
of doping impurities into the silicon through local openings in the silicon dioxide
film which are produced photolithographically. In this case, the oxide layer
serves as a masking coating, performing the functions of a"barrier" for the doping
impurity (boron, phosphorus, etc.), which is necessary to produce the individual
- IC components in accordance with the specified topology.
After fabricating the device, the oxide film remains on the chip surface and pro-
tects the p-n junctions from the environment, thereby performing the functions of
- a passivating and stabilizing coating. However, charges of a diverse nature are
present on the surface and within the oxide (the positive and negative ions of
the doping impurities, excess ionized silicon atoms, electrons, holes, "traps",
etc.), which are symbolically depicted in Figure 20 [82]. During integrated
circuit operation, the redistribution of the electrical charges takes place at
the Si--Si02 separation boundary and the near-surface region of the semiconductor
= crystal, where this redistribution causes significant changes in the characteris-
- tics of the p-n junctions and some,*.imes leads to the appearance of surface channels
with an inverse silicon conductivity ("inverse" channels). Because of this pheno-
menon, the leakage currents rise and the IC parameters are substantially degraded
(62, 79, 83].
The kinetics of the process which leads'to the formation of inverse channels in
integrated circuits is shown in simplified form in Figure 21 (a-c). The oxide
- layer which coats the chip uf an actual IC takes the form of an amorphous
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structure, the basis for which is sili-
Me con, phosphorus and boron atoms bound
x- R-* R+ x- with oxygen atoms. Moreover, atoms of
~ RR+ X_ such alkali earth metals as sodiumi
potassium and lithim are usually gre-
x_ R+ + R+stOp sent in the oxide. The concentration
~ ~ and mobility of these ions (and other
+ R+ R+ contaminants) is especially high in
+A+
the case of insufficiently effective
Si
cleaning of the surface af the plates
prior to oxidation or contamination
Pfic. 20. CxeMa pacnpeAe,neNxR sapR� ,
during the process of applying (grow-
noB, B03HNK8IOIIIHX s oxxcxoR nneHxe.:
ing) the oxide or where a high density
R+ , X- -HOxa He noeepxxocrx x axyrpa
of def ects is presenti in the oxide
sio,; (DExcess "ionized''
film. The metal ions are positive,
and in having a high mobility in the
- Si atoms; UM "trapst1
oxide structure, can easily move in
-
the oxide layer to the Si--Si02 separa-
Electrons and holes..
tion boundary when exposed to an elec-
trical field. As a result of this, a
Figure 20. Schematic of the distribution
bulk positive charge is formed in the
of the charges occurring in
thin oxide layer located directly at
an oxide film.
the separation boundary. The electric-
th
i
+
al field produced by the bulk charge of
e
ons at-
and x are
R
Positive ions serves as the reason for
surface and inside the Si02.
the occurrence of local regions (chan-
nels) in the near surface layer of the
silicon, which possess electron conductivity. The formation n-type channels
causes the depletion or inversion of the conductivity of the p-type silicon and
the accumulation of excess current carriers
in the n-type material.
~ 3 3 _ -
1 f
O 6 m ~ ~ �
p - Y
P n =
-f17 P n
(a) � 3 (b) 6
= i
- - Y
P n
0 (c)
Figure 21. The sequential stages of charge separation by the electrical
field in an oxide film and the formation of inverse channels
on the surface of the silicon.
Key: 1. Si02;
2. Si;
3. Metal electrode.
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It has been experimentally found that inverse channels can be eliminated by means
of high temperature annealing without supplying inverse bias to the IC. However,
the source of instability is not eliminated in this case and during subsequent IC
operation at an elevated temperature, the channels are formed again.
MOS structures are the most sensitive to the state of the oxide, in which the
effect of ion surface migration is substantially amplified by the overall impact
of three factors:
--The oxide under the gate is the "working" element of the IC, governing its basic
electrical characteristic: the threshold voltage;
--The thickness of the oxide under the gate usually does not exceed 150 to 200 nm,
something which, first of all, makes it difficult to assure a perfect structure
of the film, and secondly, leads to an increase in the electrical intensity in
the critical region, and thirdly, reduces the spacing which the positive ions
must overcome to reach the separation surface;
--The working supply voltages normally used to electrically drive MOS structures
substantially exceed the voltages for the majority of logic planar epitaxial
IC's [30].
The main kind of failures due to surface effects, characteristic of MOS IC's, is
threshold voltage instability when they operaze under conditions of elevated temp-
erature and negative bias.
- The design of integrated circuits of an increased level of integration with multi-
, level metallization, as well as with a single level of inetallization coated with
a layer of silic.on dioxide (glass) exacerbates the problem of surface instability
[47, 62, 81]. This is related to the fact that the additional protective oxides
applied to the surface of the sufficiently perfect, thermally grown oxide, as a
rule have a higher moisture content, degrading the properties of the silicon--
silicon dioxide separation boundary.
Supplemental doping of the oxide with phosphorus (in the emitter diffusion state)
is widely used to stabilize the surface, since the thin layer of phosphorus sili-
cate glass (PSG) formed in this case has getter properties with respect to the
alkali earth metal ions and plays the part of a barrier, actively impeding the
accumulation of ions at the separation surface [47, 62, 79, 84].
It must also be noted that when applying a glass-like film of PSG to the surface
of the oxide, its dielectric strength is increased at the same time, since the
boundaries of the grains and microcrystallites, which reduce the breakdown voltage
of the oxide, terminate at the PSG--Si02 separation boundary, not going aut to
the surface of the oxide.
However, care must be talcen when alloying the oxide with the PSG layer, because
the excessively high P205 concentration can lead to a shift in the threshold vol-
tage because of the phenomenon of PSG polarization.
Such a type of failure as a short circuit of the thin film conductor at the sili-
- con surface through holes in the oxide film are also to be numbered among failures
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due to unsatisfactory surface states of IC chips. The reasons for this are usually
various oxide defects (holes, punctures, microcracks, underetchings, etc.), which
reduce its dielectric strength or Which expose the surface of the silicon [47, 621.
In this case, only the small air gap between the metal and the silicon serves as
the insulator, the dielectric strength in the local region falls off sharply (from
4- 107 V/cm to 5. 105 V/cm and less), and when a sufficient electrical voltage
is fed to the IC, the conductor short circuits at the surface of the semiconductor
chip.
One of the reasons for failures related to breakdown of defect free dielectric
films, used in IC's with MOS structures, is the effect of static electricity dis-.
- charges on the ultrathin (usually no thicker than 150 nm) dielectric films which
- insulate the gates. Thermally grown S102 films or a combination of silicon dioxide
layers with silicon nitride, S102 + 5i3N4, are used, as has already been noted,
as the dielectric in MOS structures. Despite the fact that thin homogeneous films
of the indicated dielectrics are immune to electrical fields of up to 4- 107 V/cm,
an irreversible dielectric breakdown can be observed in MOS structures at consider-
ably lower intensities (about 4- 106 V/cm), corresponding to a gate voltage of
50 to 80 volts [89, 90]. This is explained by the redistribution of the electric-
_ al field, where this redistribution generates local regions with an elevated
field intensity in the near-surface region of the dielectric f ilm at points where
the gate metallization overlaps the peripheral regions of the p-n junctions (the
drain and the source). Breakdown of defect free dielectric films in these regions
occurs at voltages considerably less than the breakdown level for the p-n junctions
of the MOS structure.
4. Other Kinds of Integrated Circuit Failures
Because of the high chemical reactivity of aluminum and a number of other metals
~ used in IC's, as well as the extremely unfavorable i.mpact of moisture and chemical
contaminants on the properties of IC chip surfaces, the degree of hermetic sealing
of IC packages is of particular importance from the viewpoint of reliabi?ity. The
presence of microholes (leaks) in packages - defects in packages or the hermetic
seal which are not detected in time or which appear during improper apFlication
of the IC's - which promote the penetration of water vapor, di_rt, chemically
reactive substances, etc. into the IC's during their operation, especially under
conditions of elevated ambient humidity, can lead to failures due to corrosion
of the thin film conductors and resistors as well as the occurrence of ion and
inversion type leakage, the mechanisms for which were treated in detail above.
Unsealed soldered or welded seams and the points of inetal to glass joints (espe-
cially in the case of incomplete fusion, incomplete wetting with solder, splitting
and other mechanical damage to package components) are possible paths for the
penetration of moisture, dirt, etc. into IC's. Moisture and contaminants can
penetrate into plastic packages to the surface of the chips through pores in the
plastic or along the surface of the separation between it and the metal leads
(feed-throughs and flexible leads) [65, 66, 69].
An important cause of degradation which exerts a substantial influence on IC relia-
bility is the corrosion of the metal parts of packages because of insufficient
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- thickness or mechanical damage to their anticorrosion coatings, as well as because
of exposure of parts of the components fabricated from corrosion vulnerable metals,
at points of cracking or chipping of the glass insulators.
Chemical or electrochemical co.rrosion of package components, primarily the external
_ leads of a package, leads to IC failures in the external appearance or because of
the teaxing away (breaking) of the external leads during storage or operation of
the IC with power applied under conditions of increased ambient humidity.
- To eliminate the indicated reasons for failures, the most promising approach is
the refinement of inethods of checking the hermetic seal of IC's, which make it '
~ possible to ascertain leaks in the packages throughout the entire range of.inflow
rates.
_ During longterm operation or testing of IC's at an elevated temperature (on the
order of 125� C), failures are observed in a number of cases which are related to
the disruption of the electrical integrity of the soldered connections of the
external leads of a microcircuit, with the leads made of gold plated Fernico,
to the current carrying tracks on the printed circuit. The failure mechanism in
this case is related to the dissolution of the gold in the lead-tin solder [91],
which can lead to the occurrence of sections of exposed Fernico on the external
].eads of IC's (when they are mounted on a printed circuit board) and the subse-
quent degradation of the soldered contact quality (during subsequent operation
of the IC's) in the case where the thickness of the gold coating of the external
leads is insufficient, while the quality of the soldering of the IC to the circuit
board is unsatisfactory ("point" soldering).
Such are the major kinds, reasons and mechanisms of the degradation processes
which lead to failures of semiconductor integrated circuits.
In conclusion, we shall briefly treat the specific features of very large scale
integrated circuits which influence their reliability and which are manifest in
the redistribution of the dominant failures with respect to types and in changes
in the kinetics of integrated circuit failures.
To define the trends in the change in the reliability of ver.y large scale inte-
grated circuits it is necessary to evaluate the impact of the following factors:
--Multilevel metallization with dielectric film insulation applied by precipita-
tion techniques;
--The reduction in the dimensions of the active and passive componants as well as
the spacings between them;
--The increased power dissipation level per unit of chip area;
--The increase in the dimensions of the chip and package [32, 62, 71].
An analysis of the test and operational data existing at the present time large
scale integrated circuits [27, 32, 33, 30, 62, 86] attests to the fact that with
an increase in the number of gates on a chip, a redistribution of the types of
failures takes place (see the comparative data in Table 10):
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TABLE 10. Comparative Data on the Distribution of IC's with Respect to the Kinds
of Failures as a Function of the Level of IC Integration
Number of IC Failures, %
LSI
Low Level Intermed-
of Inte- iate Level Bi- MOS
- Reason for the Failure gration Integration op lar Structure
1. Thin film conductors ("metalliza-
tion") 16 25 27 4
2. Defects in the photolithography and .
diffusion 14 12 25 6
3. Defects in the structure and con-
tamination of the oxide and semi-
conductor chip 26 25 14 54
4. Defects in the assembly and sealing
(breaks in the welded contacts, ,
defects in seating the chip, dis-
ruption of the hermetic seal, etc.) 28 12 6 -
5. Intrusion of foreign particles
into the package 8 12 14 12. 6. Other reasons for failures (includ-
i ing undetermined ones) 8 14 14 24
~ .
~ 7. Incorrect use (in the form of the
ratio of failures because of .
~ incorrect use to the total number
! of detected failures) 36 17 5 15
! --For bipolar large scale integrated circuits (LSI), the specific percentage of
failures related to the metallization, diffusion and intrusion of foreign par-
~ ticles into the package increases [27, 32];
--For LSI circuits based on MOS structures, the characteristic causes of failures
are defects in the oxidation, charge instability related to contamination and
defects in the photolithography [27, 31, 32, 33, 30, 62, 86].
Problems related to the use of multilevel metallization were treated in Chapter
II. We shall now briefly touch on the influence of "dimensional effects" in
large scale integrated circuits.
A substantial increase in .the level of IC integration is manifest, first of all,
in a sharp reduction in the geometric dimensions of individual elements (for inte-
grated circuits of the third and fourth Ievels of integration, down to values on
the order of 1 to 3 um) and the spacings between them, and secondly, in the use of
structures with "small" p-n junctions with submicron doping depths for the junc-
tions and minimal thicknesses of the epitaxial layers, reaching 1 to 2 um.
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_ Obviously, elements with such small dimensions will be made with greater relative
errors than the larger elements of integrated circuits of the first and second
levels of integration, since the absolute errors in the fabrication of IC's given
the technological state of the art will be approximately the same. In this case,
considering the fact that concurrently with an increase in chip size, the number
of defects occurring on its surface will also increase, the conclusion can be
drawn that with a rise in the level of integration and when the present level of
materials quality and technological process stability is maintained, the percentage
of potentially unreliable IC's will increase. The reduction in the geometric
dimensions of elements on a chip, besides increasing the criticalness of IC's to
the layout precision and resolving power provided by photolithographic processes,
- the role of such failure mechanisms as corrosion and electromigration of the
material of thin film conductors will increase markedly, as well as the formation
of shunting leaks (shorts) between IC components, leaks and breakdowns of p-n
junctions due to disruption of the diffusion profiles because of photolithography
defects; etc. The influence of "small geometry" is manifest here in two ways:
first of all, as was noted above, with a reduction in the spacings between the
elements, there is an increase in the electrical field intensity between them,
which increases the rate of degradation processes; secondly, the reduction in
the width of thin film conductors, the doping depths of the p-n junctions as well
as the spacings between the active and passive components and current conducting
tracks on a chip increases the criticalness of IC's to the failure mechanisms
indicated above.
All of this attests to the necessity of devotLng special attention to questions of
assuring the reliability of IC's with an increased level of integration in all of
their production (design, fabrication) and applications stages.
i
I
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Chapter IV. Methods of Monitoring and Estimating the Reliability of Semiconduc-
tor Integrated Circuits
5. General Principles
In considering the methods of monitoring and estimating the reliability of semi-
conductor integrated circuits, it must be remembered that reliability is one of
the most important properties of their quality. For this reason, quality control
is at the same time a method of checking the reliability of the IC's being
monitored.
TABLE 11. Costs o� Reliability Tests for Semiconductor IC's
(1)
(2)
S3LoArsepxcAaewaa %�xapaKTepMcreKe c p�-0,9
Koaavc
crso rc�
AortycTe-
rx Koneae-
hr-1
x-10-7a-+ hr-1
ne+rr~-
vaerLS
rno orKasas-
mrx rxxDo-
fipoAOnacx-
CTOMMOGTb
1TDoAOnxe-
'
CTD\YOCT
YtipO-
UClN, mT.
CZlY D nap-
T[1, IGT.
TlJfNOCTb
ICII61'1'itlllA,
~
HCi1di8Htll1,
dc. PY6.
TllIbNOCT1
HCUdT&H01.
` q
XCGLfTaAt.
oro�
(4)
5 3
4
~
5
0
2300
-
2000010

10
1
3900
-
4000000
"
2
5300
-
5000000
^
0
230

100
1
390 �
T7
4~0
~
2
530
C
500000
9000
I 0
23
12,0
23000
400
1000
,
I 2
53
13
0
53000
9m
.
ou
pprox.
I
0
OKOno 2
I1pNMepNO
2300
160
120,0
1000n 1
OKOno 4
Tlp}+MepHO
4000
180
120,0
2
Osono 5
IIpNMepHO
5300
210
I
About 5
120,0
Key: l. Quantity of IC's being tested, items;
2. Permissible number of failed IC's in a batch, items;
3. Confirmed a characteristic with p* = 0.9;
4. Test duration, hours;
5. Test cost, thousands of rubles.
The highly reliable nature of semiconductor IC's is responsible for the insignifi-
cantly small number of device failures during even the most extensive testing,
because of which the use of inethods of monitoring and evaluating reliability based
on the determination or confirmation of a specified a characteristic proves to be
unacceptable in the majority of cases because of economic considerations and by
virtue of its excessive operating time requirements. The data cited in Table 11
which characterize the time needed to evaluate IC reliability in this way, as well
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as its cost, speak for themselves. It must be kept in mind that these are clearly
understated data, since in figuring the cost of the tests, only the costs of the
samples being studied was taken into account (taken as equal to 10 rubles), as
well as personnel salaries and overhead; such important components as the cost uf
the testing and measurement hardware, equipment and production space amortization,
expenditures for materials and electrical power, etc. were not taken into account.
Nonetheless, the data cited here are sufficient to convince onp that even the most
economic testing plans are burdensome financially and unacceptable because of the
delay in obtaining tre information needed for quality control. In essence, it is
equally impossible to lose thousands of hours waiting for the results of tests
necessary to make the decisions to ship or not to ship the manufactured product,
or having shipped it prior to the completion of the tests, several thousand hours
after finishing the tests to then take steps directed towards improving the
quality. In this case, such belated infor.mation on the quality of manumfactured
products carries a very expensive pricc. If one additionally takes into account
the fact that the estimate of the reliability obtained in such an expensive way
applies only to a definite type of IC, and it is not always possible to extrapolate
the results obtained to other types of IC's, the inexpediency of such an approach
to reliability evaluation becomes obvious [92, 93].
Another serious drawback to the method treated here is the technical complexity
of the tests. The complexity of the tested unit is responsible for the complex-
ity of the equipment used for the tests. Automated production lines, precision
measurement hardware and test stands of the most complex designs as well as `
climatic chambers comprise the equipment of microelectronics enterprises and
provide for great precision in setting production process and test modes and
conditions, maintaining them and recording the measurement results. With all of
this, errors are not permitted in the measurement of the parameters, otherwise,
a nonexistent (false) failure will be taken into account, or, vice-versa, a real
failure will be allowed. In both cases, the time and money prove to be spent in
vain. It must be noted that in step with the further refinement of individual
technological operations, the imperfection of which at the present time serves
as a source of IC failures, their reliability will approach their own physical
limit and the indicated difficulties in evaluating the level of reliability
attained will increase.
The methods of monitoring and evaluating IC reliability employed in worldwide
practice take these difficulties into account. Thus, for example, the military
specification standards of the U.S. and other foreign nations provide for a
differentiated approach to the solution of the given problem. In accordance with
the documents, production monitoring is accomplished at an easily monitored level
(for example, the basis for the U.S. monitoring plan is the requirement that a
figure of a= 10--20 %/1000 hr be confirmed), while no estimation is made of
the attained level of reliability according to these documents. It is achieved
by taking into account the data on IC reliability during operation.
By monitoring the constancy of the production level over the time segment of
interest, confidence is gained that'the reliability of the product batches
fabricated during this period is no worse than a specified level. In other words,
it is altogether sufficient to monitor the failure free rate during series pro-
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duction (in contrast to trial production, when obviously it is expedient to
determine both the no-failure operation figure and the service life).
Thus, the high reliability of semiconductor IC's renders an evaluation of their
reliability by means of testing of little promise. The solely acceptable method
of solving this problem is gathering and processing the results of IC operation.
A role is set aside for tests though in check operation which is performed in
the interest of obtaining information which characterizes the stability of the
production process and the production level during the time segment being moni-
- tored.
Confidence in the correctness of implementing the technology and the requisite
quality of the raw materials, semi-finished products and complete product assem-
blies, along with knowledge of what reliability the given technological process
assures create the prerequisites for an apriori estimate of the reliability of
integrated circuits produced over the time segment which was studied.
The product quality control system employed in worldwide practice is based*on
the following principles:
--In the process of doing the scientific research and prototype design work,
limit tests are performed, while operational monitoring is carried out during
the production process of fabricating the integrated circuit$;
- --Each production batch of IC's is subjected to acceptance tests, based on the
results of which ajudgment is made concerning the possibility of delivering
this product to the consumer; standards are employed in the acceptance testa
which are many times greater than the operational norms;
--The level of operational loads simulated under laboratory conditions is chosen
as close as possible to the actual ones which it is still possible to reproduce
using the test equipment;
--Depending on the fabrication,quality, the finished products are differentiated
with respect to reliability categories; corresponding to each category are its
own requirements and check operations; --The shipment of the products is based on the results of checking the production
level of reliability;
--The estimate of the attained reliability level is made on the basis of results
oF comprehensive tests performed for the fu11 volume, needed to determine the
quantitative indicators for reliability, service life and strength safety mar-
gins as well as the safety margin for exposure to environmental factars, taking
the operational data into account.
The most important features of a progressive quality control system can be charac-
terized as follows:
--The requirements placed on the components are as close as possible to the actual
ones, taking economic expediency into account: the cost of reliability assur-
ance programs for the supplier and the consumer are taken into account;
--Test procedures are based on intensifying the developmental processes of hidden
production defects and identifying failures, and provide for maximum rejection
of all "weak" devices;
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--During acceptance testing, product quality is checked with respect to all
major requirements;
--The most progressive test procedures and the analysis of failed products are
standardi2ed;
--The engineering and standard setting documentation provides for sharing the
responsibility for quality assurance and maintaining the reliability of IC's
during production and operation.
The engineering standards setting documentation establishes several levels of IC
quality, which differ from one another in the degree of stringency of the
requirements placed on quality and the quality evaluation criteria. In line
with existing practice, the norms adopted for checks at various production stages
are made significantly stricter than the norms used when quality control testing
the finished product. This is done in the interests of providing guarantees of
the rigorous performance of production process operations and the high quality
fabrication of the products in all stages.
For IC's intended for delivery to especially important projects, special reliabi-
lity assurance programs have been developed. They take into account the opera-
tional conditions of the integrated circuits. The monitor operations which are
repeated and targeted as much as possible towards a specific goal provide for
checking that the samples being studied conform to the requirements placed on
them. For example, it is well known that the U.S. space research program includes
general and special programs for space systems reliability support as a whole as
well as for individual equipment, assemblies and components of radioelectronic
hardware.
Integrated circui.ts, just as other kinds of equipment components which are intend-
ed for these kinds of projects, are certified by means of performing qualification
tests which guarantee the evaluation c` definite reliability levels for the IC`s,
and are incorporated in the listing of products alithorized for applicationa in
special equipment.
During the process of IC fabrication, its quality is repeatedly and carefully
checked. Reginning with the input quality control of the raw materials; semi-
finished products and complete product sets and concluding with the quality con-
trol of the finished product, integrated circuits are constantly under the
observation of shop workers, as well as the workers of technical control depart-
ments and reliability services.
The monitor operations during the production process for semiconductor integrated
circuits comprise about 40 percent of all operations. The fraction of the outlays
for monitor operations reaches 60 percent of the overall expenditures.
The numerous check operations are called upon to test the fabrication quality of
the integrated circuits at various stages in the production process. In this
case, checking is done to see that the following major requirements are met:
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--Conformity of the external appearance of the chips, plates and bases of the
; IC's to the requirements of the engineering standards documentation;
--The absence of varnishes, glue and other organic materials inside the package,
which are not authorized by the engineering standards documentation, as well
as foreign particles;
--The absence of cracks, cuts, dirt and foreign materials over the length of the
IC leads;
--The strength of the internal connections.
The quality of IC's during the production procesa is monitored by means of
measuring the corresponding characteristics and parameters, as well as by means
- of all possible kinds of tests.
For ongoing monitoring of the production level and quality of the product at
= various stages in the fabrication, tests are employed, the kinds and order of
performance of which are set forth in later sections. Recent years have been
characterized by the wide acaledissemination of nondestructive techniques for
quality control, estimation and prediction of reliability as well as apriori
methods of predicting the reliability and durability of intergrated circuits.
Integrated circuit quality control provides for establishing the fact and degree
of IC conformity to the requirements of the engineering standards documentation
~ which regulates the requirements, norms, methods, means, procedure and organiza-
! tion for the conduct of tests, measurements, as well as acceptance and shipment
rules for the received product. Such engineering atandards documents include
i state and sectoral standards, enterprise standards, model regulations and tech-
~ nical specifications [94, 95].

~ The conformity of IC's to the requirements of the engineering standards docu-
, mentation is evaluated by means of ineasurement and the determination of various
~ parameters and characteristics under various environmental conditions under
! specific loads.
The listing of the parameters to be monitored during the production process is
indicated in the routing charts, while the parameters of the finished products
are indicated in the technical specifications.
In the interest of providing for maximum quality control effectiveness (also
including economic effectiveness), the most informative parameters are chosen
as those to be monitored. These are those parameters which correlated well with
other ones and most fully reflact�the physical processes.in the IC which occur
under the applied load and with the ambient conditions, as well as the variation
in the processes. An effort should be made to see that their number is as small
as possible. An obligatory requirement placed on the parameters selected for
IC quality control is measurement simplicity, convenience and safety and the
capability of reproducing the measurement results. The listing and number of
such parameters are governed by experience with the design, fabrication and
operation of the integrated circuits. The list of the parameters being measured
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can be supplemented based on the operational results for the IC's. If failures
- are repeatedly found which are due to the inability to check a given parameter
during production, it is essential to incorporate an additional quality control
- operation.
The volume of checks is curtailed if the accumulated experience attests to the
- expediency of eliminating particular checks.
The quality control is realized by performing the following:
--Qualification tests (in the stage of getting the products in production), the
purpose of which is to demonstrate production readiness to manufacture products
which meet the requirements of the customer;
--Input quality control of the materials, semi-finished products, component pro-
ducts and devices;
--Operational quality control of the manufacturing of the IC's;
--Monitoring the production processes;
--Quality control testing of the finished product.
The tests are performed on special equipment which assures that the specified
test mode will be maintained for the requisite time and the eetimation of the
test data will have the requisite precision. Meeting the indicated conditions
assures obtaining reliable results as well as the reproduction and uniformity
of the test modes aC var'.ous times on various equipment. JusC as important a
role is assigned to :.ne choice of the type of test hardware as to the selection
of the optimum testing procedure in the efficiency of evaluating quality.
The requirements placed on the choice of the optimal testing methods and equip-
ment provide for the observance of the following main recommendations. They
should make it possible to obtain exhaustive and objective data on the tested
quality property of the integrated circuit being tested in tre most economical
manner. In other words, a reliable estimate of the capability of the test
subject to stand up to the test conditions aiid maintain operability under these
condltions should be obtained in the shortest possible time while using compara-
tively simple test equipment and gauging the minimum possible number of servicing
personnel.
In cases where stand tests do not make it possible to obtain the requisite infor-
mation, the results of full scale and ob3ective tests of the IC's are employed.
Objective tests of integrated circuits are nothing more than their operation
as part of equipment designed around them under conditions stipulated by the
_ technical specifications for the unit. By carefully taking into account the
information on IC behavior under operational conditions, the most reliable esti-
mate of IC reliabtlity is obtained without additional expenditures of time and
money.
A typical program for worldwide practice in acceptance testing is shown in Table
12 as an example.
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TABLE 12,
Kind of Tests
Subgroup I
Checking the overall
dimensions
Subgroup II
Resistance to exposure
to the soldering temper-
ature
Thermal cycling
Thermal shock
Moisture resistance
Subgroup III
Multiple shocks
Vibration strength
at a fixed frequency
Vibration strength in
a range of frequencies
Greatest Per-
missible Per-
centage of De-
fective Devices
Test Mode and Conditions in a Batch oi
a ' 10-5 hr ,
for P* = 0.9
20
In accordance with the tech-
nical specifications
The IC leads are simultaneously
or alternately immeraed for 10
sec in solder at a temperature
of +230� C to a depth of 1.5 mm
from the package
Number of immersions is indi-
cated in the technical specifi-
cations
From -65� C to +175� C. Expo-
sure time 30 min; transfer time
5 min. Number of cycles: 5.
From +100� C to 0� C. Exposuxe
time 0.25 to 5 min. Transfer
time 3 to 10 sec. Number of
shocks: S.
From -10� C to +60� C. Moisture
up to 98%. Time for l cycle,
24 hr. Number.of cycles indi-
cated in. technical specifica-
tions.
Acceleration of 1,500 g; pulse
width of 0.5 msec, 5 shocks each
in 3 mutually p erpendicular
directions. Overall number of
shocks: 15.
Frequency of 60 Hz; acceleration
of 20 g; 32 hr ezch in 3 mutually
perpendicu:Lar directions. Total
testing time: 96 hr.
Frequency of 100--2,000 Hz;
acceleratinn of 20 g; tPSting
time: 48 m3.n.
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20
10--20
Accept-
ance
Number,,
Items
5 ~
1--5
2--5
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- TABLE 12. [ cont. ]
Resistance to the action
Acceleration of 20,000 g;
of a constant (centri-
1 min each in 3 mutually
fugal) acceleration
perpendicular directions.
~
Overall.testing time: 3 min.
Subgroup IV
20 1--5
' Checking the mechanical
Three leads are checked by
. strength of the Ieads
means of suspending a load.
The weight of the load and
the time are given in the
techni.cal specifications.
Subgroup V
20 1--5
Checking the corrosian
The devices are kept for
immunity
24 hr in a chamber with a
salt fog at T=+35� C.
The concentration and flow
rate of the fog should pro-
vide for a salt precipitation
of no more than 50,000 mgm/m2
per 24 hr.
Subgroup VI
a = 10--20 -
- Storage
T=+175� C; duration of
1,000 hr.
- No-fa~.Iure operating
T=+125� C; duration of
time
1,000 hr. Nominal electrical
-
mode.
Subgroup VII
,
a = 10--20 -
~ No-failure operating
T=+125� C; duration of
time
1,000 hr. Nominal electrical
mode.
As follows fram Table 12, the various kinds of climatic and mechanical tests are
- combined into individual subgroups. The products are subjected to these tests in
a definite sequence. In accordance with the selected plan for selective monitor-
~ ing,'corresponding to each subgroup of tested samples is its own acceptance num-
ber, which expresses the permissible number of failures or the specified failure
_ rate. The re-.lts of tests are considered satisfactory if the number of inte-
- grateri circuits (IC's) which failed during these tests does not exceed the
established norms.
Production monitoring of the established reliability level is accomplished by
me~ans of tests far failure free operation, while the estimate of the attained
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reliability level during the average service
the IC's for operating longevity. Tests for
TM problem of determining the probability of no,
rate during the specified continuous testing
possible to determine the reliability of the
the guaranteed service life,
life is found by means of testing
failure free operation solve the
-failure operation or the failure
time. Longevity tests make it
tested circuits over the course of
The volume of the tests is determined 4.n strict accordance with the purpose of
the tests. If the issue is the performance of production checks of the reliabi-
lity of the output product for the purpose of determining production stability,
then in selecting the sample size and the testing duration, one should proceed
primarily from considerations of the maximum assurance of operational timeliness
of the quality control and economic substantiation of the selected testing plan.
The main factor in the determination of the reliability estimate is assuring the
requisite confidence level of the results.
The must acceptable plan in all respects for ongoing reliability monitoring is
a monitaring plan based on two specified reliability levels [92,96].
Such a plan is based on monitoring the constancy of a minimum reliability level,
Pmin, taking into account the acceptable level, Pnp [paccl, Which is agreed upon
by the manufacturer and the customer and provides for observing the interests
_ of both parties. Selective quality control pluns based on two leve].s have been
described in detail in the literature [96-94]. Because of their advantages, they
find widespread applications in many sectors of industry.
!D
~
1~ 0,8
~ 0,7
a
~ 0,6
~ o,s
Oa
~
a 0,?
~
Zj 0, I
0
-
-
-
-
~
I
I
I

I
I
i
I
I
~
I
1
i
O,f 0.1 93 0,5 1 7 3 4 5 10 10 JO ,f0 .10'S4
r
p"Pn PnOl Plor PlOj p~GS PnuNO.s
( 2~ NHmeHCUBNCCme anKajoO npu cpedNeN ypoDNe NuOemHOCmu
Figure 22. Family of operational characteristic curves for
a selective monitoring plan with two levels of
reliability.
K.ey: 1. Probability of batch acceptance
2. Failure rate at the average reliability level.
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The essence of selective quality control with respect to two levels consists in
the following. Working from the proposed or attained reliability level, which
is taken as the acceptable level Pacc, a minimum reliability levei Pmin for the
case of a specified value of manufacturer's risk a, where the constancy of Pmin
is monitored during the testing process for the case of a specified consumer risk
S. The requisite sample size, n, and the acceptance numbers, c, are determined
on the basis of the established levels. For small acceptance numbers (c = 1--3),
the difference in the values of Pacc and Pmin fluctuates from 6 to 13. Production
monitoring at a level of 6 to 13 times lower than the attained level makes it
possible for the manufacturer to test a small number of devices in a short time,
something which makes these tests economically advantageous. The interests of
the consumer are covered in this case (with a risk of S of receiving poor quality
products) with a confidence that in (F) 1 - ~ cases, the received products will
have a reliability above Pmin at least as much as is required so that the manu-
facturer's risk a(the risk of rejecting a good product) does not exceed the
established level. Thus, the constancy of Pmin will be evidence of the mainte-
nance of the reliability of the output product at the requisite level. The
family of operational characteristic curves for the selective quality control
plan based on two levels is shown in Figure 22, which clearly reflect the proba-
bility of accepting (or rejecting) products as a function of their reliability.
The use of supplemental samples is permitted during the quality control process,
the size of which is governed by the difference between the sample corresponding
to the main plan, and the sample in accordance with the equivalent plan. In
this case, the total number of failures during device testing should not exceed
the acceptance number for the main plan.
The manufacturer, in basing his work on definite production process margins, is
himself correct in choosing a more stringent plan than the plan specified by
the consumer, and implementing quality control at a higher level of reliability.
If the actual reliaUility level proves in fact to be the one for which the tests
are passed successfully, their results will be just as objective as the positive
results of tests in accordance with the main plan, while the cost will be lower.
Equivalent plans make it possible where production is well set up to successfully
implement quality control with smaller samples and improve the economic indicators
of production.
When checking and evaluating the reliability of such difficult to monitor products
as integrated circuits, failure analysis is of critical importance. Production
reliability monitoring of current products and the apriori estimation of the
reliability level can be based on the failure distribution for various circuit
tests. In particular, this applies to climatic and mechanical tests which in and
of themselves do not allow for the quantitative estimation of product reliability.
The failure distributions with respect to the kinds of failures and types of tests
obtained in the testing process are compared with the corresponding distributions
of previously tested batches, the reliability of which was acknowledged as satis-
factory. If the distributions match, it can be assumed that the quality, and
consequently also the reliability of the given batch is no worse than for the
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products tested earlier. A significant divergence between the obtained distri-
bution and that adopted as the reference standard can be evidence of the appear-
ance of a new failure source and mechanism. In this case, the given batch of
circuits is carefully analyzed and the source of the failure is determined and
eliminated.
The utilization of this method for production monitoring and apriori estimation
of IC reliability is possible only with an established technology for their
fabrication. It is j-mportant in this case to know what level of circuit relia-
bility is provided by the given technology and to strive to assure that it is
constantly observed during the circuit manufacturing process.
Reliability Estimation. Integrated circuit reliability is estimated under pro-
duction conditions in accordance with the documentation which is in force by
means of testing the circuits for longevity, taking into account the results of
_ operating equipment using the integrated circuits. The plan for conducting the
~
n~
0
ti
8
~
a~
,
,
~
r~
.
ar~ '
1
70 ~
o
~
Y
i
Y
60
T1
V
4
Di
c
~
w
1
'
A
V
V
,
V
~U
f
/I
~
u ~ 7 ,t 4 D o i o' Y !U 1/ IZ 13 f4 15.
(2) !te~u�,,N duHepumrneNne rpnNUqo KanuvecmGo omKO~sO, dCp
Figure 23. Curves for estimating the reliability of products
_ with various confidence levels of the estimate.
- Key: 1. Confidence level, p;
_ 2. Upper confidence limit of the number of failures,
ACg.
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longevity tests is set up by working from the formulated task: confirm the anti-
cipated reliability level or determine the actual reliability over the course of
a specified service life. When determining sample size, one works from the
requisite confidence level with which results must be obtained. Curves are
plotted in Figure 23 which show how the test results (the upper boundary of
the confidence interval) depend on the confidence level. By using this graph,
one can determine the requisite sample size by means of formulas (8)--(10) or
the relevant tables given in the literature [96--98].
The quantitative reliability indicators are calculated assuming an exponential
distribution of the failures, using the well known formulas:
(8)
nt
a, {t) =
;
(9)
nt
'
(10)
nt
P (t) ~ 1 - xt,
(11)
where aon is the test value of the failure rate, hr-1;
ag and ag are the upper and lower confidence interval limits respectively
for the values of the failure rate with a confidence level of
P*, hr-1;
c is the number of units which failed over a time t, :items;
AcB and AcH a.re the reduced values of the number of units which failed over
the time t, corresponding to the upper and lower bounds of the
confidence interval;
n is the number of units good at the start of the time interval under
consideration, items;
t is the time interval being analyzed, hr.
The data of Table 13 can be used to determine AcB and Acg where P* = 0.9.
An important role in estimating IC reliability is assigned to the information
obtained in the course of operating radioelectronic equipment designed around
the IC's. The special role of operational data when figuring IC reliability is
determined by two major principles: first of all, by the fact that it is spe-
cifically these reliability indicators which are required for practical utiliza-
tion in calculations of the reliability of radioelectronic equipment being
designed; and secondly, by the difficulties in estimating the attained high
reliability by means of tests by the manufacturer.
One of the ways of overcoming these difficulties is usir_e all of ttzP information
acquired over the time interval preceding the point in time of the estimate.
Utilizing operational reliability data, as well as the results of longevity and
no-failure service tests, production process tests and the results of studying
IC reliability using special programs makes it possible to increase the confi-
dence level of the estimate of the attained reliability level.
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TABLE 13.
(1) (2)
(1)
FOJINV!'
CTOO OTKS'
OAxoeTo-
~R,
AsycrOQOwmt
3 rRrep~aa

ar~-
Oe~w-
DosaaA
llsycropoexxA
(3) ex~rep~ae
?lDNYJ[
ol'paa4oB
NHT! ~A
w
s�..
s
s~~,
11~ID~
06pas-
M~~
e",
e cA. I
e co.
. WT.
l~
\T.
2/

~S.
40/ C.
WT.

mT.
IIIT.
[f1T.
0
2,30
0,00
3,00
6
10.53
2,61 11,84
1
3.89
0.05
4.74
7
11.74
3,29 13.15
2
5,32
0,35
6,30
8
17.99
3,98 14,43
3
6,68
0,82
7.75
9
14,21
4,70 15,71
4
7,99
1 ,37
9,15
10
15,40
5,43 16,96
5
9.27
1,97
10,51
i
Key: 1. Number of failed units, c, items;
2. One-way interval, Acg [upper], items;
3. Two-way interval.
The following expression is used when calculating the quantitative reliability
indicators based on several tests of batches:
rn
Cl
m (12)
~ rttj
where ci, ni and ti are the number of units which have failed, the number of
units good at the start of the tests and the testing time
for the i-th sample respectively.
The mean statistical value of the failure rate in the case of an exponential
distribution can be determined from the formula:
- -2,3 1 g pM -
~cr=-` t ~ (13)
where PCT is the mean statistical value of the failure free operating probability
over the time t.
w
P (14)
Ct
L~ R!
!~1
where ni is the i-th sample;
m is the number of samples;
Poni is the test value of the probability of failure free service of the
i-th sample;
Pon(t) = 1 - (c/n) (15)
pou (t) = i - n �
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when PCT > 0.9,
I= 1- Pn
(16)
The results of non-failure operating tests performed within the framework of the
production quality control fo r output product reliability are used to estimate
the reliability.
No-failure operation tests are performed in a forced electrical mode at an
ambient temperature of +125� C. As follows from the graph (see Figure 7), the
failure rate at this temperature averages 13 times higher than at normal temper-
ature. Using an acceleration factor of K}, = 13, makes it possible to obtain
a value of the failure rate of no more than a= 2.2 � 10-6 hr-l. Thus, even a
small volume of no-failure op eration tests can be used to determine the achieved
level of reliability.
The objectivity of the estimate will increase in step with the generalization of
the results of the periodic monitoring of the reliability.
An analysis of the existing domestic quality control and reliability assurance
system for integrated circui ts shows that the system of documents which regulate
the requirements placed on quality, as well as the norms and methods of relia-
bility and quality control encompass to an insufficient extent the existing
capabilities for ftirther imp roving the efficiency of efforts in this area.
- However, there are still als o deficiencies in the organization of IC quality
control. A number of inethod s and standards for IC tests in accordance with
additional consumer requirements and programs which reflect specific conditions
of product applications have not as yet been standardized.
The IC quality cdntrol system which is in wide use is also inadequately effective
because it does not provide for complete utilization of the information on the
= manufacturing quality of pro ducts and reliability under operational conditions
[99]. In contemporary production, of all of the information obtained during
quality control and reliabil ity checking of integrated circuits, only that part
of it is taken into account which is essential for estimating the suitability
of the finished product and for making decisions concerning its shipment to the
customer.
This occurs primarily as a cansequence of the lack of a strict quality control
system for products during their manufacture, and in particular, because of a
_ lack of automated control sy stems which provide for data analysis, storage and
feed-out at the necessary t ime, where this information is needed to correct the
production process, as well as for test program comparison and other standard
setting engineering document ation, which regulates the methods and procedures for
production control for the purpose of assuring output products of a specified
quality. -
In the literature which has been cited, the deficiencies of the existing testing
system have been formulated as follows:
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1) The development of testing programs without considering the results of the
tests of the entire preceding aggregate of output products and the introduction
of special methods of IC quality control in individual operations based on the
results of quality monitoring; 2) the failure to use the results of operational
quality control when planning tests; 3) the failure to receive information on
time, due to primarily to the use of manual labor in the monitor operation and
when processing the test results; 4) a low confidence level for the quality
estimate in the majority of cases, which is explained by the lack in a number of
cases of scientifically substantiated standards and requirements placed on the
test modes, the precision in setting and maintaining them as well as by the
methods of carrying out the measurement operations used in this case and the
reference standard base. All of this leads to the necessity of repeated tests,
which unavoidably entail an increase in the cost of production, the product, and
an extension of the time frames for p1ac:Lng the products in production and manu-
facturing them.
Replacing the existing product rel,iability and quality control system in micro-
electronics with an automated quality control system (ASUK) is the dnly way of
eliminating the deficiencies and further improving production efficiency. In
order to justify the hopes placed in it, an automated quality control system
should be based on the creation oP the techniques and hardware for metrological,
engineering, technical, software, informational and organizational support.
One of the possible variants for an automated quality control system structure
is treated in [99], which provides for shifting the center of gravity from the
monitoring of the finished product to more careful and exhaustive operationally
timely monitoring. The author of the proposed system notes with justification
that in the early stages of integrated circuit design, quality control of the
fabrication is more effective, since there is the real possibility there of
preventing the appearance of defective products.
Along with this, tests of the f.inished product remain the only way of obtaining
the information needed for a final quality evaluation of the produced product.
For this reason, control of the tests is one of the major tasks of an integrated
circuit automated quality control system. Testin control is understood to be
the development and realization of a set of organizational, technical and scien-
tific and procedural measures, which provide for the preparation and conduct of
the tests (planning the preparation, selecting the testing plan, the test-
operations, the analysis of the results obtained and working out the corrective
actions to take in production).
6. The Classification of Tests
Integrated circuit quality is composed of a number of properties which character-
ize circuit functional capabilities (resorption time, ultimate temperature,
characteristics of the major structural components which govern the integrated
circuit parameters: base, collector and emitter currents, leakage current,
junction capacitants, dynamic resistance between the emitters, forward voltage
drop across the collector--base junction, inverse voltages across the collector--
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base and emitter--base junctions, residuaZ emitter--collector voltage, etc.), the
operational capability (heat resistance and thermal stability, moisture resis-
- tance and operating stability in the presence of moisture, co13 resistance and
operational stability in the prpsence of cold, vibrational strength and vibra-
tional stability, shock strength and operating stability under shock loads,
strength in the case of free fall_and transportation, resistance to centrifsgal
_ acceleration, etc.) as well as durability, non-failure operating life and shelf
life. The structure of integrated circuit quality is shown schematically in
Figure 24. Among these properties there are a number of properties (weight,
hermetic seal integrity, lead strength) which characterize the fabrication
quality of each integrated circuit taken individually.
As is well known, reliability is one of the major quality properties of any
product, and integrated circuits in particular. It characterizes the capability
of an IC of performing its own functions under definite conditions for a speci-
fied time. Integrated circuit reliability is conditioned by its non-failure
operating time, durability, and shelf life [100]. Non-failure operating and
durability of a microcircuit determine its capability of maintaining operabi_lity
for a specified time. This difference between these concepts consists in the
fact that the former provides for the retention of operability for a specified
time interval without interruptions in operation, whilP the second provides for
the retention of operability until completely worn out, with interruptions in
operation for technical servicing and repair. The non-failure operating pro-
bability and failure rate serve as the non-failure operating time indicators.
The durability indicators are the average service life of the integrated circuits,
the minimal mean time between failures and the gamma percentage service life.
Shelf life of an IC is the property of the IC of preserving the stipulated opera-
tional indicators during and after storage and transportation, the duration and
conditions of which are established by the engineering standard setting documen-
tation. The shelf life indicator for integrated circuits, in particular, is the
_ average storage life.
All of these properties of IC quality are specified in the technical specifica-
tions and are subject to check with a definite accuracy.
Measurements and tests are the only source for obtaining objective information
on integrated circuit quality. By simulating the environment under laboratory
conditions, the IC's being studied are exposed for a definite time to various
operational loads and in this way, a rather precise idea (close to the actual
value) is obtained concerning the resistance, strength and immunity of integrated
circuits to these factors, the extent of the influence of the load on the
structure of products and the capability of a unit being tested of standing up
to the destructive effect of the ambient temperature, vibration, radiation, dust,
humidity, pressure, etc.
The engineering standard setting documentation provides for the performance of
the following kinds of tests when checking the quality and reliability of IC's:
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Strength of Leads
Heat Resistance
~ 1 ~
Ba~xodNCe
Nanp~~eMUe
'
OpvvMame
100100
Ten~ocmorlKa~cn~a
nor. , O
(2)
Bs�oaNae
NonpqMreNUe
'
(14
fepnemuvNOCmb
7lqqOs/Cl7JOOdWOACIII~
(15)
qOI�� 1
(3)
eroaNOv moK
i p0'
ei
~
~o=~cmod~rn~r
(16)
no
,
W
ht
g
~4~
BxoDn~ moK
'
,
&iotoycml&dAauns
(17)
nct.. f
(5)
/fOn)pl6/I/MUl1
XOna~OCmO~IfOC/Ab
(18)
(6)
ncmpeOneN~~
XGJO/byC/A~(Itl~L1R1
~ 19 ~
I'noRQ
(7)
BpeN~
sogepxrKu
BuOponpoaNOtms
(2-0).
t �,os.
~oyecmBo
(8)
B rN~
QUAL ITY
BuOpoyemaluu0acmi (21)
t ~
(9)
IYOJ~!/f/f/~Mll7
ycu~
u4
dIDOpN011
22)
~
~
cmo~iKarmn
(10 )
NvnoAMreNUe
cN N~ as
ySapNap
ycmo0vu0xm1'
(23)
(27)
PasNOeme
OXODNbIX M0/f 00 '
' 6l301N(0JN0L'Ilib
/lpo+~wa~r
npu mpnNCnopmupo- (24)
ars;.
eowa
(12)
Be~xodNOe

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Figure 24.
Typical block
diagram of the quality
properties of
a semi-
conductor integrated circuit.
Key: 1.
Logic "0" output voltage;
- 2.
Logic "1" output voltage;
3.
Input current
for a logic "0";
4.
Input current
for a logic "1";
5.
Current consumption, I�cons;
- 6.
Current consumption, I'cons;
-75-
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7. Delay time, toldel.;
8. Delay time, tlOdel.;
9. Gain, Ky ;
10. Bias voltage, HOM;
11. Difference in the input currents, AIin;
12. Output voltage, U+out;
13. Output voltage, U-out;
14. Hermetic seal integrity;
15. Thermal stability;
16. Moisture resistance;
17. Operational stability in the presence of moisture;
18. Cold resistance;
19. Operational stability in the presence of cold;
20. Vibration strength;
21. Operational stability in the presence of vibration;
22. Impact strength;
23. Operational stability in the case of shock loading;
24. Strength during transporting;
25. Strength in the case of a fall;
26. Resistance to centrifugal loading;
27. Non-failure operating time;
28. Shelf life;
29. Durability.
1) Mechanical tests to detect resonant frequencies, vibrational strength, stabi-
lity under vibrational loads, impact strength when exposed to one-time and repeat-
ed shocks, resistance to single shocks, strength when exposed to centrifugal
accelerations, lead strength (tensile strength, bending strength, bending
fatigue strength) and the strength of the internal connections;
2) Climatic tests for heat resistance and thermal stability, cold resistance and
operating stability in the presence of cold, storage life at an elevated temper-
ature, resistance to a cyclical temperature variation, resistance to heat shock,
moisture resistance and operational stability in the presence of moisture, sta-
bility at reduced atmospheric pressure, operating stability and resistance to
the effect of environmental factors at the due point and exposure to hoar frost;
3) Acoustical tests for resistance to sound pressure (to a single noise);
4) Biological tests for resistance to the development af mold and fungi;
5) Electrical tests for insulation resistance, non-failure operating time, dura-
bility and service life;
6) Chemical tests for explosion hazard, suitabiliLy for soldering, resistance to
corrosion when exposed to a corrosive medium;
7) Hydrolic and pneumatic tests for the effect of an elevated air pressure, the
effect of barometric shock and the hermetic seal integrity;
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8) Flammability tests.
The classification citec: here was compiled taking into account the requirements of
[101]. However, one must point out the fact that the cited standard does not
fully reflect worldwide experience and the industrial sector standard setting
engineering documents. In turn, the latter do not conform to the requirements
of the given standard. For this reason, the authors considered it possible to
employ the classification which wag acceptable at the same time both for the
presentation of the given material and on the whole for the problems of testing
devices, equipment and components. It is impossible to justify the presence of
two individual, {.,dependently sxisting classifications for teszs: tests of
_ devic.es and equipment, and tests of electronic hardware products.
We shall consider the specific features of the classification which is discussed
in the book.
It is d3.fficult to imagine a classification which would not provide for a grada-
tion of the tests, depending on the step in the manufacture of the product. Such
differentiation exists in principle in [101], but in a very veiled form and is
in need of being made more precise. In accordance with this staadard, there
exist research and operationa]. teqts. The first are performed primarily in the
stage of working out the draft plan of the product, while the second, as follows
from the name, are performed during the operation of the finished product. In
practice, these are most frequently the operation of the product for testing or
physical unit tests. However, tests performed during the production stage are
lacking in the tabl.e of the standard as an independent category, something which
is responsible for the lack of clarity and the incomplete nature of the testing
classif ication with respect to this first and most important criterion. Techno-
logical production process tests are lacking among the production tests cited
in the standard which are performed during the product fabrication stage. This
kind of testing is especially important for industrial sectors which produce
electronic equipment products. To be included in the group of production process
tests are all the kinds of tests which provide for the fabrication technology of
a product at various stages in the production process and which pursue the goal
of step by step checking for the formation of the specified product properties.
~ Tests which in engineering practice are called conditioning, rejection, production
process run, burn-in, artificial aging or seasoning't tests, etc., or completely
undeservingly bypassed by the standard [101]. Theseare very important kinds
of tests, which are widespread in industrial sectors producing electronic and
electrical equipment products. Burn-in or rejection tests are performed for
- the purpose of ascertaining and rejecting from the manufactured products the
defective, potentially unreliable product units. Another task of these tests is
to increase the operational stability of the conditioned products and reduce
the scatter in the values of the product parameters, in the gen-eral set of pro-
ducts, which in this case is IC's. Such tests provide for a substantial increase
in product quality while simultaneously increasing the plan income of an enter-
prise [4, 27, 1021 and cannot but occupy a necessary place among the other kinds
of tests. It can be assumed that not all quality control specialists are in
agreement in including conditioning among tests instead of including it among
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production process operations. Such a viewpoint has a right to exist and can
be discussed. We include these kinds of tests among the group of production
_ process tests, working from tne duality of their nature: on one hand, the for-
y mation of definite quality properties in a product, and on the other, the purely
checking functions performed by the test procedures using the test equipment.
Another deficiency of the standard of [101) which is especially important for
classifying the tests of devices and equipment is the lack of a criterion among
the classification criteria which characterizes the status of the unit being
tested: breadboarded unit, trial or prototype unit subjected to testing or a
series and mass produced product which is being tested.
The classification of tests within the limits of the criteria provided in [101]
is also not optimal and is in need of improvement.
ThL3, for example, by working from the definitions gi.ven in the main text of this
standard setting engineering document, all of the tests can be subdivided accord-
- ing to the purpose for which they are performed into research, check, comparison,
dei:ermination, developmental debugging, certification, service life and reliabi-
lity tests. It appears erroneous to merge research and comparison and check
and developmental tests into a single group. Research tests can be both compar-
ison and determination tests. One can also include developmental tests in the
group of research tests, since in accordance with the standard, these are "tests
performed in the process of developing a product to evaluate the impact of
changes made in it for the purpose of attaining the iequisite quality indicators."
A more precise formulation is given in the reference appendix to the standard
under discussion here. In accordance kith the classification given in the
appendix to standard [101], all of the tests are broken down according to the
purpose for which they are performed into check, research and limit tests.
However, in our opinion, this explanation too does not make the classification
finally complete. Differentiation of tests into research and check tests is
logical. The presence of limit tests in this group is not justified. According
to the definition given in the main text of the standard, limit tests are
- research tests and for this reason cannot appear together. The standard includes
a definite portion of the test types in the category of check tests. Exceptions
- are determination tests, which "can be included among check or research tests...",
as well as comparison, developmental debugging, certification, accelerated tests,
normal tests, stand or test facility tests, operational, destructive, nondestruct-
ive, service life and reliability tests. The association of these tests with
some category or group of tests by the standard [lOl] is not established and
~ their place in the classification table is not indicated.
Other positions taken by the state standard being analyzed here are also dis-
= putable. Thus, for example, the difference between comparison and evaluation
tests is presented in such an ambiguous manner that it is difficult to imagine
when one should be used in practice and when the other should be used.
No category is provided in the standard in which certification tests are to be
included.
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Approximately the same thing can be said about developmental debugging tests.
It is hardly correct to include the abbreviated tests provided in [101] among
accelerated tests. The formulation of this kind of test defines them as:
"accelerated tests without intensifying the processes which cause failur.es or
_ damage". But in Appendix 1 to the standard, it is explained that in the case
- of abbreviated tests, a reduction in the time needed to acquire the requisite
volume of information can be achieved, fo r example, based on the use of supple-
mental information obtained outside the t ests. and then the explanatior.
is given as to via which routes one can obtain this additional information, and
amon.g them are the application of extrapolation techniques, etc. This is
already a different way of obtaining information on the property of the product
being checked, which exists on an equal f ooting with a test, but is not a test.
In this case, the intermixing of three classification criteria is present:
duration, conditions for test performance (in nominal or forced modes) and the
source of the original information needed to estimate the quality of the product
being checked. "Accelerated tests can b e either forced or abbreviated," states
the standard, and it is right there admitted that so-called "abbreviated tests"
may also not be tests at all.
It appears that the differentiation of the tests according to the classification
criteria of "property being evaluated" and "poinc of performance" has not been
- thought through to the conciusion.
- According to the f irst of these criteria, tests are subdivided only into reliabi-
lity and service life tests. Essentially no place has been found in the standard
fer vibrational strength and operational stability under vibrational load, mois-
ture resistance and operational s.ta'Ality with exposure to moisture, heat resis-
tance and thermal stability tests as well as tests similar to them which are
performed for a similar purpose.
According to the second classification c.riterion, tests are broken down into
~ operational and test stand types. Again no place is found in the classification
table for laboratory tests which the des igner or the manufacturer of the product
perfarms on test stand equipment.
- The standar3 considered here [101] is no t tne only document which regulates the
classification of tests and the terminology in this field. In addition to this
standard, similar problem.s are also solved in [100, 103-1051, However, the pre-
sence of these additional documents does not bring any order to the problem under
discussion. Thus, tor example, in contradiction to standard [101], according to
standard [104], hydrostatic, biological and radiation tests are included in the
~ group of climar_ic tests, while acoustic tests are numbered in the group of
mechanical tFsts. While according to (101] quality control tests are tssts of a
unit periormed to :nonitor its quality, according to [105], these are tests of �
units rrom a set-up series and series produced products.
Acceptance tests, according to sta:zdard [101] are "quality control tests of
pr.otetype unirs (batches) of a product, as well as products f rom a single pro-
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ductioiz run, which are performed to resolve the question of the expediency of
placing this product in production or turning it over for operation respectively."
However, according to standard [105], acceptance tests are tests of prototypes
of new types of products, intended for series production, as well as imported
_ products." The fact that in the example considered here the issue involved
different prQducts caanot justify the differing formulations of the same concepts,
since the kind of products being tested is of no importance for the classification
af the tests.
- Even a unified terminology has not been worked out at the present time. Def ini-
- tions of strength and resistance are encountered at each step which are used to
deFine the capab!.lity of a product of standing up to the destructive effect of
a definite load and to maintain operability and external form after exposure to
this load. In contrast to the concept of "stability", which is used to charac-
- terize the capability of a product of retaining operability when exposed to th is
load, the term "strength" means the retention of operabil.ity by a product as a
consequence of this exposure [sic].
Without doubting the obvious nature and expedience of using the term "stability",
' we shall put forward our own poir.t of view concerning the terminology for des-
- cribing the capability of a tested unit of retaining its qualities following
exposure to operational factors. In our opinion, no effort should be made to
substitute the word "resistance" for ttie term "strength" or vice versa.
It is convenient to use both of these terms in practical work.
Each of them under certain conditions is more suited to the description of a
particular physical process. Foz example, when the issue is one of the capab i-
lity of an IC of standing up to exposure to a corrosive gaseous medium (for
_ example, a salt atmosphere), one does not want to talk about the "strength
of an IC with respect to a sea fog", but it suggests itself to say rather "immun-
ity to a fog". The same thing must be said ah,)ut other tests. The
operational stability of a product in the presence of moisture sounds better than
saying its moisture strength.. In the case of describing the capability of a
- product during exposure to mechanical loads, it is equally correct, in our view;
to say both vibrational strength and vibration immunity (in contrast te vibra-
tion stability). However, for the purpose of bringing order to the terminology
and the rules for utilizing it, it is probably nonetheless necessary to make a
choice of one of the terms. Taking into account what has been said here, the
following system is proposed: to describe the mechanical strength of products,
use the term "strength" (vibrational strength, impact strength or shock strength,
strength in the case of a fall, tensile (or compression) strength, strength in
the case of a centrifugal load, c:tc.). However, the capability of products of
- preserving their qualities and conforming to the requirements of standard
setting engineering documentation following exposure to climatic, biological and

chemical factors is characterized by the definitions: moisture immunity",
"corrosion immunity", "fungal immunity", "immunity (but n( ` "strength") to
cyclical temperature changes", "thermal immunity" (but not "thermal strength"),
etc.
_ -80-
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A few words are in order concerning terminology in area of testing, in which the
main kind of exposure is to gas or liquid pressure. The standard [101] does not
- reflect the physical nature of the phenomenon and does not differentiate between
atmospheric pressure and artificially produced pressure. While the first serves
as a load when studying the capability of a product of operating under natural
conditions, the second is a direct consequence of human activity. For this
reason, it is corXect to include stabilir.y testing at reduced atmospheric pres-
sure among the group of climatic tests, since testing for exposure to elevated
- gas or liquid pressure is numbered among hydrolic and pneumatic tests.
Thus, test classification ac::ording to the attribute of the "kind of acting
factor", employed in the given monograph, appears as shown in Table 14.
In this table, the authors present their own variant of test classification
based on other attributes as well. We shall not comment on the classification
table in detail because of a lack of space here. We shall only underscore the
fact once again that it takes into account the deficiencies of the standard [101]
as well as operatiunal experience in the microelectronics sector of industry.
_ Research Tests. According to the classification of tests which is given in
state standard [lOl], tests performed in the interests of studying definite
properties of a unit are called research tests. A representative of this class
of tests is limit tests. The standard definitic+n of limit tests reads: "limit
tests are research tests performed to determine the relationships between the
ultimately permissibie values of parameters for a product and the values of the
operational mode parameters."
Tests of this kind are employed for the purpose of ascertaining the range of
stable and reliable operation of a product, determining the correlation function
= of the parameters, establishing the listing of parameters to be checked and the
standards for them, working out methods of evaluating and predicting integrated
circuit reliability, as well as establishing the requirements placed on redun-
dancy of IC components and requirements placed on the measurement and test
facilities used in working with a given type of integrated circuit.
These tests make it possible to estimate the strength and stability margins of
integrated circuits exposed to various factors, and to determine the distribution
of product failure according to kinds and degree of severity of the acting fac-
tors.
Included among limit tests are thermal shock tests, thermal cycling, one-time
large force shocks, centrifugal loading, resonant frequency tests as well as
high temperature storage.
The methods for performing these tests are selected by working from the posed
problem and the design and production process features of the tested unit. Gene-
ral rules for the performance of limit tests provide for the following:
--The performance of the tests right up to the destruction of large parts Df the
samples;
- 81 -
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as a function of the load (b) and the number of
units which pass the test as a function of the
load level (c).
Key: 1. Load level;
2. Time or the number of load "steps";
3. Number of units which pass the tests, percent
Figure 25. The change in the load (a), failure distribution
--Gradual increase in the load;
--The choice of the kind and si2e of the load so that it is not accompanied by
the appearance of new failure mechanisms which are not inherent in the given
type of integrated circuit during operation.
The technique of a gradual stepped increase in the load has been recognized as
the most expedient and is universal.ly used (Figure 25). A typical curve for the
rise in failures during accelerated durability tests, performed using a stepped
load, is shown in Figure 26. Thus, the test method treated here is based on
a gradual failure of units (in step with the increasing load) which have differ-
ent defects, and which under operational conditions could appear in the course
of an extremely long operating time. _
E~
~
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70
50 229,00-C
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crease in the uumber of
failures during accelerated
tests of durability (step-
wise increase in the temper-
ature).
Key: 1.Number of failures,
- 84 -
� f0c 1i tDts
10 t
f0 ~ 100 10.7 C
Figure 27. Graph of the change in the
value of the failure accel-
eration factor as a func-
tion of temperature and
voltage.
Key: 1. Acceleration factor.
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Usually, one kind of load or another is employed. But there are cases of the
simultaneous use of sevaral loads of a different nature.
Combined exposure to two different loads makes it possible to amplify the effect
and reduced the duration of the tests even more. The growth in the acceleration
factor with an increase in the electrical and thermal loads applied to the pro-
duct at the same time is shown in the graph of Figure 27. The resulting function
reflects the results of tests of planar transistors in the reliability improve-
ment program for the Plinuteman project. The curves in the graph for temperatures
above 200� C were plotted on the basis of extrapolating the experimental data
of paper [4].
We shall consider the methods of performing specif ic kinds of tests.
The technique of limit testing using thermal shock (heat shock) is the same as
with conventional testing. The difference is in the number of cycles. In the
case of the limit variant, the number of cycles has no standards set for it.and
depends on the established criterion for evaluating the test results. The test
is conventionally terminated when SO percent of the IC's supplied for the test
fail or when the integrated circuit immunity is confirmed with the reaching of
the final stage of the test exposure. The number of thermal shocks is figured
in tens of shocks. The ultimate values of the temperature and the periodicity
of parameter measurement are indicated in the engineering standard setting docu-
mentation.
-I Testing by thermal cycling is accomplished by increasing the load in each sub-
~ sequent step. The ultimate and intermediate values of the temperature are spe-
cified in the engireering standard setting documentation. The initial and final
~ loads are selected by working from a consideration of the specific requirements
~ placed on the structural design of the integrated circuits and their fabrication
; technology. Wnen performing succeeding tests on integrated circuits of the
same structural and production process design, the same stages zre provided as in
the preceding case, however, rhe initial step is chosen two steps below that
i
one at which failures occurred during prece ing tests.
- Integrated circuit testing, which pursues the goal of determining the strength
' margin and the immunity to exposure to tempera*..ures, is performed by increasing
the temperature in steps. The duration of tY:e exposure in each step is figured
in hours.
The strength and stability margins of integrated circuits in the case of simul-
taneous exposure to the ultimate ambient temperature and electrical load are
evaluated by means of a stepwise increase in the electrical load at a constant
- ambient temperature.
The load is increased from the nominal to the ultimate value. The duration of
rhe exposure of the integrated circuits in each step is governed by their
function and the structural design and production process features, and is
indicated in the testing documentation.
3
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In the case of tests at a constant electrical load, a value of 0.8 to 0.9 of that
- ultimate load which is obtained when testing with a variable load is chosen as
that load.
Mechanical shock and centrifuging tests are performed by sequentially increasing
the load in steps, which are specified in the engineering standard setting
documentation. In this case, the products being tested are arranged so thst
- their exposures are realized in directions which are the most hazardous for them.
Production Process Tests. Production process tests serve to check the fabrica-
tion quality of products at various stages in the production process and reject
substandard products.
This very important kind of testi.ng is not reflected in the standard of [101],
has been undeservedly forgotten and not taken into account in the classification
of the kinds of tests.
The significance of production process testing is extraordinarily great in all
stages of integrated circuit fabrication. Input quality control of the raw
materials, semi-finished products and complete product sets establishes the basis
for a high quality product. Effective operational monitoring provides fcr the
execution of all production processes in strict conformity to the standard setting
engineering documentation and thereby, the observance of all the requirements
placed on production. The final total of the operational quality control serves
to prevent rejections when fabricating ZC's and the discarding of parts or pro-
ducts fabricated with a deviation from the drawings or technology. The produc-
tion process tests performed in tne final operations make it possible to "clean"
the batches of products manufactured with poor quality and assure the specified
- level of product quality. The more efficient the production process testint;,
the lesser the role of the output acceptance quality control.
- The tests performed within the framework of input quality control of materials,
- semi-finished products, etc., are carried out in ac,:ordance with programs com-
posed based on the technical specifications for their delivery.
All those tests whicli play a part in the technology in each operation and provide
for checking the conformity of the product of a given operation to the require-
ments which are established are included among the production process tests
performed in the process of fabricating the integrsted circuits. Not just the
indicated problem is solved by means of these tests. The scatter in the values
of the major parameters of the IC's in the general set are reduced by means of
them, the electrical characteristics are stabilized, by e].iminating the causes
of parameter drift with time, and what is the most important thing, the tests
provide for sorting of the finished devices into groups as a function of their
reliability.
Without going in detail into all of the tests included in operational quality
control, we shall treat the latter in somewhat more detail, which we shall call
quality control sorting.
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Sorting tests, as the name itself says, pursues the goal of quality control sort-
ing of all products into groups, depending on their quality. The necessity of
these tests is due not only to economic considerations: the striving to extract
the maximum income and make production profitable. An important factor which
governs the expediency of incorporating sorting tests is the eternal lag of the
production level of product manufacture behind consumer requirements. This
especially concerns requirements placed on IC reliability. Here as nowhere else
are the contradictions clearly manifest between the desire of the customer and
the capabilities of production. The requirements on IC reliability and durabi-
lity run ahead of the ability to achieve them, and even more to realize the
requirements placed on the production process equipment, test facilities, metho3s
and equipment for metrological s�spport of IC production and checking IC quality,
reliability and durahility.
These tests are treated in detail in Chapter Five. For this reason, we shall
limit ourselves here to a discussion of some procedural questions.
Rejection sorting test programs differ substantially from one another. The
typical programs for such tests provided in U.S. military standard for semicon-
ductor IC's MIL-STD-833 are presented in Table 15. They contain test operations
and measures to artificially age the products, where these steps are called
upon to ascertain defective and instable devices and to influence the remainder
so that the causes of parameter drift are eliminated. Included among such meas-
ures are heat treatment of the IC's, which, as a rule, is carried out prior to
, sealing them and thermoelectric conditioning, which precedes the direct rejection
; sorting of the devices with respect to electrical parameters and specified
i reliability criteria.
Various deviations from the standard program are possible in different cases.
The composition of the quality control, test and conditioning operations, their
sequence, conditions and operating modes vary as a function of the purpose of
the IC's, their structural design and production process features as well as
the requirements placed on quality and reliability.
In all cases, the resolution of procedural questions of test conduct is governed
by the following main principles:
--The choice of test types, methods and conditions should be based on knowledge
of the physical essence of integrated circuit failures with exposure to various
actions during their testing and operation, as well as on knowledge of their
structural design and production process features;
--The test methods should accelerate the development of typical defects inherent
in this IC design and given production process, but should not cause the
appeararice of new failure mechanisms not inherent in the given type of IC
design and technology;
--The sequence for the performance of the tests s:zould be chosen so that tests
are performed first which provide for the greattist rejection of substandard
products, and should contain the kinds of tests which make it possible to re-
ject potentially unreliable integrated circuits.
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TABLE 15. Program of Rejection Tests in Accordance with Method 5004 of
MIL-STD-883
Kind of Test
Visual inspection
Artificial aging (stabi-
lizing heat treatment)
Thermal shock
Thermal cycling
Mechanical shock
Centrifuging
Check of the hermetic
seal
Electricai. tests
Thermoelectric condition-
ing
Check of the electrical
parameters
X-ray flaw detection
Visual inspection
Integrated Circuit Reliability Class
A B C
Condition A Condition B Condition C
24 Ynours 24 hours 24 hours
15 cycles 15 cycles or 15 cycles or
10 cycles 10 cycles 10 cycles
20,000 g none none
30,000 g 30,000 g 20,000 g
yes yes yes
yes no no
168 + 72 hr 168 hr
yes yes yes
yes no no
Ses yes yes
The effectiveness of quality control sortin tests is govern by the correctness of
the choice of rejection criteria, the quality of the output product as well as
the requirements placed on its reliability and the listing and conditions of the
tests being performed.
It is not difficult to convince oneself of what has been said by glancing at
Table 16, where figures are given which characterize the efficiency of rejection
tests of IC's as a function of quality. As can be seen, the difference between
the, failure rate for various groups of integrated circuits reaches several orders
of magnitude [32].
The governing factor when making a decision concerning the implementation of a
particular program of rejection tests for the integrated circuits which are being
produced is the economic factor. Tables 17 and 18, which were taken from the
literature [23, 32], are convincing evidence in favor of this argument and show
how great the losses can be if timely steps are not taken to reject units which
do not meet definite requirements. The ltvn-ls of reliability regulated by U.S.
military srandard MIL-STD-883 are presentee, in Table 17. The values of the IC
failure rate, which represent the requirements of various usersy are the require-
ments of three companies using the integrated circuits, reported to national
symposia on reliability. The ARINC model is nothing more thdn the reliability
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TABLE 16. The Effectiveness of Rejection Sorting iests (Average F'ailure Rate
per 1,000 hr, _
B . .4)(blKT11lHOtTb NCqYMNYA. X
Kaaecrso naprn
(AP.M."Po 04XMSi `
-
o
I eo I
~ I
u .
l
5
10
O,OZ
O~l
0,2
Q.004
0,02
0,04
0,002
0101
0,02
0.0002
0.001
0,002
Key: A. Quality of the batch (fraction of defective integrated
circuits in percent);
B. Test effectiveness, percent.
TABLE 17. Requirements Placed on Integrated Circuit Reliability as a Function
of the Level of Complexity of Equipment Repair
HCT09NYr
Source
(A ) Hxrerersaorrr 0na305 aa 1000 q. -
B Aaa4.oewye rtpr6u9w (D)
C PlMONT OCy0lK7'~xE~'~ KaY119lCKsA
CT~WQT` tlXNYKa: QlMOIIT
NY! EDlEO� ' Nls03YO7KlN NJIs
w Easily ( With O4lHb noPor
aerxo TpyAxo
tandard
n{ ffa ~�1 t
(E) Oapua TI
iloTpe6x-
(F)renb A
florpe6x�
(G)renb B
Ilorpe6H-
(H)reah C
Mo.iaTb
(I)1RWC '
0 ,02-4 .d4
0.1
0.06
0,03
(J) OTNPC
i
~ 0,01-0,02
0,004-0,008
0,002--0.006
0,03
0,003
-
0,045
0,006
0.003

0 , 0038
-
0,02
0,006
0.002
NTe.9blM9 CT011MOCTb (HHIEKC CTONMOCTII) _
1,3 1 1.8 1 2.8
Key: A. Failure rate per 1,000 hr in
B. Aviation devices;
C. The repair is accoraplishe3:;
D. Space equipment: repair impossible or very expensive;
E. Texas Instruments Company;
F. User A;
G. User B;
H. User C
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Key [cont.]: I. ARINC model;
J. Relative cost (cost index).
- standard computed from [106] which makes it possible to determine the indicator
of product reliability improvement as a function of the kinds of rejection tests
employed, the operational conditions and the pos4tion of the estimated value on
the a= f(t) curve. The cost index is defined on the basis of the price of
100 TTL circuits with a low level of integration, sealed in C-DIP packages.
TABLE 18. The Cost of Class B Rejection Tests in Accordance with MIL-STD-883
Cost,
Dollars _
Kind of Test
Minimal
Average
Maximal
Visual inspection (condition B)
0.15
0.25
3.0
Heat treatment
0.01
0.05
0.10
Thermal cycling
0.05
0.10
0.20
Centrifuging
0.05
0.10
0.25
Check of the hermetic seal
0.05
0.10
0.20-0.25
Thermoelectric conditioning
0.25
0.50
5.00
Chack of the electrical para-
0.25
0.50
2.00
meters
Total
0.81
1.60
10.55
However, it would be inc.jrrect to evaluate only the economics. The uecision to
implement or not implement rejection tests should be made on the basis of the
results of analyzing a set of questions, among which the main ones are the
initial requirements placed on device quality, the permissible and justified
degr,;e of integrated circuit rejection at the level of modules and systems, the
requirement placed on reliability and the degree of reproducibi]_ity of IC appli-
cation conditions by E:.sndard programs.
Ttie conditioning of integrated circuits, just as heat treatment, used for artifi-
cially accelerating the aging of IC's, is more of a production process operation
than a test. In problems khich are solved, for example, in the thermal and
electrical conditioning of products, the functions of production process and
quality control operations are interwoven, if a technological operation in this
case is understood to be an operation called upon to generate definite quality
properties in the pLoduct. It is not obligatory in all cases for all of the
output products, but is used only when the issue is one of obtaining highly
reliable proaucts. The purpase of this operation can be formulated as follows:
stabilization of product parameters, reducir_g the amount of drift in the major
_ parameters of integrated circuits exposed to the applied load as well as the
scatter in their parameters and the rejection of units which do not meet the
_ set requirements.
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The kind of conditioning is chosen by working from the definition we have given
for it. As applied to electronics products, conditioning is the operation of
the products in an electrical mode under def inite environmental conditions.
5pecific featur:s of semiconductor devices also do not preclude conditioning
products in a de-energized state, but in an environment at an elevated.temper-
ature. For the sake of comparison we shall say: the conditioning of a bearing,
crank mechanism or assemblies and products from machine building similar to
them also consists in operating them, but the mechanica] operation.
The aging conditions and modes are specified by working from the specific set
task, the state of the product, its proposed quality and the requirements placed
on the level of reliability. With the exception of individual cases, when one
knowingly incurs any material expenses, the rule is the designation of aging con-
ditions such that the cost of the conditioned integrated circuits does not exceed
the cost of losses which can be incurred by integrated circuit failure during
operation.
Quality Control Tests. Electrical Tests. In accordance with the standard of
[101], electrical tests are those in which the main kind of exposure is to elec-
trical loads.
Testing integrated circuits for non-failure operating time pursues the goal of
evaluating their stability during and immunity tc, longterm exposure to an elec-
- trical load and an elevated temperature.
The tests are performed in a special chamber equipped so that is possible to
place a considerable number of products under test in it at the same time and
to create and maintain a temperature mode within a set precision for a long
period of time while simultaneously applying an electrical load to all of the
integrated circuits and monitoring the IC parameters without removing them from
the chamber.
For the purpose of creating the worst case conditions for the products being
tested, they are tested at the maximum permissible load in a static or dynamic
mode.
In the static mode, either a reverse bias or forward bias voltage is fed to the
IC's being tested. In this case, the integrated circuits operate at the ultimate
permissible power dissipation.
The dynamic test mode is realized in one of the following variants: a parallel or
series excitation circuit, or a ring oscillator circuit configuration.
In the first of these cases, the requisite supply voltages and the corresponding
input signals are fed to the IC's under test, while the maximum load is con-
nected to the integrated circuit outputs.
In the case of series excitation, the integrated circuits are connected in series:
the output of the preceding one is connected to the input of the following one.
The supply voltage is fed in, while an input signal is fed from an external
generator to the input of the first IC in this circuit configuration.
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Tests using a ring oscillator configuration differ from those treated abave in
that the requisite supply voltages fed to the products being tested, while the
IC's are connected in series so that the output of the last one is connected to
the input to the first.
Logic IC's are tested by any of the methods described here. As far as linear
integrated circuits are concerned, they are tested using both variants in a
- static mode, while in a dynamic mode, they are tested only in a parallel excita-
tion configuration.
The test procedure provides for placing the IC's in the test installation,
checking the electrical parameters under normal climatic conditions, elevating
the temperature in the working volume of the chamber up to the value correspond-
ing to that indicated in the standard setting engineering documentation, and
supplying the specified electrical conditions for the IC's.
During the testing process, the electrical parameters are monitored at definite
time intervals. The list of parameters, the periodicity, as well as the tech-
niques and equipment for the monitoring are indicated in the standard setting
engineering documentation.
The tested integrated circuits, after being kept at normal conditions, are sub-
jected to a final check: the external appearance and overall state are assessed
visually, the parameters are measured and they are compared with the initial
values. Those IC's are considered to have passed the test, the external appear-
ance of which and the electrical parameters during and after the tests conform
to the standa:.ds established by the standard setting engineering documentation.
Durability tests are performed for the purpose of confirming the specified
value of the minimal time before failure and the gamma percentage service life
established in the standard setting engineering documents.
The tests are carried out under normal climatic conditions over a period oF time
no less than the minimum duration of the non-failure operating time. The elec-
trical load is maximal. The circuit configuration is one of those treated above.
The periodicity of the testing is specified by the standard setting document.
As resuJt is considered to be a positive outcome when the external appearance
of the integrated circuits and their electrical parametere conform to the norms
of the technical specifications, of the testing program, and of the particular
document which governs the rules and procedure for the'conduct of the test.
The procedure for checking the durability of integrated circuits which is prac-
ticed in the majority of foreign countries provides for shipping the products
ahead of schedule. The stimulus to work on improving the fabrication quality
of IC's 3s expressed in the fact that for a specified test duration of 1,000
hours, the manufacturer gains the right to turn the product over ahead of sche-
dule given the condition that lfl batches of the products tested sequentially for
500 haurs showed a positive result. The conformity of the number of IC failures
during the testing process to the acceptance number serves as a positive outcome
for each test, while the criterion for the stability of the quality level of
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the output product is 9 batches which have passed the testing out of the 10
subjected to the control testing.
Integrated circuits from a batch which did not pass the test undergo the complete
program of quality control testing.
A high quality output product, which is characterized by the successful passing
of 500-hour tests by 10 sequentially produced batches of integrated circuits
gives the manufacturer the right to curtail the length of the tests to 250 hours.
In turn, the success of such tests assures a further reduction in the testing
- time down to 100 hours.
. Mechanical, Climatic and Biological Tests. The majority of the methods for
mechanical, climatic and biological tests of integrated circuits do not funda-
mentally differ from the known methods of testing devices, equipment and their
components. They have been covered sufficiently completely in the nrPss [4, 104,
107-111], and we will not stop to describe them here.
We shall onsider only those tests which are not used for quality control of
devices and equipment and are employed oniy in integrated circuit testing. Along
_ with this, we shall also analyze the so-called acce.lerated testing techniques.
Included among the group of tests to which only integratPd circuits are subjected
is a series of inechanical strength tests for the leads and connections: the
testing of IC leads for bending and tensile strength, the testing of IC's for
- the strength of the joining of the chip to the substrate and tESting the strength
of the internal connections. Testing for lead wettability as well as IC testing
for immunity to thermal shock, testing for the purpose of checking for the pre-
sence of an impermissible amount of moisture inside the IC package (dew�point
determination) and testing for immunity to exposure to dew are also included in
this same group.
Bending tests of IC leads are performed for the purpose of r_hecking the ability
of integrated circuit leads, including their fastening assemb_lies, to stand up
- to a mechanical load applied perpendicularly or at some angle to the axis of
the leads.
The test procedure consists in alternately hanging a load of a definite weignt
from each lead of the IC being tested. The integrated circuit is smoothly
inclined over to an angle of 90 degrees. One bend contains the inclining and
the return to the initial position, Several bending cycles are realized.
_ When testing for the purpose of evaluating the lead strength margin (in the
standard setting engineering documentation, this test is frequently called a
bending fatigue test of integrated`circuit leads), the leads are bent through.
90 degrees in both directions alternately. The bending radius and the point of
- load application are specified in the standard setting documentation.
A set of clamping devices and loads are used �or the tests which assure the
application of a bending load of a specified level to the leads of the packages
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of the products under test. Moreover, a set of devices and attachments is used
to prevent an end-restraint moment on the leads and to visually assess the results
of the test. An outcome is considered to be a positive test result if there are
no breaks in the leads or cracks in the insulators.
The resistance of integrated circuit leads to a load applied along the leads,
i.e., to tensile forces, as well as the lead securing strength in this case
are checked by applying a static load in the direction of the lead axis in a
definite sequence to each lead of an ZC. The size of the load is taken from
the standard setting documentation as a function of the degree of severity
establisiied for the given product type. The time that the load is applied is
figured in seconds. The procedure allows for leads which are directed coaxially
opposite to each other to have a force applied to one of them while the othe:
is secured. The result of tensile strength tests of IC leads is considered
satisfactory if no breaks in the leads or cracks in the insulators are observed
at :he conclusion.
Methods arz used fo?- testing the strength of the internal connections ia an IC
which make it possible to determine quality of the seating ef the chip on the
substrate and the force needed to tear away the welded connections. In the first
case, a load is applied by means of a special attachment to the chip uniformly
- over the surface area in a direction perpendicular to one of the side faces of
the chip, so that the resulting force is directed at an angle of 15� to 20� to
the surface of the substrate. The strength of the internal welded connections
is checked by applying a load of definite size to the lead, which causes the
contact connection or lead to break.
We shall conclude the treatment of inechanical tests with yet another curious
circumstance in our opinion which undoubtedly deserves the attention of IC
testers. It is asserted in [112] that in certain cases, tests using single
- shocks can be replaced by centrifuging.
When the necessity arises during tests with single shocks or in a centrifuge of
providing for a pulse trapezoidal waveform with a rise time and leading edge
decay figured in tens and hundreds of milliseconds, one of these types of load
can be replaced by the other. The effect on the product under test proves to
- be equivalent in both cases if the width of the leading and trailing edges
exceeds 0.09 seconds, while the law governing the rise and fall of the accelera-
tion is linear. In this case, the run-up and shut-down time of the centrifuge
is of no importance, and consequently, does not have to be standardized if the
product being tested does not have components in it having a resonant frequency
beZow 10 Hz. It is important to smoothly change the r.p.m.'s of the centrifuge.
What has been said also applies to pulses of any waveform other than rectangular.
Besides the well-known widespread methods of checking product strength with
- exposure to mechanical shock, a fundamentally new method of quality control for
connections is reported in paper [113].
The technique is based on a pulsed mechanical shock localized at a selected point,
where the shock is produced by the energy due to the effect of electrical energy,
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the pulses of which are delivered to the test object by an electron beam instal-
- lation. The thermal energy occurring as a consequence of the breaking of the
beam electrons in the material of the IC package, where the Ueam is produced by
this installation, is converted to a compressive stress which acts on the IC
leads in tris case. The Febetron-705 installation designed for this purgosed
generates an electron beam with a diameter of about 25 mm having an energy of
up to 2 MeV and directs it onto the test object in the form of a 30 nanosecond
pulse.
Specialists of the Sandia l.aboratories Compan.y are proposing the use of this
- method for selective input quality control of the welding of tab leads.
The tests which determine IC strength with a sharp change in the ambient tempera-
ture and IC immunity to this type of effect are subdivided into thermal shock
(heat shock) tests or thermal cycling testing. The essence of these tests is
the same. The specific featu?-e which distinguishes these tests, consists, first
of all in the substantial difference in the time which is allocated for transfer-
ring the tested IC from an environment at one temperature to an environment at
another temperature (during thermal cycling, this time is measure in tens of
seconds, ar.d when exposed to thermal shock, it is measured in seconds), and
secondly, by the nature of the test environment (thermal cycling is done in air
and therma? shock testing uses a fluid).
The integrated circuits being tested are placed by turns in the test environment,
having a particular ultimate temperature, and are held there for a period of
time indicated in the standard setting engineering documentation.
For convenience, the IC's are placed in special container plates, which provide
for direct contact of che products being tested with the test medium.
Liauid nitrogen, a mixture of alcohol and dry ice, ice and glycerine-are-.nsed=.as
such a medium. The choice of the material for creating the environment is
governed by the specified temperature. A"deep" cold is achieved using liquid
ni:.'rogen, a temperature of zero is reached by means of using thawing ice, and
a temperature intermediate between them is achieved with a mixture of alcohol
and dry ice. A positive temperature is achieved using glycerine. Various brands
of glycera_ne are used, depending on the specified temperature. '
The temperature limits, the duration of the exposure of the tested products to
the test conditions and the transfer time, number of cycles and parameters being
monitored are stipulated in the standard setting engineering documentation.
The tests are performed in speGial baths or chambers, which provide for the
stable maintenance of a spec=fied test medium temperature.
The integrated circuits which pass these tests, after being kept under normal
- climatic conditions, are subjected to visual and electrical testing and checked
- for hermetic seal integrity. Those IC's which are considered to have passed the
test are the ones which meet the requirements of the standard setting engineering
documentation with respect to all criteria.
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The determination of the dew point is accomplished for the purpose of establish-
ing the possibility of the appearance cf moisture inside an IC package in such
a quantity that it leads to an impermissible change in the electrical parameters
of the IC when the ambient temperature changes.
Integrated circuit:. are tested in a thermal chamber, the temperature in which
exceeds the ambient temperature by an average of 10� C prior to tne start of
the test. Having measured the parameters of the IC under test, the electrical
load is not removed. The parameters are monitored during the testing.
The test consists in changing the temperaturE in the working volume of the cham-
ber from pvsitive to negative and again to the former positive Jalue at a
certain rate. The duration of the temperature change from one ultimate value
to the other depends on the range of temperature change and is figured in
minutes. A change in IC parameters within permissible limits, stipulated in
the standard setting engineering documentation, attests to IC capability of
maintaining operability under conditions of an unavoidable dewfall.
A variant of this test is the checking of the ability of IC to operate in the
presence of frost. The procedure provides for the coating of the IC with frost
and its subsequent thawing. To reproduce the test conditions, the integrated
circuits which are tested for conformity to the requirements of the standard
setting documentation with respect to the main electrical parameters, are kept
for several hours at a slightly negative temperature (20 - 30� C) [sic]. After
this, they are removed from the chamber and kept for several hours under normal
_ conditions in an energized state. The electrical parameters are checked period-
ically. The conformity of these parameters to the requirements of the standard
setting documentation serves as the criterion for positive outicome of the check
of the given quality property of the unit being tested.
. IC testing for moisture immunity, performed in a cyclical variant, is included
among the number of accelerated testing methods.
Thermal cycling makes it possible to speed up the process of microdefect develop-
ment in the package protection for an IC, on the surface, in the internal circuit
wiring layout and other areas, which in a medium with elevated humidity can
lead to a considerable change in the parameters.
The graphs in Figure 28 (a-c) illustrate the changes in the test mode parameters
over the course of one cycle. As follows from these graphs, the tests are
- performed primarily in a heat and moisture chamber, where the tsmperature is
changed cyclically from the normal value to the working and ultimate tempera-
tures for the given type of IC's [107,109].
Each test cycle consists of exposing the integrated cire.uits to an atmosphere
with an elevated humidity at an elevated temperature and subsequei-tly changing
the temperature whiLe maintaining the relative humidity constant. The ratio of
the duration of the exposure and the period of temperature change depends on the
design of the product and the problem being solved. It is usually chosen in a
range of from 1:1 to 1:0.17.
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r=90�9B9 r�g093% r.90�98Sr.gQ.9g; r~BC7,~.oS.~00& ~ ~.95�JOID1.--
l f"_-" ~+i
3
- T,` Y ~ f-' � .
~.s ~n ~5 ~7od 74 T, u s ,p ~5 YR r v
0
~n0
~r1�C
TN
0
7i
~
6
 cym
Figure 28 (a-c). Schematic of a aingle test cycle for moieture
immunity according to various standard setting
engineering documents.
Key: 1. Four to eight fluctuations per hour.
- A typical test procedure provides for the preliminary exposure of the IC's to
' an elevated temperature and noxmal humidity for sevFral hours. After this, the
temperature in the chamber is reduced down to normal and the electrical parameters
are checked.
Following this, a humid environment is create.d i.n the chamber, while the tempera-
ture is per.iodically varied in a specified range.
Besides the steps described here, this kind of testing procedure provides for
exposing the IC's to a below freezing ambient temperature or vibrating them
� with subse;sent checking in a humid environment as the concluding step. The
requi.si:,_- effect is achieved by combining the steps and changing their sequence
and duration.
The rate of temperature change is usually not standardired.
The quantity of air which is fed into the chamber every minute.shculd exceed the
chamber volume by a factor of no less than five times.
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The vibration of the integrated circuits is realized in the low frequency range
(10 to 60 Hz) with a continuous frequency change from the l-~wer ultimate value
to the upper value, taking an average of 1.5 minutes.
- At the end of the concluding cycle, the IC is exposed to an environment with
elevated humidity and a normal temperature.
Cnemical Tests. Solder wettability tests of integrated circuits leads pursue the
goal of checking the preparedness of the leads to take solder. The ser.ond pro-
blem which is resolved in this case is an additional check of the thermal
immunity of the IC during the 3oldering of the leads. Since touching a heated
soldering iron to an IC lead is accompanied by instantaneous local heating, the
capability of the IC to stand up to the effect of a thermal shock is checked.
~ 7he testing procedure provides ior degreasing the leads with alcohol and sub-
_ sequent treatment with flux. Then the wettability of the IC leads with solder
- is to be checked. It is accomplished by immer:sing the free andS of the leads
in solder, having a temperature which is stipula*_ea in the standard setting
engineering documentation. The duration of one testing cycle is governPd by the
- testing documentation and amounts to several seconds. The solder should conform
to definite specifications. The major one of c:hem i5 a clean and shiny surface
of che melted metal.
Sometimes the testing is complicated. In these cases, prior to treating with
flux, the degreased leads are exposed for several tens of minutes to distilled
water vapor.
The IC under test is suspended above the surface of boiling water at a distance
siich that the ambient temperature does not exceed the value of the working temper-
ature of this type of integrated cir:,uit. The integrated circuit is exposed for
several hours to normal climatic conditions between the above indicated operation
~ and the testing.
- The thermal immunity of an IC during soldering is checkeo by repeated immersion
in solder with an intezval between the sequential immersions lasting no more
than five minutes. The temperature of the solder in this case is ele�aated an
average of 20� C with respect to the temperature of th.e solder when testing for
lead wettability.
A tin bath equipped with a heat regulator is used for the testing and provides
for a stably maintained specified temperature. Moreover, equipment is used which
provides for convenient and reliable immersion of the IC leads in the solder to
the requisite depth. To be numbered among the other equipment needed for this
test are the tank for checking the IC immunity to thermal shock during soldering,
an optical instrument with a magnification of 16 x and instrumQntation for
monitoring the integrated circuit parameters.
Visual inspection of thp IC's following solder wettability testing of the leads
. should establish the absence of cracks on the surface of the leads as well as
corrosion pitting, bared sections and bubbles.
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The assessment of the test results using optical equipment with a magnification
of 16x should show the absence of peeling, layer separation or bubbles in the
coating during bending of the leadp througti 180�. The IC leads are bent in a
radius equal to half of the lead diameter. Integrated circuits, in the leada of
whiCh cracks are found in the metal coatings or traces of corrosion are rejected.
A positive result is considered to be such a test outcome that the surface of
each of the tested IC is coated with a solid layer of solder over no less than
95%. In this case, its individual punctures and cavities are scattered over the
entire surface, and not concentrated at one point, there is no mechanical damage
and the electrical parameters conform to the requirements established in the
standard setting engineering documentation.
Hydrolic (Pneumatic) Tests
- In accordance with the classification given in the literature [101], to be includ-
ed among this group of tests are IC tests which puraue the goal of evaluating
the hermetic seal of the package protection. These tests are based on the
recording of the gas exiting through a hole in the product package, by means of
a special leakage indicator or visually.
In the standard [101], tests in which the major kind of exposure is to fluid or
gas pressure are called hydrolic and pneumatic tests. One can agree with such
a classification with certain conditions, howeqer, the detailed definition of
tcese tests shows that it is nonetheless closer tc reality to include them among
the group of climatic tests.
Apparently, it would be correct to additionally introduce into the standard of
[101] yet another classification group of tests: hydrolic tests, and to include
in it all kinds of tests related to checking the hermetic seal of the package pro-
tec:.ion for integrated circuits and other prociucts, as well as to the estimation
of rhe water, spray and droplet immunity of the camponents and assemblies of
instruments and equipment.
Minor defects in the package protection of integrated circuits which are responsi-
ble for a complete hermetic seal in the range of "small" leaks are determined by
mass spectrometry. The integrated circuit or batch of integrated circuits are
pressurized with helium, and then the rate of helium leakage from the IC package
is checked. A special pressurization chamber is used for the pressurization.
The preesurizatiotL is accomplished at a pressure exceeding five atm, for a
period of time of no less than three hours. With a lower pressurization pressure,
its duration is increased. Having completed the pressurization, the pressure in
the chamber is reduced to normal and the units are transferred to a control
chamber, where the rate of gas leakage is measured based on the expiration of
a definite time (up to one hour).
Used for the tests are an integrated circuit pressurization chamber, a mass spec-
trometer fo. monitoring the hermetic seal with a Teakage indicator, having a
sensitivity sufficient to register a helium leakage rate of no worse than
10-7 Z' Um/sec; a diffusion type leakage reference standard and a production
process case for storing and transferring the integrated circuits.
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Integrated circuits, the ].eakage rate of which does not exceed that set by the
- standard setting documentation are considered to have passed the test.
T.tie techniqueS provides f~r the determination of the hermetic seal in a range of
from 1- 10 to 1. 10- Z' um/sec. In using this method, it is essential to
- observe that all of the plug connections have a vacuum seal within the sensitiv-
ity range uf the leak sensor, while the leak sensor is graduated in accordance
~ with a standard diffusion type leak.
- So-calZed "mc3erate leaks", i.e., defects due to a hermetic seal failure which
is characterized by a value of 1. 10-2 Z' um/sec and more, are determined
visually based on the leaking of gas out of the IC package.
The IC's ara presslirized with frer,n in a chamber where the ambient pressure ic-
brought down to 1 Bnn Hg. The fre.ir. is fed into the chamber at a pressure of 3 to
5 atm. The duration of the press�:x ization usually runs to three hours and more.
Following the indicated exposure of the units being tested to the freon, the
pressure is reduced down to the normsl level, and the IC's are dried and transfer-
red to a bath with heated ethylene glycol or another fluid with similar physical
properties. The presence or absence of gas bubbles exiting the IC package at
points where there is a seal failure is detected visually. The absence of bubbles
attests to t:e hermetic 5ea1 of the package. IC's are tested in an indicating
fluid with the cap down. The depth of immersion of the products in the fluid
~ should be such that the bottom of the IC package is no less than SG mm from the
surface of the liquid. The temperature of the liquid is spec?Eied in *.he stan-
dard setting engineering documentation.
The result of the testing is abserved and recorded for 10 to 30 seconds. If
- several IC's are subjected to testing at the same time, it necessa?-y to arrange
them so that the appearance of individual bubbles at each of them will not go
unnoticed by the observer and will be immediately regiatered.
To test the hermetic seal of integrated circuits with this method, it is neces-
~ sary to have a pressiirization chamber: a high pressure vessel, a transparent
bath with a grid of stainless steel at a spacing of 50 mm and more from the
bottom of the bath, freon, ethylene glycol or another fluid suitable for indi-
cation purposes, a magnifier for observing bubbles and a thermal regulator
which maintains the liquid temperature in the bath in a range of + 3� C.
An IC seal failure estimated to have a leak exceeding 1 Z' um/sec, is monitored,
juat as in the case ,just described here, but without preliminary pressurization.
The dimensions of defects which determine the seal failure of a product package
are such in this case that there is no need for pressurizing the package. Inte-
grated circuits with seal failures placed in ethylene glycol, glycerine or
another indicator fluid give off bubbles.
The procedure for performing the test provides for heating the indicator fluid
_ up to a definite temperature spe.cified in the standard setting documentation.
The tested samples, just as in the case already considered here, are immersed in
- the indicator fluid to a depth of no less than 50 mm from the surface of the
fluid.
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The same equipment is used for the testing as when checking "moderate" leaks.
The gas inside the IC package expands and gets out through the holes, forming
btibbles.
Besides those considered in worldwtde practice, other methods are also used for
checking the hermetic seal of IC packages.
- Cyclical tests for moisture immunity are successfully employed to ascertain large
and moderate leaks, Defective integrated circuits are detected from the depart-
ure of the parameters from the norms becatise of the increase in the leakage
current and the reduction in the inverse breakdown voltagE and gain of the
transistors: .
The use of dyes makes it possible to precisely locate a seal failure point. When
checking the hermetic seal of IC packages to detect leaks through cracka in
the glass or defects in the seal of the pins to the glass, luminescent monitoring
is frequently used. It consists in making the leaks visible with ultraviolet
- light.
In conclusion, we shall deal with yet another method of checking a hermetic seal,
which some investigators include among accelerated techr.iques. The issue involvea
testing integrated circuits under pressure in an aqueous solution of substances
which have a strong influence on the state of the aurface oi the aemicouductor
chip. The sensitivity of the method is higher than some others. However, the
use of this methods entails a danger of the gradual failure of the IC being
checked, if it has been acknowledged as a good one initially. A portion of the
solution, having entered into capillary holes during the testing, will move
during an extremely long period of time into the interior cavity of the package,
and having penetrated there, can unexpectedlp cauae the device to fail.
Nondestructive Integrated Circuit Quality Control Methods. Nondestructive methods
are becoming-increzsingly widespread among the various techniques of IC quality
control testing. Their widescale introduction into quality control practice'ia
explained both by technical and economic considerations.
Quality control which is accomplished using nondestructive techniques makes it
possible to operationally ti-mely determine the properties and state of the
raw materials and finished products, without rendering them unsuitable and with-
out reducing their operability and service life.. The techniqLes are highly pro-
ductive and economical. They provide for an individual check of the quality of
manufactured IC's and the apriori evaluation of their reliability. These methods
are findj.ng ever greater applications not only for quality control, but also for
failure analysis for the purpose of predicting the reliability and durability of
integrated circuits. Without going into the fine points of the classification of the numerous tech-
niques of nondestructive testing, we ahall briefly treat those which have
recommended themselves as the most efficient as applied to integrated circuits
- [138, 125, 1261.
- - 101 -
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Optical (Light) Microscopy. Modern optical microscopes (general purpose, metal-
lographic, biological, comparison microscopes, etc.) are extremely sophisticated
tools for quality control and research, having definite advantages over the
scanning electron microscope: the color image, the simplicity of use, the
possibility of directly observing the units being studied (tested), and the
wide range of optical radiation.properties which can be utilized (interference,
polarization, luminescence, optical spectral properties of the radiation, etc.).
Optical microscopes make it possibla to observe microscopic objects in a wide
range of magnifications (from 3x up to about 1,800x) with a resolution of
approximately 0.2 um.
In thi.s case, plates and finished IC's with such microdefects as mechanical
damage and disruptions of the topology (size, mutual position, etc.) of individ-
ual structure components, c.ontamination and chemical destruction of IC components
(thin film conductors and resistors, dielectric coatings, wire leads, package
components, etc.) are efficiently detected.
Interferometry Techniques. An important variant of the optica'. microscopy
method is interfero:netric techniques based on the observation of the distribu-
_ tion pattern of the intensity and phase of optical radiation from a microscopic
object when it is illuminated by a monochromatic incoherent or coherent source.
When obssrving the interference pattern from a flat plate in a microinterfero-
me*_er, for example, from oxidized silicon, parallel lines are visible (inter-
ference maxima), which are positioned at an equal spacing from each other; in
this case, the pattern does not change with an increase or decrease in the
optical path difference by an amount equal to a whole number of half-wavelengths
(a/2) of the incident light. The presence of microinhomogenexties in the relief
of the surface being studied (or local sections of transparent coatings with
different indices of refraction) leads ro the curvature of the bands. Measuring
the amount-of the curvature and comparing it with the spacing between adjacent
~ parallel interference lines and with the quantity equivalent to half of the
incident light wavelength makes it possible to determine the size of the relief
unevenness (oi the inhomogeneity of the optical properties of the transparent
coating).
Optical interferometry makes it possible *_o measure relief steps in an opaque
substrate of down to 0.1 times the spacing between the interference maxima, i.e.,
the resolving power of the technique is about 0.03 um.
= Infrared (IR) interferometry is based on the use of the monochromatic IR beam of
a laser instead of visible light, which makes it possible to check plates of a
~ semiconductor material oi 3ifferent thicknesses, observing and measuring the
interference pattern by mF.ans of an electronic optical converter or a vidicon,
sensitive in the IR region [114]. T.hus, for example, for measurements.at a
wavelength of 1.15 um, the index of refraction of silicon for which is 3.4, the
spacings betwEen the interference maxima are equal to A = 1.15/(2 ' 3.4) = 0.17
um. Assuming a measurement precision in this case of (1/5)A, we determine the
resolving power of the technique to be about 0.03 um.
-102-
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Ellipsometry. The ellipsometry method is baeed on the change in the parameters
of elliptically polarized light as a result of its refiection from the object
being studied.
The appearance of lasers which make it possible to obtain narrow, nondiverging
monchromatic beams of light at a high intensity, have made it possible to use
ellipsometric techniques to study the regions of thin films of oxide and nitride
layers on reflecting surfaces [114]. In this case, measurements can be made in
small dimensional ranges (10-5 to 10-6 cm2), having thickness inhomogeneities on
the order of a few tens of Angstroms, which is 5 to 10 times greater than the
capabilities of optical interferometry. Using this technique, one can effectively
monitor the quality of opening windows in silicon oxide or nitride during photo-
lithography, determine plates which have been poorly cleaned, the thickness of
the oxide and foreign films on which can amount to 4 to 5 nm (the thickness of
the natural oxide an semiconductor plates usually does not exceed 2 to 3 nm);
monitor the processing quality (cleaning) of the glasses used in the fabrication
of the photographic templates; study the changes in the index of refraction of
oxide, nitride and other transparent thin films, etc.
Optical Scanning Microscopy. One of the effective t,_~chniques of ascertaining
defects and studying the failure mechanisms of integrated circuits, related to
processes on the surface of a passivated structure, is the technique of semicon-
ductor structure light response [115, 116].
The basis for this method is the measurement of the photoelectric e.m.f., which
occurs when a semiconductor structure is illuminated with an intense light beam
(probe). Since the level of the light response signal depends on the electro-
physical properties of the semiconductor material, the p-n junctiona and the
properties of the semiconductor chip surface, the recording of local light
response signals from various points in the structure being studied makes it
possible to ascertain and study IC defects.
The physical principle of the operation of a scanning.optical microscope is
based on generating minority current carriers in the semiconductor with the
action of light radiation. The charge carrier pairs generated by the light, in
propagating in all directions from the point of generation by virtue of diffusion,
reach the p-n junction and are separated by its field. In this case, a photo-
electric e.m.f. appears across the p-n junctian which causes a current to flow
when the p-n junction circuit is closed.
When a chip is illuminated with a localized light beam, the photoelectric current
a will depend substantially on the point of beam impact. If the distance from the
point of impact to the p-n junction is large, the photoelectric current is
vanishingly small, since the nonequilibrium electrons and hoJ.es have time to
almost completely recombine, before -eaching the junction. I� the beam falls in
the space charge region of a junction, then all of the generated carriers par-
ticipate in producing the photocurrent. When the light spot falls on a thin film
metal conductor, the photocurrent disappears. If there is an opening (defect) in
the metal film, the photocurrent rises. IL there is a localized inversion layer.
~ - 103 -
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close to the p-n junction, the photoelectric current will not fall off over the
entire extent of the junction, because of the inversion laye,:. When a portion
of a p-n junction is illuminated in which there is an accumulation layer, the
current carriers generated by the light cause avalanche ionization, leading to
a sharp increase in the light response signals.
An optical scanning microscope takes the form of an installation with electronic
scanning of the light probe and the use of scanning to obtain the light response
images. The light source in it is a projection electron gun tube, while the
light response image is produced on the scceen of a television display tube with
synchronized sweep.
As an example, we shall indicate the major technical characteristics of the,
domestically produced "Fotoskan" scanning optical microscope [115]:
Resolution . . . . . . . . . . . . . . down to 2 um
Magnification . . . . . . . . . . . . . 30 to 300x
Field of view . . . . . . . . . . . . . from 0.2 x 0.2 to
S x 5 mm2
- Light spot scanning rate . . . . . . . . . . 10 and 2 m/sec
Frame frequency . . . . . . . . . . . . . 12.5 Hz
Number of lines in a frame . . . . . . . . . 270
Weight . . . . . . . . . . . . . . . 30 kg .
Overall dimensions . . . . . . . . . . . . 1,300 x 600 x 400 mm
It follows from what has beeri said above that the major advantage of a scanning
optical microscope is the capability of simple and rapid detection of bipolar
and MOS integrated circuits with "inversion channel", "microplasma breakdown of
the p-n junction", "metallization damage", etc. type defects. An additional
advantage of a scanning optical mieroscope over a scanning electron microsc:ape,
with which one can also identify inversion channels (in an induced current mode)
is the complete reproducibility of the results, since a scanning optical micro-
scope does not lead to the degradation of the surface properties.
Laser Scanning Microscopy. A variant of scanning optical microscopy is the laser
scanning technique [116].
A helium-neon laser with power level of 4 mW generates a beain, which is focused
by a special device into a spot with a diameter of 1 to 2 um. The scanning along
the x axis is accomplished at a frequency of 600 Hz and along the y axis in a
range of 1 to 10 Hz. Moving along the surface of a chip, the beam produces
changes in the chip conductivity, which cause a change in the cv.rrent passing
through the chip. An image of the chip surface appears on the screen of a tele-
vision set, synchronized to the laser beam scanning system.
Scanning the surface of an IC with a laser beam makes it possible to ascertain
breaks in th2 metallization as well as various defects in resistors and diodes
in an operationally timely manner and without difficulty. The concentration of
the doping impurities, and consequently, the resistance of the resistors can be
measured with it. Under the appropriate conditions, by using a laser beam to
-104-
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generate a base current, one can turn on or saturate the transiators of IC's and
thereby check the correctness of the performance of various logic operations by
definite functional essemblies of an integrated circuit.
The proposition has been advanced [116] that in the immediate future, it will b�
possible to introduce the system on a production line, and after a while, by
employing a raodification of the given syatem uaing computera, one will be able
to create a fully automated production line for integrated circuits.
The use of this method in the eaxly stages of IC fabrication will assure the
timely, inexpensive and more efficient rejection of defective integrated circuits.
Testing Methods Using Electron and Ion P4icroprobes. A substantial drawback to
electrophysical and optical testing techniques is the fact that they basically
provide information on the spatial inhomogeneity of microscopic objects and only
indirect information on the inhomogeneity of their compos:ttion.
For effective checking of the inhomogeneity in the composition of materials, which
prcvides for the localization necessary for the pur.pose of microelectronics,
methods are employed using electron or ion beams wj.th energies on the order af
tens of kiloelectron volts, focused in a fine beam (a probe) [117]. Extensive
information can be obtained on micro-

scopic ob~ects by means of ineasurement
J
facilities designed around electron and
ion probe excitation of solids with
4
.
~
,
varioua recording techniques (electron

~

and ion microscopes, X-ray microscopic
i
analyzers, installations for observing
5
cathode luminescence spectra, etc.). The
schematic shown in Figure 29 illustrates
-
observation poasibilities using an
~ ~ , ~;aatr~NUe
electron probe microanalyzer.
Lo,:L_ x-ray spectrum analysis is an
extremely gromising means of checking
the inhomogeneity of the composition
of semiconductor materials.
Figure 29. Symbolic representation of
the major physical phenomena which
accompany the interaction of electrons
with solid matter.
Key: 1.
2.
3.
4.
5.
6.
7.
X-ray radiation;
Cathodoluminescence;
Primary electrons;
Reflected electrons;
Secondary electrons;
Absorbed electrons;
The solid
This method is based on the spectral
analysis of the characteristic radiation
excited in local sections of the test
ob,ject when it is bombarded witb, an
electron beam having electron energies
on the order of several tens of KeV by
virtue of rearranging the inner electron
shells of the excited atoms of the
material. By datermining the intensity
of the spectral lines of the elements
included in the cnu,r;,jition of the ob-
ject being studied, a qualitative and
quantitative analysis can be made of the
composition of the material.
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The method inakes it possible to confidently identify the elements of Mendeleyev's
- periodic ta}ile from sodium to uranium. The surface localization which is pro-
vided by the local X-ray analysis with a probe size on the order of one pm usually
amour_ts to 2 to 5 Um. The relative sensitivity of the method, as a rule, doea
not exceed 0.01 to 0.1% by weight (1018 - 1019 atom/cm3) ; the error is no more
than 2%.
Microcathodoluminescent analysis successfully complements local X-ray spectrum
analysis as applied to semiconductors with "forward" junctions, making it possi-
ble to eliminate the major drawbacks to the latter: the comparatively poor
relative sensitivity, and the difficulty of identifying light atoms which have
long wave radiation.
This is achieved by simultaneously recording the optical radiation in the electron
probe microscopic analyzer with the X-ray radiation (see Figiire 29), something
which is accomplished by means of an optical spectx�ometer when the material is
bombar'..-:d with an electron beam having electron energies of a few electron-volts.
- Microcathodoluminescent analysiG has significantly greater sensitivity (1016 atom/
cm3 and lower when the samples being studied are cooled) as compared to local
X-ray analysis, something which is explained by the absence of phenomena similar
- to X-ray bremsstrahlung in the case of cathodoluminescence.
~ This method makes it possible to analyze the composition of thin fiims with a
sufficiently high precision (for example, those based on gallium arsenide). In
this case, the size of the error even for light atoras does not as a rule exceed
1%, while the surface locality amounts to 5 Lo 10 Um.
Unfortunately, the method is inapplicable to the testing of silicon, which has
a low probability of radiative recombination.
Auger Analysis. The measurement of the energy spectrum of secondary electrQns
(see Figure 29), which fly out from a sample when it is bombarded with an electron
beam having an energy of several KeV, can be used to detect light elements [113,,
118]. In this case, onl; electrons which exit from the surface are suitable for
the analysis, since their energy is not lost in collisions.
This method has a high sensitivity, mak ng it possible to detect impurities with
a concentration of down to 1018 atom/cm~ at a depth of from 1 to 2 nm with a
resulution of 20 to 50 um, where it can be used to study silicon plates.
Ion Microanalysis. The techniques of local X-ray spectrum and microcathodolumi-
nescent analysis are not suitable for checking the composition of semiconductor
layers with a thickness on the order of several hundreds or thousands of Angstroms,
since their localization cannot be less than several microns because of the
diffusion scattering of the electrons. The distribution of the atoms of the
material in such layers can be tested by means of ion microanalysis.
A beam of primary ions, for example, argon or oxygen (beam diametar of from 50 pm
up to 1 mm and a primary ion energy of up to 15 KeV) is directed fram an ion gun
onto the sample betng studied. In this case, the ion gun can be focused down to
2 pm [119].
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In the case of ion bombardment of a test objectr secondary ion-ion emissiun
occurs as well as cathode sputtering, ion-electron emission and electromagnetic
radiation.
Ion microanalysis is based on the phenomenon of secondary ion-ion emission. The
- secondary ions are directed to a mass analyzer by means of on immersion lens and
following the appropriate filtering, fall on the cathode of an ion-electron
converter, where the ion-electrcn emission occurs. The accelerated electron flux
is deflected by a magnet to a scintillator, from which the light signal is fed
- either to a photomultiplier or to the ocular of a microscope.
It is more expedient to use an ion microanalyzer to identify inclusions in thin
- layers (of up to a nm) of semiconductor materials containing the lightest atoms
(for example, hydrogen, lithium, beryllium, boron).
- Ttie sensitivity of an ion microanalyzer differs substantially for the various
elements, however, it is significantly higher than the sensitivity of the two
techniques indicated above and can reach 1011 - 1015 atom/cm3, which is not the
limit either.
- I.t should be noted that ion bombardment destroys the surface, i.e., this technique
cannot be included amcng r.ondestructive methods, however, it makes it possible
to determine the distribution of doping impurities with respect to depth in a
thin semiconductor layer relatively ragidly with a sensitivity inaccessible to
any other technique, and from this point of view, is a powerful tool for the
" physical technical analysis of microelectronic devices.
Scanning Electron Microscopy. A scanning electron microscope is most frequently
used as an effective means of studying microscopic objects, which include, in
particular, integrated circuits.
A large number of diff erent models of scanning electron microscopes are used for
research purposes, however, their operational principle is similar [120-122].
The major part of the microscope is the vacuum chamber in which the electron gun
and the magnetic focusing and deflecting lenses are placed. The electron beam
emitted by the gun is focused by the lenses down to a diameter on the order of
0.2 Um arid impinges on the sample being studied. The deflecting coils which
- accomplish the scanning provide.for obtaining a raster sweep over the surface of
the sample. In this case, the coils which accomplish the scanning are controlled
by a generator which simultaneously controls the beam sweep on the screen of a
cathode ray tube. Thus, the scanning of the CRT beam is accomplished synchron-
ously with the scanning of the sample being studied.
The various methods of electron scanning microscopy are classified as a function
of the kind of physical phenomenon employed, which accompanies the interaction
of the primary electron beam impinging on the surface of the sample being studied
with the material of the latter (see Figure 29). A brief description of the
characteristics of electron microscopy techniques using this principle, with an
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TABLL' 19. Methods of Scanning Electron Microacopy and Their Applications
to Microelectronics
Designation of the Method
1. The reflected electron
technique
2. The secozdary electron
emission technique
3. The absorbed electcon
technique
4. Cathodoluminescence
(microcathodoluminescent
analysis)
5. The technique of
transiting electrons
6. X-ray microanalysis
(local X-ray spectrum
analysis)
7. The induced e.m.f.
technique
Kind of Physical Pheno-
menon Employed, which
Accompanies the Inter-
action of Electrons with
the Material Being Studied
Elastically and inelastic-
ally reflected primary
electrons
Secondary electrons
emitted from the material
as a result of secondary
electron emission
Area of Application of
the Method in Micro-
electronics
Microtopography of 2n
IC (quality of the
metallization, steps in
relief, quality of the
oxide, welded contacts,
surface contamination,
etc.)
Integrity of electrical
circuits, determination
of the electrical poten-
tials of individual
elements
The electron current The same
from electrons absorbed
by the material
Emission of electromagnetic
radiation in the visible or
infrared portion of the
spectrum
Identification of inho-
mogeneities in the con-
centration of the doping
impurities. Determina-
tion of crystalline
structure defects
Primary beam electrcns The same
which pass through the
material
Characteristic X-ray emis-
sion of individual chemical
elements
Chemical composition
of the material and
local inhomogeneities
in the layer near the
surface of a semiconduc-
tor, and thin film ele-
ments. Identification
of contaminants
Induced e.m.f. occurring
in a product because of
the separation of electron-
hole pairs by the p-n junc-
tion, where these pairs are
generated by the electron
beam.
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Identification of inver-
sion channels, surface
structural defects, .
local regions of micro-
plasma breakdowns, and
the temperature distri-
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TAALE 19. [cont.]
8. Scanning reflected elec- Electrons reflected from
trori microscopy an equipotential surface
located in the immediate
vic-inity over an electric-
- ally energized product
The identification oiE
inversion channels,surface structural
defects, local regions
of microplasma break-
downs and the tempera-
ture distribution of
certain elements
indication of their areas of application for purposes of atudying integrated cir-
cuits, is given in Table 19 [113, 117]. A portion of these methods has already
been treated above (local X-ray spectral analysis, microcathodoluminescent ana-
lysis). In this section, we shall briefly deal with the capabilities of ref lected
electron techniques as well as secondary electron emisaion and induced e.m.f.
methods, which are finding increasingly greater applications in microelectronics.
The major advantages of a scanning electron microscope over an optical microscope
- consist in the large raage o� magnification (5 to 50,000x), the high resolution
(15 to 20 nm) and the great depth of definition, as well as operation in a wide
range of modes, which make it possible to gather extensive information on the
characteristics of the object being studied.
Thus, for example, by using a scanning electron microscope in a reflected electron
i mode, one can obtain a high quality magnified image of any portion of an.integrated
' . circuit on the screen and record it.on photographic film. The magnification fac-
tor varies in tizis case in a very wide range.
~ A precise quantitative evaluation of the reaulta of ineasuring surface relief is ; possible by means of stereophotography.
In a scanning microscope, the stereophotography is accomplishad by obtaining two
photographs of the section under study at different angles. For this, the inte-
grated circuit is positioned strictly in the center of the frame. The resulting
stereo pair is treated by means of a mirror-lens atereoscope, which makes it
possible to identify the desired point in any of the photographs. A stereoscope
which provides for the measurement of a vertical relief comgonent with an error
of no more than 5% is suitable for such applications.
In order to illustrate the capabilities of a scanning electron microscope, we
shall describe the operations in analyzing an IC which has failed, which can be
sequentially carried out without removing the IC under analysis from the vacuum
chamber of the microscope.
Having discovered the defective element of the IC (a tnin place in a thin film
conductor,, damage to a wire lead, contamination of the surface or a change in
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ttie color of the metal or oxide because of the presence of an inclusion of
unknown origin, etc.), one can measure the geometric dimensions of the elements,
' or having connected an accessory for X-ray microanalysis, use the scanning elec-
tron microscope for the operationally timely identification of the chemical com-
position of the unknown material. Having made electrical contacts beforehand
to the sample being studied, one can study -i.t in a secondary electron emission
mode or using the induced e.m.f. technique without extracting the integrated
= circuit from the vacuum chamber, and determine whether the just detected contami-
natian is the reason for the inversion or ion type leak, or whether it is the cause
of the chemical destruction of a thin fi?.m conductor, resistor, etc. All of this
_ increases the effectiveness of physical and technical analysis to an extraordinary
extent when determining the kind, cause and source of a failure.
Moreover, in a number of foreign companies - IC manufacturers, scanning electron
_ microscopes are used in IC production to optimize the production process modes
and selective quality control, for example, for thin film conductors (especially
when fabricating large scale integrated circuits with multilevel interconnections)
[113].
Equipment complexity and expensiveness, as well as the difficulty of interpreting
the resulting information in a number of cases and the changing of the surface
properties of an IC (for example, the induction of a positive charge with the
action of high energy electron beams), which can lPad to distortion of the data,
and in a number of cases, to irreversible changes in ihe characteristics of the
sample being studied, must be included among the drawbacks to scanning electron
microscopy techniques.
Huwever, these drawbacks to the methods of scanning electron microscopy are com-
pletely compensated for by its numerous advantages, which makes the given group
of techniques an irreplaceable tool for the study and testing of integrated cir-
cuits, especially large scale integrated circuits which are characterized by
considerable functional complexity.
Thermal Infrared Analysis. Of the numerous techniques for the thermal investiga-
tion of electronic equipment products (temperature field ar_d thermal radiation
field methods) in microelectronics, the most intensive efforts are under way in
using the passive infrared technique with various ways of recording the IR radia-
tion of an IC chip, the heating of which is caused by the current flowing under
various electrical operating conditions of the IC.
Studies demonstrate that the isotherm of the maximum temperatures pass through
regions where the p-n junctions, resistances and defects are located, which lead
to local overheating of the IC components.
Infrared radiometers are microscopes which are equipped with detectors for the
IR radiation emitted by an operating integrated circuit. Series produced models
of foreign IR radiometers have a temperature range of from 25� C up to 400" C,
a sensitivity of 0.5 to 1� C and a"spatial" resolution on the order of 10 to 20
_ um [113].
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One of the major difficulties.inherent in this method is related to the difference
in the emissivity of materials, because of which the intensity of the IR radiation
emitted by two different materials (for example, aluminum and silicon dioxide) at
the same temperature is not the same.
Coatings with 3n identital,thermal emissivity can be applied to devices, however,
this solution is obviously not an optimal one, since the coating itself can have
an impact on IC operation.
This problem can in principle be solved through the use of computer methods of
processing the data obtained when converting the thermal radiation fielf to
the true temperature of the IC elemPnts.
The design of a TV microscope is reported in [123], which makes it possible to
find the localized sites of excess heat in high power IC's. The IC is placed
, beneath the microscope.objective with a magnification of 125x, and its thermal
profile is observed on the screen. All of the changes in the observed picture
which are 3ue to a change in the electrical conditions are noted visually by
the controller. The device makes it possible to study thermal,fields with'a
size of down to 0.6 x 0.6 mm. The minimum temperature difference is 0.6� C.
X-ray Techniques. In addition to the methods of nondestructive testing treated
above, X-ray diffraction analysis is being successfully used to ascertain hidden
production defects in finished integrated circuits. The method is based on the
comparison of the X-ray'diffraction patterns of the IC being studied with a
"r-`Prence standard" X-ray pattern, in which integrated circuits having typical
s are depicted.
X-ray diffraction analysis is accomplished by means of an X-ray machine with a volt-
age'range of up to 150 KV and a focal spot of no more than 1.5 mm. The films are
interpreted using any suitable device. Zn particular, the 5P0-1 microfilm reader
is used for this purpose. ,
The quality of the cap seal to the IC package, the quality of the internal inter-
connections; the plate or the glass as well as the absence of foreign particles in
_ the device package are checked with the X-ray technique.
When it is not necessary to document the results of the quality control check, X-ray
television is used to check the quality of IC's. With this method, an X-ray image
converter and a closed television system, which make it possible to visualize the
X-ray image, are used to record the shadow X-ray image. '
In the case of X-ray television monitoring [124], X-ray TV's are used, which have
a resolution of 20 to 100 pairs of.lines per mm, a contrast sensitivity of no worse
than 5% and a magnification of from 20x up to 200x.
Work on nondestructive methods of ascertaining the hermetic seal integrity of packa-
ges has been widely implemented in practice. Along with those considered above,
these techniques provide for the rejection of defective and potentially unreliable
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units. However, the utilization of these techniques for the purposes of evaluating
and predicting the reliability of IC's is considered to be less promising.
B_cause of their merit, nondestructive methods are becoming increasingly popular
and displacing traditional quality control methods from the production cycle,
where these traditional methods have come to be of poor eff iciency under modern
production conditions [125, 126].
It is absolutely no accident that nondestructive testing tools have gained first
place among the testing and quality control equi.pment planned for future years.
In the semicon3uctor industry and in microelectronics, the demand for the develop-
ment of new nondestructive quality control and physical and technical analysis
tools as well as facilities for climatic and mechanical tests is characterized by
a ratio of approximately 1:0.5:0.3.
Setting standards for the ope.rational quality properties in standard setting
engineering documentation for integrated circuits, which has been implemented in
recent years and has become increasingly stringent since that time, as well as
the relatively high production cost of these products and along with this, the
undisputed advantages of nondestructive testing facilities - all of this is res-
ponsible for the constant work on improving them. Because of the improvement in
the sensitivity and resolving power of these tools and the continuing improvement
in the other metrological characteristics of devices of this class, they increas-
ingly approach the level meeting the requirements placed on the standardized
metrological characteristics from one variant to the next. The latter circum-
stance offers the real promise of making a transition in the near future to com-
pletely nondestructive testing in the category of quality control facilities, and
to display equipment in the category of ineasurement facilities.
The Use of Test Structures. The quality control methods treated here do not
provide for a complete estimate of the quality of large scale integrated circuits.
It is practically impossible to check the elements of large scale integrated
circuits in the ma3ority of cases. One of the methods of testing such IC's is
the testing of test structures, which contain individual structural components
and make it possible to identify failures of the ma,jor components of an IC when
- the load is applied.
The design of test structures and the methodology of their application for pur-
poses of quality evaluation and predicting the reliability of i.ntegrated circuits
in the quality and reliability assurance of integrated circuits during the
stages of design and fabrication will be described in more detail in Chapter V.
7. Acceptance Regulations for Series Produced Ptoducts
The acceptance regulations for series produced IC's provide for the performance of
acceptance and quality control tests: acceptance and delivery, periodic, stan-
dard, qualification, selective quality control as well as durability and shelf
life tests. The first group of tests include acceptance and delivery testing.
Periodic, standard, qualification and selective quality control tests, along
with durability and shelf life tests belong in the group of quality control tests.
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Acceptance and delivery tests are performed for the purpoae of checking the
quali':y of the output product. For this reason, each batch of products from a
production run are subjected to these tests. The purpose of periodic tests is to check the constancy of rhe production pro-
cess over a definite time segment. Integrated circuits are subjected to these
tests which are fabricated during a reporting month, quarter, half-year, etc.
The periodicity of the tests is established by the standard.setting engineering
documentation.
Periodic tests are also performed in the case of the renewal of the production of
products following an interruption, the duration of which exceeds that permitted
by the standard setting engineering documentation.
Standards tests are performed after inEroducing such changes into the production
process for integrated circuits or into their design that they can influence the
quality of the finished product. The task of these tests is to establish the
conformity of the IC's to the requirements of the standard setting documentation'
after these innovations have been introduced.
Selective quality control tests belong to the category of quality control tests,
by means of which the consumer of a product can check the work quality of the
manufacturer practically witllin an unlimited range.
The goal of the tests for shelf lif e and durability, as follows from the names
themselves, is to check the conformity of the IC's to the requirements of the
technical specificatior,s with respect to these indicators.
Qualific4tion tests are performed when it is necessary to evaluate production
readiness to produce integrated circuits of a certain series. Based on their
results, the quality of the IC's of a aetting batch is estimated and their
acceptance is effected.
We shall treat the procedure and organization for the performance of the tests
enumerated above in more detail as w211 as the rules for integrated circuit
acceptance. ,
Qualification tests are perfornied on set-up batches of IC's. The program of
qualification tests includes: checking the external appearance and quality of
the marking of the IC's, monitoring the overall and connection dimensions, check-
ing the static parameters (direct current parameters) of the products established
by the technical specifications for the various test categories at the minimum,
normal and maximum permissible temperature, as well as checking the dynamic para-
r,eters (alternating current parameters) at the normal temperature; testing the
IC's for immunity to a cyclical temperature change, testing for strength when
exposed to individual shocks and a centrifugal load; checking the hermetic seal;
MTBF testing; testing the strength of the external leads; checking the suitability
for soldering; checking moisture resistance; testing for vibrational strength and
operational stability when exposed to vibrations; testing for impact strength
when exposed to repeated shocks; checking the shelf life of the IC's at an ele-
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~ vated temperature; durability testing; fungal immunity tests; testing for frost
resistance; testing for immunity to a sea fog; testing for immunity to elevated
pressure; testing for immunity to reduced atmospheric pressure; and testing for
ability to withstand sound pressure (acoustic noise).
The progrzm of qualification testing is not exhausted with this extens ive list.
It also includes limit tests, which provide for checking the margins of strength,
resistance and immunity of the integrated circuits to mechanical, clima tic, elec-
trical and other loads. The strength of the packaging is also.tested in the
process of qualification testing.
Thus, in checking integrated circuit quality, a thoroughgoing check is made of
production readiness to produce a product conforming to the requirement s of the
standard setting documentation which is in force. Based on the result s of these
_ tests, a decision is made concerning the start of series production of the parti-
cular type of product.
The test batch of integrated circuits intended for qualification tests is divided
into groups, each of which is subjected to certain kinds of checks and tests.
_ Its own acceptance number is established for each group in the technical specifi-
cations.
Upon the completion of all tests, a commission analyzes the results ob tained.
The reasons for failure are studied in the integrated circuits which fa iled. When
a negative result is obtained (poor IC quality in the test batch), the IC manu-
facturer develops and implements measures to improve their quality. Samples^with
defects in the external appearance and marking are not taken into account.- Inte-
grated circuits fabricated after the implementation of these measures are again
subjected'to qualification tests. At the discr.etion of the commission performing
the tests, this time the IC's can be checked only for those effects preceding the
tests for which a negative result was obtained. It must be noted that exceeding
the acceptance number in one of the groups is not a reason to terminat e the tests.
The tests are run through to the concJ,usion so as to obtain an overall evaluation
of the batch being studied.
Limit tests of the IC's are usually performed simultaneously wieh the qualifica-
tion tests for this same purpose. In this case, the margins of produc t stability
with various kinds of loads, the margins of strength of the structural components
are also ascertained, and the distribution of IC failures are established, if
this is possible, with respect to the kind and degree of severity of the acting
factors.
The tests are performed using the same methods and on the same equipment used in
testing the strength and immunity.of integrated circuits with individual types
of loads. The difference consists in the test modes, the criteria for evaluating
the results and the conditions for terminating the testing.
The use of thermal shock and thermal cycling, individual impacts of great force
and centrifugal acceleration, high temperature storage as well as alternating and
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constant electrical Zoading with the simultaneous exposure to the ultimate posi-
tive temperature is widely practiced as the loading durir_g limit testing.
Considering the destructive nature of these tests, they are usually performed on
a limited number of products (up to 10 units).
The test conditions are chosen by working from the posed problem as well as the
design and production process features of the IC's being studied. It is recommend-
ed in this case that the following main rules be observed. The load steps are
chosen taking into account the program and results of pre,~eding tests of integrated
circuits similar to those being studied in terms of the design and production
process attributes (design and production process analogs). It is recommended
that the initial step be chosen two steps lower than the one at which failures
were obtained in the preceding tests. The duration of the exposure of the IC's
to each tests mode is figured in houra.
The thermal parameters are determined at the maximum electrical power dissipated
by the device. The ultimate values of the measurement temperature are specified
in the technical specifications for the product or in the testing program.
Measurements of parameters being checked during the testing process are made at
intervals of a definite number of cycles, specified in the technical specifications
or in the testing program.
As a rule, the margins of IC ability to stand up to electrical loads are evaluated
at the maximum ambient working temperature. The voltage, current or power is
gradually increased in steps, starting at the nominal value. The value of the
working temperature, the value of the load for each step and the duration of the
exposure in each step are specified by the technical specifications or the testing
_ program.
The safety margins in the ability of IC's to stand up to a constant electrical
load are determined at a load level close to the ultimate value, established by
the method indicated above. It is usually chosen 20% lower than the ultimate
value. The ambient temperature inthis case is chosen equal to the maximum working
temperature specified by the standard aetting documentation. It is recommended
that the parameters be measured at time intervals of approximately four days.
Three single shocks are employed at each load step. The size of the load (the
maximum acceleration and pulse width) are indicated in the technical documentation.
The shocks are applied in a plane which represents the most dangerous direction
for the Ws of the type being studied. A similar approach to the testing pro-
cedure is also realized with other kinds of inechanical tests.
The integrated circuits of each group are subjected to only one kind of test. The
products which have failed are removed and analyzed for the purpose of establish-
ing the cause of their failure.
The testing is terminated when the test program is exhausted, and the number of
failed IC's does not exceed the permissible level� in other words, when confirma-
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~ tion is obtained that the IC's are capable of standing up to the applied ultimate
load. Another criterion for the termination of testing 3s the case of failure of
= half of the products being tested. The rules for the performance of the tests authorize the termination of individual
_ tests when a limit is reached at which half of the tested batch failed in the
previous case.
Acceptance and delivery tests are performed as part of the quality control for
~ each production batch of products. Selective single step qualitv control is
employed as a rule. However, continuous monitoring is also used. This is
- usually practiced at the start of production of a certain series of IC's or when
the previously registered level of quality of the output product has fallen off.
A criterion for the assessment of the latter is an increase in the number of
complaints.
Products received by the quality ccntrol section are turned over for testing. The
- accompanying documentation for a batch of IC's which have arrived for acceptance
and delivery tests should contain information on the type and number of products
in the batch, the date of batch manufacture and the date of presentatiun for
acceptance testing, as well as the results of the tests performed by the quality
control section. The integrated circuits are kept for a certain _length of time
under warehouse conditions between the acceptance by the quality control section
and the acceptance and delivery tests.
In the case of selective quality control, the batches being tested are put
together from different batches of IC's which are presented for acceptance test-
ing. The number of products in a test batcin should be sufficient to carry out
- te:ting with respect to all groups. As a rule, the standard setting engineering documentation ?rovides for no less
than five test groups. One group provides for checking the external appearance
and marking of the integrated circuits. Another provides for checking the over-
all and connection dimensions. The third provides for checking the static IC
parameters in the case of the normal and ultimately permissible a.mbient tempera-
tures in accordance with the technical apecifications and dynami.c parameters of
IC's under normal ambient conditions. The fourth provides for a set of tests,
which consist of checking the ability of the IC's to stand up to a cyclical
variation in the ambient temperature, to linear loada as well as a check of the
hermetic seal of the IC package. The fifth provides for testing the IC's uader
electrical load at the,ultimate ambient temperature.
Each group provides for testing approximately the same number of IC's and an
equal number of permissible failures. An exception is the fourth gr.oup, the
tests of which are of a destructive nature, while the IC's subjected to these
tests are excluded from the number delivered to the consumer. For these reasons,
- the number of IC's set aside for these tests is the minimum permissible.
The loads to which IC's are subjected during the testing process are specified
by the technical specifications.
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The breakdown into the first and second groups is more symbolic than of any
substantial practica.L significance. Integrated circuits from one sample are
usually subjected to these tests.
It is permissible to subject integrated circuits to testit,g in accordance with
groups I, II, IV, V, which have passed the group III tests in the case of selec-
tive quality control.
Continuous monitoring of ZC quality is accomplished in accordance with the group
III program. The number of tested products in this case is figured in hundrecls,
among which, it is permissible to have individual samples which do not meet the
requirements of the technical apecifications. However, failures because of an
open or short circuit in the electrical circuitry�of the IC are not permitted
at all. Checking of the external appearance and labeling is also included in the
listing of -the checks. I
The acceptance rules provide for returning a batch of IC's to the manufacturer,
if a negative result is obtained in the teats, even if only for one of the groups.
It stands to reason that the issue involved here is more substantial defecta than
defects in the external appearance and labeling. Such IC's are simply rejected.
Various systems of applying sanctions to a manufacturer of a subatandard product
exist. One of .,';e systems, for example, provides for terminating the acceptance
of products, if of 10 production batches of IC's presented for acceptance have
3 batches in a row which were rejected in the process of the acceptance and
delivery tests. In this case, acceptance is renewed only after receiving poai-
tive resu?ts for 3 batches in a row, the testiug of which was preceded by a
careful analysis of the reasons and sources for the rejection and failures, as
well as the implementation of ineasures in production to prevent them.
The listing of the parameters to be monitored ie established by the technical
specifications.
Periodic tests are performed within timeframes established by the manufacturer
in conjunction with the customer. This is usually once quarterly.
A test batch of integrated circuits for these testa is put together during a'
period of time between the previous and next checke. Included in the complement
of a batch are only those products.which have pasaed the acceptance and delivery
tests.
Just as in the case of the acceptance and delivery tests considered above, a
periodic testing program provides for several test groups. The test program
for IC's in the first test group provides ror repeating the tests covered by the
first three acceptance and delivery groups. The difference consists only in
the fact that these tests are completed with the check of the electrical para-
meters under dynamic conditions at the ultimate positive and negative temperatures.
The second group of IC's is tested for immunity to exposure to individual impacts
with an acceleration exceeding 100 g, as well as for moisture .immunity. The
third group of IC's are tested for MTBF for 500 hours at the ultimate positive
- 117 -
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temperature. The fourth group of products undergo testing for the hErmetic seal
of the package, suitability for soldering, as well as ;.he quality and strength
= of the external leads. A separate fifth group of IC's is singled out ~or testing
of the moisture 3mmunity during a longterm exposure.
The test sample for MTBF is made up of any one type from each group cf the types
of IC series being tested. Batches of IC's which represent any one type of
products from one.series are turned over for the remaining tests.
A positive outcome of periodic testing is considered to be the case where the
tests of all groups of IC's were accompanied by a number of failures not exceeding
that permitted by the technical specifications. Otherwise, the acceptance and
delivery of the product is stopped. Work is done to ascertain the reasons for the
excess number of failures. New technological approaches are worked out and intro-
duced into production, changes are made in the IC design, new standards are set,
etc. In a word, a set of ineasures is implemented which are called upon to prevent
the appearance of an impermissibly large number of failures as compared to the
value established by the standard setting engineering documentation.
An important place is set aside for limit tests among the methods of analyzing
the reasons for an increased number of failures.
The rules for invoking sanctions provide for returning to the manufacturer all
- of the previously received batches of IC's which have not been unloaded, without
the right of repeated presentation, if in the process of analyzing the samples
- which failed during the periodic teats it is determined that an elevated perc,ent-
age of failures was due to a degradation of the fabrication quality or the use
- of materials, component products and semi-finished products which do not conform
- to the requirements of the standard setting documentation.
This rule does not apply if it is determined that the reason for an unsatisfactory
evaluation of the test results is a defect in the equipment or an error by
personnel.
The acceptance and shipping of products is renewed after the newly fabricated
IC's successfully pass the tests. In this case, the tests are usually repeated
only for thatgroup for which a negative result was obtained.
Standard type tests are performed in accordance with a program which reflects
innovations made in the production and design of the IC's. The composition of
the quality control checks incorporated in a program of type standard tests
depends on the nature of the changes which have been made, the degree of their
possible impact on IC quality and the possibility of ascertaining this influence
by means of the proposed methods. The program includes tests from among those
figuring in the technical specifications for the pr.oduct. However, this does
not preclude using other kinds of tests also which can provide insufficient
information, including comparative tests of different products.
An evaluation of the acceptability of the changea being introduced is made on the
basis of the results of the type standard tests, taking into account the results
of all the other tests.
-118-
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Selective quality control testing is usually performed by the major customer
for the products. The scientific research facilities of the customer are, as
a rule, used in this case as the testing base. However, if mutually agreed on
the tests can be performed at the manufacturer's also.
The volume of the tests'is set in accorda.rce with the desire of the customer and
governed by the testing program. Samples for these tests are selected in accor-
- dance with the testing program from among those which have already been received ~
by the quality control section. The testing timeframes and the procedure for
their performance are established by the scheduling charts.
Tests for durability are uaually performed as part of the qualification tests. It
- is considered sufficient to perform a durability check on ar.y one type of IC from
_ each group of types froin a series. The selection of the type of producrs for
the tests is the prerogative of the commission which receives the setting batch.
The commission usua].ly performs these tests only for the first thousand hours.
Then the tests are monitored by the quality control section.
It must be said that the practice of performing these kinds of tests which has
come into being, which is supported by the standard setttng engineering documen-
tation, provides for combining the durability tests with the MTBF check of the
integrated circuits. Having atarted the MTBF teating of the dev3ces, the testing
is finished with a check of the durability indicators. This is correct in all
regards, and primarily in economic terms.
The duration of the durability tes`ing stage is determined by the minimal mean
time before failure of the.IC's eatablished by the technical specifications.
In the case where these tests are not a continuation of the MTBF tests and are
performed independently, then the IC's selected for thp indicated tests are pre-:
liminarily checked in accordance with the acceptance and delivery testing program.
In this case, not all of the IC quality properties are checked, but only the
absence of external defects, as well as the static and dynamic parameters. The
static parameters, as is provided by the technical documentation, are measured
at the normal, minimum and maximum temperatures. The alternating current para-
meters are tested under normal conditions.
Substandard integrated circuits, which are detected during the check process, are
replaced with good ones. The rejected ones are forwarded to the failure analysis
subdivision to determine the reasons for the rejection or the failure.
A result is considered to be a positive outcame of the durability teats when over
the course of the minimum MTBF, the number of failed IC's does not exceed that
permitted by the standard setting engineering documentation. A negative result
of these tests entails an analysis of the causes of the fa3lures ae well as
limit tests. - 119 -
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Shelf Life Tests. The following main goals are pursued in performing shelf life
- tests: the cnecking of tne conformitq of the IC's to the requirements of the
standard setting documentation, the gathering of data on the technical shelf life,
the more precise setting of standards for shelf life indicators and working out
~ recommendations to improve storability.
Various testing techniques are employed to check the shelf life. The choice of
the method is governed by the requirements placed on the operational characteris-
tics of the IC's. Depending on the requiremer.ts, conditions are artificially
created or selected, under which the IC's being studied are stored for a specified
period cf time.
The IC's are stored in heated or unheated repositories, under shelter or at an
open air site. They are-stored in standard packaging, or as components in equip-
ment or sets of spare parts and accessories.
Integrated circuits are not tested in open air sites in the factory packing, since
they are not adapted for this.
The heated room or storehouse with air conditioning should have a temperature set
in a range of from +5 to +40� C and a relative humidity of up to 80% at a tempera-
ture of 25� C. The conditions of an unheated room are characterized by a tempera-
ture wnich varies in a range of from -55� C up to +40� C, and a relative humidity
at standard tempe-rature which does not exceed 98%. On open sites and under
shelters, the permissible variation in the temperature fluctuates from -60� C to
+50� C with a relative humidity of the environment under normal conditions of
up to 100%.
- The duration of the testing is specified in the standard satting engineering
documentation. During this time, the electrical parameter3 of the IC's and
their external appearance should remain within the range of the established
norms. The norms are specified in the documentation for the starting point in
time and the end of the tests.
m
The following rules are observed.when choosing the IC type. Integrated circuits
of any type are turned over for testing, which represent a group of series types.
In the interests of attaining the maximum testing economy, it is permissible to
group IC's of different types together. In this case, products are chosen which
are representatives of the basic design, the standard fabrication technology or
some other functional attribute. The results of the tests are extended to the
entire class or group of products.
Here, just as in other cases, the samples for the testing are selected from a
received batch by means of random sampling. Producta having minor defects which
exert no influence either on the electrical parameters nor on the evaluation of
the external state of the IC are permitted to be subjected to this testing.
Integrated circuits which do not conform to the requirements of the standard
setting documentation..are replaced. The same parameters are checked during the testing process as during acceptance
and delivery tests. It is recommended that the measurements be performed with
- 120 -
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the same facilities during all tests. The probability of failure free storage
or the percentage of good IC's following storage under specified cond itions in
an established time interval or within a definite storage time are taken as the
criterion in evaluating whether the IC's are good.
Tests are also performed on IC's under natural cor.ditions, storing them in
different climatic zones and regions.
She?f life tests at elevated and reduced temperatures are performed in heat and
cold chambers. The IC`s are de-energized when stored in them. The duration of
the storage is figured in tens and hundreds (up to a thousand) hours. Integrated
circuits for which the external appearance and electrical parameters following the
- testing conform to the requirements of the standard setting documentation are
considered to have passed the test.
Failed IC's continue to be tested for a period of time necessary to determirie
the amount of the deviation of the parameters during the storage time. Upon the
completion of the testing, the failed circuits are forwarded for analysis.
- 121 -
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Chapter V. Ways of Assuring the Reliability of Semiconductor Integrated
Circuits
Integrated circuit reliability is a comprehensive cilaracteristic which is governed
by an aggregate of many mutually related factors. The specified reliability level
of integrated circuits is set during their design stage, and is assured during
IC fabrication and maintained during their applicatians [27, 32].
The ultimately attainable level of reliabiiity of integrated circuits depends on
- the selected design. It is specifically the design and production process variant
- of an IC which governs the strength safety margins of its components, the levels
of the ultimately permissible loads (eleLtrical, mechanical, climatic, etc.), and
in the final analysis, IC reliability under its norma'L operating conditions.
- The second ma3or factor which determines the reliability level of an IC is the
quality of the execution of the production process for its manufacture, selected
for the realization of the design and production process solution established
in the planning stage. In this case, reliability is assured by an entire set
~ of ineasures, which includes primarily the following:
--A high degree of inechanization and automation of the production processes and
quality contral operations;
--Effective input quality control of the raw materials, semi-finished products
and energy vehicles;
--High quality and efficiency in monitoring the observance of the technology and
the maintenance of technological discipline at the requisite level;
--The presence of an effective automated eontrol system for the technological
production process based on statistical quality control of the production pro-
cess using test structures;
--An effective production process testing system for the purpose of rejecting
potentially unreliable,products;
- --Reliable monitoring of the level of quality and reliability of the finished
IC's;
--Thorough analysis of the reasons for IC rejection and failure;
--Systematic development and implementation of ineasures to eliminate the ascer-
tained reasons for failures during IC testing and operation, etc.
- Finally, an exceptionally important factor which governs IC reliability during
operation is the s*rict observance of all of the requirements of the standard
setting engineering documentation for an integrated circuit in all stages of
_ its application:
--During the design of the radioelectronic equipment (REA) using the IC's;
--During the input quality control of the IC's;
--In the stage of installing and debugging the modules and systems of the
radioelectronic equipment; .
~ -122-
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