NPIC DATA SYSTEM DATA AND CONTROL SEGMENT ACQUISITION PHASE VOLUME V ALTERNATE CONFIGURATION ANALYSIS

• Document Type: CREST
• Collection: NGA Records (Formerly NIMA)
• Document Number (FOIA) /ESDN (CREST): CIA-RDP84T00037R000400030001-4
• Release Decision: RIPPUB
• Original Classification: U
• Document Page Count: 27
• Document Creation Date: December 28, 2016
• Document Release Date: June 18, 2007
• Sequence Number: 1
• Publication Date: February 24, 1982
• Content Type: REPORT

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UNCLAS SIF1ED
NPIC DATA SYSTEM
DATA AND CONTROL SEGMENT
ACQUISITION PHASE
VOLUME V
ALTERNATE CONFIGURATION ANALYSIS
24 February 1982
UNCLASSIFIED
STAT
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UNCLASSIFIED
is
NPIC DATA SYSTEM
DATA AND CONTROL SEGMENT
ACQUISITION PHASE
VOLUME V
ALTERNATE CONFIGURATION ANALYSIS
STAT
?
This data, furnished in connection with Request for Proposal 82-8-015 as amended, shall not be dis-
closed outside the Government and shall not be duplicated, used, or disclosed in whole or in part for
any purpose other than to evaluate the proposal. If a contract is awarded to this offeror as a result of
or in connection with the submission of this data, the Government shall have the right to duplicate,
use, or disclose the data to the extent provided in the contract. This restriction does not limit the
Government's right to use information contained in the data if it is obtained from another source
without restriction.
STAT
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UNCLASS1 FI ED
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Page
1
HARDWARE CONFIGURATION
V-1-1
1.1
Vendor Selection
V-1-1
1.2
Alternate Configuration
V-1-4
2
IMPACTS
V-2-1
2.1
Design Impacts
V-2-1
2.2
Development Impacts
V-2-2
2.3
Schedule Impact
V-2-4
2.4
Performance Impacts
V-2-6
2.5
Risk
V-2-9
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Figure
Page
1.0-1
Generic Architecture Requirements
V-1-2/3
1.2-1
Univac 1100 Series Processor Characteristics
V-1-5
1.2-2
Univac Host Allocation Summary
V-1-6
1.2-3
Univac Processor Configurations
V-1-7/8
1.2-4
Detailed Alternate Configuration Schedule
V-1-9/10
2.1-1
Software.Design Impacts
V-2-3
2.2-1
Software Development Impact Summary
V-2-5
2.3-1
Alternate Equipment Installation Summary
V-2-6
2.4-1
Alternate Configuration Performance Assessment
Summary
V-2-7/8
2.5-1
Risk Analysis Summary
V-2-10
3.-0-1
Alternate-Configuration.Fiscal Year Summary
v-3-1
'3.0-2
ROM Cost Analysis Summary
V-3-2
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UNCLASSIFIED
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We performed a rigorous analysis of an alternate vendor solution to our proposed generic D/C
Segment architecture, carefully assessing the design, development, performance, and cost
implications.
This volume reflects the results of a methodical assessment of implementing our proposal
architecture with UNIVAC hardware and software products. This assessment was performed using
the following approach:
a. Use our proposed generic D/C Segment architecture as the departure point for identi-
fying an alternative vendor design;
b. Select the best choice of an alternate vendor, capable of meeting the technical and
schedule objectives of the NDP;
c. Configure the alternate vendor's equipment in a manner which meets D/C Segment process-
ing objectives, holding to our generic architecture characteristics in terms of
design margins and switchability;
d. Perform a comprehensive assessment of the impacts of the alternate vendor solution to
our proposed design, development plan, schedule, and projected performance;
e. Identify the risks associated with the alternate vendor solution; and
f. Estimate rough-order-of-magnitude deltas to the proposed cost of our preferred
solution.
o implement this approach, we identified an independent project team. Their goal was to
identify and analyze the best possible vendor alternative, with emphasis on satisfying D/C
Segment functional, performance, and schedule objectives, while providing the most cost-effective
solution. The following sections reflect the results of their analysis, including supporting
justification and rationale.
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The alternate configuration definition began with an analyses of our generic D/C Segment
architecture characteristics.
The generic architecture which was selected for the D/C Segment reflects the results of exten-
sive tradeoff analyses'to determine the best solution to meet NDS processing requirements. The
preferred solution is a distributed processing architecture, in which intelligent work stations
off-load processing and data from the host processor, providing the user with improved system
responsiveness. This architectural solution was considered fundamental to satisfying D/C
Segment performance requirements and thus, became the starting point for selecting our pre-
ferred vendor design. Similarly, this same starting point is reflected here in the definition
of an alternate vendor solution.
GENERIC D/C SEGMENT ARCHITECTURE -- As illustrated in Figure 1.0-1A, the host portion of the
D/C Segment Architecture involves three host systems. Master Database (General) and the
P&A functions are assigned to one host system. Exploitation and the C2 functions are resident
in the second host system. The third host system supports the Training, Test and Development
activities as well as serving as a redundant system for the other two hosts. All DASD is
switchable to any of the three host systems - ideally by an intelligent switch which allows
for prestored switching patterns. There are at least three front-end-processors (FEP's)
which have multi-host support and have access to any host system. The FEP interfaces to the
Local Area Network (LAN).
ARCHITECTURAL HIGHLIGHTS -- Besides no single point of failure within the D/C Segment Config-
uration, there are three major architectural highlights. All functional database DASD is
totally switchable via pre-stored switching configurations. Any functional host system
may assume control over any portion or the entire functional database DASD. All host systems
are supported by multiple front-end processors (FEP's). Each FEP supports all host systems.
Figure 1.0-1B spotlights these capabilities.
ARCHITECTURE CHARACTERISTICS -- Figure 1.0-iC lists the architectural characteristics which
must be met in order to satisfy the NDS driving requirements. Careful analysis of these
characteristics fall into three major categories: function identification, processing
requirements, and availability requirements. These characteristics were used as the basis
selecting the most suitable alternate configuration.
CONFIGURATION ITEM DEFINITIONS -- Our analysis focused on the Configuration Items as defined in
our Design Specification. Some CI characteristics (Figure 1.0-1D) were relaxed somewhat so as
not to be too restrictive. This allowed more vendors to be considered. Our analysis assumed
our fundamental architecture was to be preserved. The alternate configuration analysis was
limited to the central ADP facility elements of our design. Alternatives for The Integrated
Work Station (IWS) design were considered in Vol. II, Sect. 5.8 of this proposal.
1.1 Vendor Selection
We selected UNIVAC for the alternate vendor solution, both because it is a vendor-compatible
extension of today's system, and because the UNIVAC product line can be configured to satisfy
our generic architecture. -
While several vendors offer hardware and software products which could satisfy D/C Segment
needs, we selected UNIVAC as the best vendor for our alternate solution. The primary rationale
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UNCLASSIFIED
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JAGeneric D/C Segment
Architecture
Swnd,
Cei1o1.
can/
Training.
Twt& Dar.
IA)
FEP Switah of Pdundant Pad..
I
OF
OF
uF
rC/S sermon tLocal Am Network)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Og Architectural Highlights
r ---------------
PS-ad n -AumndSwtd. Coi,nta?ee
e'e
B B B B
Hon B
uF
I/F
C-cal DASD Swndiint
D. DASD Must Be Switchable to Any Host
With Minimal Manual Intervention
D. Any Host Has Universal Access
to the D/C Segment Database
D. Each FEP Has a Direct Channel to Each
Host and Links With Each Other
DO Configuration Item Definitions
Cl Definition
? Processor and Console ? Three host-processor systems with separate
I/O processors, 16 MB memory, 2 consoles
per system with CRT and hard copy for each
console. Consoles must be able to assume each
other's function.
-. _ . _ e..._ _-__~.........i
h from one-half to
t
2 million bytes of real memory. Must support a
bit synchronous network protocol, support
multi-host connections and function as FEP,
node and concentration simultaneously, if
needed. 50K bytes per second throughput -
aggregate.
? Operating System DASD ? No separate DASD required if suitable ap-
approach is available.
? General Support and ? All DASD subsystems must have fully dual
Pre-exploitation Data controller/' equipped with at least two banks of
Base cache memory-no-less than four Mbytes of cach
Disk units must be at least 600 megabytes with
dual access capability. Transfer rate must be
1.5 megabytes or greater with a cache hit
access time of no greater than four milli-
seconds. Disk average access time should be
no greater than 40 milliseconds.
1 Exploitation Data Base ? Same performance characteristics as the General
Support and Pre-exploitation data base. All
database DASD must be fully accessible from
each host.
t Archive Subsystem ? No separate subsystems shall be configured.
Additional capability will be added to each host
system. Units shall be 9 track, 6250 GCR
with 200 inches per second tape speed.
e Display Subsystem ? Standard CRT clustered no more than 6 to
controller.
R High Speed Printer ? At least one printer per host with printing
speed of 1000 lines per minute or greater at
96 characters print font. Must be horizontal
print mechanism - no drum printers. Print
fonts should be interchangeable with the
printer capable of informing the host as to
which print font is loaded.
? Interprocessor Communi- ? May be a channel-to-channel, high speed serial
cation Facility (up to 50 megabits per second) or multiple
links between hosts.
? Integrated Work Station ? Considered in Vol. II, Para. 5.8 (INS Design)
? Remote Job Printing ? Considered in Vol. II, Para. 5.8 (IWS Design)
V-1-2/3
Figure 1.0-1. Generic Architecture Requirements
Architectural Characteristics
? Single or multiprocessors in the 8-14 MIP range (single
processors should be redundant)
? Accessibility by any host processor to any functional database
or segment.
? Redundant paths and units for all critical peripheral subsystems
? Redundant mainframe components (i.e., cache, backing storage
and I/O)
? Command and Control which can be superimposed on a desig-
nated host processing system.
? Self diagnosis of hardware faults down to the field replaceable
unit (FRU) is critical to reducing the average total mean-time-
to-repair (MTTR). This must be considered as a necessary
contributor to overall availability.
? Cache disk to optimize heavy I/O activity.
? The exploitation function will require 4 MIPS and four billion
bytes of DASD
? A computational capability of 4.6 MIPS and one-half billion
bytes of DASD is needed for pre-exploitation processing.
? A computational capability of one MIPS and
approximately four billion bytes of DASD is needed
for Training, Test and Development
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for this selection was twofold: 1) the extensive UNIVAC product line, and its ability to
provide the central processor and peripheral hardware to support our basic architectural
assumptions; and 2) the reduction in software and data base conversion effort which results
from a UNIVAC selection. There were two considerations in the selection of UNIVAC:
a. The UNIVAC host processor product line does not include a processor which meets the
execution rate requirement (10 MIPS) which is necessary to satisfy our generic
architecture's physical partitioning of operational function into two host processors
(plus one additional processor for maintenance, training, and backup). We were
forced to expand our generic architecture to three host operational processors.
Within each host processor, an additional CPU is configured for availability. Addit-
ionally, we were concerned with the life-cycle implications of not having a field-
upgradable additional processing capability for the UNIVAC candidate processors.
b. The UNIVAC multi-processor architecture at the high end of the processor line, parti-
tions the host into multiple 2 MIP processors, causing concern in partitioning the
pre-exploitation (P&A) batch processing function into four parallel processes to meet
the time requirement. The two factors to be considered were: 1) the additional
software complexity to support this additional partitioning; and 2) the additional
execution overhead and inherent iela,:;s in the additional portioning of the P&A
functini .
Both of these consider,::. 'e carefully examined, and we concluded that they result in
less potential vertical is 1,-sir growth and increased P&A turnaround time than our
preferred solution. We decide, )~,vvo;, that the UNIVAC products will meet the FOC require-
ments and do provide savings over ,the alternative vendors in terms of software conversion.
After careful assessment of the UNIVAC product line, -,'e %:ave ,Zected an 1100/84-based
hardware configuration to meet D/C Segment processi2- -,'actives.
In deriving the UNIVAC hardware configuration, we examined the characteristics of each D/C
Segment Conf,,..;.~Lion Item. Our objective was to identify the individual Univac hardware units
which would s,3tisfy these characteristics in the most cost-effective, state-of-the-art manner.
The hardware unit dcr..ition for each CI is defined and justified in the following paragraphs.
PROCESSOR AND CONSOLE DISPLh. - he first step in this CI definition process was to select
the host processor which best satisfies the D/C Segment architecture objectives. Two candidate
UNIVAC 1100 series processors were considered: 1) UNIVAC 1100/60; and 2) UNIVAC 1100/80.
Figure 1.2-1 shows the relative processing power in the various 1100 models and their corre-
sponding MIP rates. The relative value of 1.0 is the current 1100/43 production system. The
top end of the 1100 series cannot support the generic D/C Segment architecture, which reflects
P&A and General Flinport functions in a single processor, requiring 10 MIPS of compute power.
The alternate.., then, is to partition the generic architecture function into additional hosts,
so that the U.; ' processor can be employed.
The first choice to attempt to define an 1100/60-based configuration. The 1100/60 Series
incorporates the t technology, especially in the areas of availability and maintainability.
The 1100/60 feu instruction Set is particularly well suited for this environment but is
not object c mpatible with the 1100/80 Series. Object code incompatibility would require
only a minor c lion effort.
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0The 1100/80 Is the Only 1100 Capable of Processing Pre-Exploitation With Margins.
UNIVAC 1100 Series
Relative CPU Power (In M.I.P.S.)
Compared to Pre-Exploitation FOC MIP Requirement
7.0 6.0 5.0 M.0S 3.0 2.0 1.0
P
*Projection Based On 1100/62 H2 Values Multiplied by a Factor of 1.8 to Allow
for Memory Conflicts.
Reference: "Tracking the Elusive KOPS", Edward J. Lion; DATAMATION,
November, 1980. pp 99-105.
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O Performance and Compatability Dictated 1100/80 Selection.
1. MIPS Per CPU
Line 1 - 1.2 Per CPU
2 - 2.2 CPU
2. Maximum Number of CPU's
Four
Four
3. Maximum MIPS
4-4.5 Per System
7.6-8.0 Per System
4. Redundant Instruction Execution
5. Fault Injection
6. Built In Hardware Monitor
7. Direct Fetch From Backing If Total Cache
Failure Occurs Without Causing an
O.S. Reboot
8. Self Diagnosis Down to the Field Replaceable
Unit (FRU) Level
9. Extended Instruction Set for Character and
Bit Manipulation
Figure 1.2-1. Univac 1100 Series Processor Characteristics
v-1-5
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The total FOC pre-exploitation (P&A) requirement of 4.6 MIPS stresses the capabilities of a
UNIVAC 1100/64. If the 1100/60 Series were selected, an 1100/64 system would be required to
process the P&A workload alone. This would dictate an additional 1100/64 solely as back-up
to the P&A system. Any additional growth in the P&A function would require distributing the
function into multiple hosts. This would be a serious design impact. For this reason, the
1100/60-based configuration was rejected.
Next, an 1100/80-based configuration was examined. The 1100/84 CPU can support the P&A
processing requirement, while retaining the required design margins. With an 1100/80-based
configuration, three 1100/84 processors are required.
Finally, we considered a hybrid 1100/80 and 1100/60 solution. This approach was discarded
because of the incompatibility of object code between the 1100/60 and 1100/80 would require the
maintenance of two distinct software libraries. (The alternative to this would be to not make
use of the expanded instruction set of the 1100/60, one of the primary reasons for having
selected it).
After careful examination of these three alternatives, we selected the 1100/80-based config-
uration as the best alternative choice for the D/C Segment host processors. Figure 1.2-2
summarizes this choice in terms of functional allocation and projected loadings.
Function
Processor
Rationale
Exploitation/
1100/84 (8 MIPS)
o
Exploitation Requires 4 MIPS (2
CPUs)
Training, Test
o
Training, Test and Development
Requires 1 MIP
and Development
(1 CPU)
o
Availability Requires 2 MIPS (1
CPU)
General 2
1100/84 (8 MIPS)
o
General Processing Requires 4.6
MIPS (3 CPUs)
Processing/C
o
C Negligible
o
Availability Requires 2 MIPS (1
CPU)
Pre-Exploitation
1100/84 (8 MIPS)
o
Pre-Exploitation Requires 4.6 MIPS (3 CPUs)
o
Availability Requires 2 MIPS (1
CPU)
The 1100/84 Processors have been configured for both performance and availability. Each
configuration has:
a. 4 CPU's (3-workload, 1-availability)
b. 4 IOU's (3-workload, 1-availability)
c. 32K Storage Interface Unit (SIU) - Full 128K bytes cache for performance and redundancy.
d. 4 million words of Main Storage (MSU) - 32 megabytes.
The final configurations for the three 1100/84 processors are reflected in Figure 1.2-3. The
detailed configuration layouts are reflected in Figure 1.2-3 and 1.2-4.
FRONT-END PROCESSOR -- Five DCP/40 Communication Processors have been configured as front-end
processors. All front-end-processors (FEP's) have a full duplex, 36-bit channel connection
to each host. Each FEP has a node link to each other and two high speed loadable line modules
to support two Local Area Network (LAN) interface units. Each FEP is configured with 1.5
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Detailed Alternate Configuration Schematic
Total
MSU=4MW
Total
SIU=32KW
Total
CPU=4
Total
IOUs=4
1
MWords
1
MW
1
MW
1
MW
Motor
Generator
Standby
Motor
Generator
Host B
MG
Host C ' ' Host C
MG MG
Note: Controls All DASD,
Mag Tapes, Lables
& Printers.
Figure 1.2-3. Univac Processor Configurations
Standby