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JPRS ID: 9827 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY

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APPROVED FOR RELEASE: 2007102/49: CIA-RDP82-00850R040400030008-6 1'OR OI"""('IA1, llSl? ONI.Y JPRS L/9827 7 July 1981 USSR Report _ CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOIOGY (FOUO 17/81) FBO$ FOREIGN BROADCAST INFORMATION SERVICE FOR OFFZC(AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400030008-6 NOTE JPRS publications contain information primarily from foreign newspapers, periodicals and books, but also from news agency transmissions and broadcasts. Materials from foreign-language sources are translated; those from English-language sources are transcribed or reprinted, with the original phrasing and other characteristics retained. Headlines, editorial reports, and material enclosed in brackets are supplied by JPRS. Processing indicators such as [Text] or [Excerpt] in the first line of each item, or following the last line of a brief, indicate how the original information was processed. Where no processing indicator is given, the infor- ma.tion was summarized or extracted. Unfamiliar names rendered phonetically or transliterated are enclosed in parentheses. Words or names preceded by a ques- tion mark and enclosed in parentheses were not clear in the original but have been supplied as appropriate in context. Other unattributed parenthetical notes within the body of an item originate with the source. Times within items are as given by source. The contents of this publication in no way represent the poli- cies, views or attitudes of the U.S. Government. COPYRIGHT LAWS AND REGULATIONS GOVERNING OWNERSHIP OF MATERIALS REPRODUCED HEREIN REQUIRE THAT DISSEMINATION OF THIS PUBLICATION BE RESTRICTED rOR OFFICIAL USE OiVLY. APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400030008-6 JPRS L/9827 7 July 1981 , USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY (FOUO 17 f 81) CONTENTS xaRnwARE Some Results of Simulation of the Planned PS-3000 Computer System.......................................................... 1 Handbook on Integrated Microcircuits.............................. 5 New Book Discusses Parallel Computer Systems 14 Basic Configurations of Multiple Machine YeS Systems.............. 21 ~ ASVT Ni and SM Systems of Multimachine Complexes 42 Minimaks Modular System 47 Summa Modular Minicomputer System 51 MARS Asynchronous Modular System 54 Design of Recursive Computers 59 Computer Systems With Rearrangeable Structure 63 SOFTWARE Excerpts Frum the Journal 'ALGORITHMS AND PROGRAMS', September 1980 67 Excerpts From the Journal 'ALTORITHMS 9ND PROGRAMS', October 1980 72 Excerpts From the Journal 'ALGORITHMS AND PROGP.AMS', November 1980 76 - a- [III - USSR - 21C S&T FOUO] FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400440030008-6 FOR OFFICIAL USE ONLY Excerpts From the Journal 'ALGORITHMS AND PROGRAMS', December 1980 78 Academician Samarskiy Discusses Computational Experiment.......... 82 Interactive System for BESM-6 Type Computers 85 APPLICATIONS Soviet ASU Experience 89 Test System Test Results 98 Investigation of the Precision of Work and Results of Tests of 101 Software of an Automated System for Control of Vibrations....... Discrete Control Systems 103 Distribution of a Charge Over the Surface of a Cqlindrical _ Electrode of Finite Length......................a............... 104 Results of Efforts to Register C1$ssifiers in 1978-1980........... 105 New Tasks of Informatics 107 Information Security in Automating Processing 109 PUBLICATIONS Abstracts From 'REAL-TIME SYSTEMS HARDWARE AND SOFTWARE'.......... 112 New Book Discusses Systems With Variable Lag...................... 116 Papers on Computerized Processing of Meteorological Information... 120 - b - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000440030008-6 FOR OFFICIAL USE ONLY HARDWARE UDC 681.321075) SOME RESULTS OF SIMULATION OF TfE PLANNED PS-3000 COMP'v'TER SYSTEM Z"bilisi SOOBSHCHENIYA AKADEMII NAUK GRUZINSKOY SSR in Russian Vol 101,No 1, Jan 81 _ pp 101-104 [Article by I. N. Agladze, T. A. Kuprava, I. D. Rodonaya, and N. D. Chikovani, Georgi,an SSR Polytechnical Institute imeni V. I. Lenin] [Text] Simulation is broadly employed when creating new computer systems; moreover in different design stages, simulation is performed at different levels: at the level of electric circuits, logical elements, register transmissions, and the systemic level. This article presents some results of simulating the planned PS-3000 computer system at the systemic level. In the program we wrote, the model of the PS-3000 system is represented as a set of main memory modules (MMM's), instruction processing modules (IPt-11 s), and arithmetic- logical modules (ALM's). A basic diagram of this part of the system is shown in Fiqure 1. . Lon 1 non2 Ma13 MOn4 (2) MOKI Mon2 MOK3 MOK4 ~ 3) ni ~~w c ~ ~ n a Figure 1 Key: 1. MMM 3. ALM 2. IPM The following algorithm of the system's oFeration was reflected in the program model. Each IPM forms an address `.`or a request to read a portion of the instruc- tions in an MN',in, it receives that portion of the instructions from the latter, and it processes the instructions; the code of the operation and the ti.me of decoding 1 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY of an instruction by a given IPM are selected randomly. Next requests to read the operands of the instruction aie transmitted to one of the NIlMM's, selected at random. An instruction that has been decoded and prepared for execution is transmitted into one of the three ALM's, also selected at random. The results of instruction execu- tion are transmitted into one of the MNIlM's for recording. The model simulates fulfillment only of scalar operations by the system. The program model of this system's operation is written in IMSS--stochastic system simulation language. In this case the model is represented as a set of mutually associated queueing systems simulating the operation of the computer system's hardware and software, while the structure of the system under analysis is successively expressed in the structure of its network simulation model (1). The latter property of a model written in IMSS permits visual confirmation of its adequacy to the structure under analysis. A simulation network for the minimum composition of the PS-3000 is shown in Fiqure 2. Figure 2 Symbols in the simulation network are: IIT--copy buffer, CEKl-CFM--sections of an MMM, BK--an IPM's instruction buffer, BPK--buffer storing decoded instructions from the IPM, Fi6M6--IPM's output buffer, KEm --IPM results buffer, NPI'1-HPI'4-- MMM's information registers, Gl--group request source. The J130, J1BK, JI00, ancl JllP devices [not further identified] are added to the network for auxiliary purposes. Type R, M, D, S, and V units are intended correspondingly for routing, for change in names and priorities, for duplication, for synchronization, and for distribution of request flows among the different devices on the basis of a given probability. Numbers above the devices indicate the time required by the device to service re- quests, in Usec. The IMSS description of the network's devices and units and of the links between them makes up the program simulation model of the PS-3000 system, intended to be run in a computer. Simulation was performed with a YeS-1020 computer. The program model was run in the computer for different intervals of simulation time. As the simulation time increased, the results became more stable. The system's productivity, stated in operations per second, was the simulation results. 2 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY A graph showing changes in productivity in response to change in simulation time is shown in Fiqure 3. We can use it to evaluate the statistical sufficiency of the simulation results. f - ~ V., ~ ~a (2) Figure 3 Key: 1. Operations per second 2� tsim, Usec Table 1 . r,Ls5l,. . (6) (9 . M~I ~ItI/IMNf1 ~~rIwA11 INI ~ 1!M /~~i I /fl~.lA m/Y~Yn~ 4! nl /b 4 a9i 19i -47 . e i6 ~'p) isf C6,11 .~7!/SJ y~ ia07y3 O ~ ~ ili Y� . � +uwr I Mf/a.r: / d.j / CE/S2 0,V17J MI/ O.S~t79t M 12 71 ne wNUf d w. 6 i ! jf LE'~'3 AJ~/J!~ M~ ' 6 74- ~96 �,.r A ynri,v 20 7 9 CfK4 ~~41Y{) 4srrr� ni = er ...w� r t e r Anh1f .;`:i,;:; Mr f1 ss .9a A1W2 /y! 3 28 28 A5M3 S >7 16 KE M! 2 09 139 6K 2 >4d 148 6'pl( G t t 8 ff4 MO/7 e.��0 ~ M 2 " 2 W~,C IOlli4i Mf ,s Key : 1. Device 2. Load (simple) 3. Type request 4. Maximum number of requests per device 5. Number of incoming requests 6. Number of serviced requests 7. Zbtal flow 8. ALM 9. MmH 3 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 ,.M anR~.� APPROVED FOR RELEASE: 2007102/49: CIA-RDP82-00850R040400030008-6 FOR OFFiCIAL USE ONLY The jump in productivity at tsim= 200 usec to 2 million operations per second may be explained by unsteady loading of all of the system's buffers at the same time i.n the initial period of work. This corresponds to the logic of the real system's operation. Subsequently the system's productivity approaches an asymptote of 1.4 million operations per second. By studying the model of the PS-3000 system's operation, as represented by the stochastic network, in addition to determining the productivity of the system as a whole, we are able to determine some other characteristics of the devices, which are stunmarized in the table. Analysis of the simulation results permits the conclusion that work with just scalar operations results in substantial underloading of the system's potential productivity. This conclusion agrees well with the point of view of the system's _ designers (Institute of Control Problems), who planned the system for tasks in- volving a larger proportion of vector operations. Simulation of the PS-3000 system with the help of a stochastic network was an ancillary task for the authors, and it was performed with the goal of comparing these results with those obtained through functional simulation of the system. The system's functional model consists of a more-detailed description, in PL/T language, of all processes occurring in the system at the level of individual instructions. The results of these two entirely different simulation methods-- structural and functional--exhibited a discrepancy not exceeding 10-15 percent, which permits the authors to assert the adequacy of the models of the real system they developed, and to use the obtai.ned results to make decisions associated with the system's design. BIBLIOGRAPHY 1. Mayorov, S. A., "Osnovy teorii vychislitel'nykh sistem" [Basic Principles of Computer System Theory], Moscow, 1978. 11004 CSO: 1863/170 4 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040400030008-6 FOR OFFICiAL USE ONLY -.3 UDC 621.3.049.77(03) HANDBOOK ON INTEGRATED MICROCIRCUITS Moscow SPRAVOCHNIK PO INTEGRAL'NYM MIKROSKHEMAM in Russian 1980 (signed to press 22 Feb 80) pp 2-8, 10-11, 23 [Annotation, table of contents, foreword to second edition, and excerpts fran part one from book "Handbook on Integrated Microcircuits", edited by B. V. ' Tarabrin, Izdatel'stvo "Energiya", second edition revised and enlarged, 100,000 copies, 816 pages] [Text] This han3book presents information on digital and analog integrated microci.rcuits. Domestically produced integrated microcircui.ts are classified. Types of housings and their general characteristics and parameters are described. Detailed information is provided on each series of integrated microcircuits: the basic purpose of each series, the basic electric circuits, base design, and electric parameters. The first edition was published in 1977. This handbook is intended for engineers and technicians involved in the develop- ment, use, and repair of electronic apparatus. Contents Page Foreword to Second Edition . . . . . . . . . . . . . . . . . . . . . . . . . 7 Part One General Information on Integrated Microcircuits 1-1. Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1-2. Structural-Technological Types of Integrated Microcircuits 10 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Housings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1-3. Classification of Integrated Microcircuits on the Basis of Functional Purpose, and Type Designation . . . . . . . . . . . . . . . 23 1-4. Integrated Microcircuit Operating Conditions . . . . . . . . . . . . . 28 1-5. Electric Parameters of Integrated Microcircuits . . . . . . . . . . , 35 Parameters Measured in Units of Voltage . . . . . . . . . . . . . . . 35 Parameters Measured in Units of Current . . . . . . . . . . . . . . . 37 Parameters Measured in Units of Power . . . . . . . . . . . . . . . . 38 Parameters Measured in Units of Frequency . . . . . . . . . . . . . . 38 Parameters Measured in Units of Time . . . . . . . . . . . . . . . . . 38 Relative Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 39 Other Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY Part Tao Reference Information on Digital Integrated Microcircuits 42 Series K108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Series 109 and K109 . . . . . . . . . . . . . . . . . . . . . . . . e . . . . 45 Series 114 and K114 . . . . . . . . . . . . . . . . . e . . . . . . . . . . . 48 Series 115 and K115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Series 121 and K121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 ~ Series 128 and K128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 69 Series 130 and K130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Series K131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Series 133 and K133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Series 134 and K134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Series 136 and K136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Series K137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Series K138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Series K141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Series K144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Series 155, K155, KM155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Series 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Series K158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Series K166 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Series K172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 - Series K176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Series 178 and K178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 - Series 185 and K185 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Series K187 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Series K188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Series 201 and K201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 . . . . . . . . . . Series 202 . . . . . . . . . . . . . . . . . . . 236 Series 204 and K204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Series 205 . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Series 210 and K210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Series 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Series 215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 - Series 217 and K217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Series 218 and K218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Series 221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Series 223 and K223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Series 229 and K229 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Series 230 and K230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Series 231 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Series 240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Series 243 and K243 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Series 263 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Series K500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Series K511 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Three Reference Information on Analog Integrated Microcircuits Series 101 and K101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Series K118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 6 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY Series 119 and K119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Series 123 and K123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Series 124 ana K124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Series 129 and K129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Series 140, K140, KP140 . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Series K142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Series K148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Series 149 and K149 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Series 153 and K153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Series 159 and K159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Series 162 and .162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Series K167 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Series 168 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Series K170 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Series K174 . . . . . . . . . o . . . . . . . . . . . . . . . . . . . . . . 394 Series 175 and K175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 Series 177 and K177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Series 190 and K190 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Series 198 and K198 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412. Series 218 and K218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Series 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Series K224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Series 226 and K226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 Series 228 and K228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Series 235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Series K237 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 Series K252 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Series K264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 Series 265 and K265 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 Series 272 and K272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Series 284 and K284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Series 301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 Series 504 and K504 . . . . . . . . . . . . . . . . . . . . . . . . . . 507 Part Four Methods for Measuring the Electric Parameters of Integrated Microcircuits 4-1. Specific Features of Measuring Microcircuit Parameters 509 4-2. Measuring the Parameters of Digital Integrated Mi.crocircuits 511 General Premises . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Measuring Parameters Given in Units of Voltage . . . . . . . . . . . 512 Measuring Parameters Given in Units of Current . . . . . . . . . . . 516 Measuring Dynamic Parameters Representing Switch-On Delays, Propagation Delays Following Siwtch-On, and Propagation Delays Following Switch-Off . . . . . . . . . . . . . . . . . . . . . . . . 521 4-3. Methods for Measuring the Electric Parameters of Analog Integrated Microcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 General Premises . . . . . . . . . . . . . . . . . . . . . . . . . . 522 Measuring Parameters Given in Units of Voltage . . . . . . . . . . . 524 Measuring Parameters Given in Units of Current . . . . . . . . . . . 533 MeaSUring Parameters Given in Units of Power . . . . . . . . . . . . 538 7 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404030008-6 FOR OFFICIAL USE ONLY Measuring Parameters Given in Units of Frequency . . . . . . . . . . . 539 Measuring Parameters Given in Units of Time . . . . . . . . . . . . . 541 Measuring Relative Parameters . . . . . . . . . . . . . . . . . . . . 543 Measuring Parameters Given in Units of Resistance . . . . . . . . . . 556 Measuring Other Electric Parameters . . . . . . . . . . . . . . . . . 561 Determination of Characteristics . . . . . . . . . . . . . . . . . . 563 4-4. Detexmination of the Interference Resistance of Integrated Microcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 Part Five Integrated Microcircuit Applications 5-1. R,ecommendations on Assembling Integrated Microciruits 564 5-2. Examples of Building Functional Electronic Units Based on Digital Microcircuits . . . . . . . . . . . . . . . . . . . . . . . 568 Series K500 Microcircuits . . . . . . . . . . . . . . . . . . . . . . 568 Series K511 Microcircuits . . . . . . . . . . . . . . . . . . . . . . 600 Series K176 Microcircuits . . . . . . . . . . . . . . . . . . . . . . 637 Series K131, K155, K158 Microcircuits . . . . . . . . . . . . . . . . 653 5-3. Examples of Building Functional Electronic Units Based on Analog Microcircuits . . . . . . . . . . . . . . . . . . . . . . . 758 Appendix 1. Graphical Identification Codes for Logical Elements 771 Appendix 2. Conversion Table for the Identification Codes of Microcircuits Described in This Handbook . . . . . . . . . . . . . . . . . 781 Appendix 3. Index of 'L'ypes of Microcircuits Described in This Handbook 795 Foreword to Second Edition The period since the time of preparation and publication of the first edition of the "Handbook of Integrated Microcircuits" has been typified by swift introduction of integrated mi.crocircuits into general-purpose and control computer complexes; into peripheral equipment; into the data recording and transmission devices of automatic production process control systems; into instruments and equipmen} intended for scientific research and mechanization of engineering and control; into medical and . household instruments; into apparatus for agricultural needs and for environmental control, and so on. Broad introduction of integrated microcircuits into the national economy is promoted by decisions of the 25th CPSU Congress, which determined that: "The main task of the lOth Five-Year Plan is to successively implement the Communist Party's policy of raising the material and cultural standard of living of the people on the basis of dynamic and proportionate development of social production, enhancement of its effectiveness, acceleration of scientific-technical progress, growth of labor productivity, and all-out improvement of the quality of work done in all units of the national economy." Use of integrated microcircuits has made it possible to improve and to create new methods for planning, designing, and producing electronic apparatus of various purposes, to upgrade its technical and operating characteristics, and to introduce 8 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY electronics into a number of devices traditionally designed on the basis of mechanical or electromechanical principles of operation. gut at the same time, the practical experience of the handbook's authors provides the grounds for asserting that inistakes are sometimes made in selecting the nomen- clature of integrated microcircuits when designing and producing electronic apparatus: The conditions of their application are violated; a number of require- ments concerning links between integrated microcircuits are not accounted for, resulting in unstable operation of the electronic apparatus. One of the causes be-hind these mistakes is an insufficient knowledge of the para- meters and operating features of integrated microcircuits on the part nf electronic apparatus developers and manufacturers. - As with the first, the second edition has the goal of acquainting the reader with integrated microcircuits that have enjoyed the greatest application in different types and classes of electronic apparatus (rather than the entire nomenclature of industrially produced microcircuits), and to provide the reader with the minimum volume of information on parameter measurements, assembly, design of electronic apparatus units, and so on. This handbook does not override official documents (operational certificates, specifications, instructions for use), but it does allow the user to review the great assortment of integrated microcircuits being produced hy domestic industry, their parameters, and their operating conditions, to compare them with the require- _ ments imposed on the apparatus, and to correctly select both series-produced and custom-made microcircuits. The microcircuit nomenclature of this edition of the handbook is significantly different from that of the first edition (1977). In particular the composition of series TTL and KMOP microcircuits, series-produced operational amplifiers, and back-up electric power sources have been significantly supplemented as offering major promise today; microcircuits exhibiting high resistance to interference and series-produced superhigh-speed microcircuits employinq emitter-linked logical circuits have been included. Concurrently a number of series-produced micro- circuits enjoying limited use today were dropped from the handbook. The part describing the applications of different classes of microcircuits (TTL, KMOP, ESL, VPL) was expanded, and a reference table of compatible old and new identification codes is provided. The authors feel that separate editions would have to be published in order to provide fuller information on this subject, to include the behavior of integrated circuits in response to changes in temperature and load. The materials presented in this hand'book are based on a generalization of experience in using microcircuits, and on a study of their properties and parameters. The authors hope that this handbook will be useful to engineers and technicians developing and using electronic apparatus based on integrated microcircuits. 9 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404030008-6 _ FOR OFFICIAL USE ONLY The authors request all remarks and wishes for the handbook's improvement should be sent to the following address: 113114, Nbscow, M-114, Shlyuzovaya nab., 10, izdatel'stvo "Energiya". 1-2. Structural-Technological Types of Integrated Microcircuits _ Technology Modern microelectronics is developing predominantly in two basic structural- technological directions--creation of semiconductor integrated microcircuits, and creation of hybrid integrated microcircuits. Semiconductor Microcircuits The technology of their creation is based on a planar process permitting simultaneous manufacture of a large quantity of microcircuits on a single plate of semiconductor material. This process involves: Planar technology making use of semiconductor material, with components isolated by p-n spacing junctions; planar technology making use of semiconductor materials, with components isolated by a layer of silicon dioxide; planar-epitaxic technology, with components isolated by p-n spacing junctions; technology of combined circuits, where active components (transistors, diodes) are created in semiconductor material on the basis of planar technology, and passive components (capacitors, resistors) are created on the surface of the semiconductor material by the methods of thin-film technology. Each of these technological methods has-its advantages in relation to concrete semiconductor microcircuits, but planar-epitaxic technology has enjoyed the greatest successes today. Hybrid Integrated Microcircuits These microcircuits are manufactured mainly with the use of two basic technological processes: Acquisition of thick films by a silk screen method; acquisition of thin films by thermal vacuum plating, etc. Integrated microcircuits manufactured by the silk screen printing method have come to be called thick-film circuits, while those manufactured by the methods of vacuum spray-coating, ion-plasma spray coating, reactive spraying, and so on are referred to as thin-film integrated microcircuits. 10 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFIC[AL USE ONLY Z'he applications of semiconductor and hybrid integrated microcircuits have shown that they do not compete with one another, mutually supplementing one another instead. Housings Integrated microcircuits are made with and without housings. Types of Housings According to GOST [All-Union State Standard] 17467-72, integrated microciruit housings are divided into tour types (Table 1-1). Table 1-1 Housing Type Base Shape 1 Rectangular 2 Rectangular 3 Round 4 Rectangular Location of Housing Terminals Relative to Base On base and perpendicular to it Away from base and perpendicular to it On base and perpendicular to it Parallel to plane of base but away from it Housings are subdivided into type-sizes on the basis of their overall dimensions and connection dimensions; a code is assigned to each type-size, consisting of a digit designating the type housing (1, 2, 3, or 4) and a double-digit ntunber (from 01 to 99) designating the number of the type-size. The identification code for the structure of a housing consists of the housing type-size code, a number indicating the quantity of terminals, and the modification number. For examQle the housing identification code 201.14-2 would mean a type-2 rectangular housing of type-size 01, with 14 terminals, modification 2. The overall and connection dimensions are indicated on drawings (in specifications, handbooks, and microcircuit certificates) without regard to special components or devices used for additional removal of heat from the microcircuit housings, if these devices are not inseparahle parts of the housings. Special components or devices (heat transfer devices) and the means of their attachment are indicated in the technical documents accompanying concrete types of microcircuits. The following terminal spacings have been established for microcircuit housings: For type 1 and 2 housings--2.5 mm; type 3--a 30 or 45� angle; type 4--1.25 mm. Housing terminals may be round or rectangular in shape. As a rule the diameter of round terminals is within 0.3-0.5 mm, while the dimensions of terminals having rectangular cross section lie within the limits of a circle 0.4-0.6 mm in diameter. 11 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00854R000440030008-6 FOR OFFICIAL USE ONLY , Integrated microcircuits of some series developed prior to introduction of the GOST mentioned above arP contained in nonstandard housings. The structure of some types of housings for industrially produced microcircuits and their overall and connection dimensions are shown on pp 12-22. Unhoused Microcircuits P,n unhoused microcircuit is a semiconductor crystal with components created within its volume and on its surface. The crystal is protected by a film of varnish or by a thin layer of sealing compound. Unhoused microcircuits are connected to assembly boards by flexi.ble wire leads with a diameter of 40-50 u, or by rigid ternu.nals having the form of balls or pillars 0.3-0.4 mm in diameter. The structure of un- housed microcircuits is shown on p 22. 1-3. Classification of Integrated Microcircuits on the Basis of Functional Purpose, and Type Designation A GOST effective in the USSR since July 1974 applies to newly developed and modern- ized integrated microcircuits, and it establishes their classification and provides a system of identification codes. In accordance with this GOST, microcircuits are subdivided i.nto three groups on the basis of their structural-technological execution; these three groups are designated as follows: 1; 5; 7--semiconductor; 2; 4; 6; 8--hybrid; 3--other (film, vacuum, ceramic, and so on). The identification code for the type of integrated microcircuit consists of four elements. The first element--a digit indicating the structural-technological execution of the microcircuit (semiconductor, hybrid); the second element--two digits designating the serial number of the microcircuit spries (from 00 to 99); the third element--two letters designating the functional purpose of the micro- circuit, in accordance with Table 1-2 [table not reproduced]; the fourth element--the serial number of the microcircuit, based on the functional characteristic of the given series. Z'he first two elements designate the number of the microcircuit series. The first of three digits in the identification codes of microcircuits developed prior to July 1974 is positioned at the beginning of the type designation, while the second and third digits are placed after the alphabetic index. Alphabetic designations 12 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY of microcircuit functiQn are shown in Table 1-2. Alphabetic designations following the conventions in effect prior to introduction of the GOST are shown in the far right column of Table 1-2. Many microcircuits described in this handbook were developed prior to the GOST's introduction, and their functional designations are presented in accordance with the former conventions. Old and new identification codes representing the same types of microcircuits can be encountered in the literature and in technical documents today. This causes = some difficulty for engineers and techniaians developing and operating electronic apparatus employing microcircuits. COPYRIGHT: Izdatel'stvo "Energiya", 1977, Izdatel'stvo "Energiya", 1980 s izmeneniyami 11004 CSO: 1863/171 13 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY UDC 514.6 NEW AOOK DISCUSSES PARALLEL COMPUTER SYSTEMS Moscow PARALLEL'NYYE VYCHISLITEL'NYYE SISTEMY in Russian 1980 (signed to press 16 Sep 80) pp 2-8 - [Annotation, table of contents, and pref ace of book "Parallel Computer Sys- tems" by B. A. Golovkin, Izdatel'stvo "Nauka", 10,000 copies, 520 pagea] [Text] Annotation This book considers parallel computer systems (computer systems that perform parallel data processing): multimachine, multiprocessor, mainline (con- veyor), matrix, associative, combined and variable structure types, and a few other systems. Systems of these types are distinguished by greater flexibility and have high productivity and reliability. The book is a systematic description of the organization of the structure and functioning of parallel computer systems. This descriptton presents structural diagrams and baeic characteristics of several dozen domestic and foreign parallel computer systems. The book is intended for engineers and scientific workers in the fields of _ computer technology, programming, and data processing as well as advanced undergraduate and graduate students in the corresponding fields. Table of Contents Page Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 1. The Evolution of Computer Systems: From Sequential to Parallel Systems . . . . . . . . . . . . . . . . . . . 9 1.1. The Evolution of Single-Processor Systems . . . . . . . . . 9 1.1.1. Parallel Processing of Word Formats. Combining the Process of Input-Output and Computation . . . . . . . . . . . . . . . . . . 9 1.1.2. Combining Operations and Advance Scanning of = Comands and Data . . . . . . . . . . . . . . . 11 14 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY Page 1.2. The Evolution of Multimachine aud Multiprocessor Systems (Using the Example of IBM systems) . 14 1.2.1. Early Multimachine Systema with Indirect Linkage . . . . . . . . . . . . . . . . . . . 14 1.2.2. Early Multimachine Syatems with Direct Linkage. The DCS System . . . . . . . . . . 15 1.2.3. Weakly and Strong].y Linked Systems 16 1.2.4. Multimachine System with AST Auxiliary Processor . . . . . . . . . . . . . . . . . . 17 1.2.5. Structures of Mulrcimachine and Multiprocessflr Systems. Developmental Trends . . . . . . . 19 1.3. Brief Survey . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 2. Organization of the Structure and Functioning of Parallel Computer Systems . . . . . . . . . . . . . . . 24 2.1. Classification of Computer Systems . . . . . . . . . . . 24 2.1.1. Characteristics and Diagram of the Classification. Notation of Classes. 25 2.1.2. Description of the Classes of Computer Systems . 26 2.2. Flows of Commands and Data. Word and Bit Processing. - Basic Structures and Definitions . . . . . . . . . . . 28 2.2.1. Single and Multiple Flows of Commands and Data . . . . . . . . . . . . . . . . . . 28 2.2.2. Word and Bit Processing . . . . . . . . . . . . 31 2.2.3. Basic Structures and Definitions . . . . . . . . 32 2.2.4. Switching Flows of Commands and Data 38 2.3. Some Basic Relationships Among Structures of Computer Systems . . . . . . . . . . . . . . . . . . 42 2.4. The Structure of Linkages in Parallel Computer Systems . 47 2.4.1. Interprocessor Linkages in Computer Systems and Networks and Their Classifications 47 2.4.2. Internal Linkages in Multiprocessor Systems 53 2.5. The Structure of Linkages Between the Central Part of Computer Systems and Input-Output Channels 55 2.5.1. Basic Types of Linkage Structure 55 2.5.2. Interlinking with Peripheral Units 61 2.6. The Structure of Multiprocessor Systems with High- Level Language . . . . . . . . . . . . . . . . . . . . 68 2.7. Brief Survey . . . . . . . . . . . . . . . . . . . . . . 79 2.7.1. Survey of Monographs, Anthologies, and Surveys . 80 2.7.2. Survey of Classification Schemes and Struc- tures of Parallel Computer Systems 89 Chapter 3. Multimachine and Multiprocessor Systems Based on Single- Processor Computers . . . . . . . . . . . . . . . . . . 99 3.1. Conception and Early Systems . . . . . . . . . . . . . . 99 3.1.1. The Conception of Aggregating Single- Processor Computers . . . . . . . . . . . . . 99 3.1.2. The Minsk-222 System . . . . . . . . . . . . . . 101 - 15 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY Page 3.1.3. The KLASS System . . . . . . . . . . . . . . . . . 103 3.1.4. The Dnepr-2 System . . . . . . . . . . . . . . . . 104 3.2. Systems Based on the BESM-6 Computer . . . . . . . . . . . 106 3.2.1. The Structure of the BESM-6 Computer 106 3.2.2. Iriultimachine Systems Based on the BESM-6 Computer . . . . . . . . . . . . . . . . . . . 109 3.2.3. Bibliographic Reference . . . . . . . . . . . . . 117 3.3. Systems Based on the YeS Family of Computers 118 3.3.1. Structure of the YeS Family of Computers 118 3.3.2. Multimachine and Multiprocessor Systems Based on YeS Computers . . . . . . . . . . . . . . . 123 3.3.3. Bibliographic Reference . . . . . . . . . . . . . 136 3.4. Systems Based on the ASVT-M and SM EVM Families of . . 137 Computers . . . . . . . 3.4.1. Structureof the ASVT-M.and�SM EVM Families 137 3.4.2. Multimachine and Multiprocessor Systems Based on ASVT-M and SM EVM Computers 146 3.4.3. Bibliographic Reference . . . . . . . . . . . . . 149 3.5. Systems Based on the IBM 360 and IBM 370 Familiea of Computers. The IBM 303X Family. . � � � � � � � � � 150 3.5.1, The Structure of the IBM 360 and IBM 370 Families. 150 3.5.2. Multimachine and Multiprocessor Systems Based on Computers of the IBM 360 and IBM 370 Families . . . . . . . . . . . . . . . . . . . 153 3.5.3. The IBM 360/67 System . . . . . . . . . . . . . . 156 3.5.4. The IBM 360/65 MP, 370/158 MP, and 370/168 MP . 158 Systema . . . . . . . . . . . . . . . . . . 3.5.5. The IBM 303X Family and New Levelopments at the IBM Company . . . . . . . . . . . . . . . o . . 160 3.5.6. Bibliographic Reference . . . . . . . . . . . . . 162 3.6. Systems Based on the DEC PDP-11 Family 164 3.6.1. Structure of the PDP-11 Family . . . . . . . . . . 164 3.6.2. Multimachine and Multiprocessor Systems Based on the PDP-11 Family of Computers 167 3.6.3. Bibliographic Reference . . . . . . . . . . . . . 169 Chapter 4. Multipro cessor Systems . . . . . . . . . . . . . . . . . . . 171 171 4.1. Concept ion and Early Systems . . . . . . . . . . . . . . . 4.1.1. Development of the Conceptions of Multi- processor Systems . . . . . . . . . . . . . . . 171 176 4.1.2. The RW 400 System . . . . . . . . . . . . . . . . ' 4.1.3. The D825 System . . . . . . . . . . . . . . . . . 177 180 4.1.4. The CDC 3600 System . . . . . . . . . . . . . . . 4.1.5. The PHILCO 213 System . . . . . . . . . . . . . . 183 1.6. 4 The LARC System . . . . . . . . . . . . . . . . . 184 . 4.1.7. The PILOT System . . . . . . . . . . . . . . . . . 187 4.1.8. The GAMMA 60 System . . . . . . . . . . . . . . . 189 4.1.9. The STRETCH System . . . . . . . . . . . . . . . . 190 4.1.10. Basic Points of the Conception of Organizing Multiprocessor Syatems . . . . . . . . . . . . 192 4.1.11. Bibliographic Reference . . . . . . . . . . . . . 200 16 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY Page 4.2. Systems of the E1'brus Family . . . . . . . . . . . . . . 201 4.2.1. Conception of the Structure of Systems of the E1'brus Family . . . . . . . . . . 201 4.2.2. Structure of the Systems of the E1'brus Family . 205 4.2.3. Bibliographic Reference . . . . . . . . . . . . 213 4.3. Burroughs Company Systems . . . . . . . . . . . . . . . . 214 4.3.1. Conception of the Structure of Systems from the Burroughs Company . . . . . . . . . . . . 214 4.3.2. Structure of Systems from the Burroughs Company . . . . . . . . . . . . . . . . . . . 217 4.3.3. Bibliographic Reference . . . . . . . . . . . . 228 4.4. Systems of the UNIVAC 1100 Family . . . . . . . . . . . . 229 4.4.1. Structure of the UNIVAC 11u0 Family 229 - 4.4e2. The UNIVAC 1108 and 110'4) Systems 232 4.4.3. The UNIVAC 1110 System . . . . . . . . . . . 237 4.4.4. The UNIVAC 1100/10, 1100/20, 1100/40, and 1100/80 Systems . . . . . . . . . . . . . . . 239 4.4.5. Bibliographic Reference . . . . . . . . . . 244 4.5. Systems of the DEC System 10 Family . . . . . . . . . . . 245 4.6. Syatems fram the Honeywell Company . . . . . . . . . . . 250 4.7. The SYMBOL System . . . . . . . . . . . . . . . . . . . . 256 Chapter 5. Mainline Systems . . . . . . . . . . . . . . . . . . . . 261 5.1. Conception and Early Systems . . . . . . . . . . . . 261 5.2. Systems from the Control Data Conpany . . . . . . . . . . 265 5.2.1. The CDC 6600 and 7600 Systems and Other Systems of the CDC 6000 and 7000 Families 265 5.2.2. Systems of the CYBER 70 and 170 Families 273 5.2.3. The STAR 100 System . . . . . . . . . . . . . . 277 5.2.4. Bibliographic Reference . . . . . . . . . . . . 280 5.3. The IBM 360/91 and 360/195 Systems . . . . . . . . . . . 282 5.4. The MUS Sys tem . . . . . . . . . . . . . . . . . . . . . 285 5.5. The ASC System . . . . . . . . . . . . . . . . . . . . . 288 5.6. The AIrIDHL 470 V/6 System . . . . . . . . . . . . . . . . 292 5.7. The CRAY 1 System . . . . . . . . . . . . . . . . . . . . 296 Chapter 6. Matrix, Associative, and Similar Systems 303 6.1. Conception and Early Systems . . . . . . . . . . . . . . 303 6.2. The M-10 Computer System . . . . . . . . . . . . . . . . 307 6.3. The PEPE System . . . . . . . . . . . . . . . . . . . . . 311 6.4. The ILLIAC IV System . . . . . . . . . . . . . . . . . . 318 6.5. The BSP, DAR, IBM 3838, and Other Matrix Systems 327 - 6.6. The STARAN System and Other Associative Systems 339 Chapter 7. Systems with Combined and Variable Structure. Trouble- - Free Systems . . . . . . . . . . . . . . . . . . . . . 354 7.1. Construction and Early Systems . . . . . . . . . . . . . 354 7.1.2. The Application of Microprocessors 357 _ 7.1.3. The Conception of Systems with Variable Structure . . . . . . . . . . . . . . . . . . 358 17 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY Page 7.1.4. The Conception of Resistance by Computer Systems to Malfunction . . . . . . . . . . . . 362 7.2. Systems with Combined and Variable Structure . 368 7.2.1. Systems of the OMEN 60 Family . . . . . . . . . . 368 7.2.2. The MINIMAKS System . . . . . . . . . . . . . . 371 7.2.3. The SUMNIA System . . . . . . . . . . . . . . . . 374 7.2.4. Bibliographic Reference . . . . . . . . . . . . . 376 7.3. Trouble-Free Systems . . . . . . . . . . . . . . . . . . . 377 7.3.1. '1'he JPL STAR and UDS Systems . . . . . . . . . � 377 7.3.2. The PLURIBUS System . . . . . . . . . . . . . . . 382 7.3.3. The TANDEM 16 System . . . . . . . . . . . . . . 386 7.3.4. The C. mmp, Cm*, and C vmp Systems . 387 7.3.5. The COMTRAC System . . . . . . . . . . . . . . . 396 7.3.6. The FTNIP and SIFT Systems . . . . . . . . . . . 399 7.3.7. The Computer System of the Shuttle Spacecraft . . 404 7.3.8. Bibliographic Reference . . . . . . . . . . . . . 421 Chapter 8. Quantitative Characteristics of System Structures. Productivity and Costs of Systems. . . . . . . . . . . . 422 8.1. Quantitative Characteristics of the Structures of Computer Systems . . . . . . . . . . . . . . . . . � � 422 8.1.1. Formalization of the Description of System Structures . . . . . . . . . . . . . . . . . . 422 8.1.2. Operations on Formal Descriptions of System Structures . . . . . . . . . . . . . . . . . . 432 8.2. The Productivity and Cost of Parallel Computer Systems . . 436 8.2.1. Estimation and Prediction of Increase in the _ Productivity of Parallel Computer Systems . . 436 - 8.2.2. The Relationship Between Productivity and , Cost of Computer Systems . . . . . . . . . . . 447 8.3. Brief Survey . . . . . . . . . . . . . . . . . . . . . . . 451 . . 460 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 Subject Index . . . . . . . . . . . . . . . . . . . . . . . . . . . Preface This book considers multimachine, multiprocessor, mainline (conveyor), asso- ciative, and matrix systems, systems with vector flow of data and ensembles of processors, as well as systems with combined and variable structure. The substantial interest in the systems and their importance are a result of the fact that they have great flexibility and provide high and record levels of productivity, reliability, readiness, and survivability. The ratio of the productivity of these systems to their cost has increased significantly in recent years, which is especially important for broadening their area of application. In the near future we expect a significant expansion of the development of the types of computer systems under consideration, an increase in their production, improvement in performance, and an expansion of the sphere of 18 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY application, particularly in connection with the development of micro- proceasor technology and the technology of large integrated circuits. The rapid development of diverse and complex computer systems ie bringing about change and greater precision in terminology and the appearance of new concepts. This is particularly typical of the area of computer technology under consideration here. Under such conditions terminology causes aub- stantial problems. In writing this book I have used the terminology~that , is most widespread, even though in many cases it is not generally ac- cepted and established. The title "Parallel Computer Systems" (computer systems fQr parallel data processing) was selected to describe the computer systems in the book. A distinctive feature of the system reviewed here is that they have at least two control units or central processing units which work simultaneously. As a result, the central part of these systems has at least two parallel flows of commands or data. Additionally, the programming methods and computer mathematics techniques for these systems in most cases are called "parallel." Therefore, by selecting the word "parallel" as a basis, it is possible to speak with adequate clarity about the means and methods of parallel data processing - parallel computer systems, parallel programming, and parallel computer methods. Nonetheless, we will not have complete clarity because, for example, there are also elements of parallel data processing in single- processor computers: parallelism in processing word bits in the arithmetic-logical unit; merging the work of computer units in time; ad- vanced scanning of commands and data, and others. The first chapter of this book describes the evolution of computer machinea and systems from sequential data processing to parallel processing. The second chapter offers a systematic presentation of the organization of the structure and functioning of various types of parallel computer sys- tems. The last chapter considers the numerical characteristics of the structures of computer systems, evaluation and prediction of increase in the productivity of parallel computer systems, and the ratio of their prc,ductivity to their cost. The other chapters contain concise descrtp- - tions of several dozen typic2l parallel computer systems of different types. Primary attention here is devoted to standard operating and very recent systems. A number of typical early systems and conceptions of parallel computer systems are also described. The description is oriented to the organization of the structure and functioning of computer systems and illustrated with structural diagrams of ttxe systems. Figure 0.1 [not reproduced] diagrams the logical connections among chapters of the book. Several thousand works have been published in the subject area of parallel computer systems. In a book of limited scope it is impossible to review such a number of books or even to list their titles. To make it easier for readers to familiarize themselves with the literature on parallel com- puter systems and study them more thoroughly, the book includes a brief survey and bibliographic references on parallel systems which are found in the corresponding sectionS. 19 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 FOR OFFI('IAL USE ONLY The book assumes that readers will be familiar with the fundamentals of the organization of computer structures and is intended for engineers and scientists in the fields of computer technology, programming, and data processing as well as for advanced undergraduate and graduate students in the corresponding special areas. COPYRIGHT: Izdatel'stvo "Nauka", Glavnaya redaktsiya fiziko-matematicheskoy - literatury, 1980 11,176 CSO: 1863/147 20 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00854R000400030008-6 FOR OFFICIAL USE ONLY BASIC CONFIGURATIONS OF MULTIPLE MACHINE YeS SYSTEMS Moscow PARALLEL'NYYE VYCHISLITEL'NYYE SISTEMY in Russian 1980 (signed to press 16 Sep 80) pp 118-135 - [Section of Chapter 3 of book "Parallel Computer Systems" by B. A. Golovk3n, - Izdatel'stvo "Nauka", 10,000 ccopi.es, 520 pages] _ [Text] 3.3. Systems Based on the YeS Family of Computers 3.3.1. Structure of the YeS Family of Comguters [218, 244, 246, 429] The YeS [Unified System] of electronic computers is a family of program- compatible stationary third-generation computers* which have a broad range of productivity levels and are designed to perform various scientific- technical, economic, management, and other jobs. Collectives at scientific - research institutions and enterprises of the CEMA countries of Bulgaria, Hungary, East Germany, Cuba, Poland, Romania, the USSR, and Czechoslovakia are working on building the Unified System of computers. Industrial produc- - tion of the first machines was begun in 1972. At the present time YeS com- puters comprise the bulk of the computers used in the socialist countries. The program compatibility of the family of computera is achieved by uniform formats and form of data notation, addressing systems, and set of commands and an identicai structure in all the models of computers included in the Unified System. The computers of the family are compatible from the bottom up, that is, programs written for machines with lower productivity can be run on machines with higher productivity. The center of the Unified System is its processors, which cover the range of computation speed between a few thousand operations a second and several million. The processor performs operations with fixed and floating points and operations on decimal numbers. Several formats are adopted for data and commands based on the byte and four-byte word. Operations can be per- formed on half, whole, and double words as well as fields of variable length to a maximum of 256 bytes. The Unified System has adopted byte addressing with a 24-bit address. This makes it possible to form a direct address for access to memory with a maximum capacity of 16,777,216 bytes. Commands may * The YeS-1010 and YeS-1021 machines differ in structure and command systems from the other computers of the Unified System. 21 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY have 0, 1, 2, or 3 addresses depending on the format (2, 4, and 6 bytes). The full standard set of commands contains 144 commands. The main memory volume varies greatly in the different models. Some models use alternation of addresses in memory blocks operating in parallel. The processor has 16 general-purpose registers with a capacity of one word apiece. Four registers with a capacity of two words apiece are included in the processor to perform operations of greater precision with a floating point. The processors have an elaborate interrupt system. In ad4ition, a timer and means of aggregating are included in the processor. The Unified System also uses the parallel-sequential principle of per- formance of operations, for example single-byte data processing with two- byte retrieval from the main memory of the YeS-1020 machine. Selector and multiplex channels are connected to the processor. Their number and carrying capacity, as well as the set of external units con- nected to the channels, will depend on the particular model. Among the external units are magnetic tape, disc, and drum stores, punched card and punched tape input-output equipment, line printers, typewriters, screen consoles, and graph plotters of various types. Equipment is also envi- sioned to transmit data at different speeds bq telephone and telegrapfi communications lines. The structure of a YeS computer is shown in Figure 3.8 below [245]. The software of the Unified System is based on the YeS DOS [disc operating system] and the YeS OS [operating system], which can be used on all program compatible models. The operating systems provide multiprogram work. The YeS-1010 and YeS-1021 (YeS-1020A) models differ from the other models in structure and system of comands. They also differ from one anotfier, so they have their own software. The YeS OS-10 operating system has been de- veloped for the YeS-1010 model, while the YeS MOS small operating system has been worked out for the model YeS-1021. Let us go back to the YeS DOS and OS operating systems. There are several versions of the operating systems. The DOS is oriented to junior models of YeS computers with limited main memory volume (64-128 kilobytes) and af- fords maximum efficiency when used with these models. The YeS OS system is more general in application and powerful in its functtons, significantly surpassing the YeS DOS. It is used on models which fiave main memory volume of more than 128 kilobytes, and demonstrates its full capabilities wtth. computers that have medium and large main memory and adequate external memory. The YeS OS system has a clearcut modular structure which makes it more promising for expansion as the hardware of tTie Unified System is refined and accumulated. The YeS OS offers the possibility of paralleling computing processes and includes support equipment for aggregating to set up multimachine systems. One of these means is a channel-channel adaptor which makes it possihle. to 22 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000440030008-6 FOR OFF[CIAL USE ONLY (2) CUC/11EMQ BBOaQ-Bb/BOaQ KaNWa eeoaa-aerevd 3 � Munununniunv/vii _ 16M /YOMMb~ ( ~ ~ CeneKmap,vae - a E kaNana(15 ) ^ ~-~q KNI ' - /lparooeynpoenenue . (nenacpeBcmeeaNOa e~aur~oBeucineue c ~ 22 ) aHeUHUHU ocFaeKmanaJ 4) : /lynnm anepamopa( 23 ) _ Figure 3.8. Structural Diagram of a YeS Computer. Key: (1) (2) (3) (4) (S) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) Processor with Main Memory; Input-Output System; Input-Output Channels; Addresses; Main Memory; Multiplex Channel (128-256 subchannels) of the Command; Commands; Type of Operation; Control Units; Arithmetic-Logical Unit; Sign of Result of Operation; Operations with Fixed Point; Operations with Words of Variable Length and Decimal Numbers; Floating Point Operations; Selector Channel; Standard Input-Output Interface; Control Unit; External Units; Program Interrupt System; General-Purpose Registers; Floating Point Registers; Direct Control (direct interaction with external objects); Operator Console; Signals from External Actions, the Timer, Monitoring Circuits, and the like. - connect directiy channels of two (different) YeS computers, external memory _ units being used togetheY, and direct control devices. Using this equipment 23 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404030008-6 FOR OFFICIAL USE ONLY the user may construct various configurations of multimachine systems, em- ploying the aggregating software [377]. The operating systems include control and service programs, translators from programming languages (usualJ.y included in a particular programming system), system generation means for a particular set of hardware, and other equip- ment. The input languages adopted are Assembler, Fortran, PL/1, Cobol, Algol 60, and RPG (Report Program Generator).* The system has debugging and program editing units. The software also includes a large number of packages of different applied programs. In terms of input languages the DOS and OS systems are sufficiently compatible, but they are not compatible with respect to object programs received, that is, programs received by means of the programming system of one operating system cannot be performed under the control of the-other operating system. At the present time the computers of the Unified System are computers of the first and second phases of production (series one and series two). The machines of the first phase are close in architecture to the macfiines of the IBM 360 family, and the YeS computers have program succession (preser- vation of the system of commands and principles of organizing external ex- change and the operating environment of the IBM 360). Second-phase machines are similar in architecture to the machines of the improved IBM 370 family. Second-phase machines preserve program succession in relation to first-phase machines and have a broader system of commands. This expansion concerns chiefly commands for the operating system (privi- leged commands), but the number of coumiands for users increases only slightly (the YeS-1035 machine, for example, has 172 commands). Tiie pre- cision of computation is higher and other improvements have been introduced. Second-phase machines have improved logical structure over first--phase machines, as well as expanded monitoring and diagnosis equipment and better technical parameters. Their basic elements have higher characteristics than the integrated circuits of first-phase computers. The second-phase machines have a maximum productivity in the central processors of the family of up to 4-5 millir,, operations a second, the capacity of main memory has lieen in-- creased t:o 16 megabytes, and virtual addressing has heen introduced. It is important to observe that whereas machines of the first phase had a few units for aggregating to make multimachine systems, second-phase machtnes have broadened capacities for multimachine and multiproceasor organization of computer systems. As a result of these steps, the transition from phase one to phase two should provide an improvement in the productivity-cost ratio of 2-3 times and approximately double their reliability and survivability. * The Algol 60 translator is included in the Ye.0 OS. 24 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY _ Table 3.2 below gives the basic technical characteristics of Unified System computers of phasea one and two [246]. It should be noted that different values are given in the literature of various yeare L"or certain computer characteristics. The transition to phase two also involves an improvement in YeS soft- ware because it provides virtual memory, an expansion of the complement of translators and libraries, development of time-sharing regimes, dialog forms of interaction, remote processing means and means of insuring a real-time regime, the organization of data banks, development of problem-oriented programming systems, support for multimachine and multiprocessor systems, and the like. The operating system affords the possibility of combining up to four computing systems, each composed of a two-processor system; into a siiigle complex [246]. The YeS-1065, for example, as the basic general-purpose variant provides a two-processor complex. A four-processor variant is also envisioned, but only for special applications, where there are good opportunities for paralleling computations. The basic work on phase two of the Unified System in 1977 reached the final stage of technical design and preparation to submit a significant number of experimental models of hardware for testing [246]. The new YeS machines, including the YeS-1060 which has a productivity of more than 1 million operations a second, were tested in early 1978. The later and more powerful YeS-1065 works at more than 4 million operations a second [61]. Continued and comprehensive improvement of the Unified System of Computers is planned through development of phase (series) three using integrated cir- cuits with a high level of integration as the basic element. Tab1e 3.3 below shows the basic characteristics of the hardware and software of YeS computers of phases I, II, and (planned) III [246]. - 3.3.2. Multimachine and Multiprocessor Svstems Based on YeS Computers. It _ follows from a consideration of the structure of the YeS computers tfiat during development of the YeS computer hardware and software provision was made for aggregation at the levels of the processor, channels, external memory (external units), and main memory. Multimachine systems are built by aggregation at the levels of the processor, channels, and external memory. This is typical of the small and medium-sized YeS models of Phase I. With aggregation at the level of main memory, preserving the capabilities of aggregation at other levels (all YeS models provide aggregation at the level of channels and/or general external units), multiprocessor systems are de- veloped. This is typical of the YeS-1050 and Phase II models. We should note that the logical structure adopted for the YeS system of computers in principle allows processors to work with a coffinon main memory field, although program organization of such a regime is fundamentally more difficult than interaction of processors at the level of external equipment. 25 F'OR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY 0 14 h I > pq ~ ~ P~ PD P4 p4 CJ r-1 00 0 b0 >1 a 11 rl �rl ul ~ U N U O O O O O O O O O O O O O O fa N 1J 01 I I I 0~1000 000 ~100000 ' N ~H 14 124 >1 ~ c'r1 N u1 00 00 ~t 00 00 1 N M cn V1 u1 u ~ Cl .C t--I ~ V O z N.-i N rl cn M M-:r %O v1 %O ~t %.C ~ 0 G1 Ol cd b0 P6' ~i~ c ~u a u %ooo %otno%~r oooo 000000 c~, c-, '-1 r, ao cV .t .t ~ r, 0 Ln o A. ~ ~ F+ P. ~ -I c r ,-I cti cd ~ ~ U ~ ~ V 1 � r-I i-1 r-1 r-I e-1 N N N O V ~ p Q y ~TOpp 'p, tN'CNNNN ItN~t00N~t fl~ ~ G! 41 lZ N%0 U1 %D r--I u'1 r-I r-i r-I i-1 N I- NIT O% N y ~ y >1 r--I r-I N v1 u1 N u1 u1 v1 U1 O O O O H M ~ ~ ^ A4 w w w w w w rl c~1 ~--1 N 00 0 ~I-1 '1~ ~ ~ ~ ~ > 14 O U w 0 0 0 C) Ow 0 Ow 00000 0 0 ~ ~ O ~ cV~ 00000000 0 O0 0 O }a p C! r-1 00 N 0M00000 0000 00 ~ (p w w ~ M%G O ~ w ~ w w w w w 00000000 w w w w w w 000000 U U Cl O ON 0 %0 %000-4 000000 ' ~ 0 p, O O O N Nr-1 Ln ul kD M u 1 ~ ~ r~ p O w N w Ow O w w ,C H r-1 r-1 00 U W r-I � G! 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P. ~ ~ c� v ooo o~ x uo4 uc+: 9 aG +1xa-w ocw > q ~n CI v~ 4) v~ ~tn ~n m cn cn a~ ~n tn d fn fA c1 VJ Cn A xxx ~ N 0 Ntn O f/] 0 ~~~u M) a=) ~D l w::) :n w::) :z) r-I N tr'1 ~7 v1 IO r, 00 O' O ~ z r-,I r-1 r-1 r-I rl rl r-I 26 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000400030008-6 FOR ()HFIC'IA1, IISH: ONLY y. ~ ~ ~ Ol ~ ~ 'd N M w M-1 ~ N .~C -W 44 O ~ ~ O u c~ u ~ b G H u ~ 0 0 0 u W I ~ ~ u ,a ~ x u w H ri 14 N r-1 ~ H -W m ~ rn ~ ~i ~I ~ d L~J H W O! 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' y ~U ~ H r l d w ~ � c d u 0 c d ~ w b ~ H V 1 a m 0 R � 41 ~ + o ~ a~ o cnau cn wa 3 ~ eo 0 a o b k H 13 $4 0 d m .a ~ ~ O -H ON ~baU3 a H ~ N U N ~ ~ ~ 'U G l Ci ~ -I r ~ H O H 41 r -I cnWOU ~ I oa a u wM ~ c 0 0 u N w M q t t! ~ ,a 41 R a ~ o . O U rl 0 ~ ~ a i i a V ~ p ~ ~ d1 ' A Cl 40 ~4j 1 N 7 i~ u a) ~ ri O U W O w~l GD ~ cn O N a~ APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY ~ bo 1 ~ 3 ~ c d co H a0 `e ~ a o W U ~ A C! 4-I 1 ~ l r M " 41 4) 0 ld td c0 :3 4 ouaa+~~ ~ co a F' ~ o ~ c b . U ~ a H l 1~ -ri r cd q ~U1~.iW.-H[+W A ~ ~ ~ P H W .r 10, W ~ :1 N 'r'~ f3 C1 N 14 � m p a ~ u a 0 ~ w u p, ] aai 4 1 U H H H W D+ W W 41 H O 1. Q ~ ~ p ~ O m ~ cd ~ O cd rl c0 A C~ m a ~ H ~ a a ~ 4 ~ o ~ g b iC rl 0! H Q ~ p W 3 C7 ~d ~ ri q ~ H A 1 93 0 O E ~ cd ~ w 4 a ~ ~ o m ~ ~ d cn H 10 ~ ~ r a Cd m A b ~ 'b a) b ~ 0 a i a ~ - " ''i cn ,.i w o ~ 0 m a~ ~ U ~ 0 y ~ ~ U O W u M ~ ~ ~ v a n o a~ ~ r-A ,n , o . ~y ~ H $4 d) v x u a, 20 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-44850R444444434448-6 FOR OFFtC'IA1. USE ONLY Work with a common main mmeory ia more important for highly productive ma- chines and is not envisioned for such machines as the YeS-1020, YeS-1030*, and YeS-1040 [238]. The most popular aggregation schemes have been two machine configurations for multimachine systems and two-processor configurations for multi- processor systems because they are simple, improve reliability, aad make it possible to raise productivity. The typical aolution when a signifi- cant increase in productivity is required is to switch to a senior model relative to the one in use. This solves the problem up to the highest model. At the same time, provision is made to aggregate more tban two models. This may be necessary, for example, in special applications. - Let us consider the means of aggregation at each of theae levels [142, 2471. Direct control means, which include the commands DIRECT WRITE and DIRECT READ, provide exchange of control and synchronizing data among processors of a computer system or between the processor and an external unit. Oae of the processors may be connected with another processor or unit by means of the commands indicated above and an external interrupt mechanism. T[ie physical linkage between the processors is accomplished by direct control interface cables. A computer complex control console may be connected to the direct control line linking the two processors. This enables the oper- ator to follow and modify the working regimes of the computers and tfie complex (aggregate unit). An adaptor is used for aggregatiag at the channel level. It has two out- puts to a standard input-output interface and is connected to the selector (or multiplex) channels of two YeS models. The speed of data transmission through the adapter is close to the speed of data trans- mission through the channel. When the computer complex is in operation the speed of exchange is in fact determined by the speed of exchange through the channels if they are the same or the speed of the slower channels if they are different. The adapter in the channel works in a single-field regime. The adapter provides rapid exchange among processors of both control information and arrays of data. Ttao-channel switches are used for aggregation at the level of external mag- netic disk and tape memory.** The two-channel switch makes it possible to connect the magnetic tape and disk store control units to two cfiannela of different computers, which forms a common memory ffeld in the storage units they control. The work of a particular computer with the common exterctal memory field is coordinated by special commands to the two-channel switches which reserve (or connect) the unit for the tiffie it is working with the particular channel and free it after this work is completed. Because the * The main memory equipment of the YeS-1030 model can be distributed among processors of the multiple system, forming a common memory field [142]. This procedure is also called aggregation at the level of external unit control devices. 29 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY receipt and output of data by processors in this case is spread out over time, unproductive use of time by the pair of processors to interact with one another is reduced. However, this also reduces the speed of exchange compared to connecting channels by means of an adapter. Where a two-channel switch is used aggregation is accomplished in fact at the level of the control units of external memory units. Aggregation is also possible at the lower level of the external memory units tfiemselves by using a two-directional switch. Finally, both methods can be used to aggregate input-output units. Connecting the processes through a common main memory field is the most flexible and fastest method. The comnon main memory field is organized on the principle of constructing a multimachine multi-input memory. We should also note that it is possible for processors to interact by telephone and telegraph communications channels. Now let us consider certain examples of aggregating models of YeS com- puters. We will begin with the YeS-1030 machine [437]. With the YeS-1030 computer it is possible to realize these multimachine systems: consisting of two computers connected by direct control lines; consisting of several computers with access to a common external memory field; consisting of several computers connected by a channel-channel adaptor. In the systems in which two computers are connected by direct control lines exchange of information is usually accomplished by direct control commands. On these commands one byte of information is transmitted from one processor and interrupts the work of tfie other processor. This or- ganization of the complex is efficient only in those cases when the volume and speed of data transmission are low. When a multimachine system is organized connected by a common external memory field, data transmission by one processor and receipt by the other is not simultaneous, so the productivity of the interlinked computers is - not reduced. Therefore, this kind of organization is more efficient tfian linking by direct control lines. When a multimachine system is organized using a channel-channel adaptor, direct communication between computer channels is accomplished through a standard interface. Information exchange is carried on by bytes at a speed determined by the carrying capacity of the channels. By aggregating two YeS-1030 computers it is possible to realize the two- machine system knoc�+n as the VK-1010 computer complex [437]. The VK-1010 consists of two YeS-1030 computers interconnected by direct control lines through the state block of the computer complex, tfie separ- ate external units, and a channel-channel adaptor. Figure 3.9 below ahows the structural diagram of the VK-1010. 30 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-44850R444444434448-6 FOR OFFICIAL USE ONLY I 6CBK E ^r -q ' kaNa.# . ~ b (8) _(9~ Y N~Q YH/`~Q Y HM/1 H lO)cKuffc~p)�= 9) � ~ e LAKK- J 10) ~ m ~ K HPI,Q(12yr HM,q . ~14~NMA(12,~f1~`1,4 ~ � . ~ . ~ , YYH AKK-3 yyy~ HM/!~(14) (12) _ Figure 3.9. Structural Diagram of the VK-1010 Key: (1) Control Console of Computer Complex; (2) Main Memory of YeS-1030; (3) YeS-1030 Processor; (4) State Bleck of Computer Complex; (5) YeS-1030 Processor; (6) Main Memory of YeS-1030; (7) Channels; (8) New Input-Output Unit; (9) T~ao Other Systems; (10) Control Unit of Magnet Disk Storage; (11) Channel-Channel Adaptor [with appropriate number]; (12) To Magnetic Storage; . (13) Control Unit of Magnetic Tape Storage; (14) To Magnetic Storage; (15) Multiplex Channel; ' (16) Selector Channel [with appropriate number]. If both machines are in working condition, the computer complex has three possible work regimes. In the first regime both machines receive infor- mation from external units and process it, but only the primary computer outputs information. The other computer, therefore, backs up the first. If the primary computer is not able to perform its functions, the re- serve computer assumes them in full. In the second work regime of the computer complex the functions of the primary computer are kept, but the reserve computer is taken out for preventive maintenance. In this regime work is done without a back-up unit. If the primary computer goes down, the maintenance work on the second computer can be tnterrupted and it can 31 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00854R000440030008-6 FOR OFFICIAL USE ONLY be put in a working regime (but this takes more time than for the firat work regime). Finally, both computers can work as independent units; this is the third work regime of the computer complex. The current state of each computer is registered in the form of a state byte and stored in main memory and the registers of the state block of the com- puter complex. The operator assigns the work regimes of the computers of the VK-1010 and switches them to the required state from the control con- sole of the complex. It is also possible to change the state byte of the computers of the complex by program means using direct-control commands. The state block of the computer complex is designed to store and modify the state of the machines of the VK-1010. It ia connected with the com- puters by two standard direct-control interfaces. The channel-channel adaptors are designed to transmit arrays of data between the input-output channels of the machines of the VK-1010 and also for communication with other computers or aystems (see Figure 3.9). The adaptor works in a single-field regime and transmits data at the speed of the slower channel of the two that are connected. For each channel to which the adaptor is cor_nected, it is the external unit control device which is selected by the channel, receives and decodes channel commands like any external unit control device, but differa from them because it uses these commands not for work and control of the input-output unit, but rather to main- tain communications among channela and to synchronize their work. Figure 3.10 below shows the structural diagram of an adaptor. It includes two control blocks, each of which serves its own channel. Tfiese blocks are interconnected both directly by means of several signal lines and through a common eingle-byte buffer register. 3BM-1~ 1~. ABanmep Kayan-koaan( 3) I~'BM Z(2) 670,r I 16vmeavrul _I ftK KOHOA I I f P~ t~. I I..U.~~ ~ 1�M,7Z Figure 3.10. Structural Diagram of a Channel-Channel Adaptor Key: (1) Computer No 1; (5) Control Block No 1; (2) Computer No 2; (6) Buffer Register; - (3) Channel-Channel Adaptor; (7) Control Block No 2. (4) Selector Channel; The control devices for the magnetic tape and magnetic disk stores can be connected simultaneously to the selector channels of the two machines of the VK-1010. Through these separate control devices the channel of one computer can be connected with the storage of the other computer and 32 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2047/02109: CIA-RDP82-00850R000404030008-6 FOR OFFICiAt USE ONLY vice versa (the channel of any computer can be connected with magnetic tape and magnetic disk storage) [437]. The OS K1 operating system is used to control the work of a VK-1010 con- sisting of two YeS-1030 computers. This system is an expansion of the YeS operating system with multiprogramming in the regime for a fixed number of problems. The aggregation software ie included in the OS R1 operating sqstem. It permits the posaibility of controlling the aggrega- tion hardware and information exchange using them at the level of the system macrocommands of the assembler and atandard data control means. All access techniques of YeS computers can be used to conatruct the common memory field on magnetic diaks because such a field can contain sets of data with any type of data organization permitted in the YeS operating system. Only sequential methode of access, the base technique or with queues, can be used for work with a common field on magaetic tapes. This also applies to the channel-channel adaptor equipment because the data transmitted using it has a sequential atructure [247]. The VK-1010 computer complex can be characterized as an NKMIDS/NsOr (KnPmPr) a homogeneous system with multiple flows of commands and data and bp-word processing, with a low level of interconnectedness by means of cfiannels, common external memory, and direct linkage between processors. The YeS-1035 machine has a number of distinctive features [256]. This machine is a model of the improved phase II YeS computers-. TFie capa- bilities of the YeS-1035 are developed chiefly by expanding the system of commands (172 commands), organizing virtual memory, correcting lone errors when reading information from main memory, and detecting double errors. The computer provides for compatibility with the Minsk-32 com- puter [340], and a set of compatibility means has been developed for ttiis purpose: convertors for the Minsk-32 Fortran and Cobol languages; an emulator of Minsk-32 programs on the YeS-1035, and data transfer means. The emulator is a program that works under the control of the YeS disk operating system; the work of the emulator is combined witfi performance of other YeS computer programs in the multiprogramming reglne: 'Tfte neces- sity of making the YeS-1035 processor at least as fast as tfie Minsk-32, given a marked difference in the principles of performing operations in YeS computers and the Minsk-32, eatablished the microprogram base as the principal means of emulation [256]. _ The channel-channel adaptor in the YeS-1035 computer makes it possible to set up multimachine complexes on the basis of this machine by interlinking three computera, which may be other models of YeS com- puters. It is also possible to aggregate using a direct control block, which permits the processorsthat are joined into tfie system to exchange control information. The YeS-1035 has significantly expanded capabilities for organizing external memory because tfie model has an integr:ated file adapter which makes it possible to connect magnetic disk storage witfi.a data transmission speed of up to 312,000 bytes per second directly to the processor (without a control unit) [218, 429]. 33 FOR OFF(CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY The senior model of the phase I YeS computers has tfie fiighest productivity _ of the phase I models. This is the YeS-1050. Let us consider multimacfiine and multiprocessor systems based on this computer [439]. A distinctive feature of the YeS-1050 is that these machines can be joined in- to either multimachine or multiprocessor systems. They permit organization of linkages at the level of the processor, channels, external memory (external units), and main memory by means of aggregation devicas, apecifically: direct-control means, channel-channel adaptors, and two--channel switches of control devices for external units. They can also be connected by tfie re- configuration console. This makes it possible to realize any combination of the above-listed variations of linkages. Linkage at the first three of these levels is poesible for two or more processors, while linkage on the fourth level (constructing a common main memory field) is possible only for two processors. Figure 3.11 below shows a structural diagram of a two- processor system that includes aggregation at all four levels. K0M1717e1WupVea11ue ~-6noK ~ .61701r ~ NoJposaA.x: ~(a) 6n0ti- ~ 6170K i , ~ 0/1 : on r ~ ~ � On L --T nnepomaeNOu j I F' - - _ - n~TF~Pmu~b~ _ L------ . cco � npoqeccopne (c) poqecco paye NmepqeuC npAryoro y~,pasneNu - ~ ~ ~--Z--i-- � - Adanmep kaNan ~ KoHO~ ~ a- n�r,.;�c:::s ~d') N~ I KaNq~ ~l 1 . ~ r - etiewNeu ( e ) . L- mu 1 r__i__~ ' YBY YBY noroa r YBY ( ~ YBY I (9NC!!v . i ~ ycM1000cmel Key: (a) (b) (c) (d) (e) (1) (2) I------ i BNewNee i BNewNee BNCf//HBE iBN~ruNee � ~ cm nucme cm aucme cmpoucme '_!yci7lpcdcmeai ~-e---~' . j - Figure 3.11. Structural Diagram of a 1wo Processor Syatem Based on the YeS-1050 Computer Aggregation at Levels - ; Main Memory; Processors; Channels; External Memory (External Units); Main Memory Block; Processor; (3) Direct-Control Interface; (4) Channel; (5) Channel--Channel Adaptor; (6) Control Device for External Units; (7) External Unit. The system should have two-output main memory units to organize a common main memory field (in the first YeS-1050 models tTie main memory did not have two inputs). In the two-processor system with common main memory, assignment of the work regime of the system, physical distribution of system resources 34 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00854R000440030008-6 FQR OFFI('IAL USE ONLY among processors, and excluding malfunctioning units from the system are ac- complished by means of the system reconfiguration console. The direct- - address domain of the memory of one of the two processors is biased by pre- fixing the address to avoid superposing it on the direct-address domain of the memory of the other processor. The two-processor system with a common main memory field, common memory field on external memory units, and linkage between processors tfirough direct control equipment is the principal version of the computer sqstem based on the YeS-1050. All means of aggregation are basically oriented to this variation. It is.also possible, however, to construct computer systems with a larger number of processors on the basis of tfie YeS-1050. - Figure 3.12 below shows the structure of a computer system with three processors. It has one two-processor system with a common main memory based on YeS-1050 computers and one other processor. They are intercon- nected by means of channel-channel adaptors and have a common field of ex- ternal units. Depending on the nature of the problems being solved the processor shown on the left of the figure may be another type of computer, not necessarily a YeS-1050. It may be less powerful than the YeS-1050, for example a YeS-2030 or YeS-1030 processor, and perform tfie functions of loading the system and distributing the general flow of problems between the other two processors. 7) 46or. c.-m^a (Users) Figure 3.12. Structural Diagram of a Computer System with Three Processora Baaed on YeSt1050 Computers Key: (1) Main Memory; (6) Channel--Channel Adaptor; (2) Direct Control; (7) Input-Output Unit; (3) Central Processor; (8) External Unit Control; (4) Multiplex Channel; (9) Data Transmission Equipment; (5) Selector Channel; (10) External Memory Unitjs]. 35 FOR OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY The system that results from aggregation works under the control of an oper- ating system which is based on a modification of the control program that provides multiprogramming with a variable number of problems. The basic functional capabilities of the multiprocessor version of the control pro- gram (the OS-MPR) are using the processors as a single resource for processing a queue of jobs, performing input-output for a problem done by one pracessor with the help of the other processar, processing hardware malfunctions by the two processors. The realization of these functional capabilities is based on use of direct control means: the commands DIRECT WRITE and DIRECT READ, the signal "Message of Error," and the commands TEST and SET [439]. Table 3.4 below gives basic data on aggregating. It is possible to aggregate not only identical or different computers of one YeS family, but also YeS machines and machines of different types and clasaes. As an example, let us consider aggregating YeS computera and M-6000 minicomputers of the ASVT-M [Aggregate System of Computer Technology- M] [51]. In the resulting systems the minicomputers perform the functions of input-output processors, display units, switching processors, and Che like. Aggregation may be accomplished by linking channels or constructing a common external memory field. These alternatives require relatively minor modifications in the design of the computer and software. If rapid com- munication between computers of the system is needed, the alternative with communication through channels is selected. An analysis of the logic of construction of the channels of the YeS family and M-6000 computers ahows that the M-6000 input-output interface is simpler and more highly programmed. Therefore, when constructing the communications block (coordinator) it ia wise to assign it some of the functions of hardware realization of the standard YeS computer interface, but to realize most of them by M-6000 programs. Figure 3.13 givea a structural diagram of the linkage of a YeS computer and the M-6000 (the structure of the ASVT-M is described in section 3.). In the M-6000 computer the coordinator may be connected either to the pro- gram channel (Figure 3.13a) or the channel for direct access to memory (Figure 3.13b). Two interface cards, a control card and an information card, are used for the connection. The former is to transmit a11 control information and state bytes, while the latter is for data transmission. This distribution makes it possible to use the same interface cards to con- nect the coordinator to the program channel and to the channel for direct accesa to memory. The coordinator may be connected to the YeS computer through a selector channel as a high-speed external unit. This variatich of aggregating machines has been realized with a YeS-30 and an M-6000 j51J. The experimental computer system of the Latvian SSR Academy of Sciences is an example of a more complex, heterogeneous multimachine system [446, 4471. 36 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000440030008-6 FOR OFFICIAL USE ONLY ~ C1 ~ ~ ~ 0 U ~ a~ 'J4 00 ~ ~ c~ 00 a $4 00 00 d ~ cn G! r-~I ~ H a~ i.~ -H ~d bo a~i N44 a o H r-I ~a d ac ~ ~ o ~-H ~ ,d �u N ~ N 14 rl ~ a 0 H r,,{ -W ~ ~ y ~a a~ H ~ O w ,i ~ Itl 41 d N co ~ H ~ b w� H x ri) 41 ~ ~ ~ a~ 0 ~ ~ ~ ~ w $4 00 00 H ~ a w " o ~ a ~ 0 U r~l N ~ H .~C ,C tA rl u ~ 4~! ~ ~ W u ~ q � ~ W .G ~ O 7~1 d o o 0 u rl f!1 N 01 cd`tQ~~a~i~ ~ U 1~+ O i~-i H ww�au3 a~ x ~ 3 a~ N 4) o ~ a ~ o r~l GI ~ u u 0 $4 u a *H+ 3 i r'-i lb r-1 � ~ ~ ~ c + ~ ~ � ~ u ~ ix uoa i a p 0. w u 19 a~ v i Cd H U P, A ~ m Cd ~ b ~ ~ .r{ w w (d W ~ 41 R d ~ - 0 w ,-i ~ 0 M ,H obV4 ,i b Z r-i r-I a~ ~ ~ ia q ~ O H ~ N CS O Q r l ~ 1J L1 U JJ td $4 0 a~ ~ CJ u 0 H a r. i w o w � Irl a b 0 y N ! G )4 li q [3 � ~ u co ow w 0 3 0.44 ~ ~ d ~ v-4 ~ 0 r- 0 ~ p r r -I + c d l . r4 1-4 ~ Cd tn rl ld i1 C.' ~ O H ~ H~ c d ~ c J v a m a d ~cd~+ U a H l N v m a 0 N a+ + a ~o w ,J ro b m 6rqu,a�, w ,n U) 60 H a ~ -W H a~ ogb~ o G 3 U 0 ~ w Q) w o ~ tn td u ~ E+ O ~ "~d cC m O b:10 q ~ -A ,a 0 H p c41o ~ 0 u a~i 1o q w a~o r~ o ~a u P., 14 ~ ~ ~ ~ ~ 37 ON m p ~ N ~ W 0 ~ F+ 0 ~i b~ 0 Ai o y O cso1t~.Cu H LL O 0 -W H uw q ~ ~o 0~ ii y ~:j v ~ a w ~ o~ w o`~~ ,1d4+uo ~ d a" Cd u a$4 u 3 d O i~J 0 GI a 41 u W ~ 0 o a~~io~ H o u w 0 A ~ 1 H H a a 1 O 0 CdC a G~l U Cd Q m ~i a~ cd x U FOR OFFICIAL USE ONLY 1 00 ~ + v  � W W 0 K'. ~ ~ 'd d O t0 u o 1 ,a~ Cd o~ ~ ~ ~ o ~ a ~ a i p a w u 'H w a 0 ~ o `0 � + i a ~ + ~ o ~ d ~ ~ r l :j .0 l .C O v 0l cn a lw a1d " Q ~ ~ ~ r-I ~ 14 a, 41 k a~ 010 U W I tn 0 0 c tJ Gl u i 4+ q ~ ~ M ~ d N ~ ~ ~ M r-I ~g c~0 N d~l q O H M 00 d ~ -W41 O3 O G1 Fi v 4~i 1~.i P. ~ 0 ~ ~ ~ cpv H N DC W APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00854R004400030008-6 FOR OFF[CIAL USE ONLY ) 3BM Edunou 3BM (6 Coznacoea- ] Key: (a) (b) (1) (2) (3) (4) ,flbVBNUB coWaC0eam8.7A .(WY noag -~s:'"�'1 k noozpannnony ,va.vanv 0, yigure 3.13. Structural Diagram of the Interlinking of YeS Computer and an M-6000 Computer Connection of Coordinator to Program Channel of M-6000; Connection of Coordinator to Channel for Direct Access to Memory of M-6000; YeS Computer; (5) Direct Access to Memoxy Channel; M-6000 Computer; (6) Information Interface Card; Selector Channel; (7) Control Interface Card; Program Channel; (8) Coordinator. Let us consider its structure (see Figure 3.14 below). At the end of 1977 the computer system included nine macfiines. Four of them make up the central computer complex, and five machines are the founda- tions of computer complexes at institutes. In addition, the system includes data transmission equipment (adaptors), units for switching the channels of the machines (channel switchers), and channels (communications lines between the adaptors). The experimental computer system was set up for scientific investigation of the architecture of computer systems and to conatruct the machine base for an academy-wide system to automate scientific research. The three working machines (two YeS-1030's and one M-4030) of the central computer complex receive assignments, perform them, and issue results ob- tained to users. Users interact with one of the working YeS-1030 com- puters by means of displays working in a dialog regime. The supervisory machine (M-4030) of the central computer complex controls the channels, - controls flows of information from the local input-output units, receives assignments from the users of terminal computers and transmits results to them, monitors the accuracy of information being received and repeats the receipt when errors appear, converts form$ts and codes, puts back-up copies of inessages in main memory, and keeps statistics on the work of the computer system. In an emergency the functions of the supervisory machine are assumed by the working M-4030. 38 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 (b#/lodirnroveaue ciomacoeamnnn ie ,vo;;a~y irpfnoso docmyr,n e nonFmc I~1'EOCO APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY ( J i TrfT-. , ~ cs ~ i i _ / - - ~ c MacuuNS i'~ . _ . ; ~C4> Acneuuya ( 6 ) ~ i~ . iE - ](5) (9)~ ~ . AAAlarde eiauiuyaeayu� cnumenaHavx koAnwe,vcoe . : . _ uNCmumymoe. . Key: (1) (2) (3) (4) (5) (6) Figure 3.14. Structural Diagram of a Heterogeneous Multimachine Computer System Display[s]; YeS-1030; Working Machines; Central Computer Complex; Adap to r:[ s ] ; Supervisor Machine; (7) Channel Switch; (8) Local Input-Output Unit; (9) Channels; (10) Terminals of Institute Computer Complexes. FOOTNOTES 51. N. N. Bugayev, Ye. D. Gernet, V. V. Gorodilov, G. G. Dogad'ko, G. I. Zabiyakin, V. M. Kostelyanskiy, K. A. Larionov, 0. F. Pozhil'tsov, A. Ye. Rozenberg, and S. N. Rykovanov, "Aggregrating the M-6000 Mini- computer with YeS Computers," AVTOMATIKA I VYCHISLITEL'NAYA TEKHNIKA, 1976, No 2, pp 64-66. 61. V. S. Burtsev, "The Sequence of Computer Generations," PRAVDA 4 April 1978, No 94 (21794). 142. Ye. A. Drozdov, V. A. Komaritskiy, and A. P. Pyatibratov, "Elektronnyye Vychislitel'nyye Mashiny Yedinoy Sistemy" [Electronic Machines of the Unified System], Moscow, "Mashinostroyeniye, 1976, 672 pages. 218. L. N. Korolev, "Struktury EVM i Ikh Matematicheskoye Obespecheniye" [Computer Structure and Software], Moscow, "Nauka", Glavnaya Redaktsiya Fiziko-Matematicheskoy Literatury, 1974, 256 pages; 2nd ed, 1978, 351 pp. 39 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY 238. A. M. Larionov, V. K. Levin, V. V. Przhiyalkovskiy, and A. Ye. Fateyev, "Basic Principles of the Construction and Technical-Economic Charac- teristics of the Unified System of Computers (YeS Computers)," UPRAVLYAYUSHCHIYE SISTEMY I MASHINY 1973, No 2, pp 1-12. 244. A. M. Larionov, V. K. Levin, and Yu. P. Selivanov, "The Unified System of Electronic Computers (YeS Computers)," in "Entsiklopediya Kibernetiki" [Encyclopedia of Cybernetics], Vol 1, Kiev, Glavnaya Redaktsiya Ukrainskoy Sovetskoy Entsiklopedii, 1974, pp 309-310. 245. A. M. Larionov, "The Unified System of Computers and Prospects for Its Development," in"Voprosy Kibernetiki" [Issues of Cybernetics], Vyp 20, "Vychislitel'nyye Sistemy" [Computer Systems], Part 1, Moscow, Nauchnyy Soviyet po Kompleksnoy Probleme "Kibernetika" AN SSSR, 1976, pp 60-74. 246. A. M. Larionov, "Basic Conceptions of the Development of the YeS Com- puters," in "Vychislitel'naya Tekhnika Sotsialisticheskikh Stran" [Computer Technology of the Socialist Countries], Vyp l, Moscow, "Statistika", 1977, pp 41-51. 247. K. A. Larionov, V. G. Lesyuk, T. V. Makarova, and Ya. S. Shegidevich, "Hardware and Software for Aggregating YeS Computers," in "Obrabotka Dannykh na EVM Tret'yego Pokoleniya" [Data Processing on Third Genera- tion Computers], Moscow, IrIDNTP, 1976, pp 34-36. 256. G. P. Lopato, G. D. Smirnov, V. Ya. Pykhtin, and A. P. Zapol'skiy, "Design Characteristics of the YeS-1035 Computer," in "Algoritmy i Organizatsiya Resheniye Ekonomicheskikh Zadach" [Algorithms and Organi- zation for Solving Economic Problems'], Vyp 12, Moscow, "Statistika", 1978, PP 78-82. 340. V. V. Przhiyalkovskiy, G. D. Smirnov, and V. Ya. Pykhtin, "Elektronnaya Vychislitel'naya Mashina 'Minsk-32"' [The Minsk-32 Electronic Computer], Moscow, "Statistika", 19721, 160 pages. 377. A. M. Larionov (editor), "Sistema Matematicheskogo Obespecheniya YeS EVM" [The Software System of the YeS Computers], Moscow, "Statistika", 1974, 216 pages. 429. A. A. Shelikhov, and Yu. P. Selivanov, "Vychislitel'nyye Mashiny: Spravochnik" [Computers a Reference Manual], Moscow, "Energiya", 1973, 216 pages; second edition, 1978, 224 pages. 437. A. M. Larionov (editor), "Elektronnaya Vychislitel'naya Mashina YeS-1030" [The YeS-1030 Electronic Computer], Moscow, "Statistika", 1977, 256 pages. - 446. E. A. Yakubaytis, "Architecture of Computer Networks and Systems," in "Vychialitel'naya Tekhnika Sotsialisticheskikh Stran," Vyp 4, Moscow, "Statistika", 1978, pp 10-19. 40 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY 447. E. A. Yakubaytis, "Arkhitektura Vychislitel'nykh Sistem i Setey" [The Architecture of Cmputer Systems and Networks], Riga, Institut Elektroniki i Vychislitel'noy Tekhniki AN Latv. SSR, 1978, IEVT POI, 37 pages. COPYRIGHT: Izdatel'stvo "Nauka", Glavnaya redaktsiqa fiziko-matematicheskoy literatury, 1980 11j176 CSO: 1863/147 41 FOR OFF[CIAL USE CNLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAL USE ONLY ASVT-M AND SM SYSTEMS OF MULTIMACHINE COMPLEXES Moscow PARALLEL'NYYE VYCHISLITEL'NYYE SISTEMY in Rusaian 1980 (signed to press 16 Sep 80) pp 146-149 [Subsection of Chapter 3 of book "Parallel Computer Systems" by B. A. " Golovkin, Izdatel'stvo "Nauka", 10,000 copies, 520, pages] . [Text] 3.4.2. Multimachine and Multiprocessor Systems Based on ASVT-M [Aggregate System of Computer Technology-M] and SM [International Sqstem of Sma11 Computers] Computers. Let us look f2rst at complexes.based on the M- 4030 computex [17]. A two-machine system is constructed in the same way as a YeS computer two-machine system, using a channel-channel adaptor, control units for external memory, direct control equipment, and appropriate soft- ware. When the M-4030 is aggregated with other ASVT M macfiines, tfie M-4030 performs the basic functions of the central computer (see Figure 3.15 below). In this case the ASVT disk operating system on the M-4030 should contain special programs for acceas to the processors of the lower level of the hierarchy in the system, while the operating systeme of the latter should have service programs for tfie communications adaptor and a program for access to the central machine. The communications adaptora connect the machine interfacea directly. Ex- change among machines is carried on by byte. Interlinking devices that carry on exchange by byte in a semiduplex regime at tfie initiative of any of the interacting machines are used to organize remote (for distances up to three kilometers) communications among machines. Devices for comuni- cations with the object are normally uaed for communications witfi the oFi- 3ects being controlled. There are several different multimachine complexea that can be constructed on the basis of the M-6000/M-6010 machines [68]: duplex systems; hierar- chical systems with a tree structure and one-level systmes, for example with circular structure; systems with concentrators [M-40] at the lower level; hierarchical systems which uae YeS computers at the highest level, and other types of systems. The memory and input-output lines play an important part in aggregating M-7000 machines. Figure 3.16 below ahows an example of the structure of a tvo-processor system based on M-7000 machines [115, 184, 4291. 42 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000440030008-6 FOR OFFIC.IAL USE ONLY CMBHNGIflOdO/1/AEp (1 y~~~~Cy~+i~ dw M-403U, M-6U00 u M'-~i~ Figure 3.15. Structural Diagram of a Hierarchical Multi- machine System Based on M-4030, M-600, and M-7000 Machines. Key: (1) Multiplex Channel; (2) Selector Channels [Nos 1, 2, 3]; (3) Input-Output Interface; (4) Adaptor; (5) Channel with Direct Accesa to Memory; (6) Comon Line; (7) Memory Unit; (8) Device for Communications with Object; (9) External Units; (10) Interlinking Unit; (11) To Ob3ect of Control; (12) Interchangeable Adaptor for M-4030, M-600, and M-400. _ The functions and namea of the devices in the figure are given in preceding subsection 3.4.1. The memory lines are connected, on the one hand, to as many as two processors and two channels for direct access to memory and, on the other hand, to as many as eight memory units with a total capacity of 128,000 words. The input-output lines in a system with common inter- face units are connected, on the one hand, to as many as two processors and two channels and, on the other hand, to as many as three input-output ex- pandera, each of which has up to 16 peripheral units. Thus, by the use of lines the primary units become common within the syatem. 43 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/49: CIA-RDP82-00850R040400030008-6 NOR OFFICIAL USE ONLY 03A � � � ' l03Y , !!/unl mwm&k 2) (3) n~v , ye~ ( ann vnnn , P~l ve v 3) y~PaicOOmaw~~6 m ;8mrlo-4apolr( 7 ) (S) f 1B 1/6 1 fE . llr~epu~pepu~'yaN ycmpio~icmeaN (6) Key: (1) (2) (3) (4) (5) (6) (7) (8) Figure 3.16. Structural Diagram of a Multiprocessor System Based on Two M-7000 Processors Memory Unit; Memory Lines; Expander of Arithmetic Unit; M-7000 Procesaor; Channel for Direct Access to Memory; Two Peripheral Units; Input-Output Lines; Input-Output Expander. Figure 3.17 below provides an example of the atructure of a multimachine system consisting of a two-processor system based on the M-7000 and M-6000 (or M-6010) machine [115, 429]. The channel for direct access to memory is controlled tlirougTi a linkage; it is an ordinary peripfieral unit in relation to tfiis linkage. Tfie fact that the channel has two control inputs makes it possible to control them from two complexes, so it performs the function of a multiproceasor communications channel for access to the main memory of the M-7000. The multiprocessor system based on the SM-2 [359] provides with its oper- ating system for simultaneous performance of the two highest priority problems on its two processors. Tfie prolilems, like tFie operating system, are stored in one copy in the common main memory and are not assigned to processors in advance. If the problem being solved bq one of the processors goes into a state of waiting for the occurrence of some event external to it, the processor switches to solving a less important problem that is not being performed by the other processor. If the problem is not ready for perform- ance, the processor is switched to a dynamic halt. if the problem becomes 44 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400030008-6 N'OR OFNI('IA1. USM: ONLY (8) (8) Figure 3.17. Structural Diagram of a Syatem Based on M-7000 and M-6000 (or M-6010) Processors. Key: (1) Memory Unit; (2) Memory Lines; (3) Expander of Arithmetic Unit; (4) M-7000 Procesaor; (5) Channel for Direct Access to Memory; (6) M-6000 (or M-6010) Processor; (7) Input-Output Expander; (8) Two Peripheral Units; (9) Input-Output Lines; (10) Input-Output Expander; (11) Duplex Regiater; (12) Interface Card of Channel For Direct Acceas to Memory ready for performance, it goes into the processor which is in the state of dynamic halt or the processor that is working on a lower-priority problem. If the processors are both working on higher-priority problems, they do not switch to'the new problem. There is another possible work regime which takes into account the arrangement of problems in main memory. FOOTNOTES 17. V. A. Afanas'yev, S. S. Zabara, and S. I. Okunev, "The Architecture of Multimachine Control Complexes Based on the ASVT-M" UPRAVLYAYUSHCHIYE SISTEMY I MASHINY 1974, No 3, pp 133-137. 115. L. V. Gomon, A. S. Nabatov, and I. I. Itenberg, "The M-7000 Control Computer Complex with Heightened Survivability," PRIBORY I SISTEMY UPRAVLENIYA 1977, No 4, pp 8-10. 45 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040400030008-6 FOR OFFICIAL USE ONLY 184. I. I. Itenberg, L. V. Gomon, G. M. Lekhnova, and A. S. Nabatov, "Thz M-7000 Control Computer Complex," PRIBORY I SISTEMY UPRAVLENIYA 1976, No 2, pp 54-58. 359. V. V. Rezanov and V. M. Kostelyanskiy, "Software of the Sti-1 and SM-2 Control Computer Complexes," PRIBORY I SISTEMY UFRAVLENIYA 1977, No lo, pp 9-12. - 429. A. A. Shelikhov and Yu. P. Selivanov, "Vychislitel'nyye Mashiny: Spravochnik" [Computers: a Reference Manual], Moscow, "Energiya", 1973, 216 pages; second edition, 1978, 224 pages. COPYRIGHT: Izdatel'stvo "Nauka", Glavnaya redaktsiya fiziko-matematicheskoy literatury, 1980 11,176 CSO: 1863/147 46 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-44850R444444434448-6 FOR OFFICIAL USE ONLY MINIMAKS MODULAR SYSTEM Moscow PARALLEL'NYYE VYCHISLITEL'NYYE SISTEMY in Russian 1980 (signed to press 16 Sep 80) pp 371-374 [Subsection of Chapter 7 of book "Parallel Computer Systems by B. A. - Golovkin, Izdatel'stvo "Nauka", 10,000 copies, 520 pages] - [Text] 7.2.2 The Minimaks System. The Minimaks System (Minimachine Program-Switchable System) is a modular homogeneous system and has program- switchable (rearrangeable) linkages with the elementary machines included in the system. The system was developed by the Institute of Mathematics of the Siberian Department of the USSR Academy of Sciences and the Impul's Science-Production Aasociation in Severodonetsk. Work on the system was - begun in 1971. The contract design was developed in 1976. In 1977 an experimental industrial model was manufactured and tested, and series pro- duction was envisioned beginning in 1978 [67, 150, 152J. One of the prin- cipal objectives in development of the Minimaks was to gain actual experience in building a modular syatem with a large number of processors and the capabilities of reconfiguration in case of malfunctions and adap- tation of the structure to the problems being solved and a gradual in- crease in the number of modules in the system. Series-produced mini- computers were to be used as procesaors [207]. Figure 7.6 below shows a structural diagram of the Minimaks System [67]. The syatem contains elementary machines with program switchable linkages. The number of elementary machines in the system may range from two to 64. Each elementary machine contains a computer that performs data proceasing functions and a system unit that performs communications functions within the elementary machine and among elementary machines. A computer complex - based on the ASVT-M (Aggregate Syatem of Computer Technology-M), which includes an M-6000 proceasor (see subsection 3.4.1), is used as the com- puter. The system unit ia an autonomous ASVT-M module. It provides interaction between elementary units by two-way linkages (type 1: com- munication with the four immediate neighbors on the left, on the right, above, and below) and by one-way linkages (type 2: communication with the two immediate neighbors on the left and right); in this case the corre- sponding extreme elementary machines are considered immediate neighbors (see Figure 7.6B). In addition, the system unit interacts with the 47 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040400030008-6 FUR ONNICIAI. USE ONLY ~ Cucmrm ~ Z NoeycinZ uc�n~d 3 (2 3BM 1 (A) � CmpykmypNan aienv ineMenm.apyou nawuNa (3M) Figure 7.6. Structural Diagram of the Minimaks System: (A) Structural Diagram of the Elementary Macfiine; (B) Structure of Linkages in the System. Key: (1) Elementary Machine; (2) System Unit; (3) Computer. computer of the particular elementary machine (type 3: communication fie- tween the system unit and the computer of the particular elementary mach.ine accomplished from the computer in the way envisioned for its work arrtFi ex- temal units). Data transmission is synchronized by query/response signals, which provides transmission when the working speeds of the elementarp ma- chinps do not match. When data is traasmitted by types 1 and 2 linkages an - even parity check is performed 167, 207]. Interaction between elementary machines in the Minimaks System may fie of the control type or the exchange type. Interactions are accomplisfied in three stages. In the first stage the domain of coupling Fietween the ele- mentary machines participating in the interaction is formed. In the second stage the actual interaction is carried out, and in the tTiird stage actions related to the possibility of using the elementary machine in otfier inter- actions are performed [207]. Typical interactions are: (1) copying data from the main memory of one elementary machine to the main memory of others (exchange); (2) synchroni- zation of the work of elementary machines; (3) performance of a general- ized unconditionsl transfer; (4) performance of a generalized conditional transfer according to the value of the generalized cfiaracteristtc of this transfer; (5) programmed modification of the topology of system structure and the degree of participation by elementary maciiines in the above- enumerated interactions (adjustment). Interactions 1--4 are accomplished with type 1 linkages, while interaction 5 is done witfi_type 2 linkage. The two-way feature of type 1 linkages provides a compromtse between the flexibility and survivability of the system on the one fiand, and the 48 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 Cmpyxmypaceaseu"ecucmene (B) APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040400030008-6 FOR OF'FICIAL USE ONLY complexity of the system unit on the other. The relative infrequency of adjustments makes it possible to use one-way linkages (type 2) for tfiem. In this case the survivability of the system is insured by closing the type 2 linkagea in a circle (see Figure 7.6) and the possibility of bp- passing malfunctions in type 2 linkages using type 1 linkages [67]. Interactions between elementary machines are assigned by apecial system commands whicfi are realized by system hardware and the appropriate programs of the operating system. An ad3ustment may be performed in both directions (left and rigfit) from the elementary macfiine being adjusted along one-wap type 2 linkages using ad- Justment registers which are available in each system unit. T[ie adjust- ment register is a three-position unit; its contents may be modified by - the computer of the particular elementary macfiine or the computer of anp _ other elementary machine. The content of two positions of the adjustment register assigns one of the four directions of receiving data by type 1 linkages, while the content w of the third position indicates whetFier the particular elementary machine "consents" to interact by type 1 linkages (w = 1--- yes; w= 0- no). Data transmission is accomplisfied in all four directions [207]. Several subsystems that work independently can he organized within the sys- tem; within the subsystem only one elementary macfiine transmits, while all the others are receiving or transit units. In the transit elementary ma- chines w= 0 and data transmission is accomplished by the system unit with- out participation of the computers, which are not diverted from performance of current work. Each elementary machine is included in one of the sub- systems formed on type 1 linkages and may or maq not be included in one of the subsystems formed on type 2 linkages. An elementary machine whicfi is included in a subsystem of either of these types may not participate in several interactions simultaneously. Subsystems of the first type may ex- ist for aeveral consecutive interactions, whereas subsystems of the second type are set up only for one interaction and are broken down after it is performed [67, 152, 207]. The operating system of the Minimaks provides parallel processing, autono- mous work by machines, and a regime of mixed functioning wiiere one sub- system performs parallel processing and the machines of the otfiar suFsystem work autonomously. The operating system includes a basic control system and an ASVT-M real-time supervisor. Tfie parallel programming system con- _ tains languages foz writing parallel algorithms which are an expansion of Mnemokod, Fortran, and Algol, program debugging means, an experimental _ algorithm paralleler, and linguistic means for organizing stable computing processes. The latter are based on assigning check points in the program at which a return is made by the operating system or operator in the case of breakdowns or malfunctions [207]. The sphere of application of the Minimaks System is determined by the ASVT-M equipment used in the system. Minimaks systems can work autono-- mously, as auxiliary subsystems aggregated with more powerful computer systems, and as part of distrihuted computer systems or networks [152]. 49 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 NoN oFHIcinI, usH: ONLY FOOTNOTES 67. V. G. Vinokurov, Yu. K. Dmitriyev, E. V. Yevreinov, V. M. Kostelyanskiy, G. M. Lekhnova, N. N. Mirenkov, V. V. Rezanov, and V. G. Rhoroshevskiy. "Homogeneous Computing Systems of Minimachines," in "Vychislitel'nyye Sistemy" [Computer Systems], Vyp 51, Novosibirsk, IM SO AN SSSR, 1972, pp 127-145. 150. E. V. Yevreinov, and V. G. Rhoroshevskiy, "Homogeneous Computer Systems," in "Vychislitel'nyye Sistemy" [Computer Systems], Vyp 58, Novosibirsk, - IM SO AN SSSR, 1974, pp 32-60. 152. E. V. Yevreinov, and V. G. Khoroshevskiy, "Odnorodnyye Vychislitel'nyye Sistemy" [Homogeneous Computer Systems], Novosibirsk, "Nauka", Siberian Department, 1978, 320 pages. 207. V. G. Kerbel`, Yu. I. Kolosava, E. G. Krylov, V. D. Korneyev, and N. N. Mirenkov, "Programmnoe Obespecheniye Sistemy MINIMAKS" [Software of the MINIMAKS System], Novosibirsk, IM SO AN SSSR, 1979, Preprint OVS-09, 43 pages. COPYRIGHT: Izdatel'stvo "Nauka". Glavnaya redaktsiya fiziko-matematicheskoy literatury, 1980 11,176 CSO: 1863/147 50 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040400030008-6 FOR nF'NICIAL 11SF: ONI.Y SiTMMA MODULAR MINICOMPUTER SYSTEM Moscow PARALELL'NYYE VYCHISLITEL'IVYYE SISTEMY in RuFSian 1980 (signed to press 16 Sep 80) pp 374-376 [Subsection of Chapter 7 of book "Parallel Computer Syatems" by B. A. Golovkin, Izdatel'stvo "Nauka", 10,000 copies, 520 pages] [Text] 7.2.3. The Summa System. The Summa (Minimachine Control System) is a modular homogeneous syatem with programmable structure. It was developed by the Institute of Mathematics of the Siberian Department of the USSR Academy of Sciences together with industry. Work on the system began in 1972 and the contract design was developed in 1976. In 1977 an experimental industrial model was built and tested, and series production was envisioned beginning in 1979 [19, 150, 152]. Let us consider tfie Summa System, following work [75]. The Summa System contains interlinked elementary machines. Each elementary machine contains an Elektronika-1001 minicomputer and a system unit; the minicomputer may have any configuration all the way to a computer with a full set of external units. The variant of the operating system tfiat has been realized is figured for between one and 11 computers. The mini- computer p erforms data processing functions. It has single-address com- mands, 12-bit words, and a main memory with a cycle of 1.5 microseconds and a capacity of 4,000 words (expandable to 32,000 words). The computer works at up to 30,000 fixed point operations per second. The system unit performs machine interaction functions. It is a separate module and is connected to the computer as one of the external units. Each system unit may be free or engage3. In the first case it is a passive unit. The system unit can be switched to an engaged state by tfie guide unit relative to this system unit. This guide unit may be the computer of the particular elementary machine or another of the system units which is an immediate neighbor of the particular system unit. In any case the system unit can only receive information from the guide unit. The rate of exchange among system units is 2.6 million bits a second. The system unit has information and control inputs and outputs which.are con-- nected respectively with the outputs and inputs of neighboring system units. The expandable communications network of the Summa System which is tfius 51 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY formed may have different configurations, for example those shown in Figure 7.7 below. Adjustment of the network involves shaping the 1 - 1 1 3 2 3 2 , 5 3 ' 415 Z 6 5 g f G B B 6 4 4 ' . n�6 ^~B � n=10 (a) (b) (c) n=12 ' (d) Figure 7.7. Variant Configurations of the Communications Network of the Summa System. connection functions and activating the high-speed computers. This is done through the action of information propagated through the network. The message format is standardized as a packet which has a service part and a data part. The address field and the control field included in the aervice part of the _ packet are used to ad3ust the communications network. Each elementary ma- chine can have several address which determine the degree of its partici- pation in system interactions. The addresses are assigned by program. If the address in the service part of the packet corresponds to one of the addresses assigned to the syatem tinit, the corresponding computer included within the particular elementary wachine is octtvated to receive data com- ing to the system unit. In the opposite case the system unit relaya incom- ing information as a transit junction of the communications network of the Summa System and the corresponding elementary machine does not participate in the particular interaction. The software of the Summa System includes the nucleus of the operating sys- tem which controls the asynchronous interaction of Processors and a programming system, which makes it possible to write parallel programs. The programming system includes the Macro-8C input language and a trans- lator from this language, a symbol editor, loaders, and service programs. The Summa System is designed for use in control systems for industrial processes, scientific experiments, and the like. The nucleus of the oper-- ating system makes it possible to ajust the structure of the Summa System for definite work regimes such as the regime of matrix processing where it works as a system of the OKMD [expansion unknown] type, the regime of main- line processing where it works as a system of the MKOD [expansion unknown] type, and the processing regime where it works as a system of the rKMID [expansion unknown] type. 52 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400030008-6 FOR OFFICIAL USE ONLY FOOTNOTES 19. V. P. Afanas'yev, V. L. Golodok, V. I. Goryachkin, A. P. Yeremin, M. P. Zheltov, M. N. I1'in, S. G. Sedukhin, Yu. F. Tomilov, V. G. Khoroshevskiy, and L. S. Shum, "The SUMMA Computer System," in "Vychislitel'nyye Sistemy" [Computer Systems], Vyp 60, Novosibirsk, IM SO AN SSSR, 1974, pp 153-169. 75. I. V. Prangishvili (editor), "Voprosy Kibernetiki. Vyp. 43. Vychislitel'nyye Mashiny i Sistemy s Perestraivayemoy Strukturoy" [Issues of Cybernetics. Issue No 43. Computers and Computer Systems with Rearrange- able.Structure], Moscow, Nauchnyy Sovet po Kompleksnoy Probleme "Kibernetika" . AN SSSR, 1978, 180 pages. 150. E. V. Yevreinov, and V. G. Khoroshevskiy, "Homogeneous Computer Systems," in "Vychislitel'nyye Sistemy" [Computer Systems], Vyp 58, Novosibirsk, IM SO AN SSSR, 1974, pp 32-60. 152. E. V. Yevreinov, and V. G. Khoroshevskiy, "Odnorodnyye Vychislitel'nyye Sistemy" [Homogeneous Computer Systems], Novosibirsk, "Nauka", Siberian Department, 1978, 320 pages. COPYRIGHT: Izdatel'stvo "Nauka", Glavnaya redaktsiya fiziko-12atematicheskoy literatury, 1980 11,176 CSO: 1863/147 53 FOR OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 FOR OFFICIAI, USE ONLY MARS ASYNCHRONOUS MODULAR'SYSTEM Moscow PARALELL'NYYE VYCHISLITEL'NYYE SISTEMY in Russian 1980 (signed to _ press 16 Sep 80) pp 411-415 [Subsection of Chapter 7 of book "Parallel Computer Systems" hy B. A. Golovkin, Izdatel'stvo "Nauka", 10,000 copies, 520 pages] [Text] 7.4.1. The Modular Asynchronous Developable System [263]. The conception of the modulax asynchronous developable system (MARS) is based on a comprehensive approach to eliminating sucli widespread weaknesses of computer systems as the following: (1) architectural r-fgidity; (2) inadequate increase in total productivity when the characteristics of the units are improved and the power of the resources is enhanced, including an increase, in tTie number of central processors and memory volume; (3) unsatisfactory compatibility and transfer- ability of software; (4) overexpenditure of time and resources for system processes at the expense of user processers; (5) inadequate introduction of convenient, reiiable, and effective techniques of parallel programming, and the orientation of the architecture of multi:processor systems to the tech- niques of sequential programming using group operations and to parallel- sequential techniques (not elaborate, highly parallel data processing). To eliminate these shortcominge of computer systems the architecture of the MARS system envisions realization of the following basic principles: 1. Implementation of highly developed hardware support and hierarchical paralleling of both problem and system processes; 2. Construction of a hierarchical structure of the com- puter modules in the form of standard large block elements; 3. Organization of asynchronous interaction between modules and the user of botfi centralized and dis- tributed means of organtztng interaction witTi re- arrangeable (programmable) control; 4. Convenient and effective adaptation of the system and, within certain limits, dynamic reconfiguration; 54 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-44850R444444434448-6 FOR UFFICIAL I1SE ONLY 5. Use of the opgortunities offered by future basic ele- ments, including microprocessors, witfi due regard for the potential of microprogramming. 1 There are various ways to embody these principles in concrete structures. tn the conception of the MARS system the structural organization is based firat of all on comprehensive paralleling of all processes in the system and ef- fectively represemting them on the base level of the system. Tfiis envisions standardization of the rules and means of composing the system from modules of different levels, development of the functtonal capabilities of the sys- tem and its potential for adaptation bp hardware means, virtualization and specialization of modules, and organization of the base system, computer processes, and programs on a uniform, asyncironous principle. Hardware support and hierarchical paralleling of the entire complex of data processing processes provtdes an increase in the total productivity of the system. To realize problem processors a small number of different types of processors is envisioned, for example, a scalar, matrix, or vector processor and, possibly, a processor for complex data structures, The existence of a small number of sucfi specialized processora in the system does not make switcfiing and paralleling data more complex if the linkages among them are asynchronous, excfianges are accomplisfied tfirough a common "data market," and the data themselves are tagged. The organization of control and exchanges may cTiange depending on the level of hierarchy of the processor, but it is wise to select the saane method of organization for each particular level. At the lowest level, performing microoperations and operations, synchronous control (synchronous processors) and distributed memory should be used. At the level correaponding to com- putation of expressions and performance of group operations, syncTironous procesaors and distributed memory should also be used, but with a rise in the level asynchronous organization becomes more efficient. Thus, whereas for the level of computing expressions and performance of group operations asynchronous distributed control may be uaed in addition to syncfironous, for the computation of operators and work with average program modules it is advisable to employ asynchronous centralized control and coumnon memory. With a further rise in the level, for work with large program modules (sub- routines), asynchronous distributed control and distriiiuted memory should be used. System processes are maximally combined in time with user problem proceases and are realized by means of equipment oriented to performance of tfiese processes because they have the appropriate specific features and are standard for the system. ' Processors in the base system or more complex modules are singled out for system processes, with equipment for processing and control processes separ- ated into appropriate subsystems (it is even possible to break the control subsystem down further into subsystems for control of processes, assignments, data, and the like). 55 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 F()R ()H'HI('IA1, iltiH: ()NI.Y As observed above, modularity is one of the main principles of conatruction of the MARS system. Both the hardware and the software of the system are modu- lar and this, together with the modularity of para11e1 prograuming languages, ahould insure the possibility of static and dynamic reconfiguration of the system and mutual adaptation of user programs, system programs, and the ac- tual MARS base system. The MARS system is shaped as a certain hierarchical structure following standardized rules made up of standard modules at different levels and for different purposea. The module in the MARS system is a functionally closed block of heightened qualification in the sense tfiis term is used in work [166] (see subsection 4.1.1) and specializable or programmable for definite functions in the system. It can store and process data and fias an autonomous control unit to organize and monitor the work of submodules and for commu- nication with other modules. A module may Tie hardware, virtual (software) - or mixed hardware-software. . Elementary and composite modules are identified in the hierarchical struc- ture of modules. The composite modules contain submodules related to the interface, control, processing, and memory zones. The suFimodules of the i.nterface zone support all control and information linkages Tietween the par- ticular module and other modules so that from the outside the module repre- sents a"tilack box" with access for "vtewtng" only througfi the interface zone. The internal control of the module.is autonomous and programmable and ia accomplished by the submodules of the control zone wh3ch organize coatrol and, in part, information linkagea among submodules of the module. A kind of module operating system functions tn the control zone. Assignments coming to the module are processed by the submodules of the processing zone. The data which are supplied to the submodules are stored in.the memory zone. The submodule can, in its turn, be a composite module. Figure 7.19 below shows the general scfieme of a module of the MARS system. The parameters, concrete structure, and type of control of the module are de- termined by its designation within the sqstem. Modules of different levels are described by means of the specification languages of the appropriate level which insure correspondence between the structure of the description of the system module and the structure of the module itself. The module description contains clearly understandable information for adjusting the module to the appropriate configuration and work regime. The internal autonomous control organizes the work of the module. During this the module goes through these states: passive; test of the trigger functtons; analysis of the test result (return to passive state if the value is "false"); initi- ation of the module; active; and, completion. The MARS system contemplates the use of microprocessors to control the work of particular specific units suct as printers and for the performance of spe- cial functions within the system. It also envisions using microprocessors as fairly universal components of the base system, tfiat is, as elementary modules. The modules must be refined (improvement of basic parameters and elaboration of the modularity and adaptability of the structure) for micro- processors to be used as elementary modules. 56 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 Fl)It (1FF1('IAI. lltiE ()NI.Y ~ 1) 3aNa aamepq~euca nNOdyn~ ~Nas BacxodNa (2) cMmo.NUe, ycnoeue koNana KaNana moe~oc 3 4 =_=====T==---__ ---___6)1 s 1. . � o i I n y I dCIY; 0 M (S) O�  p~ ~ n drood nu 3oN-e+ no,aaml~ 7 , oe A a o j /lorlnaoynumma adpaeomn( 8 Figure 7.19. General Diagram of a Module Key: (1) Interface Zone; (2) Type of Module, State, Condition of Readiness; (3) Input Channels; (4) Output Channels; (5) Submodules; (6) Control Zone; (7) Memory Zone Submodules; (8) Processing Zone Submodules. With a fairly complete solution to the problems of modularity and rearrange- ability, the spectrum of configurations of the MARS system may be quite broad with respect to both prolilem orientation and the power of the resulting systems, from minimachines to powerful general-purpose or specialized systems, distributed computer complexes, and the like. This brings together two lines of development of computer technology, one of whicfi is building families of compatible systems of different power levels, while the other is developing standard microprocessor computer modules whose specific purposes are de- termined by the user when composing the computing system from these modules. The computer modules of the MARS system are used like standard microprocessor modules, but they are much larger units and cover a larger power range. When the configuration is fixed the MARS system becomes closed an.d represents a module that contains a hierarchical complex of modules. It is possible, how- ever, to add new equipment to the system, expand its capacities, and modify its characteristics. From this standpoint tfie MARS syatem is an open system. To insure efficiency of computations in this case a static reconfiguration of the system is possible (adding or taking away hardware or sof tware modules, replacement of modules, addition or replacement of system programs, and the like) where the system is fixed during problem-solving after reconfiguration. Dynamic reconfiguration (programmable changes in control regimes and processes 57 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400030008-6 FOR OFFI('IAI. USE ONI.Y in the modules, including in the elementary microprocessor modules); in this case changes are made during the transition from certain problems to others or even during the process of solving one problem. The following may be given as the basic types of modules: a. Modules for storage and preliminary processing of programs (peripheral processors, auxiliary memory modules, translator modules oriented to one program' ming language or one family of languages, and assign- ment control modules); b. Main memory modules and modules for control of main memory, auxiliary memory, and files; c. Problem-oriented processors (universal arithmetic, vector, - matrix and associative, symBol, and special); d. Modules of high-speed and special-purpose memory and modules to perform control processes, including the processes of virtualization of inemory and processors, processing interrupts, and control of parallel processes; e. Modules for organizing exchange and switching. The conception of the MARS system makes it possilile to organize essential sys*em investigations and design. Tfiis requires tfie construction of experi- mental systems and models. It is possible at first to liuild prototype MARS systems with limited productivity and capabilities, but possessing all the principal features of tfie systems, and the.z steadily adopt proven architec- tural concepts, build up capacities, and standardize modules [263]. FOOTNOTES 263. G. I. Marchuk and V. Ye. Kotov, "Modul'naya Asinkhronnaya Razvivayemaya Sistem a(Kontseptsiya). Chast I. Predposylki i Napravleniya Razvitiya Arkhitektury Vychislitel'nykh Sistem. Chast II. Osnovnyye Printsipy i Osobennosti" [Modular As3�nchronous Developable,System (Conception). Part I. Prerequisites and Directions of Development of the Architecture of Computing Systems. Part II. Basic Principles and Characteristics], Novosibirsk, VTs SO AN SSSR, 1978, Preprints Nos 86, 49 pages, and 87, 12 pages. COPYRIGHT: Izdatel'stvo "Nauka". Glavnaya redaktsiya fiziko-matematicheskoy literatury, 1980 11,176 CS O: 1863 /1!+7 58 FOR OFFI.CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-44850R444444434448-6 FOR OFFICIAL USE ONLY DESIGN OF RECURSIVE COMPUTERS Moscow PARALLEL'NYYE VYCHISLITEL'NYYE SISTEMY in Russian 1980 (signed to press 16 Sep 80) pp 415-418 [Subsection of Chapter 7 of book "Parallel Computer Sqstems" by B. A. Golovkin, Izdatel'stvo "Nauka", 10,000 copies, 520 pages] ~[Text] 7.4.2. Recursive Computer Machinea [284]. The structural and program organization of recursive computers is determined by the following basic prin- ciples [765]: 1. The internal language of the recursive computer includes recursively determined program elements as a generaliza- tion of machine commands and data elements as a gener- alization of machine words - operands which may have random complexities; 2. The recursive computer exercises recursive-parallel control of performance of the program, and the order of performance of program elements may be assigned implicitly by means of functional (in the general case recursive) relationships and determined during the process of performance of the program; 3. The internal memory of the recursive computer consists of blocks which may consist of cells or of blocks with program-rearrangeable linkages among them; 4. The external physical structure is uniquely determined by a finite number of recuraive relationships; 5. The internal structure which determines links among computing processes in the recursive computer is flexible, rearrangeable by program, and dynamically reflects tYe structure of the problems being solved. These principles are very general and make it possible to construct many different kinds of recursive computers. We will consider below one of the subclasses of 59 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400030008-6 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400430008-6 H'ON OFN'I
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