THIRD BIMONTHLY REPORT ON THE RT-21 TRANSMITTER DEVELOPMENT

• Document Type: CREST
• Collection: General CIA Records
• Document Number (FOIA) /ESDN (CREST): CIA-RDP78-03424A000800010020-2
• Release Decision: RIPPUB
• Original Classification: C
• Document Page Count: 48
• Document Creation Date: December 22, 2016
• Document Release Date: February 8, 2012
• Sequence Number: 20
• Publication Date: January 8, 1958
• Content Type: MISC

_
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Period:
CONIDEN-111\k_
Third Bimonthly Report on the RT-21
Transmitter Development
03/4 3/51
8 January 1959 - 8 March 1959
Prepared by:
DOC 12/ REV DATE 10 1414 BY aa3 23
URIC COMP DPI TYPE
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JUST 2- NEXT KEY 7---?/ A:3TH: HR 10-2
oniGNALct EIY 2 3 5?? et
D 72C L ON 2-'i
EXT BYND 6 YRS BY S irm
REASON 3 a-- (
L ?,1
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TABLE OF CONTENTS
Page No,
I. Purpose . . *** 0 0 OOOOOOOO 1
II. Abstract. . . ? . . OOOOOOO 0 a a a 1
III. Factual Data. ..?..?. OOOOO .. ? 3
1. Power Output 3
2. Impedance Matching. . . . .
a o o .a ? 7
3. Impedance Detector. . . . ? 13
.
4. Automatic Tuning Program O ? 17
IV. Conclusions . . . OOOOOOO . . ? . ? . 22
V. Future Plans OOOOOOOO 0 ?0?0? 0 . 24
VI. Identification of Key Technical Personnel . 24
VII, Bibliography...?.......?.... 25
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Purpose
See Bimonthly Report No. 1.
Abstract
In this report an account is given of a brief investigation which was
carried out to determine whether, by utilizing the avalanche breakdown phenomenon
in transistors, it would be possible to obtain relatively high output powers at
high frequencies from low frequency transistors.
During the past reporting period work has been continued in the areas
of antenna matching and automatic tuning of the transmitter. The former activity
has been largely of an analytical nature directed towards determining the suita-
bility of various transformation networks for this application. Efforts have been
made to devise impedance transformation methods which do not either lead to
impractically large maximum to minimum capacitor ratios, impractically small or
large values of inductance or capacitance, or inherent circuit losses comparable
to the loss which would be experienced if no attempt was made to match the trans-
mitter to the antenna. Several configurations have been studied, all except one of
which have been found unacceptable. In this report a description of the various
configurations is given as well as the reasons which make them unacceptable. A
variable transformer method is described which appears, at the present time, to
lead to a far more practical solution than the other approaches.
Towards the end of this reporting period a visit from the customer
revealed a change in antenna matching requirements. The new requirements change
the problem materially; however, at the time of writing, the full significance
had not been determined.
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Associated with the matching network is the sensing circuitry which is
required in order to indicate when a properly matched condition exists. This
report includes a description of the work which has been done in the area of
both magnitude and phase sensing circuitry.
The transmitter tuning problem has been described in earlier reports.
In this report a description is given of the steps which have been taken in order
to insure that the range of frequencies over which the electrical tuning system
operates corresponds to the maximum that the voltage variable capacitors are
capable of providing. It is clear that small improvements in available
electrically variable capacitors will not alter the picture sufficiently to
permit the whole range from 3 mc. to 15 mc. to be covered in one band. An
electronic switch has consequently been developed which will permit taps to be
moved electrically making possible automatic tuning over the whole range using
presently available voltage variable capacitors.
During the past month several high power-high frequency transistors
have become available. In particular, the Texas Instrument 2N1141 shows con-
siderable potentialities. This transistor does not approach the output stage
requirements for the RT21 transmitter but makes possible the design of a
relatively high power oscillator stage. If the output transistors which are
ultimately used have a reasonable power gain, the 2N1141 would probably be
suitable as a driver stage. Using these transistors, the crystal oscillator has
been redesigned to provide a higher output than was possible using 2N247 tran-
sistors. By increasing the oscillator output level, the total number of stages
can be reduced with a consequent reduction in the number of tuned circuits with
their associated control circuitry.
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A circuit has been designed which enables the band from 345 mc, to be
swept in three ranges with automatic switching of coil taps for each range. The
15-30 mc. range is covered without the necessity for switching coil taps, repre-
senting a maximum to minimum frequency ratio within a range of only 2:1. The
switching circuit has been built in preliminary form and operated successfully.
At the conclusion of the present reporting period it had not been integrated with
the remainder of the transmitter circuitry.
Factual Data
1. Power Output
(a) Introduction
The problem of obtaining 10 watts of R.F. power from a transistor
circuit is a function of the transistor device itself. The transistor device art
is slowly moving to high power R.F. units. However, a technique has been devised
that utilizes the avalanche multiplication effect of low frequency transistors
to produce high frequency-high current pulses. Avalanche multiplication in
transistors is analogous to a gas discharge tube where charge carriers are
accelerated in a high electric field to a high speed. When they collide with
1.
other molecules, more carriers are produced in the collision.2
. This phenomena
has been utilized to produce very narrow pulses (approximately 1 mrs wide) with
an amplitude of about one ampere.
The formation of a very narrow pulse is dependent upon the switching
time of a device. It has been shown that a transistor operated in the avalanche
mode can be used to discharge a capacitor in a very short time. If it is
possible to produce these pulses at a repetition rate of 30 mc., a suitable power
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amplifier can be produced.
(b) Circuit
3
4
As a voltage Vcc is applied to the circuit shown in Figure 1,
capacitor C will charge through RL to a value approaching Vcc. If IbRb< V bb'
the circuit will be stable with Ib = Ic and IE = 0. If the base is then
triggered with a negative pulse, the emitter to base diode will be forward
conducting and C will discharge through the nominally zero impedance transistor
to ground. This pulse of current flowing out of C can then be coupled to a
load through some appropriate coupling network.
The maximum repetition rate of the avalanche mode is limited by the
average collector dissipation of the transistor. The capacitor is charged to
a voltage VB, equal to the avalanche potential of the transistor, and the power
dissipated is Pd. Since the discharge time is negligible compared to the charging
time of C through RL, the transistor dissipates energy during a time, T, that can
be calculated as follows:
V = VB (1 - e RLC )
cc
or T CRL in
V
cc
Vcc - VB
The average power dissipation over one cycle is
2
VB2
1
2RL
in V
cc
V - VBCC
During the non-conducting quiescent state a collector current, 1c, will flow
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IA Rb
L
+Vbbo?A.AA"---+
Rb
CONSTANT CURRENT
SOURCE
?Vcc
FIGURE I
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which is:
Ic
5
V VB
cc
RL
The dissipation during this time is P which is
P Ic V IcVB
c
Hence,
where
f,
VB (Vcc - VB) VB2 V
( cc
RL RL VB
? 2(r-1) in r-1
Pd
V
cc
VB
1)
This equation represents the compromise between battery voltage and collector
dissipation that must be realized.
From a consideration of the average power the maximum repetition rate,
fmax, can be determined.
f = ?
Tmin CVB2
max
If we assume that the current pulse is in the form of a half sine wave
the peak current flowing can be calculated from:
2
-rr Ipeak t = CVB
(c) Numerical Application
If a 10 ohm load were placed in series with the capacitor C and
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we wished to dissipate 10 watts in this load, a current of 1 Arms or 1.4 Apeak
must flow. Experiments with germanium transistors indicate that the avalanche
potential, VB, is about 50 volts. Using the equation
2
rtf Ipeak t CVB
1 7: 10-6
and assuming t = 40 mc, 40
2 peak
VB
= 450/7, f
Using this value of C and a fmax = 40 mc.
CVB2
Pmax - 2T
(450)(10-12)(50)2(40)
(2)(10-6)
ax 22.5 W
The value of RL can now be computed from
VB2
1
2Pd V
cc
in
V -V
cc 13
(50)2
2 (22.5)
99.4 ohm
100 ohms
1
105
in 105-50
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These results can be summarized:
RL 100 ohm
C = 450/7,f
V .7, 105 Volts
cc
VB 50 Volts
Pd = 22.5 Watts
Hence, for the circuit to function as described, a transistor must be found that
exhibits avalanche breakdown and has a collector dissipation of at least 22.5
watts.
Several high power audio transistors, e.g., 2N174, 2N441, were examined
for avalanche characteristics without success. Since the testing for avalanche
is potentially destructive to the transistor, these tests were discontinued after
several attempts to find an avalanche transistor failed. Further work in this
area was discontinued due to the high mortality rate of transistors.
2. Impedance Matching
(a) Introduction
The original specifications on impedance matching stated that the
load presented to the transmitter would fall within the area bounded by R si 25
to 1300 ohm and X 4.1 g j1000 ohms over the entire frequency range of 3 to 30 mc.
However, in a recent conference with the customer this specification has been
changed such that the load impedance is a function of frequency. This function
is a spiral in the RX plane.
The problem involved in the original specification consisted of synthe-
sizing a network where the resistive part of the load varied by a factor of 52
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over a frequency variation of 10:1. This is an extremely large impedance trans-
formation ratio. The Second Bimonthly Report described "L" and "Pi" networks
which are theoretically possible but physically unrealizable because of the
extremely large variations in capacity that are required.
When a matching network is placed between the source and the load a
certain amount of insertion loss must be expected. However, the gain and power
output of an amplifier are functions of the transistor and its associated load.
Since the particular transistor has not been specified for the output stage of the
RT21 transmitter and there is no information concerning a suitable unit, a
"typical" transistor has been assumed. Under these circumstances, a variation in
load resistance of 52:1 which is approximately 25:1 about the center point would
lead to a 7 db. loss4 in gain for a common emitter configuration. Since the
problem is to deliver 10 watts of power into the load a loss of power by a factor
of 5 because of mismatching is considered to be intolerable and a matching network
must be used. However, if the insertion loss of the matching network exceeds
7 db., there would be no purpose in having the network present.
During the last period considerable work was done on the original
specifications; i.e., 25 to 1300 ohms. A Tee ladder lattice and variable
transformer network were studied to see if they offered a solution to this problem.
(b) Tee Network
In terms of the network shown in Figure 2, (where xi, x2 and x3
represent the reactance in the elements of the T-network, while RA I j xA represents
the antenna impedance), the input impedance, Zin, will be a pure resistance of
magnitude Ro provided
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A +J XA
IMPEDANCE MATCHING T NETWORK
FIGURE 2
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and
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RA
2
(X3 - RAR)
Ro
x3 2
(x, - RA R0 )
RA
>
Since x1 and x2 must be real numbers, it is apparent that x32 RA R0? Requiring
this inequality to hold for all antenna impedances over the specified frequency
band, again, as in the Pi-network, leads to unrealistic elements. The T-network
for the 3-15 mc. band is shown in Figure 3. Not only is the ratio of maximum to
minimum capacitance very large (335:1), but also the low value of the minimum
capacity creates additional problems. Thus, a simple T-network does not appear
to be a suitable solution to the problem.
A modification of the T-network appears, at first glance, to present
a more attractive solution to the problem. If a parallel LC combination is
substituted for the capacitors in the arms of the T-network, the circuit shown
in Figure 4 results. A network of this type contains elements whose size and
range appear reasonable. However, as in the case of the modified Pi-network,
the coil losses are excessive. If the equivalent shunt resistance of the coil
is included, the parallel L-C may be represented at a specified frequency as a
series R-C. Even with coils having a Q of 250, the R component of the R-C
representation is so large that most of the power is absorbed in the matching
network. This fact eliminates the modified T-network as a practical solution
to the problem.
(c) Ladder Network
Impedance matching properties of a three-rung ladder (shown in
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0.44 - 43ty.f
i 47kth
- 911 -
0.86-287p/2.f
j XA
T- NETWORK FOR ANTENNA MATCHING
IN THE 3-15 MC BAND
FIGURE 3
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5?,h
5/.1.h
JIMIMM4)4,MOMI.
23-605??.f
56?,h
23-750??f
+ j XA
A MODIFIED 1-NETWORK FOR ANTENNA
MATCHING IN THE 3-15 MC BAND
FIGURE 4
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Figure 5) were also investigated. Analysis of a network having this degree of
complexity becomes extremely complicated. Since the control system under con-
sideration provides for only two variable factors (impedance magnitude and phase),
it was decided to simplify the analysis by considering x2 and x4 as fixed inductors
and B3 and B5 as identical capacitors driven fro
.11
a common shaft. With these
constraints, 33 and B5 would then control impedance magnitude while Bl controls
impedance phase. The input admittance will be adjusted to a pure conductance
of magnitude Go provided B/ and B3 are simultaneous solutions of two fourth-order
algebraic equations. Since these equations do not lend themselves to a general
solution, the problem was simulated on a digital computer. An exhaustive study
of the network did not seem desirable at this time, but it appears that the
necessary tuning ranges are approximately as shown in Figure 6. This network
still requires a variable capacitor having a rather large value of maximum
capacitance. A further investigation of this network has been postponed until
other less complicated schemes have been definitely eliminated.
(d) Lattice Network
The problem of analyzing the lattice was placed on an analogue
computer. In order to instrument the computer, values for the arms of the
lattice had to be chosen. The choice of components was restrained to variable
capacitors with a 100:1 ratio of maximum to minimum capacitance and inductors
that would have small losses over the frequency spectrum being considered. Such
a network is shown in Figure 7. Although a 100:1 ratio of capacitance is
optimistic, it was felt that if the network was successful, an effort to reduce
this ratio would be made in the future.
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YIN
o
- 10A -
o
IMPEDANCE MATCHING THREE RUNG LADDER NETWORK
FIGURE 5
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3.2?h
- 10B -
3.40
7-
2 120-5300 _,F7-500
iLiLf f
\ ett. f
/ 7-500
?,p.f ,
GA + j BA
LADDER NETWORK FOR IMPEDANCE MATCHING IN
THE 3-15 MC BAND
FIGURE 6
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5 p. H
51.1. H
FIGURE 7
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However, results from the computer indicate that the input impedance
to the network cannot be made a pure resistance within the constraints that were
placed on the components. Further work on this type of network has been post-
poned indefinitely.
(e) Variable Transformer Network
Another approach to this problem is a variable transformer shown
in Figure 8. This circuit is a single tuned transformer with a variable tap on
the primary side. This circuit has been analyzed from the viewpoint of an untuned
transformer to which a tunable capacitor C is added, in order to make the input
impedance to the transformer a pure resistance, and a variable tap is added to
"tap down" this pure resistance to 500 ohms. Consider the circuit shown in
Figure 9 where r and rs are the resistance of the primary and secondary respectively.
It may be shown that
Z Z 4M
Zs 0 ZL
2
where Z r 0 jtal, is the primary impedance
P P
Zs rs jwLs is the secondary impedance
Z14 jai is the mutual impedance
ZL = RL 0 JXL is the load impedance
Furthermore, by choosing the values of the circuit elements appropriately, it may
be shown that Z is always inductive for all values of ZL specified, i.e.,
Z R 0 JX (inductive)
If a capacitor, C, whose magnitude is
C
R2 X2 - I Z I2
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- 11A -
FIGURE 8
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Z
- 11B -
FIGURE 9
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is placed in shunt with Z, Z will be a pure resistance whose magnitude can be
calculated from:
R r 1
t.321M2 (rs 1 RL)
(rs RL)2
This value of R appears across the entire coil and we can tap down to a 500 ohm
level by using the variable tap on the coil. It is seen that R is a complex
function of frequency and a large range of tap values must be allowed.
Preliminary laboratory experiments with this scheme indicate that the
entire range of load impedances, over a frequency variation of 3 to 15 mc., can
be transformed into an impedance of 500 4 JO. This involved an insertion loss
of about 0.2 db. at 10 mc. However, this was done with a modified variable
inductor (Johnson 229-203) whose dimensions are 6k" x 3" x 3". Work is currently
in the model shop to reduce the size of the coil to 5" x lk" x 1-3/4". Future
work on this scheme is pending completion of this device.
(f) Spiral Load
The advent of a new specification for the load impedance may make
the work on the original specification, described above, obsolete. However,
since these new specifications were received only recently it would be premature
to say that they simplify the problem. In fact, they may make the problem more
difficult since the dynamic range of resistance is increased from 52:1 to 120d.
On the other hand, the load is a function of frequency which may reduce some of
the difficulties first encountered.
It is expected that more concrete information will be available during
the next period.
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3. Impedance Detector
The function of the impedance detector is to produce control signals
which indicate the type of impedance produced by the antenna matching network.
These control signals will then be applied to a servo system which varies the
magnitude of the elements in the matching network until a resistive input
impedance of the desired magnitude has been achieved.
Two D.C. output signals are derived from the impedance detector. The
polarity of the first indicates whether the load impedance is inductive or
capacitive, with zero output occurring when the load is purely resistive. The
polarity of the second indicates whether the impedance is larger or smaller than
a specified magnitude, with zero output occurring when the impedance magnitude
is equal to the specified magnitude.
The theory on which the operation of the two components of the impedance
detector is based is presented as follows. The phase detector, which indicates
whether the load is inductive, capacitive or resistive, is shown in Figure 10.
The output of the phase detector is the sum of the voltages developed across
C1 and C2. This sum indicates the phase of the impedance because of the follow-
ing facts. A fraction of the line voltage (determined by the divider C3 and C4)
is applied to the center tap of the secondary. Since the voltage induced in
the secondary winding of the transformer is 900 out of phase with the line
current, the voltage at one end of the secondary represents the vector sum of a
fraction of the line voltage plus a voltage which leads the line current by 900
.
The voltage at the other end of the secondary is the vector sum of a fraction
of the line voltage plus a voltage which lags the line current by 900. To make
the mathematics more explicit, the line current is represented in phasor
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LP
PHASE ERROR
C2 1C8 OUTPUT Ep
IMPEDANCE PHASE DETECTOR
FIGURE 10
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notation as
IL0 VL (1 1 ja),
where 1(0 is a normalizing factor which depends on the magnitude of the load
impedance. The quantity "a" will be positive for capacitive loading, negative
for inductive loading and zero for purely resistive loading. The voltage induced
across LS2 is then
VLS2 g jciMk0VL (1 ? ja),
and from the indicated polarity, also
VLSI jwillcoVL (1 ? ja),
where M is the mutual inductance of half the secondary.
then to allow C1 (and also C4) to charge to a voltage
The action of D1 is
C3
V VT iCA4k0VL (1 #
Cl IC3 ? C4 "
The action of D2 allows C2 to charge to a voltage
C3
VC2 g
I C3 ? C4 VL ? j (-)MkoVL (1 ? ja) .
The error output voltage, E, is then
E- V - V
p - C2 Cl '
which, after algebraic manipulation, becomes
2 C3
Vi.-{i[ . C3 c3 ic4 i k 2(,3 2 _2
-in (1 4 a2) 2ak (.314
E g 0 0 C3 / C4
2 2_2 C3
1 (1 a2) - 2akoL3M
3 4 C.;12 ko C3 ? C4 (1)
Eq. (1) indicates the polarity and magnitude of Ep is determined by "a", the
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factor which is a measure of the amount by which the line current either leads or
lags the line voltage.
With regard to the function of the other elements in the phase detector,
L3 provides a D.C. path for the capacitor charging currents while isolating the
R.F. line voltage from the rasp: of the circuit. C5, L4 and C6 provide additional
RF filtering.
The magnitude detector, which indicates whether the load impedance is
less than, greater than, or equal to a specified value is shown in Figure 11.
The operation of the magnitude detector is based upon a comparison of the D.C.
voltage across C1 to the D.C. voltage across C3. Assuming all impedances shunting
the load are much greater than the load impedance, the action of D1 is to allow
C1 to charge to
VC1 R1
IRi Zia I V
Due to the clamping action of D2' C3 charges to a voltage
Vc3 = V
C, L
(2)
(3)
Since L1 provides a D.C. ground, the significant part of the magnitude detector
may then be represented as shown in Figure 12. In this circuit, R1 and the DC
resistance of the coil have been considered negligible in comparison to the other
resistance in the circuit. The charged capacitors have been represented by D.C.
batteries; and R2' R3 and R, 12ave been lumped into a series connection of two
4
resistors, each designated by 11'. The magnitude error voltage, Rti, may be written
as
F14
ry.
?-?
vc3
2R?
R ?
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(?
Ca
RI
- ISA -
R3
"vy?,
R4
L2
40?rirdr??
C4
C2
o MAGN I TUDE
ERROR E
'PmC3 C3ED2
0
IMPEDANCE MAGNITUDE DETECTOR
FIGURE II
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VL
vci
1 L.
- 15B -
C2 VL
vs
c2 c3
EQUIVALENT REPRESENTATION OF THE IMPEDANCE
MAGNITUDE DETECTOR
FIGURE 12
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Since R1
-16-
VC3 i VCl
2
, substituting Eq. (2) and Eq. (3) into Eq. (4) results in
(4)
V L 7
,.., R1 1
Km - " [ C2 c2 1 c3 - ZL
In order to obtain zero output when N Ro (the desired impedance magnitude),
the parameters must be chosen so that
then
C2
R1
RV
L[ 1
EM2 Ro
(5)
Eq. (5) shows that the magnitude and polarity of Em is determined by the manner in
which ZL differs from R0.
With regard to the function of the other components of the magnitude
detector, L2, C4 and C5 provide RF filtering. The pot (R3)allows for compensation
of slight circuit unbalance.
Work is in progress to evaluate and refine the operation of the impedance
detector. The degree of accuracy with which the phase detector indicates a
resistive termination has been investigated at several frequencies within the 3-30
mc. band. Since stray capacitance exists in the detector circuits, zero output
from the phase detector actually occurs with an input impedance which is slightly
capacitive. However, this effect is small enough that it does not pose a serious
problem. In view of the work to date on the impedance detector, its operation
appears to be in accordance with theory. It is anticipated that more explicit
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- 17 -
results will be available for inclusion in the next report.
4. Automatic Tuning Program
(a) Voltage Variable Capacitors
Investigations showed that in the automatic tuning system, the
full, useful range of capacitance variation of the tuning diodes was not being
realized. The reduced maximum to minimum ratio came about because the voltage
could not be brought as close to zero as was desired. When the modulator was
balanced, it was found that a second harmonic of the subcarrier appeared at
the output. The second harmonic could not be nulled and the use of traps proved
ineffective. It was consequently necessary to reduce the input to the modulator.
While this removed the second harmonic, it introduced several other problems.
As a result of the reduced input, the maximum output obtainable was also reduced.
This situation could be improved by increasing the step-up ratio of the trans-
former feeding the rectifier (T2 Figure 3, Bimonthly Report No. 1).
Difficulty was still experienced in trying to tune the capacitors
over the full range. "Lock on" was unreliable at the low frequency (maximum
capacity) end of the bands. The trouble was attributed to the long time
constant of the rectifier circuitry supplying the dc control voltage. If the
sweeping voltage overshot, even though the modulator output passed through zero,
the long time constant prevented charge from leaking off the capacitor fast
enough to allow the system to reach equilibrium at the desired point. Instead,
the voltage would continue to sweep to the high end of the band.
In order to provide a shorter time constant, the output to the storage
capacitor is being supplied at a lower impedance level. This has called for a
redesign of the amplifier and a special miniature output transformer. A diagram
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- 18-
of this portion of the circuitry is shown in Figure 13. The transformer for
this application had not, at the time of writing, been received.
During the past report period, the Texas Instrument 2N1141 transistor
became available. This transistor is quoted as operable at 750 mc. and has a
dissipation rating of 750 mw. It was felt that the use of this transistor in
the crystal oscillator stage would result in a considerable reduction in the total
number of stages in the transmitter. This is particularly desirable because of
a consequent reduction in the automatic tuning circuitry.
Due to the radically different characteristics of the 2N1141, it was
not possible to make a direct substitution for the 2N247. The original circuit
is shown in Figure 14. This circuit has the ability to produce an output at the
second harmonic of the crystal. This output is produced by amplifying the second
harmonic distortion of the fundamental crystal frequency and is not the result of
a mechanical mode of the crystal. The output level is relatively low, necessitating
an additional stage of amplification. Several attempts were made to duplicate
this type of operation using the 2N1141 transistor. In order to avoid loading
the crystal too heavily with the lower impedances associated with the new tran-
sistors, a Darlington configuration was investigated using the circuit shown in
Figure 15. The results were not satisfactory. The modification shown in Figure
16 was also tried but operation at the second harmonic could not be obtained.
Furthermore, replacing the crystal with a small capacitor, oscillation was
obtained.
The Pierce oscillator, as shown in Figure 17, was investigated with
very encouraging results. The following performance characteristics were
observed.
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ERROR SIGNAL
INPUT 14
BALANCED
MODULATOR
SUB-CARRIER
2250 CPS
- 18A -
AMPLIFIER
FIGURE 13
2
?vcc
?vcc
VOLTAGE TO
TUNING DIODES
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?Vcc
22.5V
- 18B -
ORIGINAL OSCILLATOR CIRCUIT
FIGURE 14
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?
12V
- 18C -
FIGURE 15
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Vcc
I2V
- 18D -
FIGURE 16
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- 18E -
PIERCE OSCILLATOR
FIGURE 17
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- 19 -
(a) No oscillation could be obtained without the crystal in place.
(b) An increase in output power by a factor of eight was obtained
compared with that available from a 2N247 oscillator plus a 2N247 ampli-
fier in cascade.
(c) No output is available until the output tank is accurately
tuned to the correct frequency.
(d) Requires no change in the emitter capacitance with frequency.
(e) No second harmonic output is available. However, an output is
obtained on the third mode (shear mode) of the crystal.
(f) There is no reduction of output power when operating on the
third mode. The same output can be obtained at 15 mc. whether a 5 mc.
or a 15 mc. crystal is used.
(g) No output at the third mode is available unless the tank is
tuned correctly.
(h) Tuning is sharp, thereby increasing the reliability of the lock
on system.
(i) The output impedance is low, reducing the tuning range. This
can be overcome by tapping the collector down on the tank circuit. A
somewhat similar transistor, the XT-517 manufactured by Pacific Semi-
conductors, being a higher impedance device, may remove the necessity for
tapping the coil. An order of these transistors has not yet been received.
If third mode operation is acceptable to the customer, use of this
configuration will result in a considerable simplification of the transmitter.
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- 20 -
(b) Electrical Control of Coil Taps
To tune the tank circuit to the crystal in use, two things are
necessary:
for a fixed inductance of the tank circuit, (L1, L2 or L3), to
allow the voltage Vcontrol over the voltage controlled capacitors to rise from
about .2 Volts to about 25 Volts (thereby sweeping through the diode fi capacity
range) and then reset to .2 Volts,
(ii) at the end of the first sweep to reduce the inductance from Li
to L2, at the end of the second sweep to reduce the inductance from L2 to L3'
and finally after the third sweep to reset from L3 to LI and then repeat the
three-step cycle.
The three sweeps will cover about 3-5 Mcps, 5-9 Mcps, and 9-15 Mcps.
The range 15-30 Mcps is covered by a separate coil L4, which is connected when
the manual switch is thrown to the "15-30 Mcps" position.
The method used to meet the two demands is as follows (see Figure 3,
page 6B, "First Bimonthly Report"):
(i) The charging and discharging of the capacitor Cl, the voltage of
which is Vcontrol is made to cycle between .2 Volts and 25 Volts. For Vcontrol
1,1 25 Volts, a flip-flop circuit is actuated, making a transistor (in parallel
with the lower 2N123, on the figure) saturate and thereby suppress the sub-
carrier voltage supplied to transformer T2. When Vcontrol has dropped to .2
Volts, a new signal resets the flip-flop. The subcarrier is turned on and the
capacitor C1 will charge. Independently of the tank circuit inductance, the
capacitor C1 will charge and discharge until its voltage level has been deter-
mined by resonance.
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- 21 -
will therefore vary with time as indicated in Figure
(ii) Vcontrol
18. To operate the switches that change the tank inductance from 141-L2-L3-L1,
etc., a system of flip-flops is used. The flip-flop shown in Figure 19 has a
control-transistor Tcn in one leg. When Tis reversed-biased, the flip-flop
has only one stable position. When Tcn is forward-biased, the flip-flop will
remain in the stable position. If the point D is pulled sufficiently below
ground, the flip-flop is actuated. As long as no impulse is applied to E and
Tcn remains forward-biased, the transistor will remain in this new stable
position. What has been said about the circuit in Figure 19 holds true for the
circuit in Figure 20, where 3 p-n-p transistors have been used instead of the
3 n-p-n transistors shown in Figure 19. It will be noticed that the components
and wiring are identical on the 2 flip-flops, but that the voltage connections
have been reversed. The p-n-p and the n-p-n transistors used have similar
characteristics.
The 3.9 K and 1.6 K resistors have been chosen so that the voltage
of point H (Figure 20) is between the two possible voltages of D, (Figure 19),
and consequently the voltage of point B (Figure 19) is between the two possible
voltages of point G. If we connect the base of a controlling Tcn transistor
to G, the state of the p-n-p flip-flop determines whether the n-p-n flip-flop
is bistable or not. If we connect the base of a controlling T to D, the
cp
state of the n-p-n flip-flop determines whether the p-n-p circuit is bistable
or not.
Figure 21 shows these flip-flops connected, n-p-n's and p-n-p's
alternately. All Tcn and Tcp are reverse-biased when voltage is applied, the
initial condition of all flip-flops is thus defined. During the first charging
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V CONTROL
OVER C1
25
0.2
- 21A -
Li
L2
L2
141-
-0- L3
re-
L3
?-??????Ii.
3 MCPS -0- 5 MCPS 5MC --009MC 9MC I5C 3 MC ?0. 5 MCPS
FIGURE 18
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4
- 21B -
3.9K
TO 2N428
Tcp BASE
2N358
TO POINT G
FIGURE 20
100K
39K
40.42N358
Nib
cn 56K
390
3.9K
39K
56K
FIGURE 19
2N358
11.6K
22.5 V
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I.6K
?2N428
56K 56K
39K
Tcp
390 p.p..
5.4V.
100K
2N428 TO POINT D
FIGURE 19
41
111102N428
1
TO 2N358
Tcn BASE
3.9K 3.9K
? 22.5 V.
FIGURE 20
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Z=8V
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FULLY CHARGED SIGNAL
?
NPN PNP
?
CPT II IT
I? I
NPN PNP
?
NPN PNP
03E
?22.5V
Li .0.-L2
FULLY DISCHARGED
SIGNAL
L2 4-L3
FIGURE 21
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- 22-
operation flip-flop No. I will get its Tcn forward-biased permanently by a pilot-
capacitor Cp. The first "fully charged signal" will then actuate flip-flop No. I
and thus forward-bias the T in flip-flop No. II. A "fully-discharged" signal
cp
will then actuate flip-flop No. II, thereby
(i) forward-biasing the Ton of flip-flop No. III, and
(ii) operating a transistor switch that changes the inductance of
the tank circuit from L1 L2.
1
In the same way a subsequent "fully-charged" signal,followed by a
"fully-discharged" signal, will cause another transistor switch to change the
tank circuit inductance from L2 to L3. After a third pair of "fully-charged"
and "fully-discharged" signals, flip-flops No. V and No. VI in Figure 21 will
operate. Via a transistor VR the Ton of flip-flop No. I will be reverse-biased,
thereby resetting flip-flop No. I, and via the control transistors T011 and Tcp,
the whole chain is reset.
When flip-flop N. VI has reset, the transistor VR is reverse-biased.
As R1xCp is large compared to the resetting time of the chain, Ton of flip-flop
No. I will immediately be biased in the forward direction when VR is reverse-
biased. When all the six flip-flops reset, the switches that changed the tank
circuit inductance will reset, thus resetting the inductance from L3 to 1.1. At
resonance the sequence of "fully-charged" and"fully-discharged" signals will
stop and the six flip-flops remain in the appropriate setting, thus keeping
the tank circuit inductance fixed.
IV. Conclusions
The brief investigation of avalanche operation of low frequency tran-
sistors in order to obtain high power outputs at high frequencies was terminated
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-23-
when it became clear that this method was not suited to the RT21 transmitter
requirements.
In the investigation of matching networks, the most promising approach
appears to be that using a variable transformer network. However, a change in
specifications arising out ?f a recent visit by the customer has altered the
validity of the previous conclusions. At the time of writing, the full significance
of the changed specifications had not been determined.
The phase and magnitude sensing circuits have been built and satisfactory
results obtained. Some care is necessary in order to obtain desirable operation
over the whole 3-30 mc. range.
In the automatic tuning program, a switching circuit has been worked
out which will enable coil taps to be changed automatically so that, with a
maximum to minimum tuning ratio of only 2:1, the whole range from 3-30 mc. can
be covered continuously. Various undesirable effects which had caused a reduction
in the tuning ratio obtainable with voltage variable capacitors have been over-
come. The automatic switching circuitry has been built in preliminary form but
has not been operated in conjunction with the voltage tuned diodes.
The use of Texas Instrument 2N1141 transistors has resulted in a
substantial increase in output power from the oscillator stage. As a result of
the increased power level, the numzer of stages can be greatly reduced, thereby
eliminating a very considerable quantity of control circuitry. The oscillator
is being operated at the crystal fundamental for frequencies from 3-15 mc. and at
the 3rd harmonic for freauencits from 15-30 me.
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V. Future Plans
As a result of the changed antenna matching requirements, it will be
necessary to spend some time reconsidering the most advantageous method by
which to achieve the desired matching range. Fortunately this will not interrupt
the work being carried out on the sensing circuitry. Further work will be
necessary in order to obtain uniformly satisfactory results over the whole 3-30 mc.
range. Some attention is required to insure that the slope of the output as a
function of error is steep around the origin in order to insure adequate sensitivity.
Efforts will be made to combine the individual circuits which have been
constructed to perform the automatic tuning function. When this has been accom-
plished, a critical examination will be made to determine to what extent the
circuitry may be simplified and optimized.
As stated in the body of this report, a number of transistors of a
new type are on order. These will be evaluated for this application as soon as
they are received. They will not, however, provide a solution to the output
stage problem. Transistors suitable for this stage are not yet available. If
this situation still prevails by the time the remainder of the program has been
completed, it will be necessary to combine the outputs of several transistors
in order to posvide,at least, a token output in order to demonstrate the opera-
tion of the antenna matching circuitry.
VI. Identification of Key Technical Personnel
The following name should be added to the personnel reported in previous
bimonthly reports.
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VII. Bibliography
1. Miller, S. L., "Avalanche Breakdown in Germanium;" Physical Review, Vol. 99,
#4, p. 1234, August 1955.
2. Shockley, "Theory of P-N Junctions in Semiconductors and P-N Junction
Transistors," Bell System Technical Journal, Vol. 28, #3, p. 435,
July 1949.
3. Beale, Stephenson, Wolfdale, "A Study of High Speed Avalanche Transistors,"
Proc. I.R.E., Vol. 109, Part B, p. 394, July 1957.
4. R. F. Shea, Editor, "Transistor Circuit Engineering," p. 78, Wiley, New
York, 1957.
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25X1