TECHNOLOGY TRANSFER

• Document Type: CREST
• Collection: General CIA Records
• Document Number (FOIA) /ESDN (CREST): CIA-RDP91B00046R000100040009-8
• Release Decision: RIPPUB
• Original Classification: K
• Document Page Count: 21
• Document Creation Date: December 22, 2016
• Document Release Date: January 6, 2010
• Sequence Number: 9
• Publication Date: March 1, 1982
• Content Type: MEMO

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DIREC)R OF CENTRAL INTELLIGENCE
Science and Technology Advisory Panel
MEMORANDUM FOR: Deputy Director of Central Intelligence
SUBJECT: Technology Transfer
1. 1 share many of the concerns you voiced in your AAAS speech of last
month. But it is not only the academic community that should be admonished.
The enclosed VHSIC Notes is an excellent example of the open publication of
technical information by the Defense Department. While the VHSIC contracts are
unclassified, I believe the publication in the Notes of the detailed progress
in this technology, the status of various programs and planned activities, all
presented in detail, provides a penetrating view of where we stand in this
critical technology.
2. I also wish to call your attention to a book just published by J.
Wiley:
VHSIC (Very High Speed Integrated Circuits) Technologies and Tradeoffs by
Arpod Barns. I believe it is based on DoD-sponsored research but have not been
able to get a copy. The local bookstores report that it has been a best seller
over the last three weeks. I note that Washington is not Silicon Valley.
STAT
Chairman
Enclosure: a/s
cc: STAT
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VERY HIGH SPEED INTEGRATED CIRCUITS PROGRAM
EDITORIAL: VHSIC PROGRESS
Larry W. Sumney, OUSDRE
VHSIC Program Director
The VHSIC Program is progressing well
and continues to attract widespread
attention as a model for other program
areas in the DoD technology base. In
particular, the management structure
is maturing as a cohesive entity with
effective support from the three Ser-
vices. Currently, program management
is focusing attention on the several
aspects of the program discussed below
in order to assure continued progress
toward the defined goals.
Design validation procedures for VHSIC:
chips are required at all complexity'
levels and are not now being addressed
in sufficient depth by the Phase I
contractors. Also, the various models
and model parameters used in the val-
idation procedures do not seem to be
adequate in many cases. Considera-
tion is being given to the organiza-
tion of a workshop to address these
issues as well as program support to a
standard hardware descriptive language.
Onchip testing and fault-tolerant
design s also do not appear to be
receiving the attention required,.
although they are an important con-
tractual requirement. Approaches
being followed appear to emphasize
"stuck-at" faults and non-concurrent
testing which may address design and
manufacturing errors adequately but
not important operational testing
requirements. This area will be
reviewed carefully as chip designs
mature.
January 1982
The technology insertion efforts of
the Phase I prime contractors vary
considerably. In some instances, the
additional chip designs resulting from.
the expanded number of applications
could over-extend the capabilities of
the available staff with a resulting
degraded performance. In others, a
very conservative approach has been
adopted, limiting potential applica-
tions. DoD project offices have shown
less initiative in VHSIC technology.
insertion to date but this is expected
to change as a result of current in-
formation dissemination activities.
Overall, this area has received con-
siderable attention during the past
several months and much progress has
been made.
TABLE OF CONTENTS
Page
EDITORIAL: VHSIC PROGRESS....... 1
Larry W. Sumney,.OUSDRE
WHAT IS TECHNOLOGY?INSERTION?.... 3
R.L. Remski, AFWAL/AAD
VHSIC HIGHLIGHTS FOR FIRST
SIX MONTHS ....................... 5
.o HONEYWELL ..................... 5
o HUGHES AIRCRAFT COMPANY....... 7
o IBM ........................... 10
o TEXAS INSTRUMENTS ............. 13
o TRW ........................... 16
o WESTINGHOUSE .................. 18
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VHSIC NOTES.
Vol. 2 No.I January
Editorial Board
Larry W. Sumney
VHSIC Program Director:
C. G. Thornton
Army VHSIC Director
E. D. Cohen
Navy VHSIC Director
W. J. Edwards
Air Force VHSIC Director
19,82
Editorial Staff
R. L. Remski, Issue Editor.
Air Force Wright Aeronautical Labs
T. Lindgren
Naval Electronics Systems Command
D. Elders
U.S. Army ERADC'OM:
Published by
Palisades Institute
for Research Services, Inc.
Editorial correspondence should be
addressed to:
The Editors
VHSIC NOTES
c/o Palisades Institute
201 Varick Street, 11th Fl.
New York, NY 10014
?HStC NOTES - Vol. 2 No. 1
It was realized that the team approach
espoused by the VHSIC Program for
achieving vertical integration would
be difficult to implement. Thus, it
is not surprising thRt some VHSIC con-
tractor teams are slow in defining
compatible roles for the various team
members and that teaming arrangements
are not yet as effective as they must
be to assure successful accomplishment
of the program goals. We will con-
tinue to address this problem.
A major impetus for VHSIC was and is
the achievement of chip designs that
can operate reliably in military oper-
ational environments. The most
demanding operational specifications
appear to be those related to radia-
tion hardness. While the basic fabri-
cation technologies appear to be cap-
able of achieving the required hard-
ness, there is uncertainty as to the
effect of the reduced dimensions of
VHSIC chips on hardness. More atten-
tion will be given to nuclear harden-
ing techniques by the Defense Nuclear
Agency in a program now being initia-
ted in parallel with VHSIC Phase I.
Other areas such as susceptibility to
EMP and to microwave radiation are
being studied.
Because major VHSIC chip goals are
stated in terms of feature size,
lithography is one of the most impor-
tant technologies being addressed by
the program. In parallel to VHSIC,
major corporate investments in ad-
vanced lithographic technologies are
being made. Optical techniques are
being pushed to their limits, E-beam
and X-ray machines are-being developed
and evaluated, and other alternatives
are being investigated as well. Al-
though direct-writing E-beam technol-
ogy has been. perceived as promising
for VHSIC and a large investment has
been made in that technology, the
other options have been kept open.
Now, it appears that choices can and
must be made as to lithography invest-
ment strategies in the context of re-
cent research findings, program needs,
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VHSIC NOTES - Vol. 2 No. 1
and corporate commitments. This reap-
praisal should be completed in early
1982.
Over 50 Phase III contracts: have
awarded. Phase III is designed to
provide a broad base of research sup-
port to the Phase I and Phase II
efforts. To date, however,: the coup-
ling between the research base'and the
mainstream efforts has not been as
strong as hoped. Thisresults from
the timing of the contract awards
whereby a number of Phase III efforts
were underway while the Phase I
efforts were still being defined and
by the natural maturation of the pro-
gram. For the last several months,
the nature of the Phase III effort has
been reexamined and steps are being
taken to assure a more cohesive - pro-
gram and to minimize duplicative or
non-contributory projects.
By direction of USDRE, a Defense
Science Board Task Force is studying
various. aspects of the VHSIC Program.
This study is chaired by Dr. W.J.
Perry and is addressing such issues as
progress, funding, technology inser-
tion, report controls, and standardi-
zation. It should complete its study
and make its recommendation early in
1982.
The 1981 DSB Summer Study on the tech-
nology base identified VHSIC as the
technology most likely to have an
order-of-magnitude impact -on U.S..
defense posture. This resulted from
the pervasive nature of the VHSIC
technology and the fact that it has a
high. probability of success.
While the various issues discussed
above are important to the program and
each must be addressed, it must be
realized that none represents a
crisis. Rather, each such problem is
typical of the management concerns
that must be continually addressed in
any large complex program. As the
program progresses some of these con-
cerns will persist and others will.be
resolved and replaced by new con-
cerns. For example, it is expected
that issues regarding standard versus
custom chip design approaches will
require much management attention as
VHSIC progresses because of the re-
sulting major implications on program
directions. VHSIC NOTES will be used
to apprise you of these changes as
they occur.
WHAT IS.TECHNOLOGY INSERTION?
R.L. Remski, AFWAL/AAD
VHSIC Program Office
Among the new concepts and technology
being developed by the DoD VHSIC pro-
gram is a management issue that
requires increasing attention. This
is the flurry of application-oriented
activity known as "technology inser-
tion." Rather than just the latest in
DoD buzzwords, technology insertion is
both a charge and a challenge to the
VHSIC technologists and contractors to
coordinate with systems users to pro-
vide more timely transition from lab
demonstration to system socket utili-
zation. Over the past several
.decades, technology gestation periods
have ranged from as few as five or six
to as many as 15 years!
In the tri-Service VHSIC program, for
the first time, a large technology
development program has been directed
to work with systems users to develop
an orderly transition. procedure. This
direction comes from the Under
Secretary of Defense for Research and
Engineering, Dr. Richard DeLauer. The
shape of technology insertion activity
is seen as active intra-Service mar-
keting by the VHSIC program offices in
interfacing with various levels of
system developers throughout the
Service commands. The technology
development laboratories have estab-
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lished a network of VHSIC focal points
within potential user commands and are
providing detailed technology and
overview briefings to command level,
system program offices, program man-
agers, and engineering support- opera-
tions in various application areas.
They are also providing for. the widest
dissemination of data on chip, module,
and system design permitted consistent
with the VHSIC distribution limitation
under the International Traffic and
Arms Regulations (ITARs)},. Active par-
ticipation in the detailed technical
reviews of the Phase I contracts by
consultants from the systems develop-
ment operations in the Services is
another tool being used to further
understanding of the VHSIC program and
its technology and goals.
DoD is also publishing, on a periodic
basis, these VHSIC NOTES and "VHSIC
Specification Design Handbooks". for
use by systems designers. The Phase I
programs are structured for second
sourcing of the chip technology, for
wide distribution of CAD capabilities,
and for direct consideration of system
applications in the basic statement of
work. The Phase I contractors are.
also required to sell chips and other.
VHSIC technology to qualified DoD con-
tractors through the pilot production
lines to be established and running in
mid-1984. Therefore, the very organi-
zation and makeup of the VHSIC program
is permeated with the concept of tech-
nology transfer and-insertion, to pro-
vide DoD -with itnproved digital
processing hardware and software for
many applications by the late 1980s.
The Services and the six Phase. I con-
tractors are presently actively pur-
suing opportunities for the applica-
tion of VHSIC over and above the
brassboards being developed under the
current Phase I contracts. Applica-
tion of VHSIC technology to. systems
now in development and in concept is
evolving at the chip, module, and
brassboard levels, and in the archi-
tecture and design phases as well.
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VHSIC NOTES - Vol. 2 No. I
The concept of technology insertion.is
pervasive in that it appears in deci-
sions affecting brassboard system par-
titioning, modularity, chip and chip
design library candidates, an~_iit_the
establishment of theCAD _tools?_,which
are expected to_b, usable.-by-_a?. wide
range of DoD contractors. The use of
CAD tools will significantly reduce
the design turnaround time for future
VHSIC chips. In addition, the estab-
lishment of chip pilot production
lines will provide additional copies
of the chips for application in other
systems as they emerge over the next
few years.
The technology insertion activity in
the VHSIC program is headed by Dr.
Donald Burlage, OUSDRE, The Pentagon,
reporting directly to Mr. Sumney.
In
the Army, Dr. Pete Hudson and Mr.
Al
Bramble
(AV 995-2526/201-535-2526)
of
Fort Monmouth are the primary focal
points for VHSIC technology inser-
tion. The identified technology
insertion focal points in the Navy are
Mr. Ted Lindgren of NAVELEX (AV
222-6663/202-692-6663), Mr. Charles
Caposell of NAVAIR (AV 222-2510/
202-692-2510) and Mr. Dan Gordon of
NAVSEA (AV 222-9760/202-692-9760).
Additionally, Mr. E.C. Urban of ASN
(AV 225-1444/202-695-1444) is active
in Navy insertion planning. In the
Air Force, the focal point is Mr.
Richard Remski of the AF VHSIC Program
Office at Wright-Patterson Air Force
Base (AV 785-3503/513-255-3503).
Any persons or organizations interest-
ed in coupling more" closely to the
VHSIC Program are invited to contact
the appropriate focal point in their
respective Service or Command. Types
of services that can be made available
'by the VHSIC program offices are
briefings on VHSIC technology covering
both chips and brassboards, distribu-
tion of reports and data pertinent to
specific applications areas, and
detailed technical consultation by
program office and application engi-
neers.
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VHSIC HIGHLIGHTS FOR FIRST SIX MONTHS
Contract No.: F33615-81-C-1527
Program Manager: Dallas D. Burns
COTR: Mr. Robert Werner
Honeywell's Phase la VHSIC Program is
based on the further development of a
proven dielectrically 'isolated digital.
bipolar 1.25-um feature size. process
that is compatible with:.a large family
of circuit technologies, including
I2L, ISL, DTL, TTL, CML, and
CS2L. This process flexibility com-
bined with a semi-custom design
approach based on the development of
complex functional building blocks
called "macrocells" and supported by a
complete and integrated CAD system is
Honeywell's solution to DoD's require-
ment for affordable fast turnaround
ICs that will reliably provide very
high performance in severe military
environments. Honeywell's brassboard
is the electro-optical signal proces-
sor (EOSP). Two semi-custom chips are
required: a parallel programmable
pipeline (PPP) chip and a controller
chip. In the EOSP, two controller
chips control 32 PPP chips to meet the
high-throughput requirements of typi-
cal scene segmentation and target
recognition 'algorithms -- commonly
several billion operations per sec-
ond. Both chips predominantly utilize
ISL technology for high-density low-
power logic (64,000 gates/cm2, 30
uW/gate, 2.0-nsec delay) and CML tech-
nology for. very high-speed logic
(26,000 gates/cm2, 30 uW/gate, 0.6
nsec delay). Both chips are 360 mils
on a side with equivalent gate counts
in excess of 20,000. Because of the
flexibility of the manufacturing pro-
cess, random logic, RAMs, and ROMs can
be combined on a single chip for maxi-
mum on-chip data flow efficiency. The
PPP and controller chips can be used
in a variety of system architectures
for a wide range of signal processing
applications including acoustic,
millimeter-wave, microwave, and opti-
cal applications. To achieve the
VHSIC reliability requirement (0.006%
per 1000 hours maximum failure rate),
the chips have. been designed with
extensive self-test capabilities and
the EOSP has spare PPP chips that are
brought into play by self-test provi-
sions at the subsystem level. In
addition, on-chip redundancy is used
to ensure the attainment of yield ob-
jectives, thus reducing manufacturing
risk. Chip' packagig,-_being_.developed
jointly. with the 3M Corporation,. will
be based on state-of-the-art ceramic
chip Carrie=_ technology..with_.proven
high-pincount_ comp_atibil.ity.
In VHSIC Phase lb, Honeywell is demon-
strating the feasibility of a 0-.50-um
feature size process (ADB-IV).based on
a further extension of the 1.25-um
process (ADB-III) developed in Phase
la. The key features of both process-
es are summarized in Table 1.
TABLE I. KEY PROCESS FEATURE FOR
ADB-III AND AD-IV.
ADB-III
1.25-um minimum features
10:1 direct wafer stepper
All dry etched
All ion implanted
Oxide isolated
Three-layer CuAI metal
0.50-um minimun features
E-beam direct write
All dry etched
All ion implanted
Groove isolated
Four-layer interconnect
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Density and performance goals for
0.50-um ISL gates are 150,000
gates/cm2 at 10 uW/gate while
retaining less than 2.,0-nsec delay.
For CML logic, these values will be
60,000 gates/cm2 at 25 uW/gate with
less than 0.8-nsec delay.. Thus, the
ADB-IV process being developed, in
Phase lb will easily surpass the VHSIC
functional throughput rate requirement
of 1013 gate-Hz/cm2.. Honeywell
feels that an important strength of
both the ADB-III and ADB-IV, processes
is high inherent tolerance, to radia-
tion environments. Significant radia-
tion testing activities have been
included as a part of the Phase la and
lb programs.
Status of Phase 1 as of 1 November 1981
EOSP system design is- proceeding as
planned with initial concentration on
architectural specifications, sub-
system design, and chip and macrocell
specifications. System requirements
have been generated for segmentation,
band-width compression, FFT, arithme-
tic operations, and histogram genera-
tion. A register transfer level des-
cription of a Sobel edge operator has
been generated and documented as an
example of a PPP implementation of a
typical image processing algorithm.
Detailed specifications for the PPP
and controller chip were completed and
submitted to the DoD VHSIC Program
Office. Chip and system test specifi-
cations were generated along with
design techniques that are consistent
with non-functional test (NFT) method-
ology. Both procedural and nonproce-
dural levels of simulation using ISPS
and, DL languages are in progress.
Functions verified to date include I/O
on the PPP chip, address generation on
the controller chip, floating point
addition, correlation tracker func-
tions, and a complete processing ele-
ment of the PPP chip. Specifications
for all the macrocells used in the two
chips have been written, and function-
al DLS simulations have been completed
for most of them. Circuit and chip
0 VHSIC NOTES - Vol. 2 No. 1
design accomplishments include the
establishment of firm design rules,
basic gate designs and layouts, chip
floor plans, and macrocell simulation
and layout. The design rules were
based on processing results, with test
devices and include maximum current
limits for electromigration resistance
as well as current density limits.
.These design rules were applied to the
basic gate designs to ensure compati-
bility with our simulation and testa-
bility methodology.
The controller chip contains approxi-
mately 13,000 ISL logic gates plus
on-chip ISL ROM and on-chip CML RAM.
The PPP chip contains a number of par-
allel processing elements and associa-
ted memory consisting of 17.,400 ISL
logic gates and CML RAM. The PPP and
controller chips utilize total of 43
different macrocells. CALMA layouts
have _b-e.a_n_~ompleted._fa~-LO_o~themos.t
compleg_(barrel shifter, ALU, sequen-
cer, etc.) macrocells.
ADB-III process development is pro-
ceeding as planned with work concen-
trated on incorporating new process
technology and optimizing process par-
ameters to maximize yield. Baseline
processes for both a reduced pressure
epitaxial reactor and a high-pressure
oxide growth (HIPOX) reactor have been
established. The Phase la optical
photolithography capability has been
established based on a 10:1 direct
wafer stepper. Baseline processes for
plasma etching of silicon oxide and
silicon nitride. have been established
with excellent "uniformity. A yield
model test chip__to provide data _on_ the
density of yield_reducing .faults has
been completed throug_h_d_es_ig_n and lay-
out. Baseline processes for both a
metal deposition down-sputter system
and a plasma-assisted Si02 dielec-
tric for threelayer metal have been
established. Test chips with 1.25-um
geometry have been processe.d.and test-
ed using automatic,. measurements tech-
niques for evaluation of .device.. para-
meters. Good results were obtained
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with typical transistor current: gains
of 50-100, and collector-emitter
(Vceo) breakdown voltages greater
than 6 V. ISL gate delays. were found
.to be very uniform. with average delays
of 0.72 nsec.
The ADB-IV (0.5 um) process develop-
ment is proceeding as planned::: with
completion of- initial submicrometer
.test chip runs and evaluation of
groove refill isolation processes.
This work produced functional..transis
tors with 0.75-um emitters with typi-
cal current gains of 100-150. Devel-
opment of a technology utilizing
groove refill isolation is in pro-
gress. This will result in a planar-
ized surface with reduced isolation
area and lower. temperature/ time pro-
cesses.
Samples of groove refill using several
process variations were evaluated.
LPCVD oxide appears to yield the best
results with good planarization. Pre-
liminary evaluation of, a two-layer
electron resist structure to obtain
submicrometer metal interconnect
showed very promising results with
interconnect lines down to 0.6-um
pitch demonstrated.
The packaging development has been
planned in two steps. In Phase _la,
packaging will be developed for chips
with up to ]80_.pins,__and_ beam tape
bonding will be used for high-yield
high-reliabdlity mass-bonding chip-to-
package interconnect. In Phase _lb,
the pin count will be extended to 240
Pin , s L. and an .area 'tape-bonding concept
will be used.
In summary, Honeywell is off to a good
start on the execution of its Phase 1
VHSIC contract. All program activi-
ties are proceeding as planned and
virtually all results to date have
reinforced our confidence in our abil-
ity to meet or exceed the original
objectives of the program.
Contract yo.: DAAK20-81-C-0333
Program Manager: Dr. Art Chester
COTR: Dr. Pete Hudson
Introduction
The following sections provide brief
discussions of the major aspects of
the Hughes VHSIC program. These
include: (1) the CMOS/SOS chip tech-
nology, which provides a unique com-
bination of high speed, low power, and
radiation hardness; (2) the spread-
spec tr_u_m -communication-system. brass-
board deonstration_..ba.sed__on__three
fj_ .e.x..ble _m VHSIC funct.io.n_ chips; (3) the
DAST..,activi y, especially. the advanced
CAD system,. which.. optimizes the com-
bination of _human
_...creativitywith
machine support; and (4) the submicro-
meter process development, which
builds on and supports the 1.25-um
chip technology.
Chip Technology and Fabrication
The Hughes Phase I approach is based
on CMOS/SOS technology, which provides
high speed, low power, and radiation
hardness. The 1.25-um version of this
process is a direct development from
the existing CMOS/SOS process at
Hughes that is providing LSI chips for
production systems. The evolutionary
sequence is summarized in Table 2,
which shows the basic design rules for
each process. Both the SOS II and SOS
III (VHSIC) processes use tantalum
silicide gates and two levels of
aluminum, so they are identical except
for scale.
The VHSIC pilot line is being estab-
lished in a new ultra-clean facility
with 12000 square feet of controlled
area, computer controlled diffusion
furnaces, computer controlled photo-
lithographic processing tracks and
projection aligners, computer control-
led wafer cleaners, central computer
manufacturing control, and a full com-
plement of plasma etchers and thin-
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TABLE 2. C`MOS/SOS TECHNOLOGIES.
DESIGN FEATURE SOS I SOS II :SOS III
(um) (um) (um)
Poly.Si Gate 3.5 .2.5 1.25
PolySi Pitch 10.0 6.5 3.0
Metal Pitch 12.0 14 5.0
Metal/Poly 0/Lap 5.0 3.0 0.8
Contact 4 x 4 3 x 4 1.6x 2
film equipment. Each building block
of the process is based on computer
modeling and supervised by the
computer-aided management system.
The 1.25-um process and its design
rules have been established in cooper-
ation with two second sources, RCA and
Rockwell. The second source sub-
contracts provide for concurrent pro-
cess development, with the second
sources processing both test chips and
VHSIC function chips. The first pilot
line test chip is in fabrication at
Hughes, RCA and Rockwell. The first
lot processed by Hughes using the 10:1
direct step on wafer aligner was com-
pleted in November 1981, with good
initial results. A baseline oxide
etch process is established, and work
on etch selectivity is progressing. A
silicide reactive ion etcher(RIE) is
installed and operational. Metal etch
to VHSIC dimensions has been demon-
strated, and silicide, aluminum, oxide
etch, and the double-layer metal have
been shown to' be compatible. Process
development is moving ahead strongly,
and a SOS material characterization
and improvement effort has been defin-
ed and initiated.
Communication Chip Set and Brassboard
Demonstration
The 1.25-um CMOS/SOS chip technology
is being used to implement three
reconfigurable. function chips that
provide .__ key__._s.ignal-processing func-
tions_ common to.a. very broad range of
secure, _ anti-jam communication sys
- va. i1- ,+vLca - vol. L No. I
terns. The high performance of these
chips will enable them to provide cost
effective communication systems into
the 1990s. Their flexibility, reli-
ability, and low power will enable
them to be retrofitted into existing
and developing systems with signifi-
cant cost savings and improvements in
reliability. Detailed -technology
inse rt iota-.plans._.haye._ b.een.....deve loped
for the position location and report-
ing system (PLRS), where substantial
cost and reliability improvements can
be achieved. in near-term production
programs. In the Phase I brassboard
demonstration, the three chips will
provide performance enhancement of the
PLRS/JTIDS hybrid for the future Army
battlefield information distribution
system.. These three chips have. been
defined, and the first chip is into
layout.
The three chips are a 256-stage dig-
ital _correlator chip, an _.algebraic
ernconerLdecoderi chip, and a spread
spectrum sub ystem_chip. These chips
will operate at 25-MHz off-chip clock
rates and 100-MHz on-chip clock
rates. Their complexity level
approaches 20,000 gates, and their
full power at maximum clock rate is
less than 0.7 W. The chips are
designed for nominal operation at 5 V,
but they are compatible with 3-V oper-
ation as well. The correlator chip
has completed logic design review and
is into layout. The encoder/decoder
chip is almost ready for logic design
review, and the spread spectrum sub-
system chip is at the detailed block
diagram level, with _several parts of
the logic defined.
The PLRS technology insertion plan
covers the digital signal and message
processor subsystem module of the
basic user unit, a man-aackable...-,ter-
minal. The primary impact of the
VHSIC technology insertion will be to
halve the size, weight, and cost of
the signal and message processing
module, and to double the reliability
of this module, The total parts count
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VHSIC NOTES - Vol. 2I?. 1
for the two-card module will be
reduced from 280 to about 100. A pre-
liminary estimate of the reliability
improvement indicates that there will
be an 18% increase in the: predicted
mean time between failures NTBF) of
the basic user unit as a result. of
changing the single module.. The cor-
responding cost reduction is. 12% of
the basic user unit cost, resulting in
very . substantial production cost
savings.
DAST and CAD System
Design technology,, software tools, and
chip test support are provided by the
DAST segment of the Hughes VHSIC. pro-
gram. The CAD tools being developed
provide hierarchic al___designs. The
designer works at the symbolic level,
with structured cells. Design guide-
lines emphasize testabiliy and pro-
visions for fault tolerance, while
automatic __test ernexation provides
esentially complete test coverage.
Full utilization of the performance
potential of the chip technology is
obtained by providing concurrent hier-
archical simulation of performance`,,
including the effects of interconnec-
tion parasitics. Design_...v"erification
is provided by simulation at several
levels, and by-cross check of layout
interconnections with the logical des-
cription of the chip. The set of CAD
tools interacts through a common data
base, using' a data-base management
system. The_set of CAD tools is being
developed for. the VAX-11L780 -computer.,
while emphasizing portability .to_ other
32-bit virtual memory machines.
The development schedule for the VHSIC
CAD system includes an operational LSI
level of design _ capability at six
months. This six-month milestone was
met on schedule, providing separate
CAD tools, working on a common com-
puter. This near-term capability will
be used to design the macrocells for
the VHSIC function chips. The next
. ?
step is an interim VHSIC CAD capabil-
ity.. Work on this system. has been
going on in parallel with the basic
system. The intex.im_c.apability- will
be... available- in.. the.. second quarter of
1 and it will be able to handle
the VHSIC complexity of the three
function chips. By the first quarter
of 1983, these tools will be signifi-
cantly enhanced and integrated to form
a complete system operating under a
common data base. Finally, by the end
of the program, the total hierarchical
capability will be incorporated into
the tools and documentation will be
completed, thus making the CAD system
available for transfer to the VHSIC
community.
The VHSIC CAD tool set. is 95%
defined. In addition to meeting the
first. major milestone of an opera-
tional LSI capability at the new VHSIC
design center, a hardware and artwork
description language recommendations
report was prepared and delivered on
schedule. Good progress is being made
toward the next two major milestones;
for example, a detailed information
model for the common data base is 30%
complete.
Submicrometer Technology
The Hughes approach in the Phase lb
development of a 0.5-um CMOS/SOS pro-
cess is based on continuing evolution
from the 1.25-um process. This evolu-
tion is summarized in Table 3. A key
difference is the necessity to use a
refractory metal for the intermediate
interconnect layer in the 0.5-um' pro-
cess. This process will use e-beam
direct write to fabricate the mask
levels with the smallest resolution
and tightest alignments, and the
refractory metal interconnect permits
annealing of e-beam induced neutral
traps. The process will work with a
thinned epi-layer to optimize leakage,
threshold voltage stability,' and
carrier mobility.
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TABLE 3. EVOLUTION OF 1.25-0.5 um.
SOS III SOS IV
(1.25 um) (0.5 um)
Technology CMOS/SOS CMOS/SOS'(CMOS)
Lithography DSW E-beam (DSW)
Metalization Two-level Two-level
(Al + Al) (Refract + Al)
Epi thickness 0.5 um 0.3 um
Channel
implants Double Double
Gate
metalization Silicide Silicide
Etching Dry Dry
The submicrometer development strategy
is based on using optical lithography
to determine non-lithographic issues,
performing extensive process and
device modeling, using existing
research a-beam equipment, and utili-
zing results from the Phase la 1.25-um
process development.
The first milestone, a report review-
ing all equipment' necessary to make
the submicrometer devices, was com-
pleted and delivered on schedule. The
simulation efforts started on sched-
ule. Several test lots have been pro-
cessed to evaluate different steps in
the process and to confirm theoretical
scaling laws.
Good progress has been in p+ implants,
n+ implants, double resist processes,
and anisotropic etching. Simulation
results agree with observed perfor-
mance, predicting 50-psec ' ring
oscillator speed at 3-5 V for the
present device design. Exposure and'
development studies are providing both
positive and negative resists to sup-
port the a-beam lithography.
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0 VHS IC NOTES - Vol. 2 No. 1
Program Manager: Dr. H. Cloud
Contract No.: N00039-81-C-0416
COTR: Eliot Cohen
This. report presents progress by IBM
on, the VHSIC Phase I Contract covering
the period from-1 May 1981 through
1 November 1981. IBM's Federal System
Division at Manassas, VA, has the
prime responsibility for the VHSIC
program with support from IBM's Gen-
eral Technology Division, Burlington,
VT and Research Division, Yorktown, NY.
Technology and Processing
The key technology, requirements for
the VHSIC 1.25-um program are to
develop chips which have the following
characteristics: densities of 10-30K
gates per chip; operation with clock
frquencies on the. chip of at least
25 MHz; overall functional throughput
rates (FTR) of at least 5 x 1011
gate-Hz/cm2; and the capability to
operate in military environments. The
key program objectives for 1.25-um
technology are to develop a process,
practice this process for newly devel-
oped macros and chips, and integrate
and test these chips in a brassboard
within the three-year schedule. IBM
has selected NMOS as the base technol-
ogy for 1.25-um VHSIC because it is
IBM's lowest risk technology in
achieving the above objectives within
the three-year schedule. The charac-
teristics expected in the technology
area will meet.. or exceed all VHSIC
requirements (see Table 4). In the
packaging area, IB14 is developing a
single-chip package for the brass-
board. For the VHSIC submicrometer
program, Phase lb, IBM is examining
extensions of MOS technology at IBM's
Research Division.
IBM is developing the 1.25-um technol-
ogy capability based on in-house
development work in NMOS technology.
IBM's plan for 1.25-um development is
to extend the necessary process steps
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VHSIC NOTES - vol. 2 No .111
TABLE 4. PHASE la VIIS IC CHARACTERISTICS
Chip Technology
Performance -- 25 MHz
No. of Gates -- 30K/chip
Power -- 3 W/Chip
Size--8x8mm
FTR = 12 x 1011 gate-Hz/cm2,
(approx.)
Packaging
Single -- chip carrier..
I/O -- 240 (190 signal; 50pwr/gnd)
Interconnect -- decal
Size (substrate) -- 1.5 x 2 in.
Package (2nd lev) -- avionic
Environment
Military
to 1.25 um from established process
capability, and add the necessary rad-
iation hardening enhancements to sat-
isfy VHSIC requirements. IBM is cur-
rently characterizing the process and
is making test sites for purposes of
evaluation. Process work will con-
tinue throughout 1982 with process
transfer to the VHSIC pilot line. to be
completed in the last quarter of
1982. Radiation-hardening work is
being emphasized in the IBM approach.
Plans are in 'place, to evaluate harden-
ing enhancements through 1982 with
final techniques selected and inte-
grated into the VHSIC pilot-line pro-
cess in the 1983 time frame.
Architect'ire CAD and Support Software
IBM's major objective in the chip
architecture area is to develop a
cost-effective design capability for
VHSIC which can be used for the devel-
opment of unique chip configurations
required in DoD weapon systems. The
IBM approach complements the chip fam-
ily approach in that DoD weapon sys-
tems will continue to require the
development of new chips to extend the
capability of already developed chips
so that optimum system implementations
. ?
can be achieved in VHSIC and VHSIC-
like technology. This design capabil-
ity is characterized by a chip archi-
tecture called "master image" which
utilizes a comprehensive set of primi-
tive and custom macro functions stored
in a computer library. The designer
selects from the macro library those
functions that he needs to personalize
a chip design. Table 5 summarizes the
initial macro list under development.
Primitive macros are more simple logic
structures consisting of NORs, exclu-
sive ORs, drivers, receivers, latches,
etc. Custom macros generally address
more complex functions than primitives
such as the 16 x 16 multiplier, multi-
input adder/accumulator, interface
handler, an on-chip monitor for test-
ability, and an extendable register
file for buffer storage.
Essential to the success of this
approach is a set of CAD tools which
facilitates the design process for
macros and chips. Chips of the. VHSIC
complexity must be developed utilizing
such a CAD system. TbLis CAD system
will rovide acts fnr simu-
lation, deg i=, ~and c eski_ng,..._and
documen tat ion _thr4uQhout_the_.__overall
rocess. Products of the CAD effort
will be a basic design capability
which will permit custom chip design
for diverse system applications.
TABLE 5. Phase Macro Library (CORE SET)
Primitive Macros Custom Macros
NOR 16 x 16 Multiplier
Multiplexer Three-Way Adder
Exclusive OR Register File
On-Chip Receiver On-Chip Monitor
On-Chip Driver Interface
Clock Driver
Shift-Register-Latch
Carry-Look-Ahead Adder
Transceiver
Parity Generator
Arithmetic Logic Unit
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Under the VHSIC program, IBM is
addressing the support software tools
for designing systems where the design
assets will consist of an inventory of
VHSIC and. VHSIC-like components ex-
pressed in VHSIC hardware' descriptive
language (VHDL) and macros or subcom-
ponents of VHSIC chips, also : expressed
in VHDL. An interactive: system design
capability is needed so that:thes:sys-
tem designer may have access to the
design assets and apply various tools
for analysis, simulation, checking,
and documentation relative to optimi-
zing his system design. IBM is defin-
ing the tool set and approach to sup-
port this interactive process. As a
product of the process, optimized sys-
tem designs composed of VHSIC technol-
ogy will emerge.
Chip Development
Under the VHSIC program, IBM is devel-
oping the complex multiply accumulate
chip (CMAC) as the initial chip utili-
zing 1.25-um technology and design
capability. The CMAC is a parameter-
selectable 'signal processor which can
perform 100 million multiply and ac-
cumulate operations per second. It is
intended to be used on the front end
of signal-processing systems where
processing demands require this type
of capability: The CMAC chip executes
high-performance signal processing
algorithms required in the front-end
data stream of many sensor processing
systems. By using the IBM NMOS VHSIC
technology, -a very high multiply rate
is achieved with significantly fewer
watts and in a much smaller volume
than has been achieved with current
technologies. This high performance
is accomplished with a very simple
data flow that uses a number of multi-
pliers connected in a linear array.
The simple-structure concept extends
to the control of the chip where a
parameter selectable rather than pro-
grammable approach is used. The
algorithms executed are highly repeti-
tive, simplifying the control task.
Flexibility is obtained by loading a
S
? Vl{SIC NOTES - Vol. 2 No. I
parameter, during initialization, from
an external controller to configure
the data flow for the desired algor-
ithm. The CMAC chip has two basic
classes of operation: (1) complex
multiplication of a number of four
parallel channels by a set of pre-
loaded weights and summation of the
products and (2)- any of a number of
delay, multiplication, and summation
operations on a single channel by
using cascaded sections of identical
hardware. The CMAC operates with par-
allel stages of multiplication and
accumulation, each stage operating
with a basic clock frequency of
25 MHz. Current technology sizings
indicate a chip density in excess of
30K gates for the chip.
Testability
IBM is placing significant emphasis on
testability within the chip to provide
built-in logic for manufacturing test
and sufficient on-chip logic capabil-
ities for supporting system level
availability and fault tolerance. The
basic approach requires, as part of
the design process, added logic on the
chip to implement two major xbi1-
i~ _feature.s_ level s.ensitiv_scan
design (LSSD) amd__th.e-on-chip.. monitor
(0CM) macro. LSSD is a design disci-
pline, whereby' the function of the
chip can be subdivided into combina-
torial elements, and each element
tested by inserting test patterns with
the measured response compared against
predetermined results. . For a rela-
tively small overhead, fault detection
or coverage of greater than 96% of the
gates on the chip can be expected.
Furthermore, the LSSD discipline
allows the test patterns to be gener-
ated automatically by the computer.
The 0CM is a testability macro whose
function is to control and manage the
testability of the chip. It also
serves as the standard chip interface
for testability to the overall system
testability architecture which is
defined as the availability management
system (AMS). AMS consists of a
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TABLE 6. EXPECTED
BRASSBOARD SYSTEM CHARACTERISTICS.
o FUNCTION
- High-performance acoustic
preprocessor
Increased detection
Potential for increased system
capability
o BRASSBOARD CONFIGURATION
- Expand capability AN[UYS-1.
Upgrade to input signal
conditioner
o SYSTEM APPLICATION
- P3, S3, AN/BQQ-5, LAMPS
- Preprocessing for AN/UYS-1 Navy
standard processor
0
nology due to space, weight, and cost
considerations. VHSIC technology is
an ideal match for addressing the
acoustic problem in that the signal-
processing capabilities needed for
keeping pace with the threat can be
realized. The brassboard configura-
tion specifically addresses an upgrade
to 'the input signal conditioner (ISC)
of the AN/UYS-L. Expanded digital
processing will be added to the ISC,
permitting more functions to be
addressed by the overall configuration
without the need for redesigning the
hardware and software of the
AN/UYS-1. This "front-end" improve-
ment will provide for increased pro-
cessing capability and will facilitate
technology insertion for those plat-
forms currently employing the AN/UYS-l.
software-based executive or controller
which ties into all of the OCMs in the
system. Availability management at
the system level is the primary role
of AMS and will provide -error detec-
tion, error logging, fault isolation,
and system recovery. These attributes
are essential to achieving fault-
tolerant systems of the future. The
architecture attributes of testability
will be built, into the chips and
demonstrated in the brassboard.
Brassboard Development
The brassboard under VHSIC Phase la
development is a high-performance
acoustic preprocessor (see Table. 6).
The capability being furnished will
provide for increased target detection
in anti-submarine warfare (ASW) sys-
tems. Requirements in ASW have been
evolving and growing for many years
due to more sophisticated and quieter
threats. Significant advancements
have been made in signal processing
which have lead to very demanding sys-
tem requirements for the Navy ASW
platforms. These requirements are by
no means satisfied with today's tech-
Contract No.: DAAK20-81-C-0382
Program Manager: Dr. Dean Toombs
COTR: Dr. Pete Hudson
The Texas Instruments VHSIC-l Program
is based on a small set of multiRu=-
pose programmable system componen Es.
implemented in commercially aligned
semiconductor technologies; a multi-
mode fire and forget (M2F2)
missile subsystem demonstration brass-
board and a comprehensive -set of soft-
ware/hardware design tools to support
subsystem design with the basic chip
set.
Eight chips have been defined and are
currently under development. A high-
performance NMOS memory and seven
logic-oriented components that will be
implemented in Schottky transistor
logic (STL). NMOS was selected for
"the memory because of the high den-
sity, low power, and low cost intrin-
sic to the technology. ' STL was
selected for the logic components
because of inherent reliability and
tolerance for the military environment
and exceptional speed-power product
characteristics.
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Many of the candidate VHSIC. brassboard
systems shared several basic . IC
related'requirements such as:
o Memory:
High performance, low cost.
o Data Processing:
Data-dependent arithmetic, logic,
and control operations on unstruc-
tured data streams.
o Array Processing:
Repetitive data-independent! opera-
tions on fixed-size blocks of data.
o Limited Special-Purpose Processing
and Interface:
Some application specific require
ments must be supported.
The Texas Instruments chip set. and
related design support tools have been
architected and specified to accommo-
date these needs. A brief functional
description of the chips as they apply
to the requirements follows. The
design support tools will be discussed
later with the design utility system.
Memory needs are served with a single
.general-purpose component:
o Static Random Access Memory (SRAM):
25 usec read/write access, on-chip
parity generate/check, and 1K block
write protection.
The 1750A instruction set architecture
(ISA) was selected for data-processing
requirements and three logic compon-
ents defined as:
o 1750A Data Processor Unit (DPU):
A full 1750A ISA with 6-MIP 16-bit
fixed-point throughput, multipro-
cessor support, and memory error
detection/correction.
o Device Interface Unit (DIU):
Implements direct memory access
(DMA) operations, provides interval
timing, and performs instruction
I/O.
?VHSIC NOTES - Vol. 2 No. 1
General Buffer Unit (CBU):
Supports multiple level bus opera-
tion, provides first-in/first-out
(FIFO) buffered transfers, and per-
forms parallel I/O.
These three chips, together with the
static RAM, can be configured as an
application specific or a generic data
processing node.
Four logic chips have been defined to
meet the array processing require-
ments. They consist of a highly con-
current 16-bit fixed-point arithmetic
resource and three support chips:
o Vector Arithmetic/Logic Unit (VALU):
75-MOP 16-bit fixed-point through-
put pipelined arithmetic capability.
o Vector Address Generator (VAG):
Two-dimensional X-Y array address-
ing, FET bit reverse, cycle steal
I/O support, and data memory chip
select decode.
o Array Controller/Sequencer (ACS):
General purpose microcontroller
with nested do-loop control, a sub-
routine stack, and an register file.
o Multipath Switch (MPS):
Connects memories with ports, sup-
ports cycle ' steal I/0, single
memory/multiprocessor broadcast,
and static and dynamic state
control.
As with the data processor, these your
chips and the SRAM can be configured
to. match specific or generic array
processing requirements.
The SRAM and VALU designs are to be
executed as dedicated optimized IC
ttesigns. The 1750A DPU, DIU, ACS, and
VAG are ROM programmable components
that will each be unique programma-
tions of a 1OK-gate/52-kbit ROM base
array. The GBU and the MPS will be
implemented as programmations of a
4K-gate base array. This 4K-gate. base
array will also be available with sup-
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porting software for design and imple-
mentation of special-purpose. process-
ing and interface requirements. The
entire chip set is TTL I/O compatible
and will be packaged in; Joint
'Electronics Device Engineering Council
(JEDEC) standard leadless chip
carriers.
Chip and system level testability have
.been comprehended in the component
functional specifications. `The 'pro-
grammable system ..components: (PSCs)
will incorporate on-chip self-test and
a standard four-pin maintenance port.
This will avoid the usual test band-
width limitations, allow at-speed chip
testing, and solve controllability/.
observability depth problems. Compat-
ible processor and systems level test-
ing have been defined to support fault
tolerance operation, "push . to test"
go/no-go verification, and breakpoint/
single-step operation for system
checkout.
Preliminary chip specifications have
been prepared for all components, and
detailed final specifications are in
preparation. Actual chip design is
under way for both the SRAM and VALU..
The M2F2 VHSIC demonstration
brassboard will be based on a passive
rf, anti-radiation homing (ARH) sen-
sor, and an imaging infrared (I2R)
sensor. The data and array processing
modules defined and developed for the
brassboard will be integrated with two
existing sensors to provide the signal
and control processing required for.
the operational function of an
M2F2 . missile subsystem. The func-
tions to be demonstrated include con-
trol of the ARH and 12R sensor,
multithreat processing of the ARH sen-
sor data, precision queing of the
12R sensor to the radiating target
selected, autonomous acquisition of
the potential target from the 12R
field of view and the concurrent track
of the target by both sensors. . The
software applications for the brass-
board data processor module will be
?
written in a higher order language
(Pascal) with calling provisions to
functions programmed in 'the array
processor.
The data-processing node defined for
the M2F2 missile subsystem brass-
board is a 4-MIP 22-component config-
uration with 64K. words of 16-bit mem-
ory. The array processor node is a
22-chip 75-MOP throughput processsor
with 40K words of 16-bit memory.
Missile compatible module packaging
concepts have been defined that accom-
modate both a data and array process-
ing node on a single 9 x 5 inch cer-
amic substrate. Power dissipation on
the substrate will be well inside
I. W/in.2.
Specification of the brassboard con-
figuration and system performance
requirements based on operational
scenarios are complete. Detailed
design of the system testbed and
demonstration software is under way.
The design utility system (DUS) is a
body of user executed software and
hardware that should constitute a suf-
ficient tool set for a subsystem
designer to define a set of hardware
resources and specify the PSC program-
mations required for a given subsystem
design. The concept is analogous to
the support which is currently provid-
ed for microprocessor user community.
The DUS consists of four basic tool
sets:
o A hardware description language and
integrated simulator that is use
to specify, design, and evaluate
system level configurations, array
and data processor nodes, and gate
array programmations.
o Array processor support software
that is used to specify, emulate,
and design vector processor nodes.
It consists of a configurable reg-
ister transfer language compiler,
linkage editor, and instruction
level simulator.
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o Data processor support software
that is used to specify, evaluate,
and design 1750A-based processing
nodes. It consists of an HOL
(Pascal) compiler, 1750A assembler,
link editor, and instruction level
simulator.
o A software maintenance.' panel that
supports systems hardware software
test and diagnosis.
An integrated DUS will be delivered
under the VHSIC 1 contract.'. It is
intended to be software transport-
able. Detailed design is underway in
each of the four areas mentioned above.
Program Manager: Dr. B. Whalen
Contract No.: N00039-81-C-0414
Navy COTR: Eliot D. Cohen
During the first six months, TRW
assigned definitized work packages,
schedules, and budgets to all respon-
sible organizations including our
subcontractor/teammates, Motorola and
Sperry Univac. Additional tasks for'
testability and fault-tolerant design
were added to the Sperry. Univac.state-
ment of work. Detailed schedules and
budgets were computerized on the CSSR
system to provide means for early
identification of potential cost
and/or schedule problems.
Our process. development activities,
which include Phase la and Phase lb
tasks in both 3D bipolar and CMOS,
have continued as they were proposed.
TRW began Phase 1 with an existing
baseline 1-um process. Our Phase 1
efforts are directed toward enhancing
this process with features which
increase device density, increase
operating speed, improve yield, and/or
improve design flexibility. These
enhancements include the incorporation
of arsenic resistors to permit the
independent optimization of collectors
and resistors and thereby avoid a
penalty in scaling, the use of
-
VHSLC NOTES - Vol.2 No.1
double-level
metallization to improve
both density
and
speed, dry etching of
metal and
oxide
to permit. reduced
design rules
with
a resultant increase
in functional throughput, incorpora-
tion of Schottky diodes in output
drivers, and the use of low-tempera-
ture annealing techniques to allow ion
implant activation and damage removal
with minimum junction movement.
Highlights of TRW's achievements
included delivery of 100 flash A/D
converter chips to demonstrate the
stability of our baseline 1-um process.
Similarly, at the start' of Phase 1,
Motorola was well under way with
development of a
1.25-um CMOS process
having
already
designed a Phase 0
chip.
Motorola's
goal is to achieve a
basic
operating
1.25-um process by
February 1982 and then use that pro-
cess to develop enhancements such as
the addition of a refractory metal
shunt for the polysilicon gate
material, alternative metallization to
further reduce metal pitch, buried
contact and polyresistor technology,
and the addition of a third layer
interconnect capability. Their activ-
ities during the first six months of
Phase I consisted of producing test
wafers, evaluating them, and incorpor-
ating processing changes to improve
the performance of later runs. Equip-
ment and software tool enhancements
were also accomplished. Achievements
included production of test device
chips with reasonable yield.
Development of submicrometer process-
ing capability is' a challenging task
for both 3D bipolar ahd CMOS technolo-
gies. During the first six months we
concentrated on running experiments
and gathering data that cannot be
extrapolated from larger feature size
work. This activity included the
design of test chips. Achievements
were the establishment of an opera-
tional e-beam machine at both TRW and
Motorola, TRW's definition of a sub-
micrometer process, and Motorola's
production of working p- and n-channel
devices with 0.5-um feature size.
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VHSIC NOTES. - Vol. 2 ? 1
In the DAST effort, we examined signal
processors that require both high
flexibility and substantial parallel-
ism to achieve high volume but rela-
tively repetitive number manipula-
tions. Data-processing architectures
tend to be more serial in nature,:: less
synchronous, and more control inten-
sive than signal-processingarchitec-
tures. These differences lead to dif-
Eerent requirements not only. for VHSIC
chips but, different interconnect con-
cepts as well. The V Bus interconnect
developed by Sperry Univac allows any
single pair of users to initiate,
carry out, and terminate a communica-
tion with very little overhead and
thereby fits the data-processing
requirement. Signal proc essors, 'how-
ever, require that many short point-
to-point communications occur simul-
taneously and these can be under pro-
gram control. The DAST studies
reaffirmed our Phase 0 selection of
cross-bar-type switches for signal-
processing applications.
Computer-aided design (CAD) and simu-
lation activities being undertaken by
Sperry Univac were started. The CAD
system being developed makes use of a
number- of _existing__and..evolying soft-
ware programs. These programs include
the logic simulators, circuit simula-
tors, layout_~aids,.. testability_ aids,
routing algorithms, and verification
tools. A key task of the CAD and
simulation efforts will be to unify
these separate software tools and make
them available to a designer from a
common data base and using a single
hierarchical system language whether
he operates at the system, board,
chip, macrocell or diverse level, or a
combination of several levels simul-
taneously. One of the highlights was
the interfacing of the ADLIB/SABLE
mixed level simulator to the data base.
Testability received considerable
emphasis during the first six months.
Our testability approach is to specify
a generalized test concept around a
maintenance processor, a maintenance
r
network to connect chips and boards to
the maintenance processor, and a main-
tenance node on each chip whose pur-
pose is only to handle communication
protocol between the maintenance
processor and the chip. Within this
framework we are conducting a top-down
look at testability to identify system
requirements for testability and fault
tolerance. At this time, we are
specifying the testability features of
the individual chips. Circuitry on
each chip will perform the testability
functions and convey results to the
maintenance node. Software. in the
maintenance processor will process
individual chip results. Achievements
include the design of a main- tenance
node for use on each VHSIC chip which
meets the testability requirement.'
The EW brassboard development requires
an intensive' first-year effort during
which system requirements must be
established; chip specifications pro-
duced with all functional, testabil-
ity, and interfacing requirements
defined; and a demonstration plan
baselined. In parallel with chip
design and fabrication, all packaging
design and fabrication for chips,
boards, and the brassboard must be
completed. Brassboard software must
be developed in parallel with the
chips. All software development will
use hardware emulators because no
hardware will be available until final
integration and test. During the
first six months we completed our
system requirements defintion and are
nearing completion of 'our baseline
processor design. A major effort to
design and specify our eight custom
VHSIC chips was initiated. We com-
pleted specifications. on the window
.addressable memory (WAM) chip and are
nearing completion on the matrix
switch, register arithmetic logic unit
(RALU), and four-port memory.
In the quality assurance area, quality
control patterns which will be used to
monitor chip production line perfor-
mance were defined.
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18 ? ? VHSIC NOTES - Vol.2 No.1
WESTINGHOUSE
Contract No.: F33615-81-C-1532
Program Manager: Dr. John Walker
COTR: Mr. Robert Werner
The Westinghouse VHSIC Program is a
team effort focused on the development
of a multiprocessing computer capable
of handling the signal-processing
functions of the advanced tactical
fighter environment. Included in the
team are National ..Semiconductor,
Control Data Corporation, Harris, and
Carnegie Mellon Institute. The team
has adopted a commonality concept
which includes a chip set based on
1.25-um CMOS IC technology, a set of
modular signal processors, architec-
ture capable of adaptation to a large
variety of environments, and a high-
order language programming approach.
A pilot line has been established for
the fabrication of VHSIC chips. Pro-
cess experiments and simulations have
been used to define the CMOS baseline
process which will meet speed, den-
sity, and, reliability requirements. A
process development test vehicle has
been designed and is in fabrication to
verify lithography, design rules, per-
formance, and reliability of the base-
line process. Parallel experiments
are also in, progress- to optimize the
baseline process prior to fabrication
of logic test vehicles during the next
reporting period..
A total of.36 minicells, the basis of
the hierarchical design approach, have
been designed and simulated. A hand-
book containing design information is
being prepared for use by the team
members. Models are to be introduced
into the computer data base for use in
logic design.
During the next reporting period, a
minicell test vehicle, a gate array
test vehicle, a 16 x 16 multiplier,
and a 64K memory test vehicle will be
introduced into the pilot line as a
part of the validation process. The
minicell test vehicle will contain
samples of the minicells and associa-
ted delay chains necessary for evalua-
tion of minicell performance. The 16-
x 16 multiplier is the first VHSIC
density logic circuit to be completed
using the minicell library and it
exhibits a gate density of 160K
gates/cm2. The gate array test
vehicle will provide test cells of the
gate array to demonstrate its perfor-
mance. Likewise, the memory test
vehicle will demonstrate yield and
operational parameters for the 64K
memory design.
The package development program has
identified package requirements and
has resulted in development requests'
to four package manufacturers. The
packaging study -is addressing large
pin count packages, 120-220 pins, with
leads on 20, 16.67, and 12.5 mil cen-
ters. Close center wire bonding,
approximately 5 mils, and tape bonding
experiments are in progress.
The initial emphasis of the 0.5-um
pilot-line technology' task has cen-
tered on process definition, x-ray and
e-beam lithography experimentation,
submicrometer test vehicle fabrica-
tion, and resulting device physics
analysis. Design of an advanced sub-
micrometer test vehicle and device and
circuit modeling development are also
in progress.
Process definition problems that have
been ad.fressed include thin gate oxide
development, dielectric spacer, bird's
beak, shallow junctions, and contacts
to shallow junctions. Submicrometer
n- and p-channel devices have been
fabricated. The n-channel 0.8-um
devices showed punch-through voltages
in excess of 3 V. P-channel devices
remain to be optimized. The n-channel
threshold voltages varied from 0.2 V
for 0.5-um gate length to 0.35-V for
5-um gatelength devices. Devices have
also been fabricated using a-beam
direct write on the polygate? level.
Devices with gate lengths down to
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VHSIC NOTES - Vol. 2 1
0.25 um are present on these wafers
and will be evaluated.
A submicrometer test vehicle with
three levels of design rules is being
designed. Completion of the layout is
expected in the next reporting period
and initial first-level design rule
devices are expected to be fabricated.
Chip development is presently. in the
preliminary design phase, the, purpose
of which is to define in detail pro-
ducible chips which meet system
requirements. The goals of this phase
are specifications, block diagrams,
macropartitions,
I/O
requirements,
critical
timing,
and micro-instruction
sets. Of
the five chips,
the GP con-
troller,
16-bit
AU, and
pipeline AU
are complete and a preliminary design
document has been issued. The extend-
ed AU and the 64K memory will be'com-
pleted early in the next reporting
period. Analytical models, detailed
macro-design, and testability analysis
will be undertaken in the next report-
ing period.
The module development is likewise in
the preliminary design phase with the
goal of providing the details of mod-.
ule architecture required to meet sys-
tem requirements. The tasks upon
which efforts have been concentrated
include module specifications, gate
array partitions, instructions, crit-
ical timing, and I/O requirements. Of
the five modules, progress has been
greatest on the complex arithmetic
vector processor (CAVP) and the vector
scalar processor (VSP) since their
architecture is dominated by the 1750A
embedded computer design. The float-
ing point processor (FPP) is following
the first two modules. The hier-
archical multiprocessor system con-
troller (HMSC) module is paced to sys-
tem architecture studies currently
under way. The bulk memory module
(BM) is paced by both the architec-
ture studies and the HMSC. The pre-
liminary design specifications for
these modules will be completed and
analytical models and gate array
definition will be undertaken in the
next reporting period.
The system development effort has con-
centrated on the hierarchical multi-
processor system (MS) architecture
definition and interconnection network
development. The HMS study has relied
on a multidisciplined team to address
scheduling algorithms,. software, hard-
ware, interconnection networks, and
their interrelations. Architectures
being evaluated include distributed
and centralized control structures.
During the next reporting period the
definition of the low-speed computer
bus will be completed and the high-
speed bus definition begun. The base-
line structure will be finalized and
interconnection networks defined.'
The brassboard support software task
is addressing signal-processing aids,
the Ada compiler, and the operating
system. A structured Ada methodology
for signal processing has been select-
ed. This technique allows systems
analysts to define an operational
problem as a set of graphs. The nodes
of the graphs are Ada tasks along with
control and data transfers. To sup-
port these tasks a signal-processing
instruction set has been defined.
The Ada compiler study is defining the
requirements of the front end, the
optimization processor, and post pro-
cessor. The current plan, is to employ
Army/Sotech front end. However,
schedule incompatibility is generating
difficulty in implementing the plan.
Optimization techniques are being
selected. The post-processor defini-
tion is being paced by the HMS stud-
ies. The kernal and radar operating
`'system definitions are also being
paced by the HMS study.
Radar system mission- analysis studies
were used to identify baseline radar
modes and sequences of radar modes for
the ATF brassboard. These, in turn,
were analyzed to determine' their
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r. 20
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algorithms, content, and nature.
Likewise., the algorithms are: being
analyzed to determine their signal
processing instruction mix. The end
result of this analysis is to generate
time lines and work-load descriptions
to feed the brassboard simulations.
The system. simulation has centered on
two areas. The first of these, ECSS
It, is directed toward simulating the
whole brassboard system under' speci-
fied workloads. A simplified two pro-
cessor model has been run`. A .complete
brassboard model aimed at simulating a
real time radar, input buffer is near
completion. The second simulation
task is to generate an ATF performance
baseline on an eclipse computer. The
synthetic aperture radar (SAR) mode
algorithms 'selected for brassboard
implementation are presently resident
on this computer and are being further
developed for use in the performance
baseline. Detailed descriptions of
? VHSIC NOTES - Vol.2 Nc.l
three major functional blocks as
applied to the brassboard have been
completed.
The CAD package is an integrated pack-
age centered around a data-base man-
ager and running on a CYBER computer.
The data-base manager and ASSIST sim-
ulator are in place. For high-level
description and simulation, the ISPS
language/simulator is to be added to
the system. An automatic test pattern
generator and fault simulator are to
be moved onto the CYBER from a
UNIVAC. A gate array router, a custom
layout package, and symbolic layout
package are under development.
For current design utilization, a data
base translator has been written to
allow team members access to common
information. Training has been held
for team members to allow early appli-
cation of ISPS for functional simula-
tion and design validation.
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