JPRS ID: 10531 JAPAN REPORT

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• Collection: JPRS
• Document Number (FOIA) /ESDN (CREST): CIA-RDP82-00850R000500060044-2
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• Document Page Count: 42
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• Sequence Number: 44
• Content Type: REPORTS

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JPRS L/ 10531
_ 19 May 1982
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_ CFOUO 31 f~2)
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~
~ F~~~ FOREIGN BROADCAST INFORMATION SERVICE
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- JPRS L/10531
19 M~y 1982~
JAPAN REPORT
CFOUO 3~.~'82) �
CONTENTS
SCIENCE AND TFCHNOLOGY
Characteristics of Hitachi ;i-280H Computer Described
(Kenichi Furumaya, et I~IIKl~I ELECTRC:;rICS, 1 Fe'u 82) 1
OverGeas Petrochemical Pro~ects ~'ace Difficulties
~P7THON KEIZAI SHIMBUN, 18, 19 Mar 82) 34
- a - [III - ASI~ - 111 FOUO]
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SCIENCE AND TECHNOLOGY
CHARACTERISTICS OF HITACHI M-280H COMPUTER DESCRIBED
Tokyo NIKKEI ELECTROHICS in Japanese 1 N'eb 82 pp 156-182 .
. [Article by Kenichi Furumaya (chief), Toshihiko Ktaka, Katsuhiko Takizawa,
Fumiyuki Ko~ayashi, Chikahiko Izumi of DEpt. of D~evelopment, K~anagawa Plant, Hit
_ Hitachi, Ltd.]
_ [Text] Abstract by Nikkei Electronics
The M-280H is a~eneral-purpose large coi~iputer which has
1.3-1.6 times mcre throughput than c:he conver_tional
M-200H. In order to realize this throughput, various
- improvements rave ~~en made: in the system~ and in the
semiconductor technotogy. Regarding the systems, they
= are not basically different from the M-200ia. However,
the M-280H has delicate cor~,trol, f or instance, diso~ders
in the pipeline are reduce~ by :;~lbdividing SS (storade to
~ storage) type instructi~ns fer ~_ocessing. Ir~ semiconduc-
- tor technology, the ~iegree of integration of logic-in
memories a.n~d high-speed bipolar memories is d.~ubled and
_ quadrup.ted respectively to give latitude f~r the expansion
of buff:"er memo:ies. Also, the main memory capacity i~
enlargE:d to 32 M bytes from the conventional maximum 16 M
~y;.es, and tlie channel throughput to the maximum 96 bytes/
sec.
The systems for users who utili~e large computers have recently increased ir.
scale rapidly, and the mode. of use tends to be increastngly diversif ied. In
line with this trend, computer makers strive continuously to develop new
- large models with better throughput.~~2~6~~
'Tlie tiITAC M-280H (called M-280H hereafter) is the top model of the HITAC M
series due to its ~arger scale, greater versatility and hioher performance.
It is better than the M-200H announce~ in 1978.1
The M-280H was developed under the following guidelines.
(1) ImpXOVement of Throughput
Using the latest hardware technology, the speed of the logic system was raised,
and firmware such as a system expansion mechanism and a VMA (virtual machine
- assist) mechanism, was i.ncorporated.
I
1
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- (2) Emphasis on New System Mechanism Support and k'uture Expandability
It is supplied wi_th a main memory which exceeds 16 M bytes and can accomrtnodate
over 16 cha:znel connections, anc a 3 M bytes/sec high-speed channel connection.
Also, it has room for future exp3nsion of the main storage, expansion of the
buffer storage aiid connection for a high-speed I/0 unit.
(3) Improvement in Reliability/Maintainability
Highly reliable parts were used, and it is fully equipned with an automatic
recovery functio~: and a maintenance function.
Relaxation of F.quipment Conditions
Aiminb at spa~e-saving and energy-saving, cables for connecting peripherals
(discs in particular) are more ~xtendable than in conventional models. Also,
an optical channel adapter was pr.ovided to make it possible to use cptical
= fibers in Lieu of I/0 cables.
(5) Improvement in Operabi.lity
The console functfon is fully equipped, and the automatic-run f unction is
reinforced.
Among the above developmental guidelines, the most important item is the im-
provement o~ throughput suitable for the top model.
Throughput of computer systems has two aspects: a capability based on how fast
a job can be processed and a capabl~ity based on how many jobs can be processed
, in a given time. The for:ner capability is demanded by large-scale science and
technology calculations, while the latter capability is demarided by on-line sys-
tems for bank deposits and seat reservations. Recently, demands for processing
many jobs in a given time, such as on-line processing and conversation process-
ing, are on the rise, aiid i~ipravement of system throughput has tended to be
stressed. However, with the progress of science and technology, demands for
high-speed pr~cessing of large-scale science and techn~logy calculations (one
job) are also increasing.
In November 1980, the U.S. IBM introduced a new large computer, the M-3081
(Model group D). This model is said to have a great improvement in perform-
ance over the same conr~any's model 3033, ~*hich was the top of the line until
then. Also, it was highlighted because of its double-headed processor.6 In
tl~~ case of the double-headed processor, two processors op erate in parallel,
and the capability to pY~ocess many jobs in a giv~n time is the siun of the two
processors, however, the capability to process a~ob at high speed may some-
times be determined by the capability of one processor, reducing capability,
in this case, to half of the total throughput.
Witt~ tnis ~ackground in mind, we developed a high-performance processor which
greatly exceeds that of the M-200H, incorporating a single processor in order
to ~eet the two demands--improvement of systQm throughput and high-speed process-
ing (oi one job).
2
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The M-280H can use practically all the software, peripherals and terminals A�
tlie existing M-series as system components. It is considered that a system
composed of this processor, a VOS3/SP (virtual storage operating system 3/sys-
tem product) which is a new program product, a VMS/ESO (virtual machines sysrem/
extended system option) and a new large capacity disc drive (1260 M bytes/
spindle) to be supported by these, a:Long with a Chinese character printer and
a video data sys*.ers, can very we11 acc~~odate diverse user needs.
I. Processor Outline
Figure 1 shows the external appearance of the M-280H system. Figure 2 gives
an example of the architecture o~a two-unit close-linked multiprocessor.
The M-280H is the sister machine of the M-200E, and its external aprearance and
logic structure are si~�ilar to the M-200H. However, it is a processor designed
for high speed and high reliability using newly developed high-Integration LSI
and semiconductor. memories.
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Figure 1. External Appearance of Lhe r'I-280H Processor
3
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Rc~alization of Throughput 1.3-1.6 Times Greater Than the M-200H
'1'able 1 gives thz general specif ications of the M-280H in comparison with
the M-200H and the M-180, which were yesterday's top of the line models. The
system functional specifications of the M-230H were expanded, for example,
doubling the main storage capacity and the channel numbers connectable to the
system compared to the M-200H. Also, the channel total data transfer capabil-
ity is approximately four times better than tre M-200H, to a maximum of 96 M
bytes/sec/processor.
Table 1. Architectural Compdrison of M-280H With Conventional M-200H and
M-180. System specifications ~f M-280H are expanded in main storage
capacity and in ntunber of ec.~nnectable channels.
Item ~:-280H M-200H M-180
Main storage max~imim? csnacity
(M-byte) 32 16 16
capacity (k byte) 64 64 32
buffer control system, set associative set ajsociattve
storage coltunn x line 64x16 156x4
t~lock size (byte) 64 64 32
address
translation setup, entry x level 256x2 256x2 128x2
buffer number of entries 512 512 256
maximum number of IOP 4 3 2
I/0 maximum number of channels 32 16 16
channel total data transfer
9 6 26 16
capability
Integrated array processor yes yes ~ yes
S}~stem expansion ~echanism Standard Peripheral Peripheral
~
In performance, the M-?.80H has a throughput 3.5-5 times and 1.3-1.6 times more
~ than the M-180 and the M-200H, respectively. Figure 3 gives an exam~-le of a
specific performance comparison when some jobs were processed. In this case,
the assigned jobs consisted of two technical calculations, one general compile
job and one Cobol office calculation. With the standard M-280H, performance
about 4.5-5 times superior to the M-1$0 (1.4-1.5 times superior to the M-200H)
, was obtained in handling the tech~nical calculations and the general compile ~ob,
while performanc~a 5 times superior (1.6 times to the M-200H) was obtained in the
off.ice calculation. In calculations using a M-280H with IAP (integrated array
processor), performance was approximately 6 times and almost 14 time~ better
in handling the respective jobs.
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Figure 3. Example of Performance in Benchmark Test Program
Key:
(1) performance ratio (4) general (compile) job
(2) technical job 1 (5) Cobol job
~3) technical job 2 (6) with IAP
The throughput of technical calculations using this system with IAP is equiva-
lent to approximately 10 MELOPS (million floating point operations per second).
This ran~e of performance is close to that of a supercomputer, and is very
difficult for a general-purpose computer to achieve.
The high-speed processing of the M-280H is primarily derived f rom the
shortened machine cycle time.� In order to shorten the machine cycle time, we
have developed the latest hardware technology beginning with a maximum 1,500
gate/chip high-integration high-speed LSI and logic systems suitable to that,
as will be discussed later in this article. A1so, high speed is achieved by
incorporating a system which was dPSigned to shorten the operation execution
cycle in respect to some instructions.
Upgrading of Element Integration and Expaasion of System Specifications
In the following, hardware technology, logic systems and system specifications
newly developed for the M-280H will be listed in comparison w~th those of the
M-200H.
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l. Hardware Technology
Logic LSI wit~lMa:cim~ Gate 550/1500. Improved approximately two-thirds coznpared
with that used for the M-200H in terms of s~eed power product.
Logic-In Memory Element. Used i:or address array o~ the buffer storage. The
~ degree of integration is double that of tre M-200H.
4 K Bit High-Speed Ripolar Memory--maintains 7 ns-element-level maximum access
time and is used for control storage and buffer storage. The degree of inte-
gration is quadrupled compared with that of the M-200H.
64 K Big High Speed n MOS Memory--used for the main storage. The degree of
_ integration is quadruple that of the M-200H.
18 Layer Backboard. Improved in wiring density 33 percent, to 18 layers,
compare~' with the M-200H. The backboard of the M-200H has 14 layers.
2. Logic Systems
'rhe logic systems adopted in the M-280H took basic parts from the M-200H, but
those parts were also further strengthened in several ways. What the M-280H
took from the basic logic systemsl of the M-200H are: (1) sophisticated
pipeline control, (2) microprogram distribution and layout, (3) 64 K byte
high-speed buff er storage accessible every 1/2 machine cycle, (4) 51.2 pairs
of address translation buff ers (TLB), (S) high-speed computation mechanism
calculable at 1/2 machine cycle, (6) 8 or 16 way interleaves of main storage,
(7) integrated array processor (IAP).
In the M-280H, the following further points were reinforced making the most of
the characteristics of these logic systems.
Reinforcement of Pipeline Control
Development of primitive resolution function.
' Augmentation of branch instru~tion control.
Augmentation of pipeline disorder factor detection capability.
Improvement of capability to recover from pipeline disorders.
Shortening of computation cycle numbers of deca.mal arithmetic instructions.
Int~grated array processor instruction expansion
Firmware provided as standard.
3. Expansion of System Specifications
htaximum Main Storage Capacity Expanded to 32 M Byte
'Ihat of the conventional M series is 16 M bytes. In order to expand the main
storage capacity, it is necessary to expanrl the effective address from 24 bits.
'Therefore, the page table ent~y which traMSlates a logical address to an effec-
tive address was expanded.
. 7
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_ Maximum Connectable Channel ~Tumbers Expanded From 16 to 32
The channel throughput was enlarged to accommodate an incrEase of system file
capacity and improvement o� the processor's internal processing speed.
II. Logic Structure and System Improvement
A big problem in improving processor performance is the architectural method
of the main storage system.
Many of the current general-purpose lurge processors have a bihierarchical
storage system comprised of high-speed buffer storage anc~, comparatively low-
sneed main storage. The M-200H also used a bihierarchical storage system.
When striving to enhance the performance of a single processor mainly by up-
grading the speed of the machine cycle, it is necessary to improve the speed
of the main storage in proportion to improvement of the machine cycle in order
to enhance the total performance proportionately to the improv'ement in the
machine c~cle.
On the other hand, demand for a larger main storage capacity is also increas-
ing. This is because systems that perform in parallel conversational process-
ing, batchprocessing, data base processing, etc, ali in the same s,ystem, have
increased, and a large main storage capacity suitable f or these systems is
in demand. These needs are especially prevalent in regard ~to large computers.
In other words, there are two things demandedl of the memory--improvement in the
speed of elements and upgrading of the capacity. However, from the aspect of
semiconductor technology, a project to 3chieve higher speed and integration not
only encounters technical diff iculty but also raises costs, making it difficult
to improve the cost performance ratio. Therefore, a general solution ta this
problem boils down to the adoption of a high-speed buff er storage.
An average instruction execution time Tavg of a processor with a buffer storage
can be expressed as
7
Tavg = Tb + N � Tacc
The inverse number to this, MIPS (millien instruction per second), is often
used as an index for performance. Tb is the average instruction execution time
wiien all instructions and operands are present in the buffer storage. Tacc is
the access time of the main storage viewed from ths processor. N indicates the
incidence rate, once in so many instructions in cases where data to be
- accessed cannot be found in the buff er st~rage. Accordingly, (1/N)�Tacc
expresses time taken for the main s torage access in case the buff er storage
does not contain data as an average overhead time/instruction.
(1 - 1/N) is the probability of the presence of the necessary data in the
buff er storage, and is sometimes called the hit ratio of the buff er storage.
'rhe buffer storage hit ratio is determined by the buffer storage capacity and
the nature of a job or a program. When a buffer memory is 64 K bytes, gener-
_ ally the ratio will be in the 85-99 percent range.
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Incidentally, by accelerating the processor ffiachine cycle, Tb can be prapor-
tionately reduce3. However, (1/N)�Tacc remains the same if no further measures
are taken, and the total performance sometimes may not improve in proportion
to the machine c}icle. Consequently, it is necessary to raise the previously
described hit ratio, that is, increase the value of N(enlarge buffer storage
capacity) to enhance the total performance.
- Giving Expandability to Buffer Storage by Upgrading Element Integration
Concerning the above described architectural problem of the memory systems, the
following guidelines were observed for the development of the M-280H to avoid
the complexity of inemory architecture as a whole.
(1) Elements for the main storage were highly integrated to enlarge the storage
capacity and to give it future expandability.
(2) A bihierarchical memory structure was adapted, and expandability was
giver. to the buffer storage for the improvement of the buffer storage hit
ratio.
In line with these guidelines, for the ~nain storage use, a highly integrated
64 K bit n MOS memory was developed which was suitable for enlargement of
capacity. Also, for the buffer storage use, a 4 K bit bipolar nemory was
developed, in consideration of future expansion, which was four times more
highly integrated than that of the M-200H. Tntensity of int~~gration was.doubled
for the logic-in memory (to be described latpr), also for the sake of future
expandability.
Meanwhile, in order to reduce Tb, a basic policy was set to develop high-speed
and high-integration logic LSI to be packaged at a high density to improve
~ the machine cycle. This idea to improve performance by high-speed high-density
packaging will be discussed furt~er later, but at present, specific examples of
improvement in logic systems implemented in con~unction with this will be
given.
- Furttier Strengthening of Pipeline Control System
The architecture of the M-280H is shown in Figure 4. The internal makeup. of
the central processing unit (CPU) is si.milar to that of the M-200H and con-
sists of a storage cantrol unit (SCU), an instruction control unit (IU), an
arithmetic unit (EU) and a service unit (SW). ~
The M-280H is charac.terized by the fact that the insi.de of the arithmetic
unit (EU) is subdivided into a general ariChmetic unit (GU) and a floating-~
point unit (FU), each working as independent logic unit.
As described above, by giving an independent control and memory to each
separate general arithmetic unit and floating-point unit, it is possible to
shorten the arithmetic loop time required for calculation (far example, time
taken for work register contents in a fixed-point addition executed by a
general arithmetic unit to be added up and returned to the work register),
- which eventually shortens the machine cycle.
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= Regarding GU control storage, the storage capacity is doubled compared tu the
M-20QH for the purposes of supporting an intervirtual memory comtm:nication
functinn, providing ~rarious fii~nnaare as a stanclard, and s~hortening the arith~.
~ metic cycle numbers.
: To realize high-speed operations, the standard operation width is 64 bits. The
main calculators are, for instance, a s~ri~l adder, a par.a..?lel adder, a shifter
and a multiplier-divider (HSA).
Next, improvement of the pipeline control system, improvement in reduc~ing the
_ arithmetic cycle numbers necessary for execution of general instructions, and
a contrivance for vector processing in an IAP will be described as examples of
improvements and contrivances achieved for the instruction processing system.
T, pipeline control system, similar to.the M-200H, f lows as shown in Figure 5
when tygical instructions--foc instance, !.d, Compare, etc--are consecutively
given. In processing consecu+~ive typical orders such as this, the IU can
~ transmit an interpreted instruction to the GU at 1 machine cycle pitch. The
- EU can process this a~t 1 machine cycle pitch.
The following are possible factors that disturb the above described pipeline
control.
(1) Absence of instructions created by the delayed instruction read-out due
to the concurring operand read-out and instruction read-out to the buffer
storage.
(2) Execution of branch instruc~ions.
(3) Execution of SS (storage to storage) instructions.
(4) Absence of operands by waiting when operands are read immediately after
they are written.
- (5) Execution of a system control instruction.
(1) is the absence of instructions which occurs when the operand readout of
an instruction given four instructions prior to the instruction which must be
presently read-out concurs in the same machine cycle in the flow of the pipe-
line shown in Figure 5, and the instruction read-out in such a case, is put
_ on hold.
To solve this situation, the system was tempered when the r1-200H was being
developed, so ti~at the simultaneous operand read-out and instruction read-out
become possible in the same machine cycle in relation to the buffer storage.
Specifically, it was designed to give access 1:o the high-speed buffer storage
two times in 1 machine cycle--1 machine cycle was divided into a former-half
and a latter-half cycle, and the former-half cycle was used for the operand
read-out and the latte;�-half cycle was used for read/write operation. This
system is adopted also in the M-280H. As a result, this problem was completely
solved.
11
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0 1 2 3 4 5 6 7 8 9 1Q 11
m IF D A OF E
@ D A OF E
m IF D A OF E
D A OF E
(;1 IF D A OR F,
Figure 5. Flow of M~280fl Pipeline Control
Key: M-280H pipeline example operation of
IF: instruction read-out instruction
D: instruction decode and address calculation control
A: address translation unit
OF: operand read-out. operation of
E: instruction execution ~ ~ arithmetic unit
(2) is a pipeline disorder during a branch instruction execution due to the
- absence of an instruction until an ~nstruction is readout from the branch.
In case of the branch instruction, the next instruction is read as an operand.
Therefore, an instruction from the branch can be'executed at the same time as
- ~ the execution of the instruction given three instructions later, considering
that the data read as an operand is executed as an instruction according to
the flow chart of the pipeline in Figure 5.
This flow cannot be essentially avoided. However, in case a negative result
is obtained when deciding whether or not to branch based upon the ~udgment of
branching conditions, for instance, in dealing with conditicnal branch instruc-
tions, the waiting time for the results of the ~udgment of the branch conditions
becomes wasteful pipeline disorder time since the only thing to do in reality
- is to execute the next instruction.
In order to minimize this time, for example, if there are no instructions to
change the condition code (CC) before the execution of the branch instruction
after the execution of an instruction which determines the C~ to be used for
the judgment of branch conditions, branching can be contemplated during that
time. Specifically, in Figure 5, where instruction(1) is an instruction to ~
' determine the CC for judgment of branching, step (4) is a branch instruction,
- and intermediate (2) and (3) are instructions not to change the CC, branching
can be contemplated while executing steps (2) and (3). Such a system was par-
- tially adopted in the M-280H to speed up the processing.
12
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SS 'rype Instructions Loaded on the Pipeline Flow
Next, referring to factors (3), (4) 3nd (5), curtailment of pipeline control
disorders derived from these was stressed. As an example of efforts in
achieving this goal, let us talk about a high-speed processing method loaded
on ttie pipeline processing flow for SS-type logic operation instructions,
which are often used in office calculat;.on programs, on-line programs and con- ~
trol programs.
In the conventional processing of SS-type instructions, pipeline processing
was often suspended when these instructions were interpreted because of
pipeline processing difficulty due to the procedure where data read from the
main storage (or buffer storage) was computed and written into the main
starage (or buffer storage).
As a speci.fic instruction, let us think of a move character (MVC) instructio.l.
- MVC instruction is an instruction to transf er operands of a certain number of
bytes designated by the L(length) field of the instruction from the f ield
designated by the second operand address to the field designated by the first
operand address.
For simplification, we shall asstnne that the length of an operand is 40 bytes,
and the operation of the instruction is completed a~ter 5 readings and 5 writ-
ings, 8 bytes at a time. Under this condition, we shall assume that 8 byte
loading and 8 byte storing will be executed 5 times each, and ~_mitatively,
8 byte load instructions and 8 byte store instructions will be repeatedly
processed. By treating this as repetitious consecutive processing of~ load
instructions and store instructions, MVC instructions can be put on the flow
- of the pipeline processing. The flow of MVC instructions in such a case is
shown in Figure 6 (b).
In the flow of the MVC instruction executed in Figure 6, the first operand
address is computed in the D1 cycle to keep the address available in the
address regi~ter. The (OF) cycle is not required for MVC instructions, but it
- reads out operands in an SS-type logic operation, which uses even the first
operand for the operation.
The second operand address is computed in the D2 cycle; the second operand is
read in the OF cycle using the above address and written into the first
operand address in the E cycle.
Subsequently, 8 is added to the f irst and second operand addresses and 8 is
subtracted from the operand length L, !~.nd the prQCessing from the same D2
cycle will be repeated.
With this arrangement, the pipeline processing as shown in Figure 6(b) can
be executed. Figure 6(a) shows an imaginary computer processing flow without
the above described concept. The time to execute the instruction following the
MVC instruction is approximate~.y cut in half.
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I 0 1 2 3 a 5 h i 8 9 lo li 12 13 14 is tfi 17 lN l9 20 'll tl 'L'i
\ l~
i�C ~ 1ald~ IF I) A OF E
~2~ ~ D1 A (OF
A1VC (~TiT I
D'L A OF El E2 E3 E~ E5 E6 E7 E8 E9 E10 Ell E12 E13 E14
D A OF OF E
~:ii
(3)
;~�~1n~d~'I~" Ii~ I) A UF F;
Ke 1. cnvnton 1 t 1
ui n~oFi 2. C s ti n
- 3. p i ti es 1 ti n
- nt 1
t~z n oN E 4. C ns ru ti n
5. C� mo e a a te
~4~ ~~z A OF F ( ta t fe )
~i`.~ � 6. MV st ti
~l A ~F E p ce si g y le
nx n or E �
U2 A OF E
U A OF F.
~b~
~rj~ 11~'C: n~u~~ccharnclrrl~-�Y}~~~~3~
(6) n~~�c ~r~~ iT~~PY~h'~ 'l lL
Figure 6. Pipeline Flow of MVC Instruction Processing. The n~ber of machine
cycles is nearly cut in half in the M-280H compared to conventional
computers.
As an example of speed enhancement by reducing the number of arithmetic cycles,
a decimal arithmetic instruction can be given.
In the decimal arithmetic instruction, provisions for a special arithmetic
circuit are made when there is a speed-improving effect. At the same time,
enliancement of speed was sought by adding specific microprograiu routines to
respective flows, when, for instance, the processing f low changes due to the
difference in the length of operands even within the same instru~tion.
In Figure 7, decimal instruction performance ratios of the M-200A and the
M-280H are shown. On the average, regarding the 6 instructions--addition,
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M-280H
4 ~ M-200H
1~~3
~ i~
~ ~
- ~ i `
2 ~ j
. I ~ I I
I ~ ~ ~
~ I I ~I 1 I
~ I 1 ~ I I
1
~ I I I 1 ~
~ ~ ~ i ~ i
j. I i I I I
hiS~ ~feS~ F?n: 1i.en 2;L~~ tT:~1
(2) (3) (4) (5) (6) (7)
Figure 7. Decimal Arithmetic Instruction Performance Comparison
Key:
(1) performance ratio (5) rounding
(2) addition (6) binary conversion
(3) multiplication (7) compression
(4) division
multiplication, division, rounding, binary conversion and compression.--the
performance of the M-280H Y~as improved abouc �_'::~of~id over the M-200H.
With improvement of the arithmetic systems such as indicated above, the M-280H
achieves a throughput 1.5 times greater than the M-200H in the Cobol off ice
calculation programs shown in Figure 2.
On the other hand, for science and technology calculations, it has an IAP
add-on mechanism which is unique logic mechanism. The IAP add-on~mechanism
as shown in Figure 4 consists of a vector data buffer, a vector address
addin~ mechanism and special microprograms.
'rhe IAP converts the innermost side DO loop written by Fortran into a special
vector instr.uction and processes it at high speed using an arithmetic pipe-
_ line system which is practiced in supercomputers. ~
The processing rate at this time occasionally reaches seven-eight times faster
than the cases processed by normal instructions.l~ However, the entire program
is notprocessed at such a high speed. Generally, as shown in Figure 8, the pro-
cessing rate of the entire program becomes 2.5 times faster when, for instance,
80 percent of the program execution time of a normal instruction is converted
into that of a vector instruction, and that portion is processed four times
faster. The smaller the percentage of the portion which cannot be processed by
the vector instruction, the faster the entire program rrocessing rate.

_1
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i
FoK oF~~c.~n~. ~~sN: c~N~,v
~
,
~ ~2) ~ 4
~
~ (1) ~7 h
~;u~,~;,a ~~~~~rr ie~t~~: ~3~~~ N,~ta~rit~t~8iffi5T F. .
, ~ ~ ~~'+'ir
~
i
i
i
i
i
_ I
~
i
{
i ' , /
f
(4)
- IAP 1_ x b'LjM! 'l
J
, Figure 8. Normal Instruction Processttta Time and Processing Time by IAP
J Key:
(1) r~o~al. instruction prccessing (3) portion which can be processed by
(2) porti~~i which cannot be processed vector inetruction
by vector instruction (4) prucessing by IAP
The ratio of this vector instruction processing is d.esignated as vector effi-
_ ciency, and if vector afficiency 3s designated as a and the high-speed pro-
cessing ratio (acceleration ratio) of the vec=or instruction processing is
designated as K, the improvement levei of the entire nrogram execution time R
can be obtained by the following equation:
K
S a + K (1-a)
As indicated above, improvement of vector eff iciency is important for the
. improvement of general performance. The M-200fl has provisions for 18 instruc-
tions mainly focusing on four fundamental rule arithmetic vector instructions
and vector macro.instructions such as an inner product, product sum and
sumnation.
In the DO loops of a science and technology calculatinn program, the DO loop,
which contains conditional sentences (IF statements), appears comp~ratively
frequently but is not suitable for processing the above described four funda-
mental rule operation and macro instruction by vector instructions.
In the M-280H, a new vector instruction has been added aimed at f acilitating
vector processing of this DO loop with conditional sentences, in order to
improve the vector efficiency.16 Simultaneously a Fortran compiler was devel-
oped, which automatically converted DO loops with conditional sentances into
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1
- a vector instruction. By this developmer~t, we can expect automatic improvement
in vPctor efficiency and an improvement in the processing rate associated with
it.
III. Channel Logic System Design
The channel is under a centralized contro~ system whereby one 0/0 processor
(IOP) controls all eight cliannels, and IOP is highly densely packaLed using
LSI with 1500 gates to make a more compact architecture than the M-200H. One
IOP unit and eight char.nels are housed on one backboard. IOP is given an
image of an independent I/0 operation specialty processor with an internal
control storage, and has provisions f or future functional expansion.
Generally, channel logic sonsists of an I/0 interface operation control
channel, a data transfer control which controls the data transfer operations
relating to the main storage, and an I/0 instruction control which controls
- activations and interruptions. Figure 9 is a block chart which indicates the
architecture of an I/0 processor with 8 channels connected.
The channel unit contains byte multiplexer channels and block multiplexer
channels, and the maxim~un two units of the former and the eight units of the
~ latter can be connected per one unit of IOP for a versatile connection. The
block multiplexer channel, in particular, is equipped with a synchronous
transfer f unction which transfers data at high speed to make 3 M bytes/sec
data transfer possible. The conventional maximum 16 channel limit was in-
creased to 32 channels, and the standard block multiplexer channel data
transfer speed was upgraded from 1.5 M bytes/sec to 3 M bytes/sec, to achieve
an overall throughput increase of approximately fourfold and to make provi-
sions for larger files and a better system throughput.
Data transf er control and I/0 instruction control have many interchannel
common operations and are independent of the I/0 interface operations.
- Therefore, they are concentrated and compact as a common control. The data
transf er control contains data buffer register and address register groups for
data transfer. It sends addresses to the main storage in accordance with the
read and write requests from the channel to the main storage and reads or
writes data from or i.nto the main storage.
The I/0 instruction control has a special control storage. Complicated acti-
vation and interruption processing are controlled by the microprograms within
the control storage.
Also, the I/0 instruction control has a channel storage which stores unit con-
trol words (UCW)--information that controls the I/0 device. The unit control
words can be connected to the channel and must be provided with as many as the
number of simultaneously operable I/0 devices. In the past, 256 words (8 bit
address), equivalent to the number of addresses oF I/0 devices aff iliated with
the channel, were provided for the byte multiplexer channels in consideration
of the connection of the~coi?ununication lines, but 256 words were not necessarily
provided for the block multiplexer channels, considering that the number of
simultaneously operable I/0 was small. In the M-280H, 256 unit control words
17
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- ~
- ,
main ~ '
s torage ~
~ -
_ ~ T/0 processor I/0 device
torag data transfer chanr~~l 0
ontro control ~
~ unit data..bu�-�er channel ~
sery i e ~ , ~
- ~ u
~ ~
- a ress
( ~ h
~-1 .l
i
~ ~
o channel 4
� U R1 --r--.-._,
U in~tructio
- co~�rol
- ervic " ~ ~ontrol channel 5 ~
unit stora e
channel ~ ch
~Qnso].e S~~r~~e
service channel 7
- Pr~essox
~ Figure 9. I/0 Processor's Logic Structure. Consi,st~ng of mutually indepen-
dent and overlapping channels, data transfer control and I/0
instruction control.
are Frovided for all block multiplexer channels in consideration of the
capacity increase of the mass storage system (MSS). The I/0 instruction con-
trol centralizes and manages channel memories that store the unit control ~
words~ Unit control words, for instance, store details of channel command
words delivered from software during activation, and the status information
is renewed with the pr.ogress of the channel operation. After the completion
of the operation, part of the details will be reported to the software as
_ interrupt information. iable 2 compares specif ications of the new model with
the former model.
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- Table 2. Comparison of Channel Specificati~ns
_ Number Item M-2a0H M-�200H
1 IOP number/CPU 4 2
2 number of channel/IOP 8 8
3 number of channel/CPU 32 16
4 types of channels .
byte multiplexer channel maximum 2/IOP maximum 2/IOP
block multiplexer channel maximum 8/TOP ma~cimum 6/IOP
S number of UCW
byte muitiplexer channel 256 256
block multiplexer channel 256 64
6 transfer speed
byte multiplexer channel maximum 100 maximum 100
block multiplexer channel maximimm 1.5
(M bytes/sec) maximtma 3 (maximum 3)*
*higti-speed block multiplexer channel ~
Channel Speed Acceleration by Independent Parallel Operation of Three Basic
Units
- For the acceleration of the channel operation speed and compaction of archi-
tecture, lead control and parallel control are required just as in processors.
In a processor, as a basic concept, the instruction control unit, the arithme-
tic unit and the memory control unit, known as the three basic units, are
designated to perfoYm their respective functions independently in parallel for
the enhancement of the speed.
Similarly, in IOP, the channel unit, the I/0 instruction control unit and the
data transfer control unit can perform their respective functions independently
in parallel. While multiple chan~els of the channel unit are performing I/0
interface data transfer operations in parallel, I/0 instruction control can
activate the next I/0 instruction received and can execute interrupt handling
of I/0 operations already completed. Data transfer control can process data
transfer requests from multiple channels one after another. Specif ically,
eight channels, I/0 control and data transfer control can mutually overlap
and operate. Figure 10 indicates the state of overlap operations.
rigure 10 shows the state of overlap operations in terms of the relationship
of the respective operations to time, assuming that channels A and C execute
writing into the I/0 device (reading from the main storage) while channel B
executes reading (writing into the main storage) f rom the T/0 device after
three channels, channel A, channel B and channel C, are activated.
19
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Ir, this manner, sufficient transfer capacity has been given to the preseiit
hig}~-speed file magnetic disc unit with a capacity of 1260 M bytes/spindle
. ~and a data transfer speed of 3 M bytes/sec. As for the IOP throughput, the
IOP has provisions for connecting even higher transfer capacity channe?.s when
a high-speed file is dPVeloped and I/0 interf ace data transfer capability is
improved in the future.
- IV. Improvement of ~emi_conductor Element Tectinology
In conjunction with the above described logic system improvements, we decided
to develop a new high-speed high-density LSI 2nd to devise high-density
packaging with it.
Assuming ttiat the 1,3-1.6 performance improvement over the M-200H would be
achieved basically by improving the machine cycles, a circuit speed goal and
an integration goal for elements were determined. Asswning that an average
delay/row of gates inc]uding wiring delay and loading delay is called a system
delay, this system delay must be accelerated at least 1.3 times and more. If
this can be achieved only by improving the gate switching time, the machine
cycle improvement ratio "y" will be expressed as follows, where "a" is the
percentage of gate switching time delay to the system delay and "x" is the
switching time improvement level:
1
y=-
(1-a) + X
If a= 0.6 and y= 1.3, :c = 1.6, which means an improvement of about 1.6
times is necessary. The machine cyr.le was improved f rom both angles: for LSI
with maximum 550 gates, 60 percent acceleration was planned, and circuit delay
time 0.7 ns was improved to 0.45 ns. Concurrently, packaging density was en-
hanced by admixing LST with maximum 1500 gates to shorten the wiring delay,
which contributes to the system delay.
Adoption of Three-Dimensional Packaging System Similar to the M-200H
The packaging system of the M-280H uses three-dimensional packaging which com-
bines two types of substrates called package and backboard just as in the
M-200H, with increased package der.si~y/capacity.
1'igure 11 shows a large high-density substrate (package) of approximately
40 x 20 cro size for loading LSI and MSI. In the M-280H, as in the M-200H, LSI
is admixed with MSI and SSI in consideration of gate-pin ratio (ratio of
integrable number of gates to a given ninnber of pins). In one package, a
maximum of 20 LSI and 20 MSI and SSI can be packaged.
As a connector to connect this package to the outside components, a SO-mil
(1 mil = 25.4 um) pitch connector is used; 580 pins in all, combining front
and back rerminals, can be used. The substrate is composed of glass-epoxy and
lias a total of 10 conductive Iayers. The grid pitch is designated as 75 mils
to enlarge r~:a wiring capacity of each layer for the facilitation of high-
riensity packaging.
21
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, -
.
; , : .
_ . ~ ~ ^ ~r . ~ , . f ; i ( q ` . ~ . . . ~ .
_ � Y
r ~3
t} ~Y
. ivv.,i{'! ~rF'
;,~+1;1~+2;:
r
Figure 11. Package Loaded With LST
The backboard is the substrate on which a package is housed. On one sheet of
backboard, 24 packages can be housed as a standard. An entire backboard can
house 50 K-200 K gates, and has a total of 18 conductive layers. The wiring
capacity is upgraded compared to the backboard (14 layers) used in the M-200H.
Semiconductor Process Technology Improved From the Conventional 3 um to 2 um ~
The semiconductor technology used for the M-280H is in principle an im~rove-
ment in speed or integration over that of the M-200H. However, the basic
technology used in developing these semiconductors is markedly refonned from
that of the M-200H.
To improve the speed and integration of semiconductors, the switching speed
- must be upgraded and the power must be downgraded by re~orming the sem~con-�
- ductor process. The following semiconductor technologies were developed using
the technol.ogies reformed for this purpose--2 ~m photolithography technology,
dry-etching type microwiring technology, process technology such as three-layer
wiring technology, and technology such as LSI automatic design system, LSI
diagnostic system and test sysCem.
1. Logic LSI
The logic LSI was improved in two different ways: 60 percent acceleration of
the speed of the conventional 550 gate LSI without changing tre number of
gates; achievement of high-density packaging of logic with a better gate-pin
ratio by a newly developed maximum 1500 gate LSI.
~ 'L. Logic-in Memory Element
As a new logic-in memory element, an element which can house a 6144 bit memory
and a 770 gate logic circuit was developed. The integration of this element
is almostdouble that of the M-200H. Since this logic-in memory element is
called IA (index array), we will refer below to the one developed for the
M-200H as IA 1 LSI and the one developed at this time as IA 2 LSI.
22
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3. High-Speed Bipolar~Iemory Element
A new high-speed (access time 7 ns) and high-integration (4 K bit) bipolar
memory element was developed as a memory element to be used for buffer
storage and control. This memory has the same access time but is integrated
four times better than that used for the M-200H.
4. Main Storage Use 64 K Bit n MOS Memory Eletnent
As a memory element to be used for main storage, a 64 K bit memory element was
developed. TY?e capacity of the main storage was upgraded by designing to have
virtually the same access time as the 16 K bit memory used in the M-200H with
this memory packaged in the main storage. Tables 3 and 4 show specifications
- of logic and high-speed memory. ~
Table 3. Comparison of Logic LSI of the M-280H and the M-200H
Item M-280H M-200H
1500 gate LSI nuribe~ of ~ates maximum 1500
circuit speed 0.8
nu.^?~er of pins 108
average power (W) 3.5
_ S50 gate LSI number of gates maximum 550 maximum 550
- circuit speed 0.45 0.7
number of pinS 108 108
average power (W) 3.3 3.3
Table 4. Comparison of Logic-in Memory and High-9peed Bipolar Memory
Element Devel- Element Devel-
Item oped for M-280H oped forM-200H
logic-in memory number of inemory bits 6144 3072
element number of gates 770 470
memory access time (ns) 6.7 6.7
average power (W) 5.2 3.9
bipolar memory number of inemory bits 4096 1024
element memory access time (ns) 7 7
average power (W) 1 0.8
23
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150~ Gate Ma~terslice I~SI Packaged in the Same Package as the 550 Gate LSI
While a process with a 3 um miniaturization was used for the 550 gate LSI of
the M-200H, the miniaturization was further advanced for the high-speed 550
gate LSI of the M-280H by designating 2 um as the smallest size emitter.
Consequently, speed was accelerated from 0.7 ns/gate to 0.45 ns using vir-
tually the same circuit current. Besides the miniaturization of transistors,
the chip size was also reduced to two-thi.rds in terms of area ratio, f rom 5.7
mn square to 4.5 mm square, by reducing the aluminum wir3ng width and span.
This size reduction increased the nimaber of chips to be obtained from a waf er
of identical size.
On the other hand, a maximum 1500 gate masterslice model gate array LSI was
developed using the 2~m process for the achievement of high integration.l0
A photo of this chip is shown in Figure 12. This LSI uses a 1�gli-speed ECL
system just as in the 550 gate LST. Its power voltage is -4.5V and there are
88 external in.put/output pins, which are packaged on the same 108 pin flat
package.8 The basic circuit is composed of three input OR/tJOR. Wired/OR and
Correct/AND are manipulative and can be used as logic gate equivalents, con-
tributing to the higher density of the logic gates. One block is constructed
with these four basic circuits, and this block is lined Vertically and hori-
zontally in a matrix, with the wiring channels running between the matrix.
An automatic layout and automatic wiring program ha~ndles gate layout and inte-
grate wiring. If the wiring channel capacity is too small, it takes too much

= computer time for layout and wiring and it may take design time for manual
wiring in case the unwired space is left to the end. On the other hand, if
the wiring channel capacity is too large, the chip size will increase. The
optimum number of ~~hannels ~,�as determined based upon the results of the 550
gate LSI, and 1500 gates were successfully integrated on a 5.8 mm square size
chip. The reduction of the chip size leads to reduction of costs and allows
the use of the same LSI package as the 550 gate LSI.
The automatic layout and automatic wiring programs were remodeled for use
in the ?.500 gate LSi; they can complete layout and wiring virtually within the
same time as in the 500 gate LSI.
In order to packabe the 1500 gate LSI, which is three times more integrated
than the conventional LSI, while holding down the electric constunption to the
same level on the same package, the following innovations were made. Speci-
fically, the current of the b~.sic circuit was reduced to one-third that of
the 550 gate LSI, but the on-load activation current was set at two-thirds.
- Furthermore, compared to the conventional two-layer wiring on the chip, a
three-layer wiring technology was developed at this time; the power wiring
was transferred to the third layer while the logic wiring was installed on
the first and second Iayers. In addition to this arrangement, the wiring pitch
was 30 percent more densif~ed. The power current is the same as with a 550 gate
gate LSI, so that the latest LSI can be used ~ointly with the former LSI.
� In using LSI, a 1500 gate LSI is used for the logic ~aith a good gate-pin ratio,
and a 500 gate LSI is discriminately used for other irregular logic. This
proper use of LSI resulted in an inerease in packaging efficiency, improvement
in total system packaging density and shortening of machine cycles.
21+
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APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040500060044-2
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