JPRS ID: 9920 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY

• Document Type: CREST
• Collection: JPRS
• Document Number (FOIA) /ESDN (CREST): CIA-RDP82-00850R000400040032-8
• Release Decision: RIF
• Original Classification: U
• Document Page Count: 220
• Document Creation Date: November 1, 2016
• Sequence Number: 32
• Content Type: REPORTS

APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
JPRS L/9920
~ 19 August 1981
USSR Re ort
p
CYBERNETICS, COMPUTERS AND
- AUTQMATION TECNNOLOGY
_ (FOUO 19/81)
FBIS FOREIGN BROADCAST INFORMAT[ON SERVICE
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
NOTE
JPRS publications contain information primarily from foreign
a newspapers, periodicals and books, but also from news �:;ency
transmissions and broadcasts. Materials from foreign-language
sources are translated; those from English-language sources
are transcribed or reprinted, with the original phrasing and
. other characteristics retained.
Headlines, editorial reports, and material enclosed in brackets
are supplied by JPRS. Processing indicators such as [Text]
or [Excerpt) in the first line of each item, or following the
last line of a brief, indicate how the original information was
processed. Where no processing indicator is ~iven, the infor-
mation was summarized or extracted.
Unfamiliar names rendered phonetically or transliterated are
enclosed in parentheses. Words or names preceded by a ques-
tion mark and enclosed in parentheses were not clear in the
original but have been supplied as appropriate in context.
Other unattributed parenthetical notes with in the body of an ~
item originate with the source. Times within items are as
- given by source.
The contents of this publication in no way represent the poli-
c ies, views or attitudes of the U.S. Government.
- CUPYRIGHT LAWS AND REGULATIONS GOVERNING OWNERSHIP OF
MATERIALS REPRODUCED HEREIN REQUIRE THAT DISSEMINATION
- OF THIS PUBLICATION BE RESTRICTED FOR OFFICIAL USE Oi~ILY.
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-00850R000400444432-8
FOR OFFICIAL USE ONL1'
JPRS L/9920
19 August 1981
USSR REPORT
CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY
(FOUO 19/81)
CONTENTS
INTEGRATED CIRCUITS
Analog and Digital Int~,grated C~_rcuits 1
Terminology in Micruelectronics and Classification of Inteorated
Circuits 9
Emitter-Connected Transistor Logic Circuits 22
Providing Reliability of Integrated Circuits in Their
Production and in Assembly of Apparatuses 52
SM-3 AND SM-1~
Small Computer Haxdware for Creation of Developed Complexes......... 91~
Software of the Znternational Sm~11 Comp~iter System 1~.5
Design o~ Control Computer Complexes ~77
Problem-Oriented Complexes Based on the International Small
Computer System .................o............................... 203
- a- [III - USSR - 21.C S&T FOUO]
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
INTEGRATED CIRCUITS
UDC 621.396
ANALOG AND DIGITAL INTEGRATID CIRCUITS
Moscow ANALOGOVYYE I TSIF'fiDVYYE INTEGRAL'NYYE SKHF~I7C in Russian 1979 (signed. to
press 5 Apr 79) PP 2-5~ 331-335�
[Annotation, forecvord, concliision and table of contents from book "Analop and
nieital Inteprated Circuits", hy S er~ey Viktorovich Ya:cubovskiy, Nikolay Arser.'yevich
!~arl:anov, P,oris Petrnvich 1:udryashov, Lev Ionovich Dlissel'son, ?~tikhail P'ikif.orovich
'I'opeslikin and i.yuhov' Petrovna ('hebotareva, Tzdatel'stvo "Sovetskoye radio",
68,000 copies, 336 PaFes)
[Textj Annotation
Analog and digital integrated, circuits. S. V. Yakubovskiy, N. A. Baxkanov, B. P.
Kudryashov. Ddited by S. V. Yakubovskiy. Moscow. Sovetskoye Radio, i979, 336
pages, illustrations (Design of ra.dio-electronic apparatus with integrated circuits).
This is a survey of ~he basic series of analog and digital integrated circuits pro-
duced by thQ electronics industry. Cited axe; raethals . for their manufacture . param-
eters and chaxacteristics, and the operating principles of the basic components.
Trends axe shown in the development of logic circuits. Da.ta is given on micro-
processors and the special fea.tures of their application. Factors tha.t affect the
integrated circuit reliability axe covered; special fea,tures in using integrated
~ circuits in designing ra.d.io-electronic apparatus are described.; and recommendations
axe given on preventing integrat ed circuit failures for vaxious external effects
and technological operations.
This book should be useful to engineers working in the design of radio-electronic
- appaxatus and interested. in problems of sele~ting integrated circuit components and
in the special fea.tures of their application, as well as to students of respective
specialties.
The book contains 73 tables, 186 illustrations and 6~I~items in the bibliography.
Foreword
The basic directions for the development of the national econoir~y for 1976-1980~ de-
termined by the 25th party congress, stated that among the main w~.ys to increa,se
the efFiciency of prod.uction was the problen~ of "improving decisi.~~ely the qua,lii~y
1
F'OR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
POR OFFIC'IA1. USF: O1`JI.Y
of all types of manufactured products; expandir.g the assortment of goals; and in-
creasing the production of new types of products tha,t meet modern requirements"[1].
Its solution is impossible without furthex development of electronics that provides
not only for the creation of complex automated systems for the control of produc-
tion processes, but also for the development of new in principle products for mass
consumption. The expa,nsion of the area of application of electronic devices is
~ne of the special features of scientific technical progress at the modern stage.
Starting with the sixties, the development of electronics began with the.appearance
and rapid develo.pment of integrated circuits (IC). Integrated circuits make it
possible to create modern compl~.x electronic devices of acceptable sizes and weights,
and guaxantee their high reliability. The widest applicati.on of IC was in the de-
sign of digital devices.
- To a c~nstantly greater degree, the properties and chaxacteristics of IC determine
the technical characteristics of computers. Modern digital integrated circuits
axe complex products that �realize the functions of entire blocks and units of com-
puters. It is this that was respunsible for the appeaxance of an entirely new
direction in electronics the creation of microprocessors. While simple digital
IC were the basis for designing third generation computers, the assimilation in
production of microprocessors tha.t have IC with a higher functional complexity and
universality made it possible to organize the processing of digital signals in a
new way and, therefore~ to hope for a wide introduction of digital methods of proc-
essing data into various axeas of technolo (even those where previously the use
of electronics produced no essential effect~. Fourth generation computers are
being created on the basis of microprocessor sets (4~ to 5 individual housings).
Three stages may be conditionally singled out in the development of technology
and circuitry. The first stage was the development of basic integrated circuits
that perform simple logic functions (AND-NCJr, QR-NUr, AND-QR-N~ etc.~ with each
_ series, as a rule, containing triggers). At this stage, IC with 10 to 50 elements
were created.
The second state was the development of-more complicated functionally completed
units (counters, registers, decoders, half-addors etc.) with from 50 to 500 elements.
Because of such new circuits, the functional composition of the previously developed.
series was constantly expanded.
The third stage was the development of complex funetional devices with an integration
level of from 500 to 10,000 elements on one chip. This stage arrived at the begin-
ning of the lOth Five-Yeax Plan period.. The third stage circuit~ were used to
create pocket engineering calculators with wide ca?culation possibilities on the
basis of pr?li mtnary programing of the problem being solved.
In the process of developing digital integrated circuit electronics, along with
bipolar circuits~ there were developed and widely applied unipolax MOlS ~metal oxide
semiconductors]t of the p and n types, complementaxy MC6 [KM(aP~~ MQS with nitride
insulation (MN4P) and several others. It is the digital circuits with MLXS transis-
tors that made it possible to increase the number of elements in a chip to 10,000
and design such complex circuits as ma,in memories (OZU) with a large da,ta volume,
memories with random access and perman~nt memories.
,
2
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
~
The experience of using the entire variety of inethods to manufacture the IC ob-
tained during the pastl0 yeaxs confirmed the convenience of applying the high
technical characteristics of bipolax type TTL [Transistor Transistor logic] and F3~L
~Emitter'connec~ed logic] circuits, as well as MC6 type circuit elements. The
ingle System of Electronic Computers (YeS EVM) were created by the combined e~'forts
of CMEA member countries~ as well as was a broad family of sma,ll computers and
calculators (from the simplest schoo~ calculators with four axithmetic operations
to universal calculators with programing which ma,y be used in scientific rec~axch.
The past 10-yeax period also gave apparatus developers a new basis for an analog
- component~ a lax~e assortment of universal operational amplifiers, compaxators,
analog-digital and digital-analog converters~ voltage stabilizers, swizches, as
well as a set of low~ intermediate and high frequency amplifiers. The use of analog
IC ma,de it possible t.o simplify the a.djustmer.t of devices, increase their reliabil-
ity and accuracy and, in many cases~ eliminate necessaxy servicing.
In recent yeaxs, the creation of apparatus on the basis of IC without housings with
the common sealing-in of units became an independent direction. This method ma.de
it possible to obtain high wiring density and reduce the size and weight of special
appaxatus.
The domestic electronics industry manufactures a great number of mod.ern digital -
and analog microcircuits that become the component basis of modern radio-electronic
appasatus (REA~ for industrial purposes.
The pledge of high reliability of (REA) is the correct application of the micro-
circuits and the observance of their operating mod.es; violation of these conditions,
~ however, because of insufficient Imowledge of their technical properties, electrical
paxameters and opexating modes, results in fa~.lures most frequently.
The purpose of this book is to provide the basic technical chaxacteristics of di~i-
tal and analog microcircuits, describe methods for their manufacture and the func-
tional composition of the series~ as well as to draw attention to the spzcial
features of using IC in developing radio electronic apparatus and to rFCOmmend the
reliable manufac.ture of microclrcuits and the reli.able installa,tio~t o~ the appara-
tus.
The material cited in the book is based on the results of correlating the experi-
ence in developing and using integrated microcircuits.
The authors express their deep gratitude to professor B. F. Vysotskiy, doctor of
technical sciences, B. N. F~.yzulayev, candidate of physical-ma.thematical sciences~
Ye. I. Ga,l'perin, G. A. Pod.ol'skiy, V. I. Kotikov and V. L. Shilo, candidates of
technical sciences, who participa,ted actively in discussing the content and struc-
ture of the book~ and who made valuable comments on the material content and its
arrangement. The authors are also grateful to V. N. Bulanova and V. A. Ushibyshev
for theix help in the preparation and I?~akeup of the manuscript.
The authors requestthat remarks and suggestions on improving the book be directed
toi Moscow, 101000, Main Postoffice, box 693~ IZdatel'stvo "Sovetskoye Radio".
The Authors
3
FOR OFFiCIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
FOR OFFICIAL USE ONLY
Conclusion
Microelectronics is developing very rapidly. In 1977-1978, new technological
directions were assimilated, new microcircuit memories and microprocessors using
M~ transistors of the p and n types, bipolax iri J'ection circuits (I2L) and
transistor-transistor logic circuits using Schot~Eky diodes were developed.
A number of permanent memories using MalS transistors and a number of microproces-
sor sets were developed during the prepaxation and piiblication of this book.
Of interest is a new memory the IC 556~~� This is a 1024 bit permanent memory
with the possibility of single-stage programing by the user. Ma,de with TTL com-
ponents with Schottky diodes it makes it possible to abtain an addxess access '
time of 90 nanoseconds using 0.5 milliwatt~bit.
IC K535RYe1 and K505 RYe3 4096 bit memories wer~ developesl using p type MOS
transistors. Thsse memories can be progra.med by~ order caxds. The Ic x535RY~i
has a 1.7 microsecond access time and uses 0.12 milliwatts~bit. The IC K505RXe3
has an access time of 1.5 I??i.croseconds and uses 0.25 milliwatts~bit. The cir-
cuit input interfaces with a TTL circuit through a i33~i~ circuit, while the out-
put interfaces directly with a TTL circuit.
The IC K568RYei, with full address decoding output amplifiers and an"IC access"
control circuit was created using ML~6 transistors. The IC program is also imple-
mented by order caxds. The circuit has a large capacity (as compared to pr~~iuusiy
ma,ss-produced permanent memory units). It has 16,384 bits (20~8x8), uses . 0.021
_ milliwatts~bit~ its da,ta readout time is 0.8 microseconds and the circuit output
interfaces with TTL circuits.
Of great interest axe IC memories K573~11-K5731~R14 with data erasing by means of
ultraviolet rays tha,t provides for long dat~a starage when the power source is dis-
connected. The microcircuit has a data capa,city of 4-096 bits with vaxious memory
organizationss two K573~11 and K573~12 circuits have a memory organizatlon of
512x~ bits and differ in functional purposes of leadouts, x573~i3 and x573~i4
have a memory organiza,tion of i024x4 and differ in functional purposes. It has
10 reprcg raming cycles and the da.ta storing time is 10,000 hours.
Microprocessor sets series K581, K536~ K584, K582 and K588 were also developed and
introduced in recent yeaxs.
The x536 series of the ;~iicroprocessor set is ma,de with p type M06 and consists of
13 ~.crocircuits that provide the following functionsi arithmetic-logic devices
(K5361k1 and K5362x9); microprogram devices (K5361K2 and K536~{8); input-output
control devices (K5361K3~ K536IIC4 and x536ztt5)~ voltage to code converter (K5361K6);
_ channel selector control device (x536zx7). Moreover, the sets include two power
amplifier circuits (K536UI1 and K536UI2) and a cyclo pulse oscillator circuit (K536GP1).
The series K581 microprocessor set is made of n type MC6 and consists of five micro-
circuits implementing the following functionsi arithmetic-logic devices (K581IK1,
K~81IK1A)*;
ircu ~i
w3~'i"in~c
ex A has a cycle time 7 600 nanoseconds without the
index ~ 0 nanoseconds.
4
FOR OFFIC[AI. USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
operation control (K,581IK2, K581Il{2A) ; microprogram mem~xy units (K581I~IJ1,
K581RU1A); ir..~truction storage units (K~81RU2, K581RU2A), as well as a program
memory unit 'o implement operations of expanded arithmetic and operations with a
"floating" ciecima.l point (K~81RU3 and K581RU3A).
- Series K582 and K584- microcircuits axe used to bui~d four-stage parallel micro-
processors frith injection logic (IZL). The 588IX1 microprocessor program control
device xas cleveloped with complementaxy MOS.
, Recently, new analog microcircuits were also developed. They includes the
K157UD1A,B nedium power operational amplifiers with a maximum output current of up
to j00 milliamperes; the quick-acting K574UD1 operational amplifier with a speed of
voltage rise of up to 50 volts~microsecond; and the K551UiD1A,B precision opera-
tional amplifiers.
The number of compaxators increased by the fo~.lok*ing microcirouits: 5975Ai
operating on ESL logic and 597SAZ compa,tible with TTL logic. The type 14~OUD13
preamplifier was developed with an input impedance of not less than 50 megohms.
The microcircuit series intended. for TV ar.d radio reception was supplemented by
the K174UN8 pow?x amplifier with a two-watt output power, anrl the K17~UN9 power
~ amplifier with a power output of up to seven watts. The following TV devices were
developed and assimilated in series production: the K174UP1 brightness signal
amplifier; the K17~UR3 amplifier-limiter; the K174KhA3 noise suppressor in
sound data channels; the K174KhA1 detector of the red-blue color signal dis-
criminator.
The set of semiconductor a.nalog-digital conver-ters [ATsP~ expanded further. Thus,
the following devices have been developed~ a ten-stage ATsP with M06 transistors
type 572PA1 with a multiplier, compa,tible with TTL circuits, and a 12-stage ATsP
with MOS transistors type 594PA1 compa,tible with TTL circuits. A switching series
was supplemented by 16-channel M06 switches with types 590KN1 and 591KN1 decoders,
~ compatible with TTL logic and~ finally, power sources for integrated circuits are
being developed further. Integrated, voltage stabilizers~ types 1~2YeN3 and
142YeN4, were developed with an external voltage divider and an output current of
up to one ampere.
The development rates of domestic microelectronics axe such that in several yeaxs,
the integrated circuits considered in this book, logic, as well as analog, will
change considerably and a part of the reference material will lose its value.
However, the basic conclusions of the authors tliat the high potential reliability
of integrated circuits, built-in in their development and production, must be pre-
served in the development, production and operation of radio-electronic appaxatus,
and wi'l1 remain unchar.ged. If the authors are able to impress this conception on
the reader, they will consider their problem solved.
5
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
F'OR OFFI('fAl, l1SH: ONLY
Table of Contents ~
Foreword
Chapter 1 Page
Terminology in mi.croelectronics and classification of
integrated circuits 6
i.i. Introduction (
1.2. Terminology in microelectronics 7
1.2.1 Integrated circuits, elements of cornponents (7).
1.2.2 F~lements of de3ign (7). 1.2.3. Simple and complex IC (9).
1.2.4. Microassemblies and microunits (10~.
1.~. IC classification 11
1. . System for conventional designations of IC 12
Chapt er 2
Integrated circuit manufacturing methods 1$
2.1. Film and hybrid technology i$
2.1.1. Materials for hybrid IC (19)� 2.1.2. Manufacturing of
hybrid IC elements (22). 2.1.3. iiiring of electrical
connections in hybrid IC (24).
2.2. aemiconductor techn~logy 24
2.2.1. Ma.terials for elements of semiconductor IC and their
manufacture (36). 2.2.2. Manufacture of integrated
circuits (29). 2.2.3. Division of wafers into chips,
wiring of IC (35). 2.2.4. Sealing IC chips (36). �
2.2.5. Manufacture of IC housings (37)�
- 2�3. Special features of high degree of integration of IC technology 40
Chapter 3
Digital integrated circuits y.(
3.1. Purpose and application l~(
3.2. Logic functions obtained by digital I~ 46
3�3� Classification of digital IC and their basic electr:ical
- paxameters 51
3.4. ~ansistor-transistor l~gic circuits 56
3.4.1. Basic electrical paxameters of type TTL IC (70).
3�~�2. ~nctional composition of TTL series (72). 3�~�3�
_ Some f~atures of using TTL type IC 78)
3�5. Emitter-connected transistor logic FSTL] 83
3~5�i. Ftznctional composition of the ESTY, series (80).
_ 3~5�2� Ba.sic electrical parameters and typical ch~'acteristics
of type FySTL IC (99)� 3~5�3� Some features of applying type
- ESTL ~C (,103~.
6
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR ()FFI('IA1. U~E ONLY
3.6. Digital IC made of M~6 ip9
3.6.1. Principle of IC operation with p-channel ML~
transistors (iii). 3.6.2. Static circl.its with p-channel
M06 transistors (113). 3.6.3.' Quasistatic and dynamic
circuits (116). 3.6.4. Principle of IC operation with
complementary MD6 transistors (119). 3~6�5� Basic IC
series with M06 transistors (123).
3�7. Integrated circuits of inemory units 130
3~7�1. Memory elements with bipolax transistors (131).
3~7.,2. Memory elements with MC5 transistors (134).
~ 3�7�3� Memory elements with complementary M+(~ transistors (135)�
3�7�~� Memory elements xith MNDP transistors (136).
3�7.5� Memory elements with "silicon on sapphire (138).
3.7.6. Memory elements using new ma,terials (138~
3�7�7� Basic IC meiaory units and their functional
composition (141).
3.8. Perspectives of digital IC development 142
3�8.1. Integrated injection logic (143~.
3.8.2. M06 circuits with n-channels (14~4).
3�9. Microcalculators 146
3.10 Microprocessors i49
3.10.1. Microprocessor chaxacteristics (150)
3.10.2. Medium speed microprocessor set (153)�
_ 3�10.3. High speed microprocessor set (159)�
Ghaptpr 4
Analog integrated circuits 200
~.i. Purpose and application 200
4.2. Operational ampllfiers 200
4~.2.1. Operational amplifier with a two-stage circuit (207).
4.2.2. Amplifiers with field transistors at the input (214).
_ 4.2.3. Amplifiers with super-beta transistors (215).
4.2.4. High current operational amplifier of the 153UD5
- type (219). ~.2.5� Quick-acting operational
amplifiers (221). 4.2.6. Micropower operational
amplifiers {223).
4.3. Tntegrated compaxators 227
4.4. Integrated. analog multipliers . 231
4.5. Analog IC for radio receivers 241
4.5.1. Differential amplifiers (243). 4.5~,2. Low frequency
amplifiers (UNCh) (244). 4.5.3. Specialized IC (24-8).
4.5.4. IC for designing selective devices (255)�
4.6. IC for mutual conversion of digital and analog data 257
4~.7. Analog switccies 273
4.8. Integrated. voltage stabilizers 278
7
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
FOR OFFI('IAI. U5E ONLY
Chapter 5 Page
Providing IC reliability when they are manufactured and
installed in apparatus 293
~.1. Design-technological principles for high IC reliability 293
5�2. ~Perational monitoring z95
5�3. Rejection tests 295
5.4. Effect of external factors in apparatus manufacture 305
5~5� Forming and trimming leads 307
5.6. Tinning and soldering 3i3
5.7. Mounting IC on circuit boaxds 320
5.8. Protecting IC from electrical effects 323
5�9� Dismantling ~ 3~9
Conclusion 331
COPYRIGHTs Izdatel'stvo "Sovetskoye radio", i979
' 2291
CS~: 1863/209
8
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000400440032-8
N'OR OF'I~1('IA1. US4~: ONI.Y
i1DC 621.396
'CI.?P;',IPi~~Lf1GY IP' 'fICROP.T,F:CTrf?NICS APIn Ci,AGSI.FT.CATI~N OF INTFGR~TED CIRCUITS
Moscow ANALOGOVYYE I TSIFROVYYE INT~7GRAL'NYYE SKHENIY in Russian 1979 (signed to
press 5 Apr 79) pp 6-17
[~llapter 1 from hool: "~nalod and Pir,ital Integrated Circuits", hy Sergey Viktorovich
Yakuhovs~:iv, `Iikolay ~rsen'yevich ~iarlcanov, Aoris Petrovich 1~'udrvasnov, Lev Ionovich
':issel'son, "'i};hai]."?ikiforovich Topeshkin and Lyuhav' Petrovna Chebotareva,
I::datel'stvo "Sovetskoye radio", 68,~Q0 copies, 336 pa~es]
[Text] Chapter i
_ Terminology in microelectronics and classification of integrated ^ircuits ~
i.l. Introduction
Microelectxonics is a developing field of electronics Basically, it is the creation
of an integrated element base used to develop appaxatus. The term integrated elec-
tronics combines the "element~" as well as the "appaxatus" microelectronics. .Many
concepts in the field have still not established themselves fixmly; therefore,
questions of terminology in Russian, as well as fn many forei~ languages axe
fairly complex. In 1969~ the International Electrotechnical Commission (MII{~
issued the second supplement to publication 147-0 (1966) [2] in which, for the
first time, terminology was presented in the field of integrated circuits. The
supplement included the definition of sevaral of the most common terms such as
microelectronics, microcircuit, integrated microcircuit etc.
In our country~ the first attempts to regulaxize terms and definitions were attempted
in i967 when a norm "Integrated microcircuits. Terminology" was issued. The lack
of status of this document made it impossible to recommend it as compulsory. In
connection with the considerable expansion of the use of integrated circu;ts~ the
necessity arose of a government standard on terminological questions in the field
of microelectronics xhich was developed on the basis of the above-mentioned. norm
and the MII{ publication and, in 197i~ it was approved by the USSR Gosstandart [3~.
G05T 17021-71 included 16 terms and along with general terms such as integrated
- microcircuit, semiconductorintergrated microcircuit, there were also given single-
valued definitions for parts of integrated circuits (for example, substrate, hous-
ing) .
9
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPR~VED F~R RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAI. USE ONLY
T~~ms whose definitions were given in the above-mentioned GC6T were widely used
in technical documents. However, the development of microelectronic means, the
_ increase in the wiring density and in the number of elements on one chip had al-
ready ~.ed~ in ~1973, to the necessity of reworking this G~T for the purpose of
correcting it and introd.ucin new terms. In 1975~ this work wae completed by the
approval of G~6T 17021-75
Below axe given the terms as per GC6T 17021-75, their definitions and the synony.�ns
of these terms which axe widely used in production and in technical literature.
1.2.1. Integrated Microcircuits, IIements, Components
An integrated circuit (IC) is a microelectronic article that fulfills a certain
- function of converting and processin signals and has a high packing density of
the electrically connected elements ~or elements and. cumponents) and chips. This
. article is considered a single whole ~om the standpoint of the requirements of
tests, acceptance~ delivery and operation.
In abbreviated form, integrated microcircuits axe called IMS. The synonym of an
integrated microcircuit is the term integrated circuit or, still simpler, micro-
circuit. Of all the indicated terms, integrated circuit (IC) is the most fre-
quently us~d. It has two subordinate terms, whose description is given by the
above-mentioned G~6T. These are concepts of an element of an integrated circuit
(or simply element) and component of an integrated circuit (or simply camponent).
- An element of an integrated circuit means the part of the IC that rea,lizes the
function of some simple electroradio element (for example, transistor, diod.e,
resistor, capa.citor). This par~t is insepaxable from the IC chip (or its substrate).
The element cannot be separated from the IC as an independent article; therefore,
it cannot be tested, packed and operated. bcamples of integrated elemen~ts axe:
a film resistor in a hybrid IC and an integrated transistor in an IC semiconductor.
An integrated circuit component also means a part of an IC that realizes the
function of some electroradio element. However, before assembly this part was an
independent article in special packing (complementing article). In principle, a
component ma,y be sepaxated from a manufactured IC. F~camples of integrated compo-
nents are~ a tra.nsistor without a housing or a ceramic capacitor in a hybrid IC.
- 1.2.2. Design E`lements
- In developing technical documentation for IC or in prepaxing descriptions of IC
designs~ writers of the indicated documents must 1reg.uently use such terms as
housing, substrate, board, wafer, chip, as well as some special terms that deter-
mine special features of the internal structure of the IC.
The IC housing is the part of the IC structure intended to protect it from exter-
nal effects and to connect it to external electrical circuits by lead.outs (IC are
packed in the housing). The types and sizes of the housings are also subject to
government standardiza.tion (see G06T 17~67-79
10
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040400040032-8
FOR OFFI('lA[. USE ONLY
The IC substrate is an intermediate product intended for elements of hybrid and
- film IC~ interelement and (or) intercomponent connections, as well as contact
pads to be applied to it.
The IC board is part of the substrate (or the entire substrate) of the hybrid (or
- frequently film) integrated circuit~ to whose surface the film elements of the IC,
the interelement and intercomponent connections and contact pads axe applied.
The semiconductor wafer is an intermediate product of semiconductor ma.terial
- (usua'ly it is a r~und thin disk) used to make IC semiconduct~rs. .It should be
- noted that in IC production this ter~: is used not only for the initial inter-
mediate product~ but also for a plate with elements of semiconductor microcircuits
for:~ed on it (therefore, this term is used during the entire technological process
from its beginning to the cutting of the group axticle into individua.l chips~.
IC chips are the paxts of the wa~er obtained. after it is cut (usually they form a
network in the shape of equa,l rectangles), in the volume and on the surface of
which axe formed elements of the semiconductor microcircuit, interelement connec-
- i ions and contact pads.
~ contact pad, present in axiy IC, no ma.tter what its technological or functional
- features axe, is a metallized pad on the plate or on :he chip intended to connect
contact leadouts and integrated circuits, as well as to monitor its electrical
paxameters and modes.
An integrated circuit without a housing is a term wh3.ch recently acquired great
importance because such circuits are used widely in microassemblies and microcir-
cuits. While in the usual IC the housing serves to protect against external ef-
fects, the IC without a housing has no such ~rotection of its own (at least, from
mechanical effects). Fbr connection to external electrical circuits, an IC with-
out a housing must have its own leadouts and its full protec-tion is provided by
the housing of the device in which this IC is installeri.
The leadout of an IC without a housing is a conductor connected electrically to
the contact pad of the chip and mechanically to its surface. The main purpose
of the leadout is to provide an electrical contact to one of the circuits of the
IC without a housing when it is connected to external electrical circuits. Lea,d-
outs of the IC without a housing carry a considerable part of the heat. Leadouts
of IC without a housing ma,y be haxd (round, columnax or bea.m-shaped.) . Haxd
lea.douts may be used for mechanical fastening of an IC without a housing, without
pasting it.
1.2.3� Simple and Complex IC
Until recently there was no decisive concept of the complexity of integrated cir-
cuits in literature, either abroad or domestically. When defining the term
"laxge-scale integrated circuits" (BIS), an attempt was made to use, as the basis,
~he quantitative factor as well as tha factor of the functional complexity of the
microcircuit. In the first case, suggestions were made to define the BIS as a
circuit containing 50, 100 or 10,000 circuit elements. For example, to define
11
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
~ N�~u ~rN~i~~ini. ~isH; ONLY
a"laxge digital circuit" an attempt was made to use an elementary digital
switch as a counting unit. In this case, it was considered that a"laxge" cir-
cuit must have no less than 100 digital switches. Concepts of "small," "medium"
and "laxge" scale integration began to penetrate domestic leterature from abroad.
- However, deprived of numerical definitions, these concepts in each individual
case, expressed only the ~ubjective concepts of the author. Tn the seventies,
following this tra,d.ition, in scientific literature~ the terms "very laxge in-
tegrated circuit," "superlaxge integrated circuit" and even "colossal integrated
circuit" appeax.
Supporters of defining BIS,depending upon its functional complexity, proposed
dividing the circuits into four integration levels: elemen+ary~ circuit, subsys-
tem level and finally, system level.
The study of all the proposals led. to the idea that a quantitative factor must
be used as a basis for a definition that defines precisely the quantity of the
elements in the microcircuit chip or housing. G06T 17021-75 defined the term,
"degree of integration of the integrated. circuit," as an indicator of the degree
of complexity of the IC, chaxacterized. by the number of elements and components.
The degree of integration is defined here by formula K=1gN, where K is the coef-
ficient defining the degree of automa,tion, rounded. to the neaxest laxgest integer,
while N is the number of elements and components in the IC. In accordance with
this formula, an integrated circuit of the first degree of integration is called
~,n IC coiitaining up to 10 elements and components inclusive. An IC of the second
degree af integration contains from Si to 100 elements and components inclusive
correspondingly, IC with 101 to 1000 elements and components inclusive should be
called IC of the third degree of integration. Similaxly IC with elements from
1001 to 10,000 or from 10,001 to 100,000 axe IC of the fouxth and fifth degrees
of integration.
When desi in electronic a
gn g pparatus and selecting the elements, the so-called.
_ packirig density of the elements in the integrated circuit is of great importance.
By packing density is meant the ratio ~f the number of elements and components of
the integrated circuit to its volume (without taking into account the volume of
the leadouts).
1.2.4~. Microassemblies and Microunits
- G~.ST 1?021-75~ besides using terms with a direct relation to integrated circuits
gives, in the form of reference material, a whole series of terms related to the
field of application of IC. Such terms belong to the concept of microelectronics.
Here it is defined as the field of electronics tha,t spans the problems of reseaxch,
design, ma,nufacturing and the use of microelectronic products with a microelectron-
ic product meaning an electronic device with a high degree of integration.
The term "microassembly" has several synonyms used. in technical literature and
documentation, but the definition of this term was not always given clearly.
Thus, for example, before i975 "~croassembly" meant a microc~rcuit consisting
of various elements and integrated. circuits. The synonymsfor n~icroassembly ma.y
be the terms used. in literature such as~ hybrid, integrated functional unit
GIFU , large integrated functional unit (BIFV), a laxge hybrid integrated. circuit
BGIS~ and a hybrid large integrated circuit (GBIS~.
12
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
~
G~6T 17 02L-75 defined the microassembly term as a m3.croelectronic arti~le that
fulfills a certain function and consists of elements, components and integrated
circuits (with and without housings), as well as other electroradio elements, in
various combinations, developed and manufactured by developers of concrete radio-
electronic appaxatus for improving its miriiaturization indicators. The G1~T does
not define a microassembly as an article with or without a housing, i.e., a micro-
assembly may or ma,y not have its own housing. Thus,a miczoassembly is not classi-
fied by the G~6T by its complexity.
- A microunit is a microelectronic article which~ be,ides micro-
assemblies, ma.y contain integrated circuits and components. Finally, the
miniaturization level term of a microelectronic article chaxacterizes the quanti-
tative measure of the effect of using the totality of technical solutions, directed
to the full utiliza,tion of the advantages obtained.from the reduction in volume,
weight and power used by the apparatus.
Indicators of the REA [Ra.dio-electronic appaxatus~ miniaturization level arei
HEA meeting the modern technical standaxd of microelectronic articles; other
articles used in REA meeting the modern level of miniaturiza.tion; efficiency of
' comprehensive miniatuxization of appaxatus; technical compatibility of �'noninte-
grated" articles of electronic equipment, and electric equipment with integrated
circuits.
- 1.3� IC Classification
Depending upon the manufacturing technology, integrated circuits ma,y be semi�-
conductor, film or hybrid. GCBT i7 021-75 gives the following definitions for
these three vasieties of IC.
A semiconductor integrated circuit is called an IC al1 of whose elements and inter-
element connections axe made.in the volume and on the surface af the semiconductor.
The semiconductor integrated circuit ma.y also be called a semiconductor micro-
circuit.
Sometimes the semiconductor integrated circuit is called a"solid" (or solid-body)
circuit. This term found its way into domestic literature due to unqualified
translations from the ~glish*~. G~6T 17021-75 defines this term as inadmissible.
A film integrated circuit (or film circuit) whose elements and interelement con-
~ections are made in the form of films is called an IC. This film and thick film
IC are vaxiations of technical designs.
The difference between thin film and thick film IC may be quantitative and quali-
tative. Integrated. circuits with a film thickness of up to 1 micron belong to
- thin film IC conditional~y while integrated circuits with film thicImess greater
than i micrometer belong to thick film IC. Qualitative differences ase determined
*Solid state electronics (IIiglish) semiconductor electronics.
13
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
FOR OFFICIAL USE ONLY
by the manufacturing technology of the filma. Elements of thin film IC axe
applied to the substrate, as a rule, by thermal-vacuum precipitation and cathode
spraying, while elements of thick film IC are made primaxily by silk screening
with subsequent burning in.
Finally, hybrid integrated circuits (equivalent term hybrid microcircuits) axe
IC containing, besides elements, simple and complax components (for exa,m le, chips
of semiconductor IC). A particulax case of hybrid IC is a multichip IC ~a total-
ity of several IC without housings on one substrate).
Depending upon their functional purpose, integrated circuits are divided into two
basic categories analog and digital.
_ Analog integrated. circuits (analog microcircuits) axe IC intended to convert and
process signals that change in accordance with the continuous funetion law. A
particular case of analog IC is an IC with a lineax characteristic (lineax micro-
circuit~.
Digital integrated circuits(digital microcir~uits) are IC used. to convert and
- process signals expressed in a binaxy or other digital code. A variation of the
digital microcircuit definition is the term logic microcircuit (operations with a
binaxy code axe described by logic algebra).
As a rule, analog and digital IC axe developed and manufactured by manufacturing
enterprises in the form of a series. Each series is characterized by the degree
of completeness. A series containa several IC of distinctive types which, in their
~ turn~ may be divided into rateKi types.
Accor~iing to G~sT i7o21-?5~ a series of integrated circuits contains a totality of
IC which can implement vaxious funetions, but have a single design-technological
form and axe intended. to be used in combination. As a rule, the composition of
a promising series is being expanded. with time.
IC that have concrete functional purposes and their conditional designations are
called rated types of integrated circuits. By a type of integrated circuit is
meant a totality of rated types of IC tha.t have concrete funetional purposes and
their conditional designations.
1.4. System of Conditional IC Designations
The entire diversity of manufactured integrated circuits according to the adopted
conditional designation system is divided into three groups~ semiconductor,
hybrid and others. Film IC~ which axe preaently manufacturad in a limited quanti-
ty, as well as vacuum IC and ceramic IC, axe frequently referred to as the last
group. The groups indicated above are assigned the following digits~ 1, ,5, 7--
semiconductor IC (designation 7 is assigned to semiconductor IC without housings};
2, 4, 6, 8-- hybrid IC; 3-- other IC.
According to the nature of the functions implemented in radioelectronic appaxatus,
IC axe subdivided into st~bgroups (for exa,mple~ oscillators, mod.ulators, triggers,
14
FOR OFF[C[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000400440032-8
1I1l~~llft~l'S~ nnd ty~~d:3 (t'ur dxample, frequency, phase, duration, voltage converters~.
The classification of integrated circuits in accordance with their functional pur-
poise is shown in Table 1.1. '
According to the adopted syatam of designationa, an IC must consi~t ~f 4 c~lc~mutits.
The first element a digit corresponding to the design-technological group.
The second element two-three digits assigned to a given IG series as the ordinal
~ number of the development. Thus~ in the first two elements axe three-four digits
that determine the total number of the IC ser.ies.
- The third element two letters, corresponding to the subgroup and the IC type (see
Table 1.1~.
The fourth element the ordinal number of the IC development in a given series in
which there ma.y be several equal in the functional criterion of the IC. It may con-
sist of one digit, as well as several digits. G06T 18682-73 does not limit this
number.
Below is shown an example of a conditional designation of an integrated semiconductor
- operational amplifier with an ordinal of the series development 4-0, the ordinal
- number of the development of the given circuit in the series according to the func-
tional criterion 11.
~.:~H(1) ~2~
~ yQ ~3)
!t-~.;~a~had~,~ yaMep
' /~;r~:~;.5~;n,.~�~ ,y:/A;DOCXCMb/ /70
I I ~1~/tin�'GV~1~9GN0.'1~ q,0!l3HdKy
I ~ ,s~:~Hr,~~i cepuu
~ Bud (no ~i,;~:.a;,�,~~~�r.-r��.~ ~~y~ ~~~.~~i4~veHUro)
i
i -
I r6~ !/aJzvynna _
I ~
~~f yiu Nonep pd3,~~6~inku l~(IHHO~ cep,r~
I.�__-- ,
~7~ .7.'�.. ':~;�'+',^,~lYNO-/lIEXNO/!U~!!4'BCKUM~ u~n~~~.sew,;:t;
l
.
l. Series 5. Subgroup
2. UD 6. C~dinal number of given series
3. Qrdinal number of a microcircuit 7, Group (according to the design-
development according to funetional teehological makeup~.
criterion in the given series
~ 4~. Type (according to functional purpose~
1~
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFIC'IAI. USE ONLY

i
Table 1.1
Functional classification of IC
Subgroup Lette~
- T~ Designation
Name Letter Name Letter of the rated
Designa- Designation ~
tion
4scillators G Haxmonic signals S GS
Rectangular signals G GG
(including self-excited
multivibrators~ blocking
oscillators etc.)
I,inearly changing signals L GL
Special shape signals F GF
Noise M GM
,Others P GP
Detectors D Amplitude A ~
Pulse I DI
Frequency s ~
~ Phase F DF
Qthers
Switches and K Current T KT
keys Voltage N ~
(lthers P KP
Logic elements L II.ement AND-NDI' A LA
Element aR-NOT Ye LYe
IIerent AND I LI
IIement DR L LL
IIement NCIr N ~
IIement AND-OR S LS
Element AND-NOT~OR-NUr B LB
IIement AND-OR-N+Cl~ R LR
El.ement AND-OR-NCI!'~AND-()R K LK
Element OR-NC1r~QR M LM
~panders D LD
' Others P LP
Multifunctional Kh Analog A ~
circuits Digital L KhL
Combined K KhK
Other P ~
Modulators M Amplitude A ~
Frequency S MS
16
FOR OFFICIAL U'iE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONI.Y
Table 1.1 continued.
, F~uzctional Classification of IC
Sub~roup T.ype Lett~r
Designa-
tion of
Name Letter Name Letter the rated
Designa- Designation ~
tion
Modulators Fi Amplitude A ~
F~equency S MS
Pha.s e F MF
Pulse I MI
Others P M~'
Sets of N Diod.es D ND
elements ~ansistors T ND
Resistors R NR
Capacitors Ye NYe
Combined K ~
Others P Np
Converters P F~equer.cy S PS
~ Phase F PF
Duration D ~
Voltage N ~
Power M PM
Level U ~
Code-analog A PA
Analog-code B PA
Code-code R PR
Others P PP
Circuits for Ye Rectifiers V YeV
secondary power Converters M YeM
_ sources Voltage stabilizers N Y~N
Current stabilizers T YeT
Others P YeP
Delay circuits B Passive M BM
Active R BR
Others P BP
Selecting and S Amplitude (signal level) A SA
compaxing cir- Time V sv
cuits FY~eq,uency S 5S
Phase F SF
4thers P sP
17
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
FOR OFFICIAL U~E ONLY
Table i.i continued
Flinctional Classification of IC
3ubgroup Type Lettex '
Design~,-
Name Letter Name Letter tion of
~ DESigna- Designation the rated
t i cn t.ype
Triggers T Type JK V TV
Type RS R TR
TyPe D M TM
Type T T TT
Dynamic D TD
Schmidt L TL
Combined (types DT~RST etc) K TK
llthers P TP
- Amp~ifiers U High frequency~ V UV
Intermed.iate frequency~ R UR
Low frequency-~ N UN
pulse signals~ I UI
Repeaters Ye UYe
Rea.d-out and retrieval L UL
Indication M UM
DG`~ T UT
~perational and
differential* D UD
athers P UP
*Voltage and power
amplifiers (including
low-noise
Filters F Upper frequencies V FV
Lower frequencies N FN
Band Ye FYe
Rejector R FR
~Qthers P F'P
Shapers A Rectangulax pulses G AG
(biased. multivibrators,
blocking oscillators, etc.
Special shape pulses F AF
Address currents (shapers A A1~,
of volta~es or currents)
Dischaxge currents R AR
(sha,pers of voltages
or currents)
Others P AP
18
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
FOR OFFIClAL USE ONI.Y
Table i.i continued
F~uictional Classification of IC
Subgroup ~r.ype Letter
= Desig-
Name ~etter Name Letter nation of
the rated
Designa- Desi~nation t,ype
tion
Memoxy matrices~ R Storage
elements Main memories (OZU) M RM
Permanent memories (PZU) V RV
OZU with control circuits U RU
PZU with control circuits Ye RYe
PZU with control circuits T RT
and one-time programfng
PZU with control circuita R RR
and multiple programing
Analog memory (AZ[1) with A RA
control circuits
Others p
_ ~l.ements of I Registers R ~
axithmetic and Adders M IM
discrete devices Ha,lf-adders L IL
Counters Ye IYe
Coders y I~
Combined K ~
Others P IP
A lett~r is sometimes added to the end of the conditiona.l designation that de-
finestF~e technological s~read of the electrical paxameters of the given rated type.
The concrete value of the electrical paxameters and the difference between the
rated types is given in the tachnical documentation (for example, IC133LA1A differs
f.rom IC133~11B) .
19
_ FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
FOR OFFICIAL USE ONLY
In some series (this is also stipulated in the technical documentation), the let-
ter at the end of the conditional designation of the IC defines the type of the
housing used for the given rated type. For example, the letter P designates a
plastic housing, while the letter M-- a ceramic housing. For microcircuits
utilized in widely used devices, the letter K is at the beginning of the conditional
designation. The designation then appears as K1~OUD11. If, after the letter K,
there is also shown the letter M ahea.d of the series number, this indicates that
all the given series is manufactured with a ceramic housing (for examgle, xNti55LAi).
- A series made for export(with a pitcn of housing leadouts of 2.54 mm) is especially .
J stipulated with the letter E before the letter K in the conditional designation,
(for example, IIC561LS2), while the series in the vaxiation without housing, without
leadouts being connected to the chip of the microcircuit is stipulated by the
letter B ahead of the series designation (for example, KB524RPiA-4).
For IC without housings, in the shortened designation, a digit is introduced after
a hyphen to characterize a corresponding design modification (for example,
703LB1-2)~ with fleJVible leadouts-i*; with ribbon leadouts, including those made
with polyamide film-2; with hard leadouts-3; on a common plate (undivided)-4;
sepaxated without loss of orientation (for example, pasted on the film~-5; with
contact pa.ds without leadouts (chip)-6.
It should be noted that before the introduction of GC6T 18682-73 [6] (i.e.~ before
- 1973)~ the assignment c,f conditional designations was made in accordance with the
existing technical-norm documentation. After 1973~ most IC received new condi-
tional designations. However~ for a certain number of IC for which no new techni-
cal documentation was issued., old eonditional designations were continued.
The old and new conditional designations differ by the letter designations of sub--
gr_oups and types (the latter is due to an increase in the number of types in
C~ST 18682-73 as compared to the previously existing docun~entation.
A.~ example of the old designation of an IC type iLB331 is shown on the next pa,ge.
~Modification "i" is applied to microcircuits with a number of lea.douts no greater
than 16.
2.0
FOR OFFICtAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
~
CeP~A ~1~ ` .
Ifo~AdKOBa~u HoMep pa3pa-
- bomKU (no ~ykKyuoHan6-_
1 ~6 33 ~ NOMIf /ipG3NOX(f B dOHHOU
cepuu)
- ilbp~dkoBa~u NoMep paapQbomku aayr+ou cepuu
/i/IQ U BUa ~n0 ~yHKI{UON[UIbHOM!/ Ha3H~4EHU/0)
novzpy -
fpyn,n (no KoHCmpyKmuBNO-mexHnnv2uyecxoMy ucnnnHeHUwI
1. Series 4. Subgroup and type (accord-
ing to functional purpose)
2. Drdinal number of development 5. Group (according to design-
(accorciing to functional criterion in technological makeup)
the given series)
3. (~dinal number of development of the
given series
BIBLZOGRAPHY
1. Basic directions of national econoir~y development for 1976-1980. Moscow,
Polit~zda,t, 1976.
Second supplement to publication M~{-147-0 (1966). Basic pa,rameters and
chaxacteristics of semiCOnductor devices and general princi~les cf ineasure-
men-~s. General informa.tion and terminology.
3. GC75T 17021-71. Microcircuit~i Terms and definitions.
- 4. GcsT 1702i-75� ~tegrated micro~ircuitsi Terms and definitions
5. GosT 17467-79. Integrated. microcircuitsi Ba.sic sizes.
6. GC6T 18682-73. Integratsd microcircuits~ Classifications and systems of con-
ditional designations.
CQPYRIGI-Qi Izdatel'stvo "Sovetskoye ~adio"~ i979
- 2291
CSO: 1863/209
21
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-00850R000400444432-8
FOR OFFICIAI. U~E ONI.Y
L'DC 621.346
' ??1~iTTFR-C~'+~I~IFCTED TPA`ISISTOR LOGIC CIRCL~ITS
- Moscow ANAL+OGOVYYE I ~SIFROVYYE INTDGRAI,'NYYE SKHENIY in Russian 1979 (signed to
press 5 tipr 79) PP 83-109
[Sr_ction 3.5 of chapter 3 f.rom hook "Analo~ an~l Dirital Inte~rated Cir.cuits",
by Sergey Viktorovich Yaki~bovskiy, Piikolay Arsen'yevich Barlcanov, Boris Petrc~vich
_ Y.tidryashov, ],ev Ionovich 1lissel'son, *1ikhail Plikiforovich Topeshkin and
T,yubov' Petrovna ('hehot~reva, Izdatel'stvo "Sovetskoye radio", 68,000 cories,
33G nar.,es ]
[Text~ Chapter 3
3~5 Em3.tter-connected Transistor Logic Circuits
Digital IC emitter-connected transistor logic circuits (ESTL) axe transistor
switching circuits with connected emitters and, compaxed to other digital keys,
ha,ve the highest speed of operation and a high power consumption. High speed. of
operation (or to put it another way,a small average +.ime of propagation delay~ of
- ESTL is due to the fact that transistors in these keys operate in an unsaturated
(lineax) mode. F~nitter repeaters tha,t accelerate the process of chaxging the
- capacitance of the load are used. at the circuit output. A reduction in the
prapagation delay time is also achieved due to the limitation of the output volt-
age gradient which, however, leads to a reduction in the interference rejection
of the ESTL circuits. Of the digital IC ~STL developed in recent years, the most
widely used are series 100 and K500 that are similax to a widely kn~wn MS10,000
series abroad (original developer the Motorola Co.).
We will cons3der the principle of designing the ESTL switch on an example of a
basic series 100 logic element that implements simultaneously functions QR-N ~
and L1R (Fig. 3.21). The circuit consists of a differential a,mplifier assembled
with VT1 and VT4 and VT5 transistors. When the signal gradient is applied to the
input of thi~ amplifier, current I~ may flow either through transistor VT5 to
whose base is constantly applied reference volta.ge U~ =-2.9 volts (during this
time a negative blocking voltage is present at inputs Xi-X~), or through transis-
tors yTl-VT4~ when a voltage grea,ter than U~n is applied to ~heir bases. '
22
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
_ ~
Output emitter repea.ters (transistors VT7 and VT8 are connected to the bia.~ leve7.
source U~My =-2 volts + 5~ through external load resistors RH1 and R~ with
rated resistances of ~1 ohms. The low output impedance of tha circuits provides
for the ma.tching of the output and input levels of the logic elements when they
- a.re operating together and the possibility of feeding signals into a cable with
50 ohm wave impedance. The F~TL circuit is connected to a negative voltage power
source Uw~=5.2 volts + 5~. The collector circuits axe grounded. Such a connec-
tion provides a lower dependence of the output voltage Qn inductions from the feed.
circuit and a better interference rejection. The value of the logic gradient for
the FSTL is 0.69 millivolts, while the interference rejection reserve is ~125 ~-1-
livolts. Negative and logic levels of the ESTL circuits (U~b~x =0.96 volts,
Uab,X =-1.65 volts~ low in value, m~ke it impossible to interface them directly
with the TTL [Transistor-transistor logic~ series circuits. The joint operation
of TTL and F~TL circuits is implemented by special circuits of mutual level con-
- verters, entering the composition of all the above-indicated ESTL series.
utuu >
R! N? R10 06uluu Z
VT7 !rz
Bbixod N/lill
I^~ ~ ~ t ~r vre ~31
v~~
BO/XOd N/1H-NE
V// VT? VIS l'~ l'I:i
VDf
VD2
Rs 1, 1 F'6 R9 Rnt R~z
43 K4
i 1, .I` , Xs A.4 -L~xn ~cn9~J/
\
Fig. 3�21. Basic logic element OR-N+(7I'~QR of the F~TL series
1. Common i � UN n
2. OR output
3. OR-N~ output 5� Ucrt y
All inputs to the base logic element through leakage resistors R3...R6~ with a
resistance of about 50 kohms, axe connected to power source UNn =-5.2 volts + 5~.
This connection makes it possible to leave the unused inputs in the appaxatus
unconnected. To eliminate the effect on the logic part of the circuit of pulse
interferences originating in the collector circuits of the emitter repea.ter at
23
FO~R OFF[CI~.L USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFIC'fAl. USE ONI.Y
the moment of switching the circuit when operating with a low imp eda.nce load, two
"ground" buses axe usedi one for output emitter repea,ters and the other for
the internal logic paxt of the circuit.
_ Reference voltage UU17 ='2�09 volts is produced by a special temperature-compensated
_ circuit (transistor VT6, diodes VDi, VD2, as well as resistors R8, R9, R10) and
is selected so that it would be lower than minimum voltage 1. We will consider
the principle of operation of the ba.sic logic element (Fig. 3.21). If a low
voltage level, corresponding to 0(Uax =-1.85 volts~, is applied to all inputs
X1...X~, transistors VT1-VT4 axe cut-off (only leakage currents axe flowing) be-
cause their emitters have the following voltage appliedi
U~ = Uun UG~ V'1'S = - ~,29 ~).8~~~ _ - VOZf.S
The level of current I3 is determined by voltage U3 and the rating of resistor
- R7. Current I3 flows through open transistor VT5 to whose base is applied refer-
ence voltage Uo~ , as well as resistors R7 and R2. A voltage drop U~=-0.98 volts
is produced across resistor R2. The voltage at the OR output at this moment
corresponds to level 0(Uab,x =-1.65 volts), while at the output of OR-NC~, the
- voltage corresponds to 1(U Qti~x =-0.96 volts~ (voltage Ud9 of transistor VT7 should
be added to the voltage drop acroas resistor R2).
When a high voltage level, i.e., 1(UdX =-0.81 volts), is supplied. to one of the
inputs (or to all inputs Xi...X~), the input transistor ogens because the refer-
ence voltage selected was more negative than the minimal voltage i. Transistor
VT5 closes by the formed voltage gradient and all of current I~ will flow through
the opened input transistor (one of the VTi-VT4 row) and resistors R1 arid R7. The
negative voltage on the joined collectors of the input transistors will increase
to level -.97 volts and a level, corresponding to 0, will be established at the
output of the emitter repeater VT8, while 1 will be established. at the output of
emitter repeater VT7. Thus, the circuit produces logic function QR at the output
of transistor VT7 and logic function OR-NUr at the output of transistor VT8. Thus,
_ jumps in the input signal cause switching of currentI~ which, depending upon the
value of the i.nput signal, flows either through transistor VT5 or through tran-
sistors VT1-VT4. Because of this, the circuit with joined emitters is frequently
called a current key. The paraphase outputs of the basic F~STL switch shorten the
propaga.tion path of the signals in digital devices. The presence of emitter re-
peaters that have low output impedance at the circuit outputs, provides a consid-
erable load capacity of the ESTL circuits (KpQ3 > 15~� To provide a still higher
load capacity the F~TL digital series include special circuits with a high branch-
ing coefficient (K ~,3= 50...100 at CH ~ 100 picofarads~.
21~
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040400040032-8
FOR OFFIC(AL USE ONLY
An increase in the joining coefficient with respect to inputs ma,y be achieved by
connecting a logic expander to the basic circuit; however, this causes a consider-
able reduction in the speed of operation of the circuit due to parasitic capaci-
tances; therefore, expander circuits are not included in the F~TL series [3]. We
will now consider ESTL circuits in greater detail.
3~5.1. F~nctional Composition of the ESTL Series
In recent years technological successes ma.de it possible to increase the functional
possibilities of the FSTL series considerably. Along with logic elements and D
triggers, decoding and multiplex circuits, memories and axithmetic device units
were introduced into these series. This provides for their wide use~ in high speed
= computers. The functional composition of the FSTL digital series, developed. in
recent years, and their analogs axe shown in Table 3.13�
We will consider in greater detail the purpose and special features of operation
of several IC of series 100. IC types 100LMi0i, 100LM102, 100LM105, 100LM109 and
100LYe106 (and corresponding IC of series K500) implement functions OR-NUr and G.re
dsstgned with the basic logic element.
IC types 100LP115~ 10oLP116 are receivers from the line and may be used in two modesi
as receivers of a paxaphase signal from a two-wire communications line (in this
case, the built-in lea,d.s in the housing of reference voltage source axe not used)
and as logic elements with constant voltages 0 or i at the output (with an external
connection of the leadout from the reference voltage source with certain input
leadouts. The use of both mod.es simultaneously for elements oontained in the same
IC housing is permitted.
IC type NR400 is a ma.trix of loa,d resistors (four resistors rated at 500 ohms and
four resistors rated at 800 ohms) which, with proper switching, axe used as a load
on the nonmatching inputs of the logic circuits of the series.
~ IC type 100TM130 (Fig. 3.22 ~ axe two D triggers "latches," equipped with
setting (S), resetting (R), synchronizing (C~ inputs and a general synchroniza,tion
input (C). D~.ta is received. from input D during the time when C=O; CE=O. In this
case~ any change in the data at input D is transmitted to the trigger output. The
_ data is stored at the moment tha,t the signal at input C changes from state 0 to
state 1. For CE 1, the trigger is suppressed. at input C. A forced setting of the
trigger into state 1(input S) and resetting (input R) is done when C=CE=1; in
this case~ the signal at input D does not affect the trigger. When the trigger is
controlled by the R and S inputs, the setting and resetting pulses should not
overlap in time.
IC type 100TM134 ~Fig. 3.22b), unlike IC type 100 TM130, has two data inputs~ D1
and D2 and an additional selector input S. When 1 is applied to input S, the
data is reaorded only by input D1; when 0 is applied to input S, the data is
recorded only by input D2.
25
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
~ FOR OFFICIAL USF. ONI.Y
_ . t
EE ; ; i
~ ;
~ t~nr ~at i0;,
i ,-t- ~ "i' t
k, ~ I - ~ '
~I I ~
s _ ;
_ , - i
t

_ o
I~ '
o, I -
, t t~~cc I ,
- --;-c- ~ ' ~ ~ ~ ' i t
' i _r~o}yCC _ ~;_,,,i 7675 taApP
i . i ~
G,'
~i -
-
~
,
r
l ~
cf - ~
- - ~
. . . _
01 ---1 ti~ ~ f
. ~ - ' ' i I ~
' _ _ _ . - - - -
__y
~Z ~ - i
~ i - _ _
S - - ---T-----j----_- ' ~ t
~t
~ ~ i ~ tII
o _ _ . t~~~~.s ~
I ~1D I I ~ r 0 `
Gt. ti,5 tNI.S t
. i ---~7'~-- ia~ ~ i I t.C ~
~ ~0,7 f0
._._.,,.t~-' t_~= "'1''" yi i'~}d ~L ~ oyADS t)A PS
tac ec ~
Fig. 3.22. Time diagrams of D trigger operation for IC type 100TM13~ ~a) and
type 100TM134 (b~.
~ '0tl1"'~� ,aanM,os~2~
s
(1~ ~ 01 4 v 2 C.'< C~-----
l �r ~
5 ' ~ t
4rm... ;
o R
_ c ycir ..0 ~ t
CI -
C/: - t
L f4 ~
C
al 6J
. Fig� 3.23� F~eQuency divider for IC type 100TMi3i (a) and its time diagram (b).
1. Zero setting 2. 100LM105
26
- FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFIC[AL USE ONLY
~
c*i
m~
~
~y ~ N C`1 ~ ~ ~ ~
a
N 4i f-~ n1 N ~ ~ N N N
P ~ V~] c''1 c'1 M c~l c'1 c''1 ~
H a ~
z~
~
a~
~
~n
~
~
p r~ll N ni ~ ~O N ~ O
~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~ ~
~ c~d O o O O O ~ ~
~ ti` L~~- ~ ~ N ~ ~ L`
~ Y-I
~ ~ ~
~r-I
~
~ .
O
O ~
O c~1 ~l
~ o ~ ~ ~ ~
r~l o ~r~-t ~ . ~
~ ~ ~ O O O O O O
O ~ ~ ~ ~ . ~ ~ ~
+-I
~
U H ~
~ ~ N N ~ uH'1 O O l~- ~ O~ ~ O O
4-i ~ ~
~~..1 ~ N N .~-i ~ O r-1 rl
~ a. �o ~ ~ ~ ~ aa aa~
a~ tn a a aa a a ~a aa aa a
0 0 0
~ m~ o� �o 00 0�o 00 00 00 00
~ m x x xx ~ x x~ x~ ~x
~ ~
m r' cv o 0 0�~
r' ~ W ~ ~
a
~ � a a~ ~
a o a � �
- H r+ e-+ ~
~ ~ I
�i ~ ~ ~ I\ I .C
O N
~o ~~d mz ~ o as~ mZi ~z m~
~ p
O rl U O,-UI N T1 ~ N (~2 ld ~('rl I E3 TI ~ 1 ~I
r~ cd rl (~l 40 m\ U N\ U Pr,~ N 40 '~r V ~ V~ m
4D vJ \ O tA cd ~ H ~rl VJ ri N �r-1 r-1 -~i O VJ I rl ~
~-1 O N U+~ rl -F~ m o h0 ~ m R 40 C~l N rl P~ 0 u1 ~ ~ M O~
v] ,-1 m r-~ ~ Z ~ i+ z ~ '~i t+
O O m'zi N N U I rl m N O! rl U] U I ~ m r-1 7] rl t~
a ~ G i m~ z~-+ s~,-i m m o o~ ~ o~~ a
~�'xd~a, ~ aoad om ao~d o~ho~d'
o o~ r+p~ o o ~ m o ~ md ~ m.~ ~
_ U ~ fS, m N H m Q rl N ~ m'~..~ e-i c~1 E-~ ~ rl ~ H m m H~ 1l1~ H~.~C ,-1
~
27
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
FOR OFFICIAL USE ONLY
r r ~~r y r w ~ N N y r�w ~
m m o ~ ~ o i~ m .~i' � ?~U. o o ~
t ~ ~~oq o i aq w o ~ ~w o ~
1~-~ N t
7 t~ n C ~ n i- ~ f
A t y ~~j1 I-~ c D c~i- id F~
C~ ~o(D c+ a N ~ 04 O I d4 F-' 1-~~ Z O I-'~
~ ~ ~7(D I~-+~ d (D y~n ~g aNn ~ c~p ~(~j ~
c~D N W~ OUqq N Z m W Z ~ ~ I~-~
1~ I~ m ~ l~ 1-~ c+ d I~--~ hi m c�t- N
ci- e~ . W c+ fi c+ ~ FK-" Z N~, c~i m ~'S
?~i ~~-i w W ~ w ~ k \ c~+ < ~~p U4 c~+ u~i
~ w W U1 W U! ~ Fi ~ fp (p
~ ~ ~ ~
~ ~
F~+ F-+ F+ H F+ F+ F-? I-~ F+ F-~
O O O O O O ~ Q p p ~
. .~-.~q. ~ ~ y c~n v~i r r r
~ ~ ~ ~ ~ ~ ~ ~ ~
0
N N N W F-? t+ O
ln ~ F-+ ~O aD V O~ lh
_ ~y
, ti
rl I~ I`i Il lI_`i ~i r1 r~f 1/_`i r~Y r~ 1^i 1^i 1^i ~i 1^i 1/_`i 11~_`I ~
~ ~ ~ ~ V ~ ~ V 4 ~ ~ ~ ~ ~ ~ ~ V l v {
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Q ~ ~ ~ Q 0 Q ~
~ ~ ~M ~ Q ~r ~ Q ~ ~ ~ 0 ~ ~ ~ ~ ~ 0 Q
~ ~ `--1 ~ ~j.j ~ ~ N ~"r F"a ~ ~ ~ ~ N f4~ ~ N
r i-+ f-? r+
N N N N iV N W W ir ~..a N ~...a F.,a t+ F,p
H~ H ~ H ~ ~ ~ y ~ y~ ~ H
~ ~ ~ ~ CA ~ ~ ~ ~ ~
O O O O O O I O O O O
iv !v fv W i-~? r~? i-~+ i-~+ i-�+ O f~...~
ln ~ ~0 OD ~7 O~ ln F+ O O
O
H
W
v'
~ N
~ ~7 v ~7 V ~1 ~7 V ~7 ~7 ~7 c~f- ~ m
O O O O O O O O O O O
O O O O O O O O O O O p~~''~
- ~ ~ x ~ cn rri~ ~ ~ ~d "rd ?~r'e i c~i- pi w
f-? ~ f+ f+ t+ f+
n~ N N w F-+ i o 0 0
~.,n ~ F+ i-+ ~p OD N ~7 O~ ln r~
N N N N N iv N 1v N t-~+ ai ~ c~+
N ~ ~
_ ~
_ i1+
W W W W W W W W W W ~ CA ?r~
iv iV N N N N I N N tv N ~ b w O
~
- V Q~ ln ~ W N r-~? O ~ (
D ( D O
N ~ ~ ~
28
FOR OFF[CIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400440032-8
I~()R (1l~NI('IA1. I1tiH: nN1.Y
a~ ~ ~
~
~-I S 00 Q~ O N c"'1 ~ ~ ~ L` 0p ~ O r-I N
[T, ,uj N r+ N N cV cV N ~ cV c~2 N N c~l c~l c"1
~ a c~1 N N N N cV cV N N N C~t N c~t c~t N N
O~ c'l c''1 c'~l c'1 rl Cl c"1 c"1 ~''1 rl c~l c~1 rl c~l c"~
N
O ~ '
z
~ o N cV N N ~ N c~t N c
~2 N N
ti
~ ~ ~ .~"1-~ y~ ~ ~O ~ ~ ~ ~
~ ~ H H H H I I I 1 H i-Aj A A F-j H z
v ~ cp O O o O O ~ O O O O O O
O~ O O O O O 0 O O O O O O
~,O L~ C` L~ L` ~ C` L` L` L` L~ ~
~
c'~ '1
m ~
~
.n
_ RJ
H
. O N'~ ~O L` r+ CO O N ~ O O
O c'l c�'1 c'1 ~ (�1 (rl 3 ~J' ~ ~O ~O ~ L` c0 ~
O r1 .-1 r-~ .-1 ~ r+ .-i .-1 ri
O O O O O O O O O O ~ O O O O O O
~ ,'~r^ rf e-1 r-i H ri r-I ~ e-1 r-I ~-1 r-1 rl ri v-1 ~-1 ~--1
~7 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
O o cH'1 c~`l ~ c~''1 c''l ~ ~ O ~ ~ ~ H H E-+
ao 00 `o r+ cv rn rn o 0 0
r~ r~ r~ r~ r~ c~ c~i r~ ~ ~o ~ c` c~ ao co 0
~ ,a r+ ~ ~ ~ m ' .-i ~ G~ ~ ~ ,-i .-i .-i
~ ~ ~ ~ ~ ~ ~ ~ a ~ ~ A A A p,~p,~ a
U] E-~ H H E-~ E-~ H E+ E-~ H H H PG ~i H H H H H H 'zi
N O O O O O O O O O O O O O O O O O O O O O O O
�-1 O O O O O O 00 p O O 00 O O O O O 00 00 O
FI ul ul u1 u1 Ul ul ul ul ~+l u'1 Ul Ul Ul Vl irl V1 ul ul u1 Vl ul vl ul
~ ~ x x x ~ X ~ ~ ~C ~ ~ ~ S~C ~C ~ x ~ ~C ~ ~ x
~
� a
H
~ o
c''1 C'~1 ~ ~ ~ ~ ~ O~ O O
p ~ .-r ~-i .-1 r-1 N ,-i .-i r-i ~~p-~i o~0
~ H C~-~ H H ~ ~ ~ A A A H H ~
O O O O O ~ C ^ O O O O
O p O O O O ~
~-1 rl ~-i rl ' r-1 ~ ~-1 ~ ~ ~~-1 rO-1 ~~-1 r~i ~
-I~
~j ~ m b ~
u7 ~ O
U ~N i~ Ry 'd
r~l ~ ~ +i ~ U m 'd m}~ ~ ~
~ .L' U U m i~l .~C ~ rl 4S N ~
o ~ ~ ~ ~ � m > a o w
~ ~ v~ ~ ~ ~ ~ ~ ~ ~ ~ ~ aHi ~
N m f~l m ..~1 m .C ~ 3~ ~ ~ ~ 4.,-to
40 40 ~ 40 .a 'd ~Q +-1
cd ~ ~ 4~D ~ rl rl ri 3 ~ r~l .i"., ri ~ ~ O ~
~ f~ f~ ~ i-~ cd cd cd ~ f~ ' r
1 ~
-i~ A A ~ A m ~ m ~ ~ ~ ~d c~d ~ ~d a5 ~ ~
o > > a ~ ~ .a ~ ~ -N
0 0 ~ o i oo ~n o a a.o m
~ [-~i E-~~ w� ~ ~ ~ ~ v1 ~ c%~ c%~ oo ~ ~ ~ a
~
29
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
1~()R UFFI('IA1. USE: ()NI.Y
n H ~ ~ ~ ~~d ~ ~ ~ o ~ ~ orH a ~in
O ~ h'' f'' O Q~ O(D i-~ O(D O(D F" N(D H" ~ f''
a o o oa o H w tv ~i c+ y p y K ~ ~n ~ ~ c+
~ ~ ao ~ o ~ o ~rno w ~o ~ o
~ ~s o O m?d ~ uPi' r~ ~~i,' r~ ~s o o
oq m ~]d ?d dd ~ o~ ~ ~ o~~ m~ w o~ w
Fd � i o ~i m m ~ r~ o w~+ P~ o rn ~
m ~t oa z ~ ~ m ~ ~s ~ ~ r~ ~ ~ ~t ~ ~ ~ i
- ~ 4 ~ o m o r~ u, o~- F-� o~- N� o a~ W a.
fy H H O4 w~ w~ ~ vNm o c~+ ~
m o o t~ o o ~ N t~ ~ ~ ~ N
~ ~ o ~ m o ~ ~i ?j tv . o g ~
c+ m oq c+ m oq o a' tv o ~Y tv ~ c~- ~n ~i tu ~ m ~
o n r~ ?
d N ~ w ~ o w o o ? ~ w o 0 0~- rn a~ ~
~ ~ f~ ~(D hA C~ (D c+ W c+ ~ O ~'i O O
F-" O c+ g c+ ~ cF ~7' Or' c+ F+ Q' n N
c+- w ~ rn m ~ a o H (p ~ m W ?i r~ ~ m
~ c~' F-' ~ N ~ O W c+ W c+ O a' c+ F-~ F-"
~d ~d N c+ N< F-' O W A U~ 1-' F-~ U1 c+ ~ c+
H F~." c~+ N ~ ~ ~ ~ c+ ;7' ~ fA
O c~+, N� t3' ~ c~+ N ~ N ~j N~'
W ''i tn O 0~ 0~
cl' (A Fj ".s' v
~
H ~ N ~ ~ I I I I ~ ~ O
~ ~ ~ ~ ~ � ~ ~ ~
O~ aD N OD
ln O ?y O i-+ N t-+ H
N ti
N
~S
x~ ~ ~ ~ ~ x~ ~
O O O O O ~ I ~ N
~ ~ ~ ~ ~ ~ ~ o
~ y ~ N i-~+ O ~ t-+
~
~ ~ ~ ~ ~ ~ N
o O ~ ~ ~ ~ ~ 0 ~
~ ~ i~v F-~? O ~ O o
~
W
(U
p r~
p O O O c~+ Q~
~ I I 1 1 ' .r~-'~ P~
~ ~ ~ !d U'
N ~ N
fv N N W
F+
I--~ ~ O w
cp N � O
W W W W W W W N F~ O ~
~ ~ ~ cf
N N N N N N iV c+ ~
~ OWO ~7 ~ ln ~ W ~d Q9 ~
~IU 1 I
So
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
'IAI. l ItiH: ONI.V
O O~ o Fr'~ F-r~ y O~ ~ O ~
f~A ~ ~ N N < ~ (D ~ c~+ ~ ~ ~j n
FA
Q4 ~ I~-~ F+ (~D l~A ~ iS ~ ~R O ~ l'j ~
F~ N ~
~
~ ln I-~ � O iv c+~ Fy c+ ~ c+ ~
?d iv I~-+ H C F~-~ m ~ 'G F~-~ I-~M 04
N O~ fA ~ ~'S F~-" ~ n 1~-'~ ~ Fi ~
� N O
fD
O Q~ N~ ~ F~'~ N F~-~ ~ F~'~ ~
O~~ F+ fA DG' cf' F'S c+ c+
ln iv Oh F-? ~n tn ;s'
~ OD ~ O F~'~ I~-~
N � c+ c+
- ~ O~ lA ~ `3'
~-?N~ c''
rn- ~ ~
i ~ ~
~w 0� o 0 0 0 0 0 o I'y
o 0 0 0 0 0 0�
w � o r r
a{p~�m v ~ ~ ~ ~ ~ ~
>i N I~ ~O r Oo Q~ O W ~
. N
I~ N N '~ri ~
~
O F+
~ ~ ~ ~ ~ ~ ~ ~ O N .
~Qp P(~p+~ c+ ~-ro+ N~
fi iS !~A ~ ~ ~ ~ ~
F~~~~ H~
O ~ N p~
c+
w w
~ x
N I'~i ~N O
O c+ F-'~
F+ ;S' N ~
� (D 0~ I
F+ F+
rn~pCO
~ o o .j. ~ C o'
~ i o ~ m
w
.
~ v w
~ r~n p' ~ o
[A ~ W ~
f,~ c?-
A aq m ~y
~
~o~ ~
~~m b~o
~ Nm ~~~'fi
F"
~ ~
c+ Oq
I
~
- 31
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
FOR OFFICIAL USE ONLY
IC type 100TM1 (Fig. 3.23) is two double D triggers of the ms type with sepa,rate
inputs for setting S, resetting R, synchronizing CE and with common synchroniza-
tion input C. The data is received on the ma.ster trigger from input D at
C=0 and CE 0. During this time, the slave trigger stores the data receivpd by the
, trigger in the previous cycle.The data storing occurs when the signal changes at
input C from state 0 to state i. In this case, trigger m changes to the storage
mocle, while trigger s changes to the receiving mode. Previously recorded data in
the m trigger is transferred to the output of the circuit. At CE 1, the trigger
is blocked. at input C.
To achieve the calculating mode it is ngce~�saxy to co ect output Q to input D
and feed counting pulses to input C or CE ~Fig. 3.23b~. Compulsory setting (5)
and resetting (R) axe achieved at any moment of time, independently of the state
of other trigger inputs (Fig. 3.24).
, __-__y
_ ^ , t
~ v
- - - -
~ - t
_ - - . _ t
~
~ ~
,_~_~~r- . ~
~
t~D tonD ty0 t
j
t
Q -C~1 l, .
: ~:a uc ~in pc i'
~ ! Qf
~ t~q p5
tjp p R
Fig. 3.24~. Time diagram of a D trigger type 100TM13~ operation in the calculation
mode.
IC type 100TNa33 is four D triggers with strobing elements at the trigger inputs.
Strobing elements axe divided with respect to trigger pa,irs by strobing outputs
(G1, G2), synchronization input CE and common synchronization input C. The da,ta
is received from input D at C= 1 and CE =1, in this case direct data transmission
from the input to the output of the system may be blocked by signal 1 at the input
of the strobing element. Da.ta storir_g occurs when the signals change at inputs
G1 and G2 from state 1 to state 0. When all triggers axe synchranized with
respect to the common input C, 0 must be set at the inputs of separate synchroni-
zation or they must remain switched off. With separate synchronization of trig-
ger pairs with respect to C~ inputs, the common syn~~ronizatic~ input C must
remain switched off , or si al 0 must be fed to it ~Fig. 3�25J�
32
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ON ,
.
~ ~ t
CE t
A t
t~D t~D t0
i
C to D t
P t
10
tqA D~[ ~ t1A pD tbA~VC . t~A DC
t~A PCI t~Q~pD~
FYg� 3�25. Time diagram of D trigger type 100TM133�
To provide proper operation of the trigger circuits,it is necessaxy to take into
account a number of additional paxameters shown in the above-cited time diagramst
l;�;,,1;~5 minimum allowable delay time of the signal front or cut-off at in-
puts D or S with respect to the positive synchronization pulse frontf ~o~S Dr loh�s
minima.l allowable time for advance of the front and cut-off of signals at in-
puts D or S with respect to the positive front of the swith respect~to theeD inhe
valuES of these paxameters must be as followsi to~,o
put not less than 2.S nanoseconds; to~s with respect to the S input not
less than 3.5 nanoseconds, ~iD with respect to the D input not less than 1.5
nanoseconds and ~~S with respect to the S input not less than 1.5 nanoseconds.
IC type 200ID164 is an 8-channel multiplexer with an inhibition input W made of
- basic logic elements. The presence of the inhibition input ma.kes it possible to
organize high level decoding circuits and implement an "QR wiring" operation of
circuits for multiplexing (combining) over eight channels. IC type 100IYe160
(12-input paxity check circuit) is a combination of nine logic elements that im-
plement the "OR lockin " to function. The circuit is designed to determine a
pa,rity of words up to ~2 bits long. The output voltage corresponds to level 1 if
an odd number of digit "units" is present at the circuit inputs.
33
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAI, USE ONLY "
IC type 100IP179 is a high-speed carry unit and is designed for combined use
with IC types 100IP180 or 1002P181 in high-speed acting arithmetic and logic
devices, operating with long words. The circuit consists of ten OR-NG~-OR logic
c~lements in which the collectors of the input transistors are combined in an
"OR wiring" circuit. IC type 100IP181 are high-speed universal arithmetic-logic
devices (ALU), designed to im~lement 16 logic functions and 16 arithmetic opera-
tions with two four-bit numbers.
A~...A3 and B~...B3 are data inputs. Input vaxiables A and B in the positive logic
circuits ase fed in the complementaxy code and output function Y, in this case,
is also formed in the complementaxy code. The direct code of vaxiables A, B and
of output funcetion Y is used in the operation of the ALU in the negative logic
function (0 corresponds to the upper level and 1-- to the lower level). Inputs
SD...S are used to assign the code of the function being implemented. Depending
upon the signal at output M, the device implements logic or arithmetic operations.
~11 internal carry circuits are built-in in the ALU circuit. Input C is the
caxry input from the previous stages. The caxry signal into the following stage
is formed at output X2.
The combined utilization of IC types 100IP 181 and 100IP179 makes it possible to
almost halve the arithmetic operation time for 32-bit words. Two complementary
group carry signals (outputs X1 and X3) prod.uced in the ALU are used in the accel-
erated carry operating mode. The implementation of logic transformations of in-
put vaxiables A and B is done when signal 1 is fed to input M which blocks the
internal carry circuits.
The value of the typical parameters of the ALU in inplementing axithmetic opera-
tions with words from 4 to 64 bits long, using accelerated caxry circuits in
100IP179, are shown in Table 3.14. For the combined operation of series 100 and
IC series 133 and 155 circuits, IC type 100PU124 is used. It consists of four
2-input level converters for transferring from TTL to IC of the F~TL type, as well
as type 100PU125, which consists of four 2-input level converters for transferring
from ~TL to IC type TTL.
We will consider the operation of level converters in greater detail. Fig. 3.26a
shows one of four level converters included in IC type 100PU124. It consists of
input diodes VDl-VD4, an input emitter repeater (transistor VTl~~ a differential
amplifier (transistors VT5 and VT7), operating in a current switching mode~ emit-
ter repeaters(transistors VT4 and VT8~, as well as a source of reference voltages
(transistors VT9 and VT10).
TTL feed voltage (5.0 volts is fed to leadout 9 and the FSTL feed voltage
(-5.2 volts � 5~) is applied to leadout 8. Leadout ~6 (common) is grounded and
- the load is connected to paxaphase outputs 4~ and 2. For strobing all four elemen-
tary converters located in this IC~ second inputs of each converter are combined at
leadout 6.
34
FOR OFFIC'IAL USE ONL1'
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
Table 3.14
Typical paxametersof the ALU type 100IP181 when operating with accelerated carry
circuit type 100IP179
Worci Adding time Number of IC
length~ nanoseconds
bits With series With accel~rated. type 100~P181 type 100~179
carr~r carrtr in ALII in ALU circuit
with accelerated
carry
~ 7 ~ - 1 -
8 11 - 2 -
12 14 13 3 ~
16 17 16 4 1
32 30 18 8 2
48 43 zo i2 3
64 56 22 16 4
The reference voltage source forms the bias voltage for tne current oscillator
(transistor VT6). This voltage is ~aken off the emitter of transistor VT10. Two
reference voltages axe also crea.ted, Uon~=- 1.8 volts and Uon2 =-0.7 volts. Volt-
age Uo~~ from emitter of transistor VT9 is fed. to one input of the differential
amplifier (base of transistor VT7), the voltage from resistor R12 enters the base
of still another current oscillator (transistor VT2). When a 2.4 volt signal is
applied to the input, a voltage of about 0.05 volts originates at the base of
transistor VT3 and the volta,ge on the ba.se of transistor VT5 will, in this case,
be approximately equal to 0.8 volts which corresponds to level 1 in the ESTL cir-
cuits. Tra.nsistor VT5 is found to be open, level 0 is established at output 4 and
level 1-- at output2, To suppress interference pulses originating at the moment
of switching in the feed circuits of the TTL circuits, diodes VD1 and VD2 axe in-
stalled at the level converter input.
Fig. 3.26b shows a circuit of one of the four level converters in IC type 100PU125.
The circuit consists of a current key (transistors VT3, VI'S and VT10)~ equipped
with a stable current oscillator in the emitter circuit (transistor VT6 and re-
sistor R9) and an output stage (similar to the inverter in the TTL circuits~,
operating in the saturation mode (transistors VT4, VT7,...VT9�)� Feed foltage
5.0 volts � 5,~ is applied to lea.dout 9 and feed voltage -5.2 volts + 5~ is applied
to lea.dout 8. Leadout 16 (common~ is grounded.
A bias is applied to the stable current oscillator from the internal source of
reference voltages (elements VT1, VT2, VD1...VD4~, R1...R4) and two reference
voltages axe also usede Uo~~ =-2.8 volts, taken off the collector of transistor
VT2 and Uo~2 =1.29 volts, entering from the emitter of transistor VT1. Reference
voltage U is used to fix the output voltage of 0 when the circuit inputs axe con-
nected to the -5.2 volt voltage source or are free.
35
FOR OFF'IC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
I~OR OFI~1('IA1. UfiF: ONI.Y
9 af vD5 ~D7 u 2
>6
RZ R3 R6 RB R1p A12
6 VD3
VT3 VT9
VD4 VTf ~T4 VTB
5 VT10
vo> vD6
VD2 ~TZ VTS VT7 VD8
~ ~ VD9
VT6
R4 RS R7 R9 ~P1f ,913
B
4/ .
f6 9
-o
VT> RZ VT3 VT5 VT1p R8 R10 ~Pf3
R5 Vl8
7 V r4 VT7
: C> q3 vD7
i/9~ k .
- RJ1 q11
%T1 VT6
_ ~D3 ~DS ~T9
~04 VD6
o~ .
A1
~'4 p7 ~G9 Rl4
_ 8 2 3
d/
Fig. 3.26 Level converter for transferring from the TTL to the ESTL (IC type
100P'U124 ~a) and for transferring from the ESTL (IC type 100PU125) (b).
When using the circuit as a one-input level converter, the reference voltage U
; (le~.dout 1) is fed to leadouts 2 or 3 depending on whether the circuit must pro-
duce an inverted or noninverted conversion. Thus, in case U~n2 is connected to
input 3 and 1 is present at input 2, transistor VT3 is open, while transistor VT10
is closed. The voltage of the VT3 transistor collector is about 1 volt which is
enough to block transistor VT8 reliably. The current through open transistorVT7
enters the base of transistor VT9, insuring its saturation,as a.result of wlzich
36
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
voltage U�~bfz < 0.5 volts is established at output 4, corresponding to level 0
of the TTL circuits. When logic 0 is fed to input 2~ transistorVT10 opens and
VT3 closes. The voltage on the base of transistor VT9 reduced to the level of
1 volt which leads to the closing of transistor VT9� The voltage on the collector
of transistor VT3 increases~ which leads to the opening of transistor VT8. As
a result a voltage is est3blished at output 4 which corresponds to level 1 of TTL
circuits (U~=2.4 volts).
~ When all four elements of circuit 100PU125 are used, reference voltage ~arom
leadout 1 is fed to corresponding inputs of all four elements. In designing
functional un~ts using level converter circuits, it should be taken into account
that the zero level U�~,X ` 0.5 volts is somewha,t higher than the zero level of
TTL circuits (U� < 0.4 volts) which reduces the noise resistance of the latter
Bolti \
by 100 millivolts.
The branchin~ coefficient of level conterters when operating at inputs of IC series
123, 155 is no greater than 8, and at inputs of IC series 130 no grea,ter than
6.
IC type 100RU401 is a superoperative memory with nondestructive readout and con-
sists of a matrix of trigger memory elements organized as 16 one-bit words. The
matrix is equipped with a circuit for address and bit control. The electrical
functional circuit of such a memory (F'ig. 3.27a) consists of 16 triggers (elements
for storing data) organized into a two-dimensional (along X and Y~ 4x4 matrix
(VTl-1...VT4-4), 8 address formers (F), xead-in amplifiers( 3t1 0,311 1) and two
read-out amplifiers (Cq O,C~i 1). The circuit operates in three modesi data
storing, read-out and read-in. Addressing (sslection when reading out and reading
in) is done by simultaneously feeding level 1 into selected. address buses (X,Y).
Zero level must be maintained at all address buses not selected. When there are
no signals at read-in amplifier inputs (UBX ~~o =0, U~X 3n~ =0) the signal from
the selected cell of data storage is fed over the read-out buses to the input of
the read-out amplifier 0 or 1. Depending upon whether 0 ax 1 were read-in in the
selected cell, level 1 is formed at the output of the corresponding ~,mplifier.
The interrogated cell stores its data. Switching the trigger to the new state
will occur only when new data is received. To read-in 0 or l~it is necessaxy to
supply level 1 simultaneously to the selected buses x~ y and to one of the read-in
buses (3n o or,3(1 1 respectively~ .
The data storage element (Fig. 3.27b) is an unsaturated trigger with direct coup-
- ling made with two three-emitter transistors VT1 and VT2, and three resistors.
In the storage mode~ the trigger has emitters E2...E5 operating while the circuits
of emitters II, E6 axe disconnected. Jn the read-out and read-in modes, tha trig-
ger has emitters E1, E6 operating, while circuits of emitters F2...T5 axe discon-
nected. Read-out and read-in is done over the P1 and P2 buses.
IC type 100RU402 is an associative memory device. The associative memory device
(AZU) is designed for operation with 2-bit words. Besides storage functions, the
37
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
1'Vn Vfl'1l.~ML UJG VIrLi
'~j , : Y3
(1} f � f
D
r~� ~ r~' J r f~ 4
i
c
r2,: r~.~ �:.3 rz~:, ~26`) ,
.1~~ ~ JOI.f 44M~~
TS~; r,y T3r;, D
1 _ . _
I
ro, ~ , ~--i ' . ~ ra,,
~
~ J ~ ~ Bax Cv�0"
i~ D
D
a~ R3
~3~ ' rri ~rz .
F.~:p.udvua ~u.vd 3f ~6
- PI ~73 30 3s PZ
r ~
6i
- :io. j.2^. ~'.ectrical functional circuit of a superoperative memory (a) and a
data storage element (b).
1. 8x 3n! input read-in 1 3, bit bus
2. Sb~x 3n l output read-out 1.
~ZU cioes axithmetic operations on the stored numbers. At the basis of the AZU
desi~-:z is a system of access by a tag the access to the needed word and its
~elec~ion is made by a ~ag contained in the desired word itself. Associative
select'_or. (seaxch mods) in microcircuit 100i~U402 ma,y be made under conditions of
"maskino" ~he interrogated data. The retrieval is over two buses for each address.
Comb'_nations 1-0 and 0-1 are used respectively for the retrieval of the 1 ar~d the
0 sta�es. Combinations 1-1 correspond to the "mask," i.e,, in this case, the re-
_ action at the "word compa.rison" output cc~responds to :~oncoincidence of the inter-
~ c~~. ~ ed data and any data st ored wider any address .
38
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
3.5�2� Basic Electrical Parameters and Typical Chaxacteristics of IC type ESTL
Digital type ESTL IC, besides the usual list of electrical paxameters typical for
other digital IC also ha,ve special static paxametersi input and output threshold
voltages.
~1, C/e~,C -!,6 -1,4 -f,0 -0,8 -0,5 /g,,r~A~~`
- ~ ~ -UB , 6l
~
QI
~ I
- -1,C I
~ I
/ ~ I
~ - -1,2 .,0 ~ 5~ I
. ~ ~
j Uoa Uer,~
~ - -1, 4 ~tlmx,~vA
/ ~H
/
/ - -!6 i
.,U.. ~ ../'_--y. �
- --1, 8 ~un i Uduix, B
i I I ~
9LY~ B
UDx UAx nop U~x nap ~Q.r 3~
~2~ �1 el
Fig. 3.28. Chaxacteristics of basic logic element of the ESTL series;
a-- transfer ( QR-Pd(7I' output, solid line; OR output, broken line)
b-- input, c-- output, with respect to current.
1. U~X , volts input voltage 3. U~iX volts output
2~ Ugx naP t~eshold input voltage
voltage 1~. Isx , mi.lliamps input
, current
~ 5� Uo~ reference voltage.
39
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
Fig. 3.28a shows the typical transfer characteristics o~ a basic logic element of
_ series 100, K500 with direct and inverse outputs. By means of these curves, it
= is possible to gi~re the following parametor definitions for FSTL circuitsi
Uex nop ~ Uo ~m~ Onput threshold voltages; igbi~ nop UB~~xR:,P output threshold
voltages; UpX ~ U~x input voltages; Ueb,x Uab,x- output voltages of unity
- and zero. These paxameters ma,y be used to calculate the following~ voltages of
static noise resiitance ~Un
M' U~b/x nnP -Ul and U~ - U~ 'U~ br,~ n~p , logic
6x nop IroM dx neP _ 1 0
gradient U~ -UBbi~ -U~~X as well as the zone of switching G1 U - Uax noP- U'
BX R OP
Taking into account the low values of output logic and the unavoidable technologi-
cal spread of rated elements (therefore, also of the electrical parameters of the
keys), maximum and minimum paxameter valuea were established for the ESTL circuits
- that determine the transfer characteristic (Table 3.~5). These paxameters cor-
respond to the allowable values of static interferences (for -10 t~ 75�C~
Ulncry ~ 125 ~.llivolts, U~oM > 155 ~11~vo1ts; to deviation of output lovels
of 1 and 0(for t= 25�C), d, U~ i 690 millivolts; switching zone (for t= 25� C~
ab~x
~ U~ 37~ mi-llimeters.
We will now consider the input chaxacteristic of the basic logic element L1R-NOT~
OR of the ~STL series (Fig. 3.21). The ir.put chaxacteristic of this circuit
' (Fig. 3.28b) has four zones.
In zone 1 the input transistors are blocked and the input current is low (equal
_ to the leakage current between the collector and the base). F3ztire current I3
flows through the emitter circuit of transistor VTS. In zone II, as the voltage
increases on one of the input transistor VT1-VT4, it gradually becomes conducting.
The input current increases which increases collector current Ikl due to the cor-
responding reduction in collector current IK2 of transistor VTS. At a certain
value of voltage UeX ~ collector current I~ is reduced to a value considerably
lower than I~ . In this case, the current through resistor R7 rema,ins practically
consta,nt.
In zone III, as voltage UQX increases further, current I~ and voltage UR7 will
increase as a result of which the differential input impedance of the circuit will
rise shaxply. In zone IV, the transistor becomes fully conducting and picks up
all of current IK1 .N I3 = const.
_In the cut-off state of the circuit, at voltage 1 on output 2, its working point
is located on zone I of the input chaxacteristic, while in the conducting state
in zone III. Zone II is a transition zone. In this state the input impedance is
minima,l, while in zones I and III for U~equal to voltages 0 or 1 the input imped-
ance is high.
40
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
_
a�~ ~i r�~
N 00 CO 00
~ I 1 I I 1 I
1 I I r'-I i I r'-I
N I
'b
~
rl ~ r~-I N
~ ~~ti
' V~ r-I m 1 I I - 1 I I I I 1
~ N ~ 000
~ ~
c''l U
N r-I ~ o ul Vl O O O O
- P ~ x
cd 4-i O m �
H O+~ ~ i{ ' ~ il r'1 r'i r~l r'I r'1
~VI N ul U1 ~l ul ul ul O O O
�rl ~ rl r~-I ~ rl ~ O a0 00 ~
N cd ~ m ' � � �
U ~ ~ r{ r~ 1 ~ i ~
i r
~ I O O O
~
_ ~
~
U
O ~O ~
~ ~ ~O ~
4-i
~ ~ . O i I r'i
cd
~
~
~
O ~ N O
~ ~ O~ O~ a0
N ~ O O ~
~ ~
td
-N ~ c� t�n
a~ ~ o~ ~o ~o
~ ~
- ~ ~ � i i
~a ~
~ m ~
- m a�o ~
a ~ ~ rn rn ~
~
O O ~
~ cd N � � .
a
m
~ ~ ~
~ ~ ~ ~ ~
~
U ~ ~ ~
H
O
00
~ ~ O O ~
tn O � ~
ri r-1 ~
~ 1{ 1 I ~
0
N ro Q
~ 'b t x t~
~cd ~
p~ r~!] cd O m] c~d >
~ > ~ ~ _
~ r-~ O - ~ O ~
U ~ ~ ~ )lt
~
-1~ ~ ~ cd U] ~ r1 m ~ cd V~ ~ O~
~ a~i a ~ a ~ ~ ~ a ~
- '~w a ~ > ~ r-i ~ > > ~ o
41
FQR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
Table 3.16
Electrical paxameters of IC series of F~TL
Parameter Values Ambient temperaturei
minimal maximal to, C
Input current 0, I~X , microamp . 0.5 - ~ 25
Input current 1, IeX , microamp. - 265 25
Output threshold voltage -.92 - 75
1, Ul$b~f ~oP , volts - 1.04 - -~0
Output threshold voltage - -1.605 ?5
o, u~b,.~ �o~, , volts - -1.650 -~o
Output voltage 1, Uae,x ~ -0 ~ 9 -~�72 75
volts -1.02 -0,86 '-l0
Output voltage 0, U ab~x ,volts -1.88 -1.67 -10
Current us ed I ~o r~. ma - 25 75
Time of propagation delay when - 2�9 25
- connected, t
Rp~, nanoseconds
Time of propagation delay when - 2.9 25
disconnected t
~p ~ nanoseconds
Output branching coefficient ~5 75
-ZO
Power consumed PRoT , - 35 25
milliwatts ~per logic element
OR-N CIr~ OR )
The output characteristics of the key at the transistor VT8 output (see Fig. 3.21~
are shown in Fig. 3.28c. Depending upon the value of the given voltage at the
output, current IBe,z will flow into or out of the circuit. At each circuit state,
the reduction in U~b;,~ at the VTS transistor output leads to this transistor being
mo~e conductive~ and an increase in outflowing output current Igb,x . An increase
in U makes this transistor less conducting and iilcreases the inflowing output
BhI.K
current I~~;~ . A further increase in U~~xmay make the emitter repeater fully
nonconducting, after which the current will be determined by the loa.d impedance
which will determine the slope of characteristic Ieb~~ (Ueb~x
The low output impedance of the emitter provides a high loading capacity of the
FBTL circuits on DC. However, the actual loading capacity in the dynamic mode~ due
to the input capacitance of the circuit and the capacitance of the wiring is re-
duced to x~Q3 = 15�
!~2
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
We will now consider the dynamic paxameters of the ESTL elrcuits. The basic param-
eter that determines the dynamic properties of the circuit is the propagation delay
time when connecting and disconnecting (t1~0, t0,1~~ ~TL circuits axe the quick-
3R. P 3,~1'
_ est digital IC. At normal conditions and load impedance RH 51 ohms, their typical
propa,gation delay time is 7 nanoseconds. The delay time is measured at the level
of 50~ from the full gradient of the logic level when the circuit is switched.
- It may be seen from the chaxacteristics shown in Fig. 3.29 that the greatest effect
on the propagation delay is produced. by a change in the feed voltage, the voltage
bias level and by an increase in the capacitive loading.
FSTL series 100, K500 axe considered to have identical electrical parameters and
differ only in functional composition, the type of housing and the operating con-
ditions. Table 3.16 shows the values of the operating electrical paxameters of the
basic logic element of series 100 and K500 in a temperature range. The limiting
allowable modes of operation for the ~5TL series is shown belowt
Maximum feed voltage, UN~ ~ volts -7 for 5 millisec;
-6 constantly
Maximum input voltage Uax max ~ volts 0
Minimum input voltage U8~ m~n , volts -5�5
Maximum output current Iab,x max, milliamp 40
3�5�3� Certain Special Features in the Use of IC type ESTL
We will consider the special features of using IC type ESTL on an example of the
series 100. As already mentioned above, ESTL circuits have a negative feed voltage
source of -5.2 volts t 5yb and, because of this, negative voltages of logic levels.
Moreover, ESTL circuits logic levels axe low in absolute value~UBb~x 1 volt and
U~�X ~-1.65 volts). All this does not allow direct connection to inputs and
outputs of IC type FSTL to IC type TTL or the use of MCS structures. For the
mutual interfacing of logics, special circuits of converter 100PU124 and 100PU125
must be used. Ir. wiring appaxatus of IC series 100 (besides IC types 100LP115~
100LP116 and 100LP124) all unused inputs and outputs axe left free.
Un~sed inputs of IC types 100LP11~ and 100LP116 must be connected to a reference
= voltage source (leadout 9 of IC type 100LP115 and leadout 11 of IC type 100LP116)
or to feed voltage source UN~ _-5.2 volts + 5qb. Unused inputs of IC type
100PU124 are connected to feed source U~,,, = 5.0 volts + 5~ through a resistor
rated at 1 kohm. No more than 20 unused inputs ma,y be connected to one resistor.
If it is necessaxy to feed a constant signal 0 to inputs of several IC, it may be
obtained from any logic IC series 100 that forms si~a1 0 with the connected inputs.
The number of loads which may be connected to the output of such an element should
not e~xceed 24.
43
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
1~()It OFH'1('IAI, lJ5E ON1,Y
o> >o 1
tbA p~~ p~ NC 1/ ' tj/1 D' t}A hC �
t~~ .
Of
Z- ~ P t3a P - 3
JO f 1,0
~ tfA A 4 p Z
50 150 150 R~~ UN~,6 -5,6 -5,2 -4,8 -4,4
al
o,f fo of fp
, tbap,tbAP,NC t}AP~tiap,yC
4 tb4D t~'~
bA F
3 0~ 3
1 t~A P l'3A P 2
~ 1
0 40 BO CM,~~3J~ny,B -1.6 -1,2 -1,8 -1,4
- 61 d~
t qiP. taq P. HC
Q~
t~~ p
5
~a
4 faa a
~ ~ ~
-10 0 ZO 40~ 60 BO T, �C
e _
Fig. 3.29. Relationships betxeen dynamic ~,rameters andt resistive load (a~,
- load capacitance (b); voltage feed source (c); bias voltage (d~;
and temperature (e).
1. nanoseconds 3. picofarads
2. ohms
The ESTL microcircuits considered above allow a combination of direct and inverse
outputs into a"wired OR" and a"wired AND" with a combination coefficient Kod ~
~ 4, as well as a combination of a direct output with an inverse one (Fig. 3.30).
The latter combination method makes it possible to receive and transmit signals
from several elements over one common communications line (Fig. 3.31a~.
44
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
X~ n' rs X. ~ n~
X' ~ y x' ~ & o ~ r~ ~ ~i
X3 XJ X3
D= D2 D2
x~ ~ Y~ f ~ Xt ~ ~2
~X - t Y
3
XJ '~S X3 -
a) .
Fig. 3.30. Combination of IC type F~TL outputs into a"wired OR" (a) into a
"wired AND' (b)~a combination of direct and inverse outputs (c).
It should be remembered tha,t as the number of combined outputs is increased, the
levels of output voltage change~ which leads to a reduction in the noise resistance
of the IC. Moreover, in the "wired L~R" operating mode when even one IC is switched
from state 1 to state 0, a negative interference appears at the output of the com-
bined circuits (Fig. 3.31b) which ma,y cause a false operation of the load element.
The amplitude and duration of the interference depends on the length of the com-
munications line that connects the elements in the "wired UR." Taking the above
into account, it is recommended to combine outputs within one board and, if possi-
ble, outputs of IC which axe beside each other. Taking the output from the boaxd
of an IC that does not have an output combination is recommended.
;s `l~ ; - - . _ _ - ~ --y
, X~ ~:1~ , ~ ~ t
~ ? ~
~
~ r- - _ . -
, .
~ ~7 ~ I I.-y I - rf 1 ~~r~ r
ny
. , i f. -_',y
_ ~2~- ~
~ (~i
r
~'Mi `
r f'~
~ ~aM l3) 6~
Fig. 3.31. Circuit for signal transmission f~om several IC type ESTL over one
common communications line (a) and a time diagram (b~
l. UriX~ input voltage 3� Uebix-- ou~tput voltage
2. U~vM interference voltage 4. 2'noM interference time
~5
FOI~ OFFiC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
1~OR OFFI('IAI. USE ONLY
As already mentioned above, ESTL circuits have a fairly high load capacity
(K~,U~ ~ 10) which is due to the low input impedance of the emitter repeaters
with which the keys are equipped and the low values of the input current (less
than 265 microamperes~. Within one board, the load capacity increases to
K pA~ = 20 and for microcircuits 100LL110 and IOOLYelll, designed to operate simul-
taneously on three transmission lines, the load capacity is still higher ( KPQ~ = 30).
It is recommended that the output of trigger circuits be loaded no more tha.n with
6 inputs of IC loads. It is recommended to connect inputs of no more than 16 key-
loads to the output of circuits, combined in a"wired OR." In this case, the re-
duced level of the output voltage and an increase in the propa.gation delay time
- should be taken into account.
When the logic element operat~s with a load resistor rated at 51 ohms (at UcM J-
-2 volts) the delay increase when connecting one inpu~ of the IC load is 0.1 nano-
seconds, wnile the change in the duration of the output signal front for an in-
crease in the load from 1 to 10 inputs does not exceed 0.5 nanoseconds. In all
cases, when determining the allowable number of inputs that ma,y be connected to
the IC output, it is necessaxy to take into account the combination of several in-
puts within these IC. With the direct operation of elements with one another
(over short lines of communications), resistors of vaxious ratings connected to
voltage sources UNn =-5�2 volts or to U~,~y =-2.0 volts may be used in the emitter
circuits of the output repeaters.
The presence in the above-considered F~STL series triggers and logic elements of
various types ma.kes it easy to design typical functional computer units and dis-
crete automatic system devices. Fig. 3.32 shows a 4-stage shift register circuit.
The output part of the circuit is made up of 100TM131 triggers, the parallel data
input circuit is made up of IC type 100L5119, while the output part is a decoder
with two inputs and four outputs ma,de of IC type 100LM105. To increase the number
of register stages~ data is fed to input D_1 from the output of the previous stage
- a.nd to input Dn_4 from the output of the following stage. Depending on the type
of signal, operations, enumerated in Table 3.17~ axe implemented at inputs Sl and
S2 by the circuit.
Synchronous binaxy pulse counter (Fig. 3�33) is ma.de of IC types 100TM131 (D5,
D6, D8.1), 100LS118 (D1...D'+) and 100LM105 (D~). Input Qn_1 implements the caxry
from the previous stage and output Qn~ the caxry to the following stage. The
counter operation is controlled at input 5 of IC100LM105. With 1 at the S input,
the circuit implements the function of a counter. With 0 at the S input, the
circuit operates as four triggers and receives data in inputs DD...D3.
The combined utilization of ~STL and TTL circuits (Fig. 3.34) ma.kes it possible to
design special purpose units. F`i.g. 3.34a shows an indication circuit, designed
with IC type 100PU125 (D1) (series ESTL) and IC type 1.33r~7 (D2) (series TTL~
using the NSM 6,3-20 incandescent lamp as an indicator.
46
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
. ,
~
i~, o
~m ^
O u
~ I o~ ~ a ~
"n~7h~0 n~ w N w~.w O
4 ~ ~ q~ ~
ywW ~~,i ~ ~ a
_ h'o~.a ~'~Q~' DO
. qc H
fJ
n ~ , ~
~ ~ ~
. . MJh~ t~p~~ w ~ w T~
� . q` A
~
- - ~
~
' H
O
O
ri
N
H
~ - - N
~
4D
~-1
. f~l
~
4i
O
~ I m
?
G t~ ~
O + q
io ~ ~ ~
N ~ w
M Q h w w w w w f�~
r.~ h F~ ~
~ hl~'' 4ca vhlc`~'nR f~l~
- b ~ O ~
~ ~
~ ~
~
4i
N ~
~ VI A
^ ~ ~
rn s~n cw a ~ ~ ~ 40 O~
f~ ~
r'~
a" j~ a
~ o
0
. c~ ~
U
; 4-i H
N rn b ~ ~ h ~ O~ O
Q ^ ~ ~ ~
V o h~.~ ~ ~ w ~-I 1~
. v A ~
N ~O ^ ~ ~
`V
q M
J h v1 }a. : ~ y ~
L. ---0~, 40
~
47
FOR OFFICiAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE UNI.Y ,
Table 3. 17
Operations implemented by the four-stage shift register, depending on signals S1
and S2
Inputs Implemented operation
Sl 52
0 0 Blocking
1 0 Shift right
0 1 Shift left
1 1 Da,ta received in inputs D(the cir-
cuit operates as four triggers with
separate inputs and outputs)
Table 3.18
Rated resistance resistors R1 and R2 with parallel ma.tching
P, ohms R1, ohms R2, ohms
50 81 130
75 lzl . 195
10o i62 z6o
150 243 390
Taking into account the high-speed action of the ESTL circuits, special attention
should be given to the arrangment of the communications lines between individual
IC, as well as to boards and units. Circuits types 100LP115 and 100LP116 which
are paraphase signal receivers from a two-wire communications line, were considered
previously. However~ data transfer between individual circuit boards may be im-
plemented by single-phase signals (Fig. 3.34b).
When a single-phase signal is fed from the output of IC series 100 (D1...D3) to
one of the inputs of the IC type, looLP115 (DS...D7~ or 100LP116, a reference
voltage must be fed to the second input, produced in IC type 100LP115 (leadout 9)
or 100 LP116 (leadout 11) located in the board from which the signal is transmitted
Fig. 3.34b). ~e reference voltage source on the transmitting board (DrJ~~ may be
loaded in the receiving boaxd with no more than 10 inputs. ~,ch IC type 100LP115
or 100LP116 may be used as a reference voltage source (D4) when transmitting be-
yond the limits of the board and as a signal receiver from the communications
line (DS...D7). The reference voltage transmission line must be decoupled at the
transmitting and receiving ends by no less than 1000 picofarad capacitors.
Three basic communications methods axe recommended within the limits of one board.
The series method is used for a communications line not over 200 millimeters
48
FOR OFF[CIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
OR-~ c
D3 �
x ~ 3 ' $ D5
s' s r p~ �
1 p 6 - 2
=�5~~~ 6 ~ y ~ .
_ : y ~ 3
~.i; ty 1,~ C T 0~~~ ,
1 12 g /,5'
i-- Ir jL � 15 1I
Jf ~I
~ f2 ~ ~ J4 DB.1 .
~ 5 S T Ona4
I L~r ' 14
y E 2
4 D
R
C 3
~
/1? D4 L S D~ ~ 2
- 1,5 3 f & 5 S 7
t, 2 6�~ ? On�: 5
1 .
4 p 9 f
Iv bl 6~ 9~ S 10
~ L f1 ~ ,
4 9 17 C t,y s f2 ~ f4
ll " I ~ ' & /5 � r~ ~4 13 ~5 �
' 15 1i ~ R
i1 1 l
I 1 t 1~
~ ~ - ~ ,
,
- -
, ~ t .
y,~
j~'~U- ~1-1-Ll-LS-1-f-Ll-' t
' " I - t
,
� -
r'.rj (
J t
v.v~ ~ .
t
~ _
4Rii �
- t
bl
Fig. 3�33� Synchronous binary pulse counter from 0 to 15 (a) and time diagram
of counter operation (b).
1~9
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
I~()N ()1~1~1?tG; corrosions, presence of drops of glue,
tin on the flangeoof the housing on the side of the cover~, as well as defects in
assembly (chip on board glued too high, boaxd bent~ that origina~~e in inaccurate
assembling of IC.
After annealing to stabilize, parameters and sea,ling, IC are subjected~ in turn,
to the effects of the~ high and low values of ambient temperatures to detect a
misma,tch between thermal expansion coefficients of individual IC parts. After
these tests, the IC must preserve their external appearance and the electrical
parameters.
The mechanical integrity of the design is checked by testing on a centrifuge. The
microcircuits are attached to the housing in a special device and are subjected to
the effect of linear loads which produce forces along the vertical IC axis corre-
sponding to accelerations of 10,000 g for hybrid, and 20,000 g for semiconductor
microcircircuits. These forces axe usua.lly sufficient to det.ect defects of welded
connections of internal leadouts and poorly attached chips.
In testing IC, devices with improper seals axe re,jected.The widest failure mechanism
- in such IC is due to the moist air penetrating the housing and water vapor con-
densing causing corrosion of the metal coating. F1~rther electrical tests are ma.de
_ in which IC not corresponding to technical norm documentation (INTD~ are rejected.
After that, IC which are to meet higher reliability requirements are subjected to
special electrical thermal tests which are tested until they fail. This type of
- testing shows defects not detected in visual inspection very effectively. Typical
defects which may be overlooked in visual inspection (but may be detected in ther-
mal current tests) are scratches on the metal coating, thinner metal coating on
the oxidation treads and microholes in the oxide under the metal-coated tracks.
These defects may also include poor electrical contacts and surface contaminations
that cause instability of IC parameters
The final type of test is an all-around investigation of basic IC electricl param-
eters under normal climatic conditions~ as well as at the upper and lower t~alues
of the temperature in the specification. Electricaltests axe also ma.de at a com-
bination of electrical modes (input signals, loads, feed voltages~ which are the
worst for the given type of test within the limits of specifications. Rejection
tests axe completed by checking commercial type IC~ with special attention being
given to inspecting the quality of welded and soldered joints, glass in the metal
joints, the labeling and integrity of the coatings of the leadouts and the housings.
By analyzing typical experimetal data that chaxacterize the effectiveness of rejec-
tion tests in the process of production (Table 5.5), it is possible to conclude
that the complex of rejection tests makes it possible to detect a considerable num-
ber (including 4~i.2~ of the number tested) of potentially unreliable IC and thus
raise considerably the quality of IC lots supplied for use in the REA.
61
FOR OFFICIAL L1SE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
Table 5�5
Effectiveness of rejection tests
Type of test Shaxe of Basic types of defects and their
defective IC shaxe~ ~
Visual inspection of 5 Absence (unwelded) c~onnection 26.4
quality of connecting Repeated thermocompr~ssion 17.0
leadouts Shift of leadout beyond area of contact
pa,d 13.6
Pinched leadout 10.6
Shift of welded joints on the crosspieces
8.0
Others 24.4
Visual inspection of 3.7 Splits 10.7
chips Photolithography defects 10.7
fJthers 29
Annealing for
stabilizing paxameters~
before sealing 0.0 -
after sealing 0.0 -
Cyclic effect 0.0 -
of temperature
Linear loads 0.0 -
Leak tests~
sma,ll leaks 7.0 Not in accordance with norm
medium and large 1.9 same
- leaks
Monitoring electrical 7.4 -
parameters at norma,l
conditions
IIectrical thermal 0.7 -
aging
II.ectrical testst
check of static paxam- 0.6 -
eters at higher temper-
ature
Check of static param- 4.7 _
eters at lower tempera-
- tures
Check of dynamic 1.6 -
paxameters 10.6 Splits and cracks in housing ~.4
Inspection of exterior Twisted leadouts 16.0
of IC
Labeling defects 9.4
Damaged coa.tings 20.2
62
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
� FOR OFFICIAL U'~E ONLY
_ h se ~
o .
a . .
~ 40 ~
o ~
~ ;V . _
V
~
~ _
~
~ SO ' �
> 1 . 3 6
~5) _
A B A B A B
/liiamoi 6narru /1pu60pa~
6 (7) ~ (8)
Fig. 5.2. Distribution of IC failures in production and testing of apparatusi
l. failures of printed boaxds B. stage when product is released
to quality control department
2. failures in units
3. failures in devices 5. f of total number of failures
4. total number of failures
A. shop test stage 6. circuit boards
7. units
8. devices
S
Inasmuch as rejection tests using above-cited methods axe compulsory for all
manufccturing plants, the IC quality of vaxious suppliers is equa,lized to a consid-
erable extent. Now IC that have passed through one and the same "rejection bar-
rier" at various plants have a similar quality level.
5.4 Effect of bcternal Factors on Appasatus Prod.uction
A typical technological process of apparatus manufacture using sma.ll-scale mecha-
nization tools is shown in Fig. 5�3�
63
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
FOR OETICIAI. USE ONI..Y
z - F z . ~ z ~a t ~z>~ .
~ 4,~ 5,6,~ L 5 I 1>,5 95.16
J
i 1 9 ,i 1 10 Z 8 Z 12,1 >4
- ~ 5 19.5 5 5, 6, 7 >6, 20, 2>, 22
L
;
>3 ~4 24 s~ 7.7 >4~ 30 14~ 34 35
>6, 23 L_ 25,16~ ~28,1 � J 3>, 25, 1819
31, 33, 2Z '
~ � al . . .
1 9 1 3 1 8 1 12 >4 11
5 4,5 5,6,7 5 >8,70,2f,Z2
' 14 36,1 14 74 14 27 14 30 14 34 35
75,16,13 25,16 18 29 3~ ZS 1819
' 32;33,1Z '
61 ~ ~
Fig. 5.3. Technological route of passage of IC circuit in manufacturing appaxatus
in housings types 1 and 3(a) and housings type 4(b)i
1. IC 1~9. die forming and trimming to size
2. technological packing 20. spatula
_ 3. f'orming and trimmin.g leadouts 21. device for gluing
4~. die for forming and trimming the 22. thermostat
size .
5. magnetic vacuum or optic tweezers 23. semiautomatic soldering device
6. crucible with thermal regulator 2~. cleaning flux from boax3s
7. device for tinning 25. brush
8. tinning leadouts 26. vat
27. regul~tion
9. ma,king up sets 28. control panels~ devices
10. trimming inactive leadouts 29. hot-cold chamber
11. die with keying device 30. protection against moisture
12. installation 31. paint and varnish
13. soldering 32. centrifuge
14~. board 33. pulverizer
6~.
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
Key to Fig. 5.3. continued ~
15. device for soldering IC without 34. functioning and control check
gluing
16. electric soldering device single-core 35. assembly unit
17, gluing 36, fluxing
18. injector
The sequence of operations and transfers indicated in the technolqgical routes of
circuits may change depending on the special design features of the assembly units
and the specifics of production. In passing over these routes~ the IC axe subjected
to the effects of various external factorst mechanical, temperature, chemical and
electrical (Table 5.6).
Mechanical forces axe applied to IC in assembly operations, forming and trimming
leadouts~ and mounting and gluing the IC to the printed. circuit boaxd. Forces
acting on leadouts and their insulation may dama.ge the sealing of the housing.
Temperature effects axe related to the operations of tinning, soldering and dis-
mantling. In these operations, heat pa,sses through the leadouts to the chip or
substrate and produces heating of the structural elements of the IC. Chemicals
affect the plating material of the housings and the IC labeling when fluxing,
cleaning the flwc off the printed circuit boaxds, applyir.g moisture protection and
dismantling. And, finally, electrical effects axe rela,ted to discharges of static
electricity through the IC. This effect also takes place at all technological
operations if no special measures axe taken to reduce and remove static electricity
charges from production areas.
As may be seen from Table 5.6, IC are subjected many times~ although to a different
degree, to effects of external factors in the environment. The most dangerous of
them axe thP actions of the operator because they depend to the greatest degree on
the individual prepaxation of the operator and they axe the most difiic~lt to con-
trol.
In the process of appaxatus production, if the modes and equipment quality do not
correspond to the problem of producing highly reliable apparatus, vaxious kinds of
IC defects and failutes ma.y originate (Table 5.7).
5.~ Forming and Trimming Leadouts
One basic requirement that the IC housing must satisfy is the preservation within
it of comparatively dry air during its entire service life. The gresence within
the housing of moisture, chemically active and electrically incompa,tible with semi-
conductor~ substances facilitate the origination of sudden, as well as gradual,
failures. They happen due to the corrosion of inetals and their alloys and inter-
contact connections, and the deterioration of electrical characteristics caused by
changes in the surface and volumetric conductivities and ionic contamination.
- Under norma.l conditions, any surface of a substance is covered by a thin moisture
of from 0.01 to 0.001 micrometers. Due to the sma,ll values of a molecule of
65
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
Table 5.6
_ EScternal factors acting on ZC in the grocess of apparatus assembly
Source of action Assembly Forming antl Fluxing and Mounting Fluxing
trimming tinning ~d gluing and
leadouts wires I~ on cir- Solderin~
cuit board
Dperator E, M E E E~M E
Material covers of E - - E E
working positions
and rooms
Packing E,M E,M E,M E.M -
Assembly tools E,M E~M E,M,T E,M E,M~T
Technological - M,E E M -
~uipment
Flux - - Kh - ~
Solder - - T - T
Washing liquid - - _ _ _
Varnish solvent - - _ _ _
II~uipment and
materials for
moisture protection - - _ _ _
Cleaning Regula- Moisture F~Znction- Disassembly
off flux tion protection in~ test
CJperat or E E E ~ E, M
Material covers of - - _ _ E
working positions
a.nd roams
= Packing - - - - ~ M
~
Assembly tools - - - - E,M,T
_ Technological M,E E E E -
eq uipment
Fl ux _ _ _ _ ~
Solder _ _ _ _ T
66
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
)NLY
Table 5.6 continued
EScternal factors acting on IC in the process of apparatus assembly
~ource of action Cleaning Regula- Moisture FLinction- Disassemblv
off flux tion Protection in~ test
Washing liquid Kh - - - _
Varnish solvent - - _ _ ~
D~uipment and
materials for
moisture protection - E,M - -
Notei designations of actions~ E-- electrical; Kh chemical; T-- temperature;
- M mechanical.
2.7x10-10 meters and the low viscosity of water~ moisture is able to penetrate
even the intermolecular spaces of complex inorganic compounris. In this case,
mechanical destr.uction of materials occurs, along with a change in the electrical
properties of the surfaces, corrosion of inetals and their alloys. To avoid this,
the sealing of microcircuit housings is usually done in an atmosphere of dxy
nitrogen in which the xater content does not exceed 10 parts per million.
Metals, glass and ceramics uaed in manufacturing IC housings axe practically im-
- penetrable to gas and moisture. Most plastics axe hygroscopic to some degree. To
preserve a dry inert atmosphere within the housing, the seams between unlike metals
should be ma.ximally sealed. According to the adopted norms, a good soldered seal
passes not over 1 cm3 of gaseous helium at a pressure difference of 1 atmosphere
in 30 years (practically, t~is means absolt~te air impenetrability).
Metals axe joined to metals by soldering with soft or brazing solders, hot or cold
welding or their combination. Soldering of glass to glass or ceramics is done by
melting them at high te~peratures, or gluing with low-melting glass. Sealing a
metal-gJ.ass sea.m which insulates the leadouts electrically from the IC housing is
a complex technical problem. This is because most of the common glass has low
coefficients of linear expansion and heat conductivity, while most metals conduct
heat well and have high linear expansion coefficient. The differerlce in the speeds
of the heating and cooling of glass and metal parts og soldered joints, and the
difference in the lineax expansion coefficients lea.ds to mechanical stresses and
dama.ge to the joints. As fax as IC operatng conditions are concerned, glas~ and
metal axe considered compatible if the difference in their lineax expansion coeffi-
cients do not exceed 4xlOr7 pex centigrade degrees ~4~.
_ Usually, in sealing IC leadouts where they.come out from the housing, crystalliza-
ble glass solders (for example, of the "Piroceram" type) axe used. The technology
of obtaining such a sealed joint by soldering is based on the formation of a glass-
ceramic joint with the crystallization of boron lead-zinc glass. In this method!
67
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE QNLY
- the glass is melted by the heat and spreads thuroughly, wetting the joi.ned sur-
faces of the ceranics, glass and metals like the metallic soldex wets and joins
metal paxts in co;nmon soldering~.
When the soldered glass is heated further "devi~rificaticn" occurs and centers
and crystallization of the seam material are produced. The sizes of the crystals
formed are proportional t~ the time and temperature o.f the process. The s~rength
of such a sealing seam is determined by its crystalline structure and is twice
that of a seam from amorphous glass. Moreover, at mechanical loads, microscopic
cracks are formed in joints with noncrystallized glass which create paths for mois-
ture penetration into the housing through the glass. In crystallizable glass, how-
- ever, the microscopic cracks end at the crystals and do not pa,ss through the joint.
By regulating the content of the crystalline phase of the seam material, it is pos-
sible to chax~ge its temperature linear expansion coefficient (TKR) from 40x10-7
_ to 120x10-7 per degree centigrade which agrees well with the TKR values for a great
number of glass, ceramics and meta,ls used to make housing parts.
The Kovar alloy (iroi~, nickel, and cobalt) or the Si.lmet alloy (iron, nickel and
chromium) are most frequently used for IC leadouts. These alloys have low TICR ~
values that agree well in the working and technological temperature range with the
expansion coefficients of most glass (the TKR for Kovar is 47x10-7 per degree
cPntigrade and for glass 46x10-7 per degree centigrade).
An essential special feature of most types of IC housings is that part of the lead-
out le~gth is under the cover of glass (or ceramics~. This cover should not be
- dama.ged in forming the leadouts.
- Contradictory demands axe made on the IC housing. Thus, the housing must be suffi-
ciently strong mecl:anically to withstand loads originating in the appaxatus pro-
duction and opsration and, at the same time~ it must be as small as possible with
a shape permitting the grea+.est der~sity of REA assembly. This contradiction must
be taken into account, providing a romplex of technical mea,sures for pxeserving
the reliability of the microcircuits in designing and producing the appara-
tus .
.Ln implementing the technological operations on prepaxing the IC for assembling on
the printed circuit boaxd (straightening, f'orming a.~d t..rimming leadouts~~ the lead-
- outs are subjected to stretching, bending and compression. In this case, the
- stretching force P1 is applied to the most sensitive mechaniral forces zone of the
housing the seal . inlet (Fig. 5,4). If the stretching fores is excessive,
- cracks may originate in the glass or cera~r~ics of the housing where the leadouts pass
- the housin~ leading to an immediate, or what is worse, a subsequent loss of housing
seal.
The die design for forming and trimming leadouts (~'ig. 5.5~ must insure the produc-
tian of independent and sequential forces for clamping P2~ forming P3 and trimming
P~. 'Dlie values of these forces a.re selected so that they insure the integrity of
leaduut plating, apply the minimal stretching force along the leadout axis and
obtain a given configuration. In forming and trimm;.ng the IC leadout~, it is
68 ~
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
Table 5.7
Possible types of IC failures under various effects
Oject of Technological Effect factor Type of possible vio].ation
effec~ operation paxameter and failures
Mechanical
IC leadouts Straighten, Pulling force Insulator cracking, causing
= formin~ a.nd Clamping force loss of. housing seal; leadout
trimming deformation (pinching, twisting,
breakage)
Insulator, Mounting Static Insulator cracking, causing ~
housing base, and gluing IC force of los~ of housing seal. Deforma,-
flexible con- to the board, clamping tion of housing bottom causing
_ nections, chip dismantling housing to cracking and separation of chip,
or substrate board substrate and breakage of flex-
ible conductors. Destruction
of riousing
Tempera,ture
Leadout coating Input control Force of Dents and scratches on leadouts
straightening, clamping lead- leading to corrosion
forming and out
trimming
Leadout insula- Tinning~ sol- Overheating Insulation cracking, causing
tor, chip, sug- dering, dis- the leadout loss of housing seal. Peeling
strate, active mantling, or solder ~ of substrate or chip ( in case
elemsnts and drying they axe glued) from the mount-
_ flexible lead- in~ surface of the housing,
outs causing breakage of leadouts
Increased Thpxmal deforma,tion of protective
operating coatings of chips, causing
temperature breakage of flexible leadouts
Chemical
Coating and Fluxing, Chemical Corrosior~ of coating or basic
labeling cleaning, activity material of leadouts and hous-
moisture-proof- ing, and destruction of labeling
ing, disman- designations and paint-varnish
' tling coa,tings
69
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPR~VED F~R RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
FOR OFF(C'[AL USN: ONI.Y
Table 5.7 contintaed
Possible types of IC failures under vaxious effects
- Object of Technological Effect factor Typ~ of possible violation and
effect operation paxameter failures
Electrical
Passive and All tech- Electrical Puncture of oxide, degra.da.tion
active IC nological chaxge of IC paxameters due to punc-
elements, metal operations (number of ture in the semiconductor
co.ating, p-n effects, structure
_ junctions, capacitance
protective oxide and resist-
ance in the
- discharge
circuit~voltage
difference)
permitted to leave tool traces (prints) on the IC leadouts, tha,t do not damage the
plating on the leadouts. Table 5.8 shows allowable values of clamping and forming
forces at which dama.ge of plating does not lead to corrosion. Depending upon the
cross section of the IC leadouts, the value of stretching force P1 should not ex-
ceed the values st~own in Table 5~9�
Table 5.8
Allowable forces of forming and clamping
S~~ uence of force Cross section of Clampin~ Formin~
actions housing leadouts, N microPa N MicroPa
mm
Weak traces of working O.1x0.3 1~.7 30.~ 18.6 29.4
parts of the die on the 0.15x0.45 19.6 30,4 27.4 29,4~
surface of leadouts in
the form of compacting
the coating
Maximum allowable traces O.1x0.3 17.6 39.2 2~.5 39�2
of die parts on leadout 0.15x0.45 27.4~ 39�2 37�2 39.2
coating
Impermissible dam~.ge of 0,1 x 0.3 21.6 48,0 31,3 4g,p
leadout coating 0.15x0.4~ 32.3 48.0 46.0 49.0
in the form of dents
70
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
- The die design should profice rigid fastening of each IC leadout outside the glass
or cerma.ics buildup. A leadout section of 1 mm from the body of the housing should
not be subjected to bending or twisting deforma,tions. Allowable bending radii
should be ma.intained in forming. Forming IC leadouts of a rectangular cross section
should be done with a bend radius of not less than two leadout thicIrnesses, while
leadouts with a round cross section with a radius not less than two diameters.
Table 5.9
Maximum values of stretching forces
Leadout cross section, mm 5tretching force per one leadout~ Ne~on
Up t o O l 0. 24~5
_ Above 0.1 to 0.2 0.49
Above 0.2 to 0.5 9�$
Above 05 to 2.0 19.6
The IC leadouts inside the housing or leadouts not used in the circuit of its ap-
plication and not affecting the working capacity of the IC, may be trimmed 1.0 mm
from the housing body; however~ it should be taken into account that a considerable
paxt of the heat is removed over IC lea,douts (especially of small sizes~.
In a typically improper design of a technological device, the forma,tion of lead-
outs of type 4 housings (Fig. 5.6b), a gap (not less than 0.5 mm from the body of
the housing), necessaxy to preserve the integrity of the ceramics was not left.
A die of such design may da,mage the housing seal of the IC.
Fig. 5.7 shows another typica]_ assembly error. We will assume that the forming of
IC leadouts, intended for installation on a multilayer printed circuit boaxd with
open contact pads, was done at the depth of the second-third layer (Fig. 5.7a~.
Actually, however, it was necessasy to solder them to other layers. In assembly,
the leadouts were bent manua.lly at the inlet of the seal (the bend angle in the
vertical plane may reach + 60~~. Straightening the leadouts made without rigid
fastening of the leadout zone on a section 1 mm from the body of the housing (i.e.,
without using the technological device) ma.y lead to dama.ge of the lea.dout a,t the
housing. With such a method of assembly, the IC may ].ose itfi seal during the con-
sequent a~gchanical forces when operating the apparatus because the deformed lead-
outs axe in a stressed condition (Fig. 5.7b~.
5.6 Tinning and Soldering
In the production of radio electronic apparatus, group methods axe widely used to
implement individual technological operations, for example, tinning IC leadouts by
"dipping into melted solder" or soldering by means of a"wave of solder." These
modes of operations (temperature of the melted solder, contact time between the
solder and the housing leadouts, axea. of the contact zone of the leadout with the
solder), selected without taking into account the heat transfer chaxacteristics of
concrete types of IC housings ma.y lead to a destructive effect of heat shocks on
_ IC.
71
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
1~()R ()l~1~1('1;11. lltil~: ()N1,1'
~l)
~ P~~rQfN
\ ~ \ ~ ~
O, Smax'"
-?ir -
Fig. 5.4~. Direction of stretching force in forming and trimming lea.douts
1. P1 N 0.1 Newton
~ ~l~
~
l~ / P~
~-T _ ' -
~ ~
i
- - - ~
ifs r~~
% �
.i
. - - --i--
t~;, ~ a,
~ . .I~..~~_-~'_~;~ ~ j.
,
~i
ti t': ;i
~,,~'.i--- 2 3 , 4 5 l, yN
l�lnn 5 T,G t-2c ~
f~a �
7U0 - -1 �
~i Z 80 3 ~ . _ p .
~ ~ ~ a~~ ~ :
7~
60
~ /.~i~~'' :2 ~ 2
SO - ~
_ 3-- ' ~ --S '40
_ 3
JO -
2 3~ 4 5 6 t, c 1 2 3 4 5 l, yn
6') .
.1-1nM 3 ~ t-1c ' '
~ �C T � ~ ~ . .
900 - 100 ' ~ ' �f o o 2' � ~
P1 r x^x - -3 . ~ ,
L~~~~J
� � 1 00 ooa 4
90 ~ ~ 4 eo -
- . 3~ .
2
b0 - 60 ~~~~~'~l/
_ ~ o 0 0~ 3 1
~
40 - ~a3' 4 90 q .
i ~ ~ ~ ~
2 3 4 s 6 t,c 1 2 3 9 s l~ha
~
Fig. 5.10. also continued on the next sheet
77
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
r,�~ T�~ o,t-~5) .
>ZO ' r j- frYrY 2 t r 2C "+t"~G ~
'0~ oox
~~0 ' ~ ~ o o ~ ,
80 ~
% x
8~ / ~ ~~x x .
' ' 6~ - x s
~'0 ~ 6~ ~
2 a ~ s 6 t,c d~ 2 ~ 6 G,~~1 .
Fig. 5.10. (continued from previous sheet) Relationship between temperature of
IC elements in the process of tinning and tinning time (t) and the
- distance (1) between the level of solder for housings series 217 (a),
106 (b), 218 (c) and 122 (d). The numbers on the curves correspond
to the points of the IC elements at which the measurement is ma,de;
solder temperature is 260 + SoC.
5. t= 2 seconds 6. t, seconds
In tinning, the solder should not touch the seal inlets of the housing. The sol-
der should not fall on glass or ceramic parts of the IC housing. The boundaxy of
solder flowing on leadouts should be no closer than 1 mm to the body of the hous-
ing (Fig. 5._lla); however, some nonuniformity of tinning along the length of the
leadout is allowed. The minimum length of the tinning section along the leadout
length from its end must be no less than 0.65m~ (jig. s.llb), but "icicles" on
the ends of IC leadouts are permitted (Fig. .llc .
It is necessary to make sure that connections axe not formed between the leadouts
and the soldering surface should be continuous without cracks, pores and untinned
sections (Fig. 5.lld).
D~uipment used for tinning must insure the setting and measuring of the tempera-
ture with an error no greater than t SoC.
The quality of soldered connections should be determined by the following criteria~
the soldered surface should have a light or mat finish without daxk spots and
foreign inclusions. The shape of the soldered connections must have concave fil-
lets of solder along the seam (without an excess of solder~. The contours of ~he
leadouts should come through the solder. In soldering IC housings with planar
leadouts the following is permitted~ a flooding form of soldering in which con-
- tours of individual IC leadouts axe fully hidden under the solder on the soldered
side of a connection (Fig. 5.lle, f), partially coveri~g the surface of the con-
tact pad with solder along the soldering perimeter, but in no more than two places,
78
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
~
not exceeding 15f of the total area (Fig. 5.llg), solder bi~s of conical shape
(Fig. 5.llh) and rounded shaF~ (Fig. 5.lli) where the soldering tool is removed,
a small shift of the lea.dout within the contact pa,d (Fig. 5.llj~ and the sprea.d
of solder (only within the boundaxies of the leadout length~ suitable for wiring).
~ ~ ~
n
2 Z T
~ ~ / N . ~ `
~
^ In~
6~Kd ~ ~7)
Nen~nyareHN6ia ,
_ yvacmaK
a1 , 6l c~ ~d~ .
1 ~ ~
5 5
5 3
/3 , 3 q
4 f
e) . ~ .
~ � 'S �
~ %5 3 .
3 y
~
h i J~ .
Fig. 5.11. bcamples of tinning and soldering leadouts of a planax housingr
a-- zone of solder fZow; b-- allowable nonuniformity of tinning;
~ c-- presence of "icicles'.'; d-- nonuniform tinning and false connec-
tions; e, f-- flooding form of soldering; g-- pa,rtial tinning of con-
tact pa,d; h, i-- conical shape solder beads; j-- sma.ll shift of
lea.douts; 1-- leadout; 2-- housing; 3-- contact pad; 4--printed
circuit board; 5-- solder; 6-- connection; 7-- untinned section
" When soldering IC leadouts into metal-coated holes, the soldered connections must
be accord.ing to the sketches shown in Fig. 5.12a-d. The solder on the side of the
housings should not spread beyond the boundaxies of the contact pads. The leadout
end may be untinned. The metal-coated wiring holes must be filled with solder to
a height of not less than 2~3 of the thicImess of the board. The correction of
defective connections from the side of the IC mounting on the board is not per-
mitted.
79
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000400440032-8
1~OR (11~1~1('L~I, IItiIC f)NI.Y
- 1 2 3 , ,
~ ~ ~ I I '
~
y'~ i~4 b! C~ ~ T~y d~ ~
a,
~
~ J ; ,
Y "
/ i .
4 1 3 4 1 3 g~
e) f)
Fib, 5,12. Examples of soldering housings with plug-coupler leadoutst
a, b, c, d-- soldering in metal-coated holes; e, f, g-- soldering
in nonmetal-coated holes; 1-- leadout; 2-- metal-coated hole;
3-- printed circuit boaxd; 4-- solder; 5-- cavity in solder;
6-- contact pad; 7-- end not tinned.
When soldering IC leadouts to contact pa.ds of printed circuit boaxds with holes
not coated with metal~ the soldered connection must be ma.de according to the sketch
(Fig. 5.12e-g). The spreading of the solder along the IC leadouts should not re-
duce the minimum distance from the nousing to the soldering point, i.e., it should
- be within the zone suitable for the wiring shown in the specification. There need
be no solder at the ends of the leadouts.
_ The equipment and fixtures used in soldering must provide the following; automatic
ma.intenance and con+rol of the melted solder temperature with an accuracy of � 5�C
- when implementing the "soldering wave" operation; ma.intenance and periodic control
(every 1 to 2 hours) of the temperature of the soldering bit with an accuracy of
~ 5�C in the individual method of soldering> control of the time the IC leadouts
are in contact with the soldering bit or with the molten solder in group soldering;
_ also control of the distance from the housing body to the boundary of the solder
:~lon~; the leng-th of the leadout. The soldering bit must be gounded (the gr.ound re-
.,ist;3,nce should be no greater than 5 ohms). Table 5.10 shows the recommended modes
- of TC soldering using single-bit and group raethod.s.
80
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400044432-8
FOR OFFICIAI. USE ONLY
Table 5.10
Recommended IC soldering mode
Paxameter Soldering IC with Soldering .IC with
planax leadouts ~lu~-coupler leadouts
1-bit group method 1-bit group method
method method
Max. temperature of solder- 265 - 280 -
r ing iron core, ~C
Max. contact time 3�~ - 3.0 -
_ of each leadout, sec-
onds
Min. time interval 3.0 - 3.0 -
between soldering of
adjacent leadouts~
seconds
Ma,x. temperature of molten - 265 - 265
solder, ~C
Max. contact time - 2.0 - 3.0
of each leadout with
solder
Min. distance from 1.0 1.0 1.0 1.0
_ housing to solder along
leadout, mm
Min. time between 5.0 ~.0 5�Q 5�Q
two repeated sc~derings
of same leadouts, min.
5.~. IC Assembly on Printed Circuit Boards
The folloxing axe the design features of IC housingso the presence of seal inlets
and sealing seams, and a relatively "thin" housing base (0.1..00.2 thick), to which
are fastened the substrates or the chip, determine a whole number of specific re-
_ quirements which must be implemented in assembling IC on printed circuit boaxds.
All precautionary measures, in this ca,se~ axe reduced to protecting th~ IC housing
from impermissible deformations.
81
~ FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
I~Oit OF'F((7A1. USE ONI.Y
On one hand, the assembly method must provide mechanical strength that would guar-
antee resistance to mechanical loads expected in operation but, on the other hand,
"rigid" attachment of the housing is impermissible t+ecause the deforma,tion of the
printed circuit board (if its deflecti.on is even several tenths of a millimeter~
ma,y result either in the cracking of the sealing joints of the housing, or in the
deformation of the bottom and the rupture of the substrate or chip.
In most cases of IC application~ mechanical stability is insured only by sol3ering
all leadouts to contact pads. The necessity and methods for additional fastening
of the IC to the board are determined by the rigidity of the operating conditions
of the apparatus, as well as the weight and size of the IC nousings.
Tfie design of the appaxatus must insure efficient removal of heat by air convect~.on
and heat-removing metal buses. The convection is nrovided by using housings with the
ma.ximum permissible gaps betweEn the plane of the boaxd a,nd the bottom of the hous-
ing. The housing arrangement on the printed circuit boaxd must provide the possi-
~ bility of coating it with moisture-protective varnish without having it fall into
places that should not be coated, and have free access for dismantling any IC.
Taking into account the necessity of przserving the integrity of the housing and
to pz�ovide for heat removal, recommendations axe given below for using vaxious
types of IC.
~ /lpa,rnadti~
a~ ai ~O`~ .
~ /1pQn,~adKa
~1~
d~ b e f )
~ig. 5,13, Variations of mounting vaxious housings on the print circuit board with
metal-coated holess
_ a,b housings with plug-coupler pins without additional fastening;
_ c,d housing with plug-coupler pins with additional gastening;
e-- plastic housing; f-- ~ylindxical housing without additional
fastening; g-- cylindrical housing with an electric insulation spacer
1. Space r
82
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
~
I~'ig. ~.13u~b ~tiow5 variations of mounting housings with plug-coupler pin leadouts
(housings 151.15-4 and 151.15-6). These housings axe mounted in metal-coated holes.
The IC do not have leadouts. The gap, equal to 1- 0.5 mm, is chosen to insure
IC stability in the entire range of inechanical loads and the preservation of the
integrity of the housing (at sma,ller gaps, it is possible to damage the seal inlet
of inetal-glass housings due to the therma.l effect of soldering~.
IC in housings 151.15-2, 151.~5-3 (~g. 5.13~) and "Aktsiya" (Fig. 5.13d) require
additional fastenings. IC in housings 151.15-2 and 151.15-3 axe glued ta insula-
tion spacers, for example, made of D6V-2-R-2M (GC6T 17~78-72) or AG-4- tG06T 10087-62).
The spacers must be fastened rigidly to the printeci circuit boaxd. In choosing the
dimensions of the insulation spa,cers, it is necessaxy that they be as close as possi-
ble to the area of the IC housing base and that the integrity of the seal inlet
= be preserved. The IC in the "Aktsiya" housing (Fig. 5.13d~ is mounted against an
- LN cement, placed along the perimeter. Cover should be provided with a two-sided
arrangement of conductors in the board under the electric insulation of the IC
housings.
IC in housings 201.14-1 are mounted on boaxds with a single-side or a two-sided
arrangement of printed conductors into metal-coated holes with a gap insured by
the design of the leadout (Fig. 5.13e). Fir. 5.13f,g shows variations of mounting
IC with housings 301.8-1~ 30?.8-2 and 301.12-1 with formed leadouts. They axe
_ mounted with a gap of 3+ ~.5 ~(Fig. 5.13f~. If the appaxatus is subjected to
_ higher mechanical forces in operation, rigid spacers of electrical insulation mate-
rial must be used. The spa.cer should be glued to the boaxd and the base (to the
bottom) of the IC (Fig. 5.13g). The design of the spa,cer must also insure the
integrity of the seal inlets of the microcircuit. IC with cylindrical housings
without leadouts are mounted onto metal-coated holes with a 1-~0.5 mm gap.
_ ~T~
" Ur 61 C~
Fig. 5.14. Variations of mounting planax housings~
a-- against the printed board; b-- with gap; c-- against a spa,cer
IC in housings 401.14-1 and 401.14-2 with shaped lea,douts may be mounted on the
boaxds with a single-eide or a two-sided arrangement of printed conductors by the
following methodss against the printed board or on a spa.cer (Fig. 15.14a,c~ or
with a gap of up to 0.3 mm(Fig.15.14b). In this case, the additional fastening is
provided by coating with varnish. The gap ma.y be increased to 0.7 mm~ but then
- the IC housing must be fastened additionally to the boaxd by glue.
Planar housings must be glued to the entire plane of the housing base. The thick-
' ness of the seam is determined by the chosen vaxiation of forming the leadouts
(the distance from the plane of the IC base to the boaxd~~ but the gaps between the
IC a.nd the boaxd must all be filled with glue. ilhen IC axe mounted on planax
83
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OF'FI('lAl, l1SE (1NLY
~l1/.J yN-131 !2~ '
~~fr,, t r
r,n,.,. :
T
171
~IN 9P-ZJ>
~
,P�~^j~
6~ -
_ Fig. 5.15. bcample ~f proper (a) and improper (b) mounting of a planar housing on
a printed circuit
l. IN 2. UR-231
housings a shift of the free ends of the leadouts in the horizontal plane is per-
mitted within t 0.2 mm for ma.tching with the contact pa,d,s. F~ee ends of leadouts
- ma.y be shifted within + 0.4 mm in the vertical plane from the leadout position af-
ter forming.
The use of glues VK-9(ShehI0.026.400TU) or AK-20 (TU 6-lc)-1293-72), as well as
cement LN (TU MKP. 3052-55) to glue IC to printed boards is recommended. The dry-
ing temperature of materials used for factening IC to the boaxd should not exceed
the permissible temperature for opera~in~ IC. The recommended drying temperature
is 65 � S~C. In gluing IC to the printed board, the squeezing force should not
exceed 0.08 microPa. It is not permissible to glue IC with glue or cement applied
at individual points on bases or at the ends of the housings.
Fig. 15b shows an impermissible variation of IC mounting which is glued to the end
of' the housing (thia may be done for simpZifying the disma,ntling of IC~. In this
method, the gap between the bottom of the IC and the boaxd is partially filled
with cement. In implementing the moisture protection operation, UR-231 varnish may
get into the gap which~ by polymerization, may be able to cause the deformation of
the bottom of the housing (0.1...0.15 mm thick), the ungluing of the chip or break-
age of the internal connections of the IC. In all cases of installation of IC on
printed circuit boards, no force should be applied that leads to the deforma.tion of
the housing of the IC.
84
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000400440032-8
FOR OFFI('IAI. USE ONLY
5�8. tC protection Against Electrical ~:ffects
The degree of integration of the IC (i.e., the density of the grouping of elements
on one wafer) is increasing with time because of the development of a technology
that ma.kes it possible to reduce the dimensions of the elements, as well as those
axeas by means of which the elements are electrically insulated from each other on
the IC wafer. Such an increase in the density of the elements on the surface of
the wafer makes it possible to improve the electrical and functional parameters of
the IC~ but is accompanied by a reduction in allowable electrical loads, and in-
creases the sensitivity of the microcircults to static electricity dischaxges.
Table 5.11 shows comparative typical characteristics of transistors manufactured
by different technological processes.
Table 5.11
Some paxameters of various designs of transistors
Technical characteristics Planar epitaxial "Izoplanar-1" "Izoplanax3I"
technolo~y technolo~y technolo~.y
Dimensions of emitter 25x38 jx25 2.~x12.5
axea, micrometer
Breakdown voltage 23 7 5
emitter-collector, volts
Breakdown voltage 55 22 14
collector-base, volts
Actually, an analysis of IC that failed in the process of production indicates that
the cause of failures of up to 40 to 50f of such IC is electrical overload.
Tn dama,ged IC there is detected a deterioration of the steepness of the volt-ampere
slope or a complete breakdown of the p-n junction although there are no changes in
the metal coating visible under a microscope. ~3nitter junctions are dama.ged more
frequently than others. F~cternally the defect is manifested in that the value of
= the reverse current increases by several orders of magnitude, while the current
amplification coefficient decreases essentially (by 70qb). In this case, the elec-
trical overloads cause irreversible changes in the p-n junction structures leading
to the deterioration of the efficiency of the emitter. A typical volt-ampere chax-
acteristic of the junction for a reverse bias is shoWn in Fig. 5.1'6. The emitter
current (curve 2) is almost linear which may be due ~ the appeaxance of an ohmic
shunt on the surface, or in the volume of the p-ri junction.
A partial or complete burn-out of the metal coating and the forma,tion of jumpers
_ between adjacent tracks may occur, along with highly visible traces of p-n junctions
breakdowns on the surface or under the pa.ssivating layer.
85
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
1~()R ()I~I~1('IAI. Iltil~: ()NI,Y
~36a.nK~S) 4
~ 3
Q~
O,OPf
2
1
~ ~ z a,,B (6)
Fig. 5.16. Volt-ampere chaxactsristics of emitter junctions of two transistors
without housingsi
1,2 transistors in working order; 3,4 transistors after a 600-volt
di~chaxge through the emitter junction in the reverse direction;
5 microamperes; 6 volts
IC that failed due to electrical overloads are characterized by the meltin~; and
spattering of aluminum (when boiling) and the formation of short-circuited adjacent
sections of the metal coating. The burn-outs occur most frequently at the "weak-
est" points of the current-carrying tracks that have local thinning (at the "steps"
of the oxide~.
One cause of IC failures of the above-indicated +.ypes ma.y be the effect of dis-
charges of static electricity originating during various technological aperations
due to the wide use, under production conditions, of strongly electrifiable syn-
thetic and other insulation ma.terials. Moreover, due to poor grounding of device
housings and technological tools, considerable network noise inductions ma.y occur.
The origination of static charges is due to several generating mechanisms and the
value of these charges depends on many factors. The values of static voltages
(U~) on the surface of the dielectric, independently of the mechanism of their
generation are always proportional to the specific surface resistance of the (PS
This can easily be seen by analyzing the experimental data on the value of static
voltages originating on the surface of several ma,terials at a relative humidity of
50% (Table 5.12)~
86
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
Fig. 5.17 shows the relationship between the static voltages and the relative air
humidity of two types of ma,terial used widely for the special working clothes of
production personnel Lavsan and cotton cloth. The rela,tive humidity of the air
is used as the parameter when measuring the voltages. In analyzing these relation-
ships, it should be noted that static potentials at low relative humidity of the
air (40 to 50~) rzach 3 to 10 kilovolts. The static voltage on La.vsan is higher
than on cotton cloth and depends strongly on the relative himidity of the air
(at 65~ humidity the voltage on cotton is zero, while on Lavsan, it exceeds 3 kil-
volts).
In developing measures to protect IC from the effect of static electricity dis-
charges, it i_s necessary to take into account also the ability of insulating mate-
rials to retain charges accumulated on their surfaces for a cextain time. As the
chaxge retention time is assumed the time ('C y) during which the accumulated
static voltage reduces to a half or a third.
2'y ma.y be measured as follows~ the surface of the tested material is chaxged (for
example, by rubbing) to a certain volta~e and a flat metallic contact electrod.e is
applied to the surface of the material. The electrode is connected to a type 5-95
static voltmeter and then the time it takes for the voltage to drop to half or a
third is recorded. The charge retention time is proportional to the specific sur-
face resistance of the materials exactly the same as the values of the static volt-
ages.
Table 5.12.
Static voltages and surface resistance of various ma.~;erials
Material U~,Kvolts ohms
Polyvinyl chloride 1.3 - 2.8 1x101~
Wood 0.7 1.4x1413
Glass 0.6 - 0.8 9.6x1012
Getinaks 0.45 4.3x1012
Table 5.13
Charge retention time on various surfaces
Material ~,y i seconds ohms
Papar 25 ~3�3 -91~)1011
Varnished wood 1200 1.4x10
Polyvinyl chloride 7800 l.Ox101~'
Glass 9000 2.2x1o15
Synthetic linoleum 12000 4.Ox101~'
87
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
FOR OFFICIAL USE ONLY
: a~T.~~- ~ ~~.T. ~ - , . _ _
o ~
>oooo . . . . ,,s,~,~ ( )
. I
~ ~ . ~n,.~; o �
1000 x � - . ` .
_ . ~ I:
. ~ o . . ,
l.~
_ � x
. .100 ' -
1 Z 'G
n1 .
50 7Q 90 ,
O~ca+a~a~a~s, 96 . � ; , ,
0
5�7-7� Rela,tionship between the value of static o
and relative humtdity of air for cotton
cloth (1) and Lavsan cloth (2) ~ ~
3. volts 4. ftumidity ,
9
~ 5~ ,Sf~
' ~2~ Bna.wNOCmo c~adyxa, %
~6� 5�1R� Relationahip between
specific surface re-
sistance ( Ps ) of poly-
vinyl chloride and the
level of the relative
humidity of the ai.r ,
1. Qhms 2. Air Hu-
miditY-,
~ ~
Table 5.13 shows experimental data on charge retention tim~ at the relative humidi-
ty of the air of 6596. The time retention titae on the aurface of synthetic linoleum
was measured at a lower humidity (60y6).
It may be concluded from Fig. 5.18 that an increase in humidity from ~0 to 83~ re-
duces the specific surface reaistance of polyvinyl chlaride by five orders of ma,g-
- nitude.
In organizin.g apparatus production using IC~ it must be remembered tha,t considerable
atatic voltages, from hundreds to several thousands of volts, are produced on the
hands of the workera ~rhen doing various technological operations. The value and
polaxity of these voltages depend on mariy vaxious factors, including the humidity
88
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFF[CIAL USE ONLY
of the air in the room, the material of the clothing worn~ the materials used to
cover the table and cha,irs~ the technological and teat equipment and the degree
of insulation of the worker from the "ground" (ma.terials of shoes and floor)
Fig. 5.19).
An analysis of the data in Fig. 5.19 shows that with working shoes with rubber
soles (curves 2), the static voltage on the hands of the workers is 2 to 2.5 times
higher than when working in leather ahoes (curves 1). This is due to the fact
that the leakage resistance of ahoes with rubber and leather soles differs ~ay a1=
most two orders of magnitude (leakage resistance of shoes with rubber soles is
1.Sx108-2.8x109 ohms~ while on leather soles it is 5.6x106 to 1.9x107). It
should also be noted that high values of static voltages on the workera` hands
correspond to the case where dielectrica xith high specific surface resistance
axe used at the working position.
a`~,e ~3) a~,e u~,o ~~T.e
o , ~ '
~an o ,
~ ~ ~ x ~ % '
~ ~ ~Z ~ ~ . ~oo x >c~ x x z
~ - 2 ' x ~
1
f0 ~ >0 A7
Jjl 7Q 90 d0 30 70 ~ SO 70 90 50 70 , 9!7 ~
d~ % 61 C~ B/1G',MIVQGYJI6 ~ % .
Fig. 5.19. Ralationship between the static voltage originating on the workers'
hands when rubbing diffarent materials and the relative level of the humidity of
the air for the table sirface bein of polyvinyl chloride (a)i varnished wood (b),
te.xtolite (c), covered with �lasa ~d). Workers' shoes with leather (1) and rubber
soles (2).
3. Volts
4. ftumidity~ 9~
When the workers walk on a floar covered with synthetic linoleum~ char~es are also
ac~cumulated on them (Fig. 5.20). The prevention of atatic electricity charges in
tha production process should proceed in two directionsi first reduction of the
possibility of static elaetri~ity charge generation axid, secondly, insurance of the
removal of accumulated charges from the production and technological equipment and
warkers.
89
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000400040032-8
FOR OFFICIAL USE ONLY
In organizing appaxatus production sections where IC axe used the use of finishing
materials with high specific surface resistance is not recommended. The use of
finiahing materials for production furniture, floars testing and technological'
equipment materials with low not over (1 to 5)10~ ohms,insures the necessaxy
oonditions for the rapid draining of the static electricity charges.
u~,a ~3). ~
, ,
_ o , . ~ _
. .
~x.~ , .
2Q7 . x
>00 % ~ . ~
~ ~
' ~ ~
f0
SO ~ yp ~p .
O~r,Mx~ocsa~e,
Fig. 5.20. Relationship between static voltage on the worker at various values
of the relative humidity a,nd degree of insulation from the floor, if
the workers' shoes have leather (1) or rubber (2) soles.
3. Volts 4. Humidity, 96
Table 5.14
Relative cha,racteristics of two types of linoleum
Type of synthetic P5, ohms Py , ohm.cm 'Z'y, seconds
linoleum
Common 4x1o14 5,9x101? 12000
Antistatic 5x109 2.4x109 0,5
A special antis+,atic linoleum is recommended to cover surfaces. The compa,rative
electrical paxameters specific surface (~6 ) and volumetric ) resistances
- and the time of charge retention (`t~ ) of common and antistatic linoleums are
shown in Table 5.14.
The u,ge of antistatic linoleum eliminates the possibility of charge accumulation
on the worker~ a contact by the worker's hand with a surface coverec by the anti-
_ :tatic linoleum befare doing the next technological operation insures draining of
the cr~arge in 1 second. Synthetic cover-P-2-E-S-S has tl~e best antistatic proper-
tiesi specific surface resistance of the material is lOd ohros. The use of such
ma,terial insures the complete destruction of the static chaxges because the drain-
ing time of a chaxge from a person is only 2ac10'4' Seconds. ~
90
FOR OFFiCIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004400040032-8
~ -"~g~~ , ~ . . ~ + . ~ . . . `
. . ~~4 '
? ~J � � . . .
f0~2 - � . ' y
~p ~ ' ~tt .
j ~Z ~
~~t 9
_
E5)
- ~p9 ~ ~ ~ ~ ~ i i
1 T 3 4 5 7 f0 t,a~u
Fig. 5.21. Relationship between specif ~c surface resiatance ( PS ) of various
materials and time before ~ ~ and after ( ' ) their
treatment by "Charodeyka" ~;~aste~ ~ ~
1. synthetic linoleum 3. cardboard
- 2. textolite 4. ohms
5. days
~ Qie of the methods recommended to reduce the apecific surface resistance of covers
is to use surface-active substancea (PAV~~ for example, "Chaxodeyka" paste
(TU-6-15-604-71), which is appl3ed. in a thin layer on the working dielectric sur-
~ faces oi" tables, test and technological equipment, packing for storing IC and
assembly units, and is used to mop floars and wash paper covers far production
furniture. The antistatic properties of the paste with respect to time are chax-
acterized by experimental data (Fig. 5.21).
The increase in aurface resistance with time of the processed eurface is due to the
natural drying and aging of tha paste and also to its being rubbed off in opera-
tion. The resiatance increases by an order of magnitude in 10 to 15 days; there-
fore, the interval between applying the paste should be determined on the basis
_ of concrete productions. In the Case of using antistatic linoleum, a$ Kell as
91
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFI~I('IAI. USE ONLY
- in using PAV to drain chaxges, it is necessaxy to insure good electrical contact
of one-two points of the processed surface (contact area not less than 1 cm2~ with
the "ground."
To reduce the surface resistance of covers at working positions, it is recommended
to insure the maximum relative humidity in the groduction axeas (a satisfactory re-
sult ma.y be achieved at 65 to 70qb humidity) .
Materials with surface resistances of 106 and 108 ohms are recommended for inter-
operation packing. The packing material may be coated with aluminum current-
conducting paint. The paint layer does not prevent charge draiaing because it has
a low P$ .
The continuous oontact between the worker and the "ground" should be provided
by a special antistatic bracelet, connected through a high-voltage resistor (for
example, the KLV type 10 kilovolt resistor). However, it should be taken into
account that the use of an antistatic bracelet i� effective onlf when the working
position, gacking and fixtures axe made of materials with low surface resistances
that prevent the accumulation of static electricity chaxges. Otherwise the possi-
bility of IC dama.ge is high. Actua.lly, charges of static electricity on a high
resistance surface, for example, on interoperation packing, ma.y produce a voltage
of up to several thousand volts on the packing itself~ as well as on the IC in it.
At the moment of contact between the worker and the IC: when there is a current
circuit "IC-worker-ground" the pulse of the dischaxge current may cause the failure
of the IC ~2~.
The workers' clothes should be made of cotton cloth, be laundered with antistatic
''Cnarodeyka" pa.ste or other surface-active substance. The workers should wear
leather or semiconducting rubber soles.
5 � 9 � Dismaxitling
In manufacturing apparatus, it frequently becomes necessaxy to dismantle IC. The
following axe recommended for this operation. If IC with planax leadouts are to be
disassembled, it is necessaxy toi. remove the varnish at points of leadout solder-
ing (if needed); unsolder the IC lea,douts using a mode tha.t does not exceed the
soldering mode specified in the IC certificate; lift the ends of the leadouts from
where they weze fixed in the seal inlet; remove the IC from the boaxds thermome~
chanically by means of a special device. (This device is heated to a temperature
that prevents the IC housing from overheating above the temperature indicated in
the certificate. The heating time should be sufficient to remove the IC and not
permit cracks, chipping and dama.ge to the housing).
When removing an IC with pin leadouts, it is necessary to~ remove varnish at the
points of soldering of the lea.douts; unsolder the leadouts with a special soldering
tool (the solder should be dxawn off according to a mode not exceeding the solder-
ing mode, specified in the IC certificate, until all IC leadouts axe freed from
- connection with the metal-coated printed circuit board); remove IC from the board
(not permitting cracks, chipping of glass or deforming of the housing and the lead-
outs). In this case also~if necessaxy~ it is permitted (if the housing is fastened
92
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
to the boaxd with varnish or glue) to use a thermomecha.nical method to remove the
IC that preventa overheating of the housing, ar chemical solvents that have no
effect on the coating, labeling and material of the housing.
BIBLIOGRAPAY
1. Integrated Circuits. Principles of Design and Production. Translated. from
the II~glish. Ddited by A. A. Kolosov. Moscow. Sovetskoye radio, 1967.
2. Ka,verznev~ V. A.; Zaytsev, A. A.; Ovechkin, Yu. A. "Static IIectricity in the
Semiconductor Industry." Moscow. Fhergiya, 1975�
CC~YRIGHPs Izdatel'stvo "Sovetskoye radio", 1979
2291
cs o~ 1863/209
93
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
FOR OFFICIAL USE ONLY
SM-3 AND SM-4
SMP,LL COMPUTER HARDWARE FOR CREATION OF DEVELOPED (:OMPLEXES
Moscow MALYYE EVM I IKH PRIMENENIYE in Russian 1980 (signed to press 14 Aug 80)
pp 95-141
- [Chapter 3 from the book "Small Computers and Their Application", edited by B. N.
Naumov, Izdatel'stvo "Statistika", 34,000 copies, 232 pages. Additional sections
of this publication appeared in the USSR REPORT: CYBERNETICS, COMPUTERS AND AUTO-
MATION TECHNOLOGY, JPRS L/9G75, 21 April 1981]
['l~ext] The main purpose of the first step in realizing the program for development
of small camputer hardware (and software) included development, testing a;~d indus-
- trial adoption of single-machine single-processor complexes of differen~ designa-
tion. Further development of small computers along with improvement of single-
machine complexes envisions the development of hardware and software oriented
toward design of multiprocessor and multimacnine complexes.
Development of the functional capabilities of single-~rocessor small computer com-
plexes is primarily related to the need to remove the restrictions on the number of
devices connected to the complexes ar.d on their configuration and to creation of
conditions that permit more complete utilization of available resources of central
processors and achieving the maximum functional return from the complexes. This
problem is partially solved by mearis of the interface expander (RIF SM).
No less imFortant is the problem of maintaining a sufficiently high level of con~-
plex productivity when using a large number of high-speed direct-access devices in
it. It can be solved by using an interface segmenter (SGI SM) in the complex whose
main function is relieving the "Common bus" (OSh) mainline of the most frequently
repeated direct-access exchange operations.
The possibility of parallel connection of interface expanders and interface seg-
menters to the common busses of SM-3 and SM-4 complexes permits development of
multiple, but highly productive small computer complexes and systems of different
designation.
A programming timer (TMRP SM) has been designed to relieve the central processor
of constant routine operations in real-time formation by programs. Its use is es-
pecially effective in SM-3 (SM-4) complexes that control complex facilities and
processes in real time. ~
~4
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
- The productivity, reliability and other characteristics of single-machine single-
processor UVK (Control computer complexes] or of campute_ systems do not always
meet the requirements of ASU [Automated control systems]. In these cases an al-
ternative solution of the problem may be the use of multimachine or multiprocessor
_ complexes and systems. The small camputer hardware that permits development of
both con~entrated and decentralized multiprocessor and multimachine complexes and
systems of different desig*_zation is related to AMS SM [Intercomputer communications
apparatus], PSh SM [expansion unknown), USVM [expansion unknown] devices anfl so on.
3.1. The Interface Expander
The desire to utiliz~ more fully the configuration capabilities and productivity
of central processors in developing efficient control computer complexes or systems
leads to an increase of the number of devices connected to the communications main-
line (MS) of the systems input-output interface (IW). However, the number of de-
vices in the system cannot be increased infinitely due to the limitation on the
load capacity of the mainline amplifiers (components of signal sources).
Moreover, the problem of designing the complexes with at least a small number of
devices but whose disposition requires an increase of the physical length of the
interface communications mainline frequently arises to meet the requirement of op-
timum configuration. Rigid restrictions are placed on the length of the communica-
tions mainlines in any computer systems.
The restrictions of physical length and load cap~city of interface mainlines actu-
ally existing in many cumplexes and computers can be eliminated by using additional
devices. One of these devices is the interface expander (RIF).
All the peripheral devices in traditional computer systems with three-bus communi-
cations structure are distributed by their own buses and therefore requirements on
load capacity are placed only on the communications program channel in which the
number of devices (in complex systems) may exceed the ca~abilities of the mainline
amplifiers. All the devices in complexes with single-bus structure (SM~3 and SM-4)
are ~onnected to a single interface communications mainline and therefore its cap-
_ abilities are considerably limited in length and load.
The load capacity and physical length of communications mainlines are important
systems parameters that largely determine the functional and technical capabilities
~ of designing complex systems based an small computer complexes. Since the produc-
tivity of the central processors (TsP) of SM-3 and SM-4 complexes and the carrying
capacity of communications mainlines are adequate to service a large number of
peripheral devices, these characteristics of the complexes become important and
largely determine the capability of developing complex, but effective systems based
on small computer hardware.
The communications mainline in SM-3 and S~I-4 complexes pe~-mits connection of up to
- 20 devices to it provided that each device loads it only with a single load unit
with a total length of the mainline up to 15.0 meters (with regard to all possible
- branches). If ~ach corinect2d device laads the communications mainline with more
than one load unit, the maximum possible number of devices in the complex is re-
duced sharply.
95
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400044032-8
FOR OFFICIAL USE ONLY
Uneconomical consumption of load capacity (some devices from the small computer
hardware nomenclature load the communications ma~.nline with more than one load
unit) and the length of the mainline (nonoptimum laying of communications mainline
wires in BKI [expansion unknown] type uni ts and the need to leave more than one
meter allowances of con�non bus cable to move complete units or BRS [expansion un-
known] uni ts from the bay) lead to the fact that these indicators are considerably
limited in standard configurati~ns of SM-3 and SM-4 complexes and the capabilities
_ of the communications mainline may be insufficient for users developing ASU based
on standard small computer complexes (TK) having a reserve langth and reserve load
capacity of the communications mainline. The geometric length of the communica-
tions mainline must be taken into account when selecting the configuration of any
complex. It is obvious that a reserve length facilitates configuration of the de-
vices in bays and in the area of the computer center or ASU and brings it .close to
the optimum. The resources of tlie complex usually remain unutilized in the use of
load capacity or length.
The SM-4101 interface expander (RIF SM) permits elimination of all the noted
restrictions.
The SM-4101 interface expander is designed for complexes and systems that utilize
the "Common bus" interface as the systems interface.
The device is r2quired to design multiple complexes with number of peripheral de-
vices that exceeds the capability of the main segment of the interface mainline.
The interface expander t~as the following specifications and designation factors:
The interface for connection of the device at the input ~central segment of the
communications mair~lin^_) and at the outp~it (the peripheral segment of the commun-
ications mainline) is the common bus of the small computer. The method of connec-
tion is series, parallel and combination (parallel-series and so on).
The load capacity through the output is 19 load units. The natural load on the
input--output interface is 1/1 load units.
The geometric length of the interface mainlines after the expander is not more than
15.0 meters.
The additior.~al delay of the exchange cycle upon access to the 6evice, established
after the expander, is not more than 0.35 microsecond when executing the READ oper-
j ation and not more than 0.25 microsecond when executing the WRITE operation.
The component base is TTL-IS and SIS. The electronics capacity (in arbitrary hous-
ings of integrated circuits) is 80. The design version is the small computer plug-
i n unit and the n umb e r o f printed-circuit cards (two-digit electronics un i t) is
Z and the number of types of cards is 1. The mass of the device is n~ more than
- 3.0 kg.
The power supply voltage is �h5 + 0.25 V. The consumed power is no more than 9.0 W.
,6
FOR OFFiCIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
The operating conditions are group 3b according to GOST [State Standard] 20397-74.
The version ~s ordinary according to GOST 21552-76.*
The eff~ciency checking deviaes are the ir.._erface expander tester and thg test pro-
grams for it and tests of the device~ connected after the interface expaniier.
Identifiers of the device on the common bus are not required.
The interface expander increases the functional capabilities of small computer com-
' plexes by expanding the systems characteristics of the input-output interface with
a slight reduction of productivity. It permits the mainline of the complex to be
extended to 15 meters and permits control of an additional 19 load units. A fur-
ther increase of the interface capabilities is provided by series or parallel con-
nection of the expanders.
No software is required in the complexes to control the operation of the interface
expander.
B 6 1 A
300 _ 100 Bb~x. otu cM(n)
400 =200 ~ X.
OjU
Ciy(n) 4
a~ 63 9402 Boix. 0!U CM 3'
63 9402 Bx. 0[U C~~1(L() Z'
1
~ Bx. ot~ c~f(q1 -
BbIX.
~PN4~Z
3 4
BX. B6iX.
o~r cM (n)
S 6 ~
- - - - - - - - Bc~ r om ,r,ti/o)
- 30uI C.y 4
bl _ 6,3 9402 30[U CM 3
6.3 9401 Bx. OU/ CM(L(J 2
. ~
om cM~ul our cM(n~
BX. 1 PN~ 4 Bb/X.
30111 .30W~
Figure 3.1. Configuration and Possible Layouts of Connecting the Interf.ace
Expander to thz Common Bus
Key:
~ 1. Output 2. Input
*The operating conditions and the version correspond to the indicated normative
documents for a small computer hardware.
97
FOR OFFICIAL USE Ol~'LY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
The interface expander is a structurally independent unit (plug-in paCkage unit--BK)
designed for installation in units of type AKB, BAM or BRS* of SM-3 and SM-4 com-
plexes. The following devices: the interface expander. tester TRIF SM (BE9401),
the status designator of the small computer common bus ISOSh SM (BE284 is illed
in place of the TRIF SM if necessary), common bus plugs (ZOSh 5M) and common bus
cables or jumpers (POSh).
Possible diagrams of the body configurations of interface expanders are shown in
Figure 3.1.
The parallel method of using interface expanders also increases the number of di-
rections of increase of the common bus mainline, which significantly simplifies the
configuration of the complexes (Figure 3.2).
The interface expander tester and common bus status designator (included in the
nomenclature af small computer devices used in complexes of automated designer job
sites ARM (SM-3-M-400 ARM))can be connected by the expander body both on the central
and on the peripheral segments of the communications mainline.
Parallel, series and combination principles of increasing the peripheral devices
(PU) in the complexes are possible when using int~iface expanders (see Figure 3.2).
The function not only of signal translation fr~m one (central--Ts) segment of the
common bus to another (peripheral--P), but also the function of restoring the time
relationships between common bus signals is entrusted to the expander duri.ng oper-
ation in the complex, as a result of which series connection of an unlimited number
of interface expanders and achievement of a mainline of infinite length is possible.
The function of restoration includes an additional delay in the exchange cycle be-
tween devices located on different common bus segments<
The delay introduced by the expanders is added with series use of tnem, which
reduces the total rate of exchange with the devices located behind the expanders.
The length of the exchange cycle between devices is calculated according to the
for.mula
Ttso - TO(1 + Tr'n),
where Ttso is the time of the exchange cycle, nanoseconds, To is the time of the
exchange cycle between devices of the sanie bus segment, nanoseconds, Tr is the
average delay introduced by the expander, nanoseconds, and n is the number of
expanders used in the complex.
Thus, the para].iel r�_inciple of ._::nnecting the expanders may b~ used in which there
is no increase of the delay introduced by the expanders with an increase of their
number in the complex. In this case the maximum delay introduced by the expanders
is achieved upon participation cf two different peripheral segments of the common
*AKB--self-contained complete unit, BAM--self-contained installation .unit and
' BRS--systems ~expansion unit.
q~
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R440400040032-8
FOR OFFICIAI. USE ONLY
bus in the exchange of the devices and comprises 2Tr + To. If the devices are
located on the central and peripheral segments, the exchange cycle Ttso Will always
be equal to Tr + To.
If the number of peripheral devices used in the system exceeds the capabilities of
the expanders connected in parallel to the central segment or if devices separated
by 30-50 meters from the bay must be connecteci by using the common bus mainline,
the parallel-series pr.inciple of connecting the expanders may be used.
a] . .
' i
n j � -
30[!/ On 30lU 30[!/ . L J� 30lI/ 3011/ 30lU ~
~ o~u cM(u1 PN~ ~om cM(n,)I pN~ Our cM~nz1
~ ~ 2
2
_ ~P !!b /ISl /ly /7y /7y ny
� b1 _ .
30lU On ~ 30m
O!U CM~UI ~
1 2
l7P- !ly PNm~ ny PH~P2 .
' � 30lU 0!U
. ny ny
' . ~ ry
- r-- ~ `
- i on r ~ �
- - . L_J~ ' v ' ~
. o !ly o ny .
30LU 30[ll
C~ 3 4 .
JOCU On � 30ly
o~ cM/ul '
~ ,-l I 2
na ny Ptic~, ny PHCOz
3or~ om cr?~n,l 30
3 y
on ny 3o~c ny
' . au~ cM(n2) 3or~
s s
on ns~ ny .
Figure 3.2. Principles of Build-Up of Common Bus Mainline Using an
Interface Expander
99
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
An additional delay of the exchange cycle through the common bus, which occurs due
to the use of the expander (for devices connected after the interface expander),
plays no significant role since it is short 350 nanoseconds). On the other hand,
program-control devices which are very slow with respect to the processor and mem-
ory speeds, may be connected behind the expanders and the overall reduction of the
productivity of the complex will be insiqnificant. High-speed devices having short
(critical) service waiting time, such as NNID [Magnetic disk carrier), computer com-
munications devices (USVM) and so on, should be connected before the expander~ on
the main common bus s~gment.
Inclusion of interface expanders in small computer complexes permits more complete
stilization of the capabilities of the SM-3P and SM-4P central processors in serv-
- icing a large number of peripheral devices and makes it possible to develop complex,
but economica~. control systems for different facilities and processes.
The Interface Expander Tester (TRIF SM)
The interface expander tester is used as the service equipment of SM-3 and SM-4
complexes and is designated for a complete check of the efficiency of the interface
e:cpander without using peripheral devices. A minimum of one device would have to
be connected to each of the interrupt levels (ZPD, ZP7-ZP4) to check the interface
expander by means of peripheral devices. The tester also permits one to check the
common bus exchange with the central processor and the internal memory devices and
to organize interrupt modes at all four program levels and the direct-access level
and makes it possible to check the interaction of all common bus signals.
The specifications of the interface expander tester are as follows.
The interface connecting device is the small computer common bus. The natural load
on the interface is one load unit.
The main modes of exchange of the devices with the tester are the executor, inter-
rupt servicing and direct access.
The tester forms the following types of interruptions: program generation of re-
quests at any of the ZP7-ZP4 levels and apparatus generation of requests at ~he
direct-access level with period of approximately 1 microsecond.
The component base of the device is TTL-IS artd SIS. The device is structurally
made in the =orm of a two-plug t~nit of BE9401 components. The power supply volt-
~ age is +5+0.25 V. The consa~med power is no more than %.5 W.
The device is installed in the interface expander body or by means of an attenuator
in the cable compartment of the common bus in the plug-in package unit of other de-
vices. The mass of the device is no moxe than 0.6 kg.
The tester has a 16-digit storage consisting of 16 registers with access time of
no more than 250 nanoseconds. 7'he addresses of the registers are 767700-767736.
~~ith program use of the file of these registers, the tester can ~e serviced by the
executor in communications sessions through the common bus controlled by any device
of the system.
.
. ~ y
1~0
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
i ~E ONLY
� The level of interruption should be given to organize the interrupt mode. The four
lowest orders of the interrupt request register (RZP), ha~~ing address 767740, are
used to store the number of the level of interruption. A"1" is entered by program
or from the console in one of these RZP digits, corresponding to the selected level.
- The outputs of digits 3-0 form the ZP7-ZP4 signals on the common bus.
- After the interrupt authorization signal (according to RP7-RP4) has been rec~ived
from 'che central processor, the tester generates a sequence of signals through the ~
common bus according to the algorithm for processing the interrupt procedure (see
2.6). The address of the interrupt vector issued by the tester on the common bus
. is first entered in the zero register of the tester storage device.
The type of operation (read or write) and the type af access from the tester (only
to the memory cell or to the keyboard register), besides the direct-access request
itself, are gi.ven (by program or from the console) to organize the direct-access
mode. These data are stored in the three digits of the RZP: a"1" in digit 4 de-
notes "write" and a"0" denotes "read": a"1" in digit 5 denotes a series of ZPD
signals; a"1" in digit 6 denotes access to t'he internal storage cell and a"0" ~
denotes access to the internal storage cell and to the keyboard register (the ad-
dress of the internal storage cell is 000214 and the address of the keyboard regis-
ter is 777562).
A one recorded in digit 5 of the interrupt request register induces the tester to
emit a series of ZPD signals. Having received authorization from rhe processor
(RPD), the tes*e~ generates a series of exchange signals according to the direct-
access algorithm (see 2.6).
� When writinq in the direct-access mode, the data are selected from register 6(when
writing in the internal storage cell) or from register 9(when writing in the key-
board register) of the test register block.
The tester generates a sequence of executor signals (the executor mode) during the
communications cycle thro~xgh the common bus by the corresponding algorithm (see
2.6) with access to it through the address of any of the 16 registers of the tester
(767700-767736) or the interrupt request register (767740). Thus, the necessary
information can be entered in any register of the tester or the contents of the
register can be read (only writing is possible during access to the interrupt re-
quest register).
Test programs are used to check the exchange througti the common bus by means of the
interface expander tester. Diagnosis of malfunctions when the tests are stopped is
given in commentaries to the halt instructions.
3.2. The Interface Segmenter
The devices in complex with single-bus structure of the systems interface cannot
carry out para11E1 exchange of information due to the need for time sharing of the
single data transmission mainline.
101 -
FOR OFFiCIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
FOR OFFICIAL USE ONLY
Since all information flows travel over only one path, the time delays in this
system may be longer than in other systems containing a larger number of informa-
tion transmission mainlines. In a system with a comanon mainline when one source
transmits data to a receiver, the third source (and the others) waits for clearing
of the mainline. Although aonflicts between devices for the right to utilize the
common bus are automatically resolved and present no serious problem, they still
occur and delay the ovE~all operation of the complex. The productivity of the sys-
tem is thus dependent on the speed of the communications mainline (on its exchange
cycle). The use of a large number of devices in a complex with single-bus commun-
ications structure may lead ta an impermissibly long waiting time for servici.ng of
"remote" devices (from the central processor arbitrator) as the compositifln is ex-
panded, especially with frequent exchange of data files (at the level of direct-
ac~ess requests).
The interface segmenter permits a reduction af the effect of the single-bus struc-
ture on the overall productivity of SM-3 and SM-4 complexes.
only two devices, one of which is a controller and the other of which is an execu-
tor, participate in each data exchange cycle through the common bus mainline in the
SM-3 and SM-4 control computer complexes. Other devices which the mainline also
requires for exchange wait for completion of the current exchange cycle. During
exchange of information between the controller and executor, only that part of the
mainline is required which connects these two devices (althoug~ the mainline con-
nects all the devices of the complex in series). During this time the remaining
parts of the mainline, except relay of electrical signals, carry no functional load
o f ariy kind .
The use of an interface segmenter device in SM-3 and SM-4 complexes permits one to
increase their productivity by reiieving the common bus mainline of the most fre-
quently repeated direct-access exchange operations. Relief is accompZished by
dividing the interface mainline by means of the segmenter into individual address
sections (peripheral segments of the common bus) to which devices that perform a
more intensive exchange with each other are connected. Independent operation of
the devices within sections and parallel operation of sections with each r~zner and
with respect to the central segment of the common bus are possible.
The integrity of the system (and of the interface) is retained in this case, i.e.,
the interface segmenter device maintains the capability of information exchange
betwesn devices of different segments if the need f~r this volume occurs. Control
of isolated devices by means of a processor and self-contained operation of devices
on the peripheral segments of the common bus are provided by the corresponding ad-
justment of the segmenter address selectors to the address zones (segments). These
address zones may be the register addresses of the devices or the address zo:~es of
the internal storage devices.
When the interface segmenter is used in the complex, besides its main �~-_lction, it
performs the functions of an interface expander that permits lengty~ening of the
interface mainline by the same length and control of the same additional number of
loads as in the main comanon bus mainline.
102
~ FOR OFFICIAL USE ONLY .
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL l1SF ONtY
The interface segmenter is structurally completely identical to the interface ex-
pander device. The body configuration corresponds to Fig�,ire 3.1, except BE9403
instead of BE9402 components are used in place of the blocks. Therefnre, the main
installation on the body is different than in the interface expander. The capa-
bilities of installing other devices in the interface segmenter body completely
correspond to the list presented in the interface expander (these are the interface
expander tester, the comm~n bus status designator, the common bus plugs and so on).
The diagrams for connecting the segmenters t~ the common bus of small computer com-
plexes are similar to those for connecting the expanders (see Figure 3.1). Ttiie
length of the exchange cycle between devices on both sides of the interface seg-
meater is calculated by the same formula as for the interface expander.
The use of the interface segmenter in SM-3 or SM-4 control computer complexes may
yield a significant effect. For example, there is one each graphical display of
the EPG type in SM-3 or SM-4 automated job sites which interact intensively with
the internal storage, regenerating information files (which may have capacity of
4-8K words) at frequency of 50 Hz, as a result of which they take "for themselves"
almost SO percent of the carrying capacity of the common bus ~nterface of each
complex. Taking into account that there are also other devices (processor, NNID
[Magnetic disk carrier], NML [Magnetic tape carrier] and others) interacting in-
tensively with the memory, it is practically impossible to realize an econo~nic com-
plex of an automated job site with a large number of EPG.
When using segmenters, the ntunber of EPG SM displays connected to the complex
through them may be rather large and will be c~etermined by the internal storage
capacity rather than by the carrying capacity of the common bus. The structure
of the computer complex based on *_he SM-4 control computer complex with three EPG
SM connected through segmenters and with self-contained internal storage units is
shown in Figure 3.3.
The use of interface segmenters in combination with other devices permits one to
develop original small computer complexes of increased productivity and provides
expansion of the input-output interface functions by increasing the loaci capacity
and physical length of the common bus mainline.
3.3. A Programmable Timer
A circuit that generates interrupt signals at network frequency (50 + 1 Hz) is
provided in the central processors to organize real-time service in SM-3 and SM-4
complexes. The processor, reading the interrupt signals from this network timer
(TMR-S), measures the real time and if necessary the individual time intervals.
The need f4r continuous execution of the time interval read programs and astonom-
ical time after each interruption requires specific time expenditures of the cen-
tral processor which could be used by it to perform more useful functions.
The use of a programmable timer TMR-P SM in SM-3 and SM-4 complexes makes it pos-
sible to do away with program accounting of time and to increase its useful return.
The programmable timer provides self-contained processing of programmable time
intervals with shaping of the interrupt signals, recordirig of astronomical time and
other operations. It can also be used to check the efficiency of the complex.
103
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
A further build-up of the interface capabilities (in load and length) is provided
by series or parallel connection of the segmenters to the mainline of the complex
- or system. Parallel connection of the segmenters is preferable. The use of seg-
menters also significantly improves the configurations of the devices in the bays
and outside them.
_ Ar? interface segmenter may be used to design multiple complexes with a large number
of high-speed devices with direct access to the memory that exceed the capabilities
of a systems interface by its carrying capacity, load and (or) length.
No special software is required to control the operation of the device in the
complex. �
The interface segmenter has the following specifications and designation.
The interface is connected to the device by the small computer common bus at the
input (the central segment of the communications mainline) and at the output (the
peripheral segment of the communications mainline).
The method of connecting the device is series or parallel. The method of indicat-
ing the address zones on the peripheral sections of the common bus is rigi~ily pro-
grammed prior to the beginning of use (by means of electrically programmed PPZU of
the K556RE4 type). The dimensions of the possible address and word zones are from
2 to 124 K(with spacing of two or more). The arrangement of the address zones a.s
arbitrary.
The load capacity at the output comprises i9 load units. The natural load on the
' interface is one load unit through the input and output.
The geometric length of the interface mainlines after the segmenter is no more than
15.0 meters. The additional delay of the exchange cycle upon access to the device
installed after the segmenter is no more than 0.5 microsecond.
The component base of the device is TTL-IS and SIS. The electronics capacity (in
conditional integrated circuit bodies) is approximately 100.
The device is made structurally in the fozm of a small computer plug~in unit and the
configuration of the cards is identical to the interface expander). The number of
printed-circuit cards (two-plug) is two and the number of types of cards is one.
The mass af the device is not more than 3.0 kg.
Power supply voltage is +5+0.25 V and consumed power is no more than 15.0 W.
The means of efficiency checking is the interface expander tester and the test pro-
grams for it.
_ Note. A special "Programmer" device for automatic broaching of this microcircuit
by means of the SM-3 (SM-4) control computer complex can be set up together with
the interface expander device to program the K556RE4 semipermanent memory unit.
104
FOR OFFICIAL U5E ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007142/09: CIA-RDP82-40854R040400040032-8
~ FOR UFFICIAL USE ONLY
' HM,Q ny
- 0lUCM~l13)
, C~N3
!lp CM-Y ~k3y yB8 C~N~ ~~N2 - K
Cno6 f~
~ - (1) . .
6k cnoQ 16K~no8
. ~Q ~a
Figure 3.3. Structure of Computer Complex Based on SM-4 Control Computer
Complex With Three EPG SM Conn~cted Through Interface Segments
Key:
1. Words .
The use of a timer in the complexes that control facilities and processes in the
real-time mode is especially effective.
The specifications of the progra~nable timer are as follows.
The interface connections of the device are the small computer common bus. The
natural load on the interface comprises one load unit. The method of shaping the
length of the time intervals and interruptions is apparatus.
The device operates in the single interrupt and repeated (cyclic) interrupt modes
and the external signal counting mode with interruptions and the astronomical time
counting mode without interruptions.
The rates of counting the time intervals with synchronization (for these modes) are
110 Hz from a crystal oscillator (witih timing accuracy of not less than 0.01 per-
cent) and 50 Hz from .ietwork frequency with deviation frequency of the external
analog signal.
The component base is TTL-IS and SIS. The electronic:s capacity (in arbitrary in- l
tegrated circuit housings) is 50. The device is made structurally in the form of
a two-plug component uni t. The mass of the device is not more than 0.6 kg. The
- power supply voltage is +5+0.25 V and consumed power is not more than 7.5 W.
The means of testing the efficiency is the programmable timer test. The identi-
fiers of the device based on the "common bus" are ZP6 for the interrupt level and
104 for the interrupt vector.
The timer is included in the complex by installing its component uni t on any free
adjustable point in the BSI or BKI units which are in turn included in the BAM or
l05
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
NOR ONFICIAL USE ONLY
BRS units, respectively. An auxiliary unit of BE9514 components installed in the
BSI or BKI cable compartment is used to connect~the timer to the external signal
sources or to signals with frequency of 50 Hz. This unit of components contains
an optron isolator and matching resistors for reception of the external signal and
a printed-card insert for connecting the external signal reception cables and the
_ 50-Hz signal. The 50-Hz signal reception cable is included in the timer. The
50-Hz signal source is the connect-disconnect uni ts (BW) of the bay power supply
of the complex.
The operation of the davice is controlled by transmission of information (by means
of the processor instructions) to its registers having the following addresses:
772540--instruction and state register (RKS), 772542--buffer register (RB) and
772544--counter register (RSCh).
The distribution of the RKS digits and the functions connected to them are pre-
sented in Table 3.1.
The buffer register (16-digit) is designed to store the counting intervals. It
provides automatic reloading of the counter in the periodic interrupt mode. The
buffer register is useci only to write by the program and is reset by the PODG sig-
nal and also upon overflow or antioverflow in the single interrupt mode.
The counter register (16-digit) is a synchronous binary counter with the capability
of counting in forward and reverse directions at one of four program-controlled
rates. Information can be read during operation. In the direct counting mode, an
interruption on the common bus is initiated with counter contents equal to 177777
(overflow). This mode is used to count external signals. An interrupt on the com-
mon bus is initiated in all digits (antioverflow) of the counter at zero in the
reverse counting mode used when working with a pr2viously set time interval.
3.4. Computer Integration Device
An ASU may include several multimachine control computer complexes as a function of
the complexity, territorial disposition of the control facility, the importance of
the problems being solved and other factors. The functions in multimachine com-
plexes are always distri.buted among machines (subcomplexes). In this case one of
the machines coordinates the actions of all other machines to solve a common pro
problem.
Another type of organization of multimachine complexes is hierarchical construction
of the system (the relationship between complexes is established by the seniority .
principle). Fox example, one or several parallel-operatinq lower level complexes
(peripheral machines) gathers information from the controlled facility, first
processes it and transmits it t~ an upper level subcomplex (a central machine--
TsM) for a production process contzol system. 'I'he central machine carries out
secondary processing of the entered information and makes economic calculations
and issues information to the lower level subcomplexes to change the operating mode
of the facility.
Complexes with hierarchical structure may have two or more levels of hierarchy.
Upper level subcomplexes usually perform more complex calculating functions and
are constructed on processors of higher productivity than lower level subcomplexes.
106
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
Table 3.1. Functi~nal Designation of RKS Digits of Programmable Timer
DiQit Name Function
0 Operation The counter register is triggered when set to
"1." It is reset upon antioverflow and over-
flow of the counter in the single mode and also
by the PODG signal in all remaining cases
1.2 Assignment of counting ProvidPS selection of one of four possible
rate counting rates:
Digits Rate
2 1
0 0 100 kHz
0 1 10 kHz
1 0 50 Hz
1 1 External signal
Both digits are set by the program and are re-
set by the PODG signal
3 Operating mode The operating mode is given with interruptions:
periodic with "1" and single with "0." It is
set by the program and reset by the PODG signal
4 Direct-reverse counting The operating mode of the counter register is
given: direct counting with "1" and reverse
counting with "0." It is set by the program
and reset by the PODG signal
5 Single step A single time step of the counter is induced
upon setting. Counting is under program control
6 Interruot authorization Setting of digit to "1" provides interrupt of
� processor program if th? "Readiness" digit is
also set to "1." Setting to "0" prohibits
interruption. It is set by the program and re-
set by the PODG signal
7 Readiness It is set only upon overfilling and antiover-
filling of the counter. It is reset by program
or by the PODG signal
8-14 Not used
15 Error It is set (with periodic operating mode) when
tihe last (second) overfilling or antioverfill-
- ing occurred prior to detection of the previous
interrupt. It is reset either by program or by
the PODG signal
Territorially concentrated complexes, in which the distance between central proces-
sors of subcomplexes does not exceed 30-50 meters, do not require data transmission
apparatus for organization of communications. Data transmission apparatus is re-
quired in dispersed control computer complexes to organize communications between
processors.
- The small computer hardware contains devices that permit creation of hierarchical
complexes of these two classes. Specifically, the USVM A71118 computer integration
107
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R400404040032-8
FOR OFFICIAL USE ONLY
device helps to solve the problem of designing concentrated hierarchical compiexes
and ASU based on them.
The USVM A71118 device is designed to organize multimachine hierarchical systems
based on models of the M-4030 and M-4030-1 control computer complex ~or any other
computer of the YeS EVM series) as a central machine and one of the SM-3 or SM-4
, complexes as the peripheral machine (PM).
The device is connected to the M-4030 (M-4030-1) model on one side and to the SM-3
(SM-4) control compute:- complex on the other side as a peripheral device.
The specifications of the device are as follows.
The interface is connected to a Ye5 EVM (with the possibility of connection to a
multiplex MK or selector SK channels) on the side of the central machine and to the
small computer common bus on the side of the peripheral machine. The algorithm
of the YeS EVM is realized as schematic.
The possibility of org-tnizing the beginning and end of an exchange session is ac-
complished at the initiative of any of the machines (peripheral or central machines).
The possible transmission modes on the side of computer integration device-central
machine exchange when connected to the multiplex channel is monopole, multibyte
(portions of eight bytes each) or multiplex (one byte each).* The possible modes
of continuation of transmission on the side of the computer integration device-
peripheral machine exchange is at the level of proqram control (upon interrogation
of the readiness of the device), program interrupt or direct (extraprocessor) ac-
cess to the internal storage.
Th~ t~�pes of information exchange on the side of the peripheral machine are byte
by byte in the program interrupt mode and word by word in the direct access mode.
Data are exchanged with the internal storage of the peripheral machine in the ~
direct access mode under the control of only the program of the central machine
and without any participation of the programs of the peripheral machine. The max-
imum data transmission speed in the program interrupt mode is 40,000 bytes/s and
in the direct access mode is 400,000 words/s.
The device is program compatible with the A7119 computer integration device that
pro~~ides communication of the M-4030 central machine with the M-400 control com-
puter complex. The maximum 3istance between the integrated machines is up to 55
meters. The natural load on the common bus interface is two load units and the
component base is TTL-IS.
The composition of the device is a control device (made in the form of a UTK cab-
inet of the modular computer equipment system), an interface u n i t(BI)(in the
form of a complete small computer u n i t) is inserted in the bay of the SM-3 (SM-4)
complex and a set of communications cable.
*
During one communications cycle.
108
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
The overall dimensions are (B X L X H) are 600 X 650 X 880 mm for the cabinet and
482.6 X 767 X 146 mm for the interface block.
The power supply for the cabinet is from a three-phase AC network with neutral con-
- ductor a* voltaqe of 380 V, 50 Hz and that for the interface uni tsis from a single-
phase AC network with voltage of 220 V, 50 Hz separated in the bay (cabinet) of
the SM-3 (SM-4) complexes.
The mass of the cabinet is not more than 130 kg and that of the int~rface unit is
not more than 20 kg.
The devices for checking efficiency are by means of testing the computer integra-
tion devices in the hierarchical system and by means of a built-in controJ. console
(in the cabinet) that simulates the operating mode of the central machine interface
(M-4630) and so on in the self-contained mode with a peripheral machine.
The identifiers of the device on the common bus are ZPD and ZP5 for the interrupt
level and the first vector 170 for the interrupt vectors; the second vector is 174.
The computer integration device is selected and responds to the instructions of
the central machine and the peripheral machine exactly the same as any controller
of a peripheral device. However, it utilizes these instructions to establish com-
munications between the channels of the central and peripheral machines and to
synchronize their operation rather than for working with the peripheral device.
The device consists of two parts: a cabinet (control device) and interface unit
connected to each other by two cables. The distance between the cabinet and M-4030
device and between the cabinet and the interface unit is determined by the the
lengths of the cables delivered with the device, which are equal to 16 and 5 meters,
respectively.
The receivers and transmitters used in the device permit the cabinet to be separ-
ated up to 50 meters by means of an IKM-2 type cable. The design version of the
device is shown in Figure 3.4. The structure of the hierarchical system based on
the A71118 computer integration device is illustrated by Figure 3.5.
rc
i i~TO~,Kp
CM 3Bh1 ~
~ , ~
. ~
~
rya6n ( 2 I ~~H; ep~euc~~oiu
ta~ l~. . L~L~nak .J
' ,Yn�.i,):l j
a.l.+:~l C3~.:`~
1,.+'1~-1~ I / .
i: .ah',~~) n~nvenu (5 ) ~r;\:~r.,~.~
Figure 3.4. M-4030 (M-4030-1 and YeS EVM) and SM-3 (SM-4) Computer
Integration Device
[Key on following page]
109
FOR OFF'ICI::L USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
FOR OFFICIAL USE ONLY
[Key continued from preceding page]:
- 1. SM EVM oay 4. To M-4030 (M-4030-1 or YeS EVM)
2. cabinet channel
- 3. Interface unit 5. Cables
Interaction of the device with the peripheral machine is organized by means of four
program-accessible registers: a data register RD (address 777500), instruction and
state register (address 777502), address register (address 777504) and length of
file register (address 777506).
All the control information in the form of instructions and notations for commun-
ic~tion of the computer integration device with the SM-3 (SM-4) is located in the
instruction and state register. The functional designation of the digits of the
instruction and state register is presented in Table 3.2. All the capabilities in-
cluded in the instruction system of the GM-3 or SM-4 processors are used for working
with these digits in the driver of the computer integration device from the direc-
tion of the peripheral machine. The algorithms for interaction of the computer
integration device with the central machine after program initiation of the exchange
mode are realized by the apparatus method.
The computer integration device is controlled by a special driver when working in
the hierarchical control system (automated production control system and so on) from
the direction of the peripheral machine and by means of a program that organizes the
corresponding exchange modes when working from the direction of the central machine.
The program driver for working with the computer integration device includes DOS-ARM
[Disk operating system of automated job sites] of the SM-3 ~.nd the small computer
FOBOS [Basic real-time background-operating system].
3.5. The Common Bus Switch
As noted, the required high productivity of the complex can be achieved both by the
use of highly productive components and by designing the complex in the form of a
multimachine or multiprocessor system.
The reliability of the complexes is enhanced by using so-called "hot" redundancy of
its individual components, which are automatically replaced by duplicate devices if
they break down.
Such problems as access of each of the processors to each of the external devices
common to them and to internal storage uni ts, synchronization of the operation of
processors with common data files and automatic reconfiguration of the complex if
some of its components break down are solved when designing local multimachine
complexes.
These problems help to solve intrasystems communications devices existing in the
nomenclature of small computer hardware, specifically, the SM-4501 common bus
switch (PSh SM).
110
FOR OFF[CIAL USE O1VLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFIC'IAL USE ONLY
_ _ _ _ . , . . . . . - . . ~ . ~
- i i~,ou.. . n 03y 03y Ily ny ~y ~
I I
i - - 06r~lop muHa � I
i i yCBM ~ CM-3 (CM-4) i
I i P,Q PMC PA PqM i
~ 3 6npk uNrepq~eucHa~u (6N) ~ .
~ . ~ . . . 4 _ 0 5 M : _ ^ . _t___. . . ~
~ ycrvoucreo(5) ~ I
~ ynpoBneHUa . I
L- - - - - - -
Nyrepq~euc (6~
EC 3BM (d0 'S/SUM7
~ M~ !ly /7;; . . . . /1'J /ly . �
~ ! ~poy eccop crr r. i
I , CK2 ,
CK3 I
I-. . . . ~y . . . ny . . M~40~.J
Figure 3.5. Version of Structure of Hierarchical System Using the A71118
Computer Integration Device (RD--dat~ registerj RKS--instruc-
tion and state register; RA--address register; RDM--length of
file register; PU--peripheral device)
Key:
1. Processor 4. Up to 5 meters
2. Common bus 5. Control device
3. Interface unit 6. YeS EVM interface (up to 15/50
meters)
The common bus switch is designed to construct multimachine complexes of different
configurations on the basis of SM-3P and SM4P processors: two-machine complexes
with time-shared common devices, including the internal storage units, external
magnetic dis k and magnetic tape storage devices, peripheral devices and systems
of enhanced reliability due to the use of one of the complexes (or part of it) in
"hot" reserve that is switched on automatically in place of one that is broken down.
The common bus switch is an electronic device that permits connection of an addi-
tional "Conunon bus" section to the common bus of one of two processors. Ang de-
vices except the processor can be connected to the additional "common bus" section
(DSh) (Figure 3.6). The additional common bus section fully meets the requirements
of the Common Bus Interface Standard.
111
FOR OFFICfAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
Table 3.2. Functional Designation of Digits of Instruction and State Register of
Computer Integration Device
Digits Name Func~ion
0-2 Instruction or notation Different instructions to the device from the
direction of the peripheral machine program to
continue or halt operation of data exchange
- 3 Byte arrangement notation Indicates the order of byte arrangement of the
central machine in the word issued to the mem-
ory (or received from the memory) of the pe-
ripheral machine at the extraprocessor level
4,5 Memory expansion Permits the device to utilize all 18 digits of
the coma~?on bus address
6 Interrupt authorization Indicates whether the peripheral machine pro-
gram authorizes work in the program interrupt
mode
Note. Digits 0-6 can be set only by the pe-
- ripheral machine program
7 Data register request Used only during operation of the device in the
SM-3 mode to indicate readiness for the next
data transmission cycle
8 Instruction and state Used only during operation of the device in the
register request SM-3 modej informs of the readiness to transfer
any information of state to the peripheral ma-
chine program
Note. Digits 7 and 8 are set by apparatus and
can only be read by the peripheral machine pro-
gram for organization of work in the readiness
interrogation mode
9 Execute Used only in the SM-3 mode when organizing work
on readiness interrogation to indicate to the
device completion of the next data transmission
cycle by the peripheral machine program
10 SM-3 mode Indicates in which mode (SM-3 or M-400) the de-
vice is. Writing a one in the given digit con-
verts the device to the SM-3 mode
11 M-400 mode Writing a one in the given digit converts the
davice to the M-400 mode in which complete pro-
gram compatibility with the A7119 computer in-
tegration device is provided
Note. Digits 9 and 11 can be only written by
the peripheral machine program and digit 10 can
alss~ be read.
12 Parity error Indicates that information with incorrect par-
ity was detected during data transmission from
the central to the peripheral machines
[Table continued on following page]
112
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000400040032-8
Table 3.2 [Continu~d from preceding pagel:
Digits Name Function
- 13, 14 Halt or reset Indicates the reason for completing the data
exchange operation
15 Response delay (tin~e Indicates that the device turned to a nonexist-
out) ent memory cell during data transmission at the
extraprocessor level
Note. Di,~its 12-15 are set by apparatus and
can only be read by the perip2~era1 machine
program
OlUI `
(1) . -
qonanHUrenoNb~u
nA1 n~ ~ uvor.'TQK D~~(,q~rJ �
/]P2 " G3y B~1 8y~
- OcU2 . - , _
Figure 3.6. Diagram for Connecting Additional Devices Through the Common
Bus Switch: two processors (PR1 and PR2), internal storage
device and external devices (W)
Key :
1. Additional common bus section
The common bus signals are relayed by the switch without distortion. Z'hus, if the
common bus switch were connected to the additional common bus processor, the oper-
ation of the processor with devices connected to the additional common bus is
provided as if these devices were connected directly to the common bus. Exchange
_ can be carried on with them both through the program channel and through the direct-
- access channel. The delay of the signal transmission cycle through the common bus
switch is no more than 500 nanoseconds.
The common bus switch consists of two identical structural and electrical sections,
each ~f which is connected to the common bus of the corresponding processor (see
Figure 3.6). There is also internal communication between sections in the form of
common signals.
The load capacity of each section of the common bus switch is two load units at the
input and 18 load units at the output. The control modes of the common bus switch
are local manual, remote manual and program.
_ The component base is series K131, K155, K559 and K599 microcircuits. The common
bus switch is structurally formulated in the form of a self-contained complete
un it built into the standard small computer bay. The overall dimensions of the
common aus switch are 667 X 482 X 266 mm and the mass is not more than 30 kg.
- 113
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
FOR OFFIC.IAL USE ONLY
Power is su~~lied from a stabilized DC soi~rce of 5 voits. The consumed power is
0.5 kV�A.
' Each of the common bus switch sections identical in structural and electrical ver-
sion is connected to the common bus of the corresponding processor. Each section
contains its own swi tch which performs the functions of an electronic key and a
common bus expander that regenerates and relays signals.
The switch itself consists of an addressable monitoring a~nd state register (RKS),
address selector, int~rrupt signal shaping uni t, signal shaping u ni t for commun-
ications between two switch sections and a timer.
_ TI-~e state of the swi tch is monitored and controlled by information reading and
~ writing to the corresponding digits of the monitoring and state register. The ad-
dress of the monitor and state register and the vector interrupt address are con-
ferred on each section of the common bus switch. The address of the monitor and
state register is 17 7420. The range of addresses 177420-177436 is reserved to con-
nect several common bus switches to their monitor and state register.
The address of the interru~t vector is 540. If need be, the user can change the
address of the interrupt vector to 544 by means of jumpers.
The processor, referring to its own common bus switch section, displays the address
of the monitor and s tate register on the address buses and enters the necessary
information in the specific digits of the monitor and state register or reads them.
The designation of the digits of the monitor and state register is given in Table
3.3.
Each section of the common bus switch has its own timer that is started if the
processor must be connected to the additional common bus section, which may be con-
nected to the first or second processor or may be in a neutral position.
If the additional common bus section is in the neutral position, the following qp-
eratzng modes of the timer are possible:
if the additional common bus section is connected to the requesting processor
~ for 10 milliseconds, the timer of the common bus switch section of t.his processor
is reset;
if the additional common bus section is not connected to the requesting pro-
cessor for 10 milliseconds, the timer is reset during this time and digit 15 of the
monitor and state register is set.
If the additional common bus section is connected to one of the processors (A),
digit 12 of the moni tor and state register is set, the signal for interruption of
processor A is shaped and the timer is started upon request to the additional com-
mon bus section of another processor (B) in the common bus switch section connected
to processor A.
Processor A, having completed the interruption, may disconnect the additional com-
mon bus section by resetting digit 0 of the monitor and state register or may
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
FOR OFFICIAL US~ ONLY
Table 3.3. Functional Designation of Digits of Monitor and State Register
Digits Name Ftulc~ion
1 2 3
0 Request Set by request of the processor to connect the
- additional common bus section. If the addition-
al common bus section is free, connection occurs
immediately (no later than within 1 microseconcU.
If the additional conmlon bus section is occupied
by another processor, digit 12 of the monitor
and state register in the section of this pro-
cessor working with the additional common bus
section is automatically set and the timers of
both sections are switched on. If the processor
working with the additional common bus section
does not release it and does not reset digit 12
of the monitor and state register of its own
section of the common bus switch during the
timer cycle, digit 0 of this monitor and state
� register is reset and emergency release of the
additional common bus section occurs. If the
processor releases the additional common bus
section during the timer cycle of the section
of the common bus switch of the requesting
processor working with the additional common
bus section, the additional common bus section
is connected to the requesting processor
6 Interrupt authorization Set by the processor to authorize interrupt of
the common bus switch in the following cases:
upon connection of the additional common bus
section, if the additional common bus section
is active ~nd is requested by another processor
and upon completion of the timer cycle. It is
accessible to the processor for reading and
writing
7 Connection Set for reporting to the processor that the ad-
ditional common bus section is connected to it
and for authorization for signals to pass from
the common bus to the additional common bus
section. It induces interruption together with
.digit 0 if digit 6 is set. It is accessible
for reading. It automatically sets digit 11 of
the moni~or and state register of an adjacent
section of the common bus switch.
9 Initial setting It is set to emit an initial setting pulse
(RESET) to the additional common bus section if
it is connected. It is automatically reset
[Table continued on following page]
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
Table 3.3 [Continued from preceding page]:
Digits
10 Interrupt authorization It is set by the processor to authorize inter-
ruption of itself upon completion of the work
of another processor with the additional common
bus section

- 11 The additional common bus It is set by the common bus switch by digit 7
section is coniiected to of the adjacent section of the monitor and
another processor state register. The additional common bus sec-
tion is occupied by another processor if bit 11
is set
12 Request from another It is set so as to inform the connected proces-
processor sor of the request for the additional common
bus section from another processor. It causes
interruption jointly with digit 6. It switches
on the timer. It is accessible to the processor
for reading and reset ~
13 Activity It is set to initiate occupation of the addi-
tional common bus section. It is accessible to
_ the processor for reading
14 Main power supply It is set upon the appearance of the main power
emergency supply emergency signal on the additional com-
mon bus section. It is accessible to the
processor for reading
15 Timer overflow It is set if the additional common bus section
was not connected by request during the timer
cycle. It is accessible to the processor for
reading
Note. The remaining digits of the monitor and state register are not used.
continue working with the additional common bus section, by resetting digit 12 of
the monitor and state register.
If digit 12 of the monitor and state register is not reset by processor A and the
additional common bus section will not be released by it, this situation will be
regarded within 10 milliseconds as breakdown of proc~ssor A and the additional com-
mon bus section is automatically disconnected from it.
Let us consider as examples some possible configurations of multimachine complexes
that utilize common bus switches.
The configuration of a two-machine complex with two time-shared processors PR1 and
PR2 with external magnetic disk memory NMD3 and external magnetic tape memory NML3
is shown in Figure 3.7. The time-shared external memory units NMD3 and NMT,3 are
connected to the common bus of grocessor PR1 and are accessible to it in the posi-
tion of the common bus switch key (position "A"). During this time processor PR2
can perform operations that do not require exchange with NNID 3 and NML3. If pro-
cessor PR2 needs to exchange information with these devices, several methods of
116
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
F(
� na1 oay~~ HM,q~ r~
Duv
NM,Q3 NM713
0
nur "
6 ,QononHU~enbHaA 0!U
(1)
O!U? ~
nP2 , 03y2' HMq7 IZ
Figure 3.7. Configuration of Two-Machine Complex With ~ao Time-Shared
Processors PR1 and PR2 with External Storage on NML3 and
NMD3 (T1 and T2 are terminal devices)
_ Key:
1. Additional common bus section
satisfying it can be organized by means of the control and informing digits of the
monitor and state register.
~ Method 1. Processor PR2 periodically sends requests to use the additional common
bus. Each such request causes an interruption in the processor working with the
additional common bus. But until the additionaZ common bus is required by this
processor, it extinguishes digit 12 (no later than within 10 milliseconds) in the
monitor and state register of its own section set during each request of PR2 for
the additional common bus. When PR1 completes operations with the additional com-
mon bus, it releases it and PR2 gains access to the devices connected to the addi-
tional common bus.
This method has the advantage that the working order of PR1 is determined simul-
taneously with sharing the external devices connected to the common bus between two
processors. If PR2 does not extinguish digit 12 within 10 milliseconds from the
moment the request occurs on the additional common bus, this fact is identified as
a breakdown of it and the additional common bus is automatically disconnected from
it. The disadvantage of this method may be regarded as the additional time expen-
ditures to organize periodic requests of PR2 for the additional common bus and to
process interruptions from these requests in PR1.
Method 2. Processor PR2, if there is a need for common devices, sends a request to
the additional common bus. If the additionai common bus is free, it is immediately
connected to PR2. If the additic~nal common bus is occupied by PR1 (digit 11 of the
monitor and state register of the requesting processor is set to one), PR2 sets
digit 10 of the monitor and state register of its own section to one and changes
the tasks requested by the additional common bus to the interrupt wait mode until
the additional common bus is free. Z~vo problems can be processed on the processor
in this case. PR1 releases the additional common bus after the exchange with the
shared (common) devices is completed. After the additional common bus is released,
there is an automatic interruption in PR2 which may connect the additional common
bus to itself and carry on exchange with common devices.
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
_ FOR OFFICIAL USE ONLY
J This method can be used only with distrib~.tion of common devices between proces-
sors. Breakdown of a nrocessor working with the additional common bus cannot be
established by this method (if only the processor working with the additional com-
mon bus did not break down prior to the request of the other processor for the
additional common bus). These two methods can be used in the system. For example,
if one of the problems whose functions is following the efficiency of PR2 is being
solved, method 1 is feasible when working with the common bus switch. Method 2 is
used to solve the remaining problems which require an exchange with common devices.
.
~ nP~ 03y1 NM~f 1 r~ Aun~l
0(U 1 U3.y.~
l7lU ~
OU/2
/1P2 D3y2 HM,Q? T2 Aq/ly2
Figure 3.8. Configuration of Ztao-Machine Complex With In`.ernal Storage Unit
OZU3 Shared Between Processors PR1 and PR2
The configuration of a two-machine complex with internal memory unit OZU3 shared
between processors PR1 and PR2 is shown in Figure 3,8. The logic of the processors
working with shared internal memory unit OZU3 may be similar to that presented
above. it is important for this scheme that the total capacity of the internal
- storage, including the common internal storage with which each of the processors
will work, not exceed the maximum memory capacity of the processor being addressed.
The maximum capacity of the internal storage unit being addressed comprises 28K
words for the SM-3 processor and 124K words for the SM-4P procQSSOr.
Different examples of making the equipment redundant by using a common bus switch
are illustrated by Figures 3.6, 3.9 and 3.10. The redundancy scheme that provides
for maintenance of system efficiency upon failure of one of two processors is shown
i~ Figure 3.8. However, devices connected to the additional common bus section are
not redundant.
~ O(!/1 � � ~
n~u ~~v
nPr .4u~
Q~
- 03.Y1 HM,Q1 yC0/ 03y2 HM~f2 yC02
Oul2 ~
' nP2
Figure 3.9. Example of Redundancy of Common Bus Switch (USO--control facility
integration device)
ll~
FOR OFF'ICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL YJSE O1VLY
Redundancy iipon failure of. any of the devices of the system,including the common
bus switch itself, is presented in Figure 3.9. An example of redundancy with simul-
taneous failure of several devices is illustrated by Figure 3.10.
~ OJI~
' A[U
r:u am nr~ n~r ~~r~~ ncu
o,~~; hM~; ycn~ c~~z yco2
i1~_'
~~ll ~
Figure 3.10. Redundancy Scheme of Several Devices
Systems having increased survivability can be designed by using a common bus switch
in combination with an interprocessor communications adaptor (AMS) of the "window"
type. An example of designing this system is given in Figure 3.11.
npf o3yf HM,4~ Tr
'd[~~
nr~ - nm
ac ..~tu ~1~
,7P~ 03y2 HM,,Q? T2
~"v~ l10f yco< mponent units
(a selector and driver) and which meet the requirements for connection to SM-3P and
SM-4P processors and dev~ces and controllers of external devices in the form of a
plug-in unit and whic;, mE.et the requirements of the common bus interface to com-
plexes of the international small computer system.
Each systems interface unit permits connection of up to six W controllers. The
W controller usually consists of two component units: a selector that determines
the address of the connected external device and that performs interrupt and con-
trol functions of the controller mode (it is installed in the plug and socket unit
of zone C) and a driver that performs specific logic control functions of the VU
mechanism (it is installed in the plug and socket unit of zone B) and also cables
for connection of the external device (installed in the plug and socket unit of
zone A) .
The BSI has regular installation. The signals of the common bus interface enter
the BSI through the common bus cable to the upper plug and socket unit of zone A
(A6) and emerge from the BSI through the lower plug and socket unit of zone A(A1).
zf there arE: two BSI in the BRS, they are connected to earh other by a cable in-
stalled between plug and socket unit A6 of the lower BSI and unit A1 of the upper
ssz.
182
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
If there are no other devices in the complex connected to the common bus inter,face
in series after the BRS, a common bus blind panel from the makeup of the complex
should be installed in plug and socket unit A1.
The power supply unit permits connection of a load up to 20 A(but not less than 1
A) to the 5-volt bus.
The configuration of the system for communicating with the facility (USO) occupies
a special place in the structural configuration. This is determined by the com-
_ plexity of design of similar systems and by the variety of possible configurations
of complete USO.
BKI-AV and BKI-DV units are arranged in the system expansion unit (BRS) installed
in the processor bay.
The systems for communicating with the facility can be configured from USO modules
(see section 5.2) connected via the USS-OSh/2K integration matching device. The
- USS-OSh/2K consists of a control unit (USS BU) and an interface unit (USS BI).
Each of the units occupies 6U.
The process of structural configuration consists of two steps: determination of
the composition of structural components that permit arrangement of the selected
composition of devices and the configuration of the complex.
During the first step:
the baseline complex of the international small computer system and the com-
position of auxiliary external devices from the nomenclature of the international
small computer system are selected;
the number of free standard locations in the bays of the baseline computer
complex is determined and the capability of arranging auxiliary devices in them
(in the AKB) is checked. If there are insufficient free locations, an additional-
ly o~dered bay is used. Configuration data of devices of the international small
computer system are presented in Table 5.2;
the number of free standard locations in the I3SI of processors and BRS is
determined and is compared to the number of auxiliary external devices (of second
type) required for arrangement of the controllers. Missing BRS are ordered
additionally;
the possibility of installing a'evice consisting of the available BRS in the
plug-in unit is checked if these dev.;.,es exist among the auxiliary devices. If
there is no BRS or if it is filled, an additional BRS is ordered.
The diagram for configuration of the bays of the computer complex is developed dur-
ing the second step on the basis of ergonomic and aesthetic requirements.
Electrical Configuration
183
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
The first step of electrical configuration includes finishing the structural-
logic circuit for connecting the devices of the computer complex, i.e., connection
of the interface units and controllers to the common bus and connection of devices
~o the controllers, expanders and so on according to the principles which are con-
sidered below.
Examples of structural-logic diagrams for the two baseline complexes are presented
in Figures 5.4 and 5.5.
CM-6i'0?,0~ CM.-~y02 ~A~UHiPGR.7E'P)
(3) JV~'
� D[, !U ~ 2~ i~' ULL' JO~ /7:/IlIAO
. - ~ 4 ~oui
` - �
.M :zcs ( - C - -,i.= np~uecCapa (5 ) C/ti-54cz (.v~~or;u~ens) (6 )
. ,z s , Y-,
a ~^,Y , � } ~ n..i nn
~ ' ? ^ - _ _ :,~,.T ~ � n n
~7 - . r n ~r o..
~
~M,-6300 (n
CM-3100
~
un
~1~~
36 (l
Figure 5.4. Structural-Logic Diagram of SM-1301.03 Complex
Key:
1. Controll~r 6. Storage device
2. Common bus input 7. Desk
3. Common bus output 8. Cable
4. Common bus blind panel 9. Controller
S. Component unit of processor 10. Floor
The following configuration characteristics of the SM-3 and SM-4 should be taken
into account when interface units and controllers are connected:
the common bus is physically realized in the form of main installation plug
and socket units on a plug-in unit (section A) of individual devices of the
18l~
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
nr�
CN-6102.01 CM-5407OS (Kor,rponnep) 3
~ xo ou/ ( 2 ) axa
CM-2JQ4 E? ~Poue~~OPv CM-5402 OS jNcKOnurene) A">
C~�' N30T 1370 H12 �
. _ _T.7`' ~TD~1.' iT`_~'n~~",' �
___L~.~~lli i !._r r~~w~,~n. ~.:.1:~
~ _Ty1~' 1.i~
( 4 ) - ~
_ _ ~ ~ : ~f- ~~;77 ?5 (N:ranu-en.ti) N�2
~ N~Oi 1370 N 12
rrf-b.Da 01 -
6PC
CM-~
10f '
;n' l33
(8) g .
. ,',y',
, `~o
c.~tv
~�s r~
Figure 5.5. Structural-Logic Diagram of SM-1401.03 Complex
Key:
1. Controller 6. Storage device
2. Common bus input 7. Cable
3. Common bus output 8. Floor
4. Desk 9. Common bus blind panel
5. Component unit of processor
computer complex (the processor, IZOT 1370 storage controller, BRS and so on) and
the common bus cable that connects these devices. The common bus of the devices
has a beginning (common bus input) and end (comanon bus output). If several de-
vices are connected through the common bus, the common bus input of the second
device (for example, the storage controller) is connected by means of the common
bus cable to tt~e common bus output of the previous device (for example, the proces-
sor) and so on. The internal storage (OZU) is connected to the co~non bus input
of the processor, to the common bus output plug and socket unit of the last device
connected to the common bus and a cottmlon bus blind panel is installed;
the length of the common bus should be no more than 15 meters;
the load on the common bus of the complex should not be more than 20 load
units;
_ 185
FOR OFFiCIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000400040032-8
FOR OFb'IC'IAI. USE ONLY
if the enumerated conditions are not fulfilled, an auxiliary device--inter-
face expander OSh (RIF) in the form of a plug-in unit and installed in the BRS--
must be used. The RIF permits additional connection of 18 loads;
an integration matching device (USS OSh/2K) must be ordered for use in the
modules of external devices with 2K interface (from the M-6000, M-7000, SM-1 and
SM-2 nomenclature). Structurally, the device is made in the form of 2 AKB--a con-
tro~ unit (6U) and interface unit (6U) which are installed in the SM-3 and SM-4
bays and are connected to each other by two cables. The interface unit permits
connection of up to 16 external devices to the 2K interface or up to 8 expanders of
15 external devices each.
Physically, the USS OSh/2K does not exceed two load units.
The set of conductors required for electrical connection of the complexes is se-
lected during the second step for the configured devices.
The third step includes checking the conformity of the output of the established
power sspply source consumed by the devices and selection of additional power
sources if necessary (see Table 5.2).
The power supply of SM-3 and SM-4 complexes includes that of the bays and the power
supply units of the AKB designed to supply power to the devices in these AKB.
The total consumption of the auxiliaYr component uni~s or devices in the plug-in
unit is determined during this step and the balance with the vower supFly sources
availabin in a given AKB is established. If the plug-in units are installed in a
separately ordered AKB, the power supply source conforming to the power consumed
by thE component unit must be selected.
5.3. Devices for Communicating With the Facility
Functional Capabilities and Composition of the Devices
The devices for communicating with the facility (USO) provide:
normalization of signals from resistance thermometers of all standard
- gradations;
temperature compensation of cold thermocouple junctions;
entry and conversion of 1ow- and medium-level analog signals to binary codes;
noise suppression of co~.nmon and normal types in the measuring channel of
an alog signal input;
~ digital signal input;
i.itiating signal input;
number-pulsed signal input-output;
- 186
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400440032-8
FOR OFFICIAL USE ONLY
digital sign~l output;
analog signal output;
autonomous retrieval of the initiating channel address;
information exchange with SM-3 and SM-4 processors through the cammon bus
interface.
The devices for communicating with the facility contain a portable normalization
unit (BNV), an analog signal input device (WA) and a digital signal input-output
device (WD) .
The portable nor.malization unit (BNV) is designed for:
normalization of resistance thermometer signals (gradations according to
- GOST 6651-78 and measurement range according to GOST 7164-71);
automatic compensation of the thermoelectromotive force of the free ends of
thermoelectric thermometers;
_ positive bias of the entire range of output signals of thermoelectric
thermometers;
transfer from individual cables that carry signals from the thermoelectric
thermometers and resistance thermometers to the common (group) cable.
The BNV is designed for joint operation with the analog signal input device WA in
the SM-3 and SM-4 control computer complex.
The unit functions under operating conditions provided by GOST 20397-74 for arti-
cles of group 3a; ambient air temperature of 5-:.:;'C, relative humidity up to 90�
at 30�C and atmospheric pressure of 630-800 mm Hg.
With respect to stability to mechanical effects, the BNV tolerates vibration at
fre.;uency up to 25 Hz with amplitude of no more than 0.1 mm.
The maximum number of sensors connected to one BNV is equal to 16.
The communication line of the BNV to resistance thermometers is three-wire. The
maximum cross-section of the strands led in by the cables is 2.5 mm2. The commun-
ication line of the BNV with the thermoelectirc thermometers is two-wire. The
range of the normalized output signal of the resistance thermometers is from 0 to
, 35 mV.
Power is supplied to the BNV from an AC system with voltage of 220 V and frequency
of 50 Hz. The consumed power is not more than 50 V�A and the overall dimensions
are 456 X 465 X 220 mm.
The unit functions in the following manner. Signals from the thermoelectric ther-
mometers are fed to the BNV, where the thermoelectromotive force of their free ends
187
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
is compensated for (and the band is shifted if necessary). The compensating
voltage is shaped by a bridge, to ane of whose arms a temperature-inedepent re-
sistor is connected. This resistor and the free ends of the thermoelectric ther-
mometer are in a space insulated from the surrounding air--a so-called passive
thermostat. The remaining components of the bridge are located outside the ther-~
mometer in BE 361. The number of bridge components depends on the gradation of the
thermoelectric thermometer. The number of BE 361 used in the BNV depends on the
version.
Signals from the resistance thermometers are fed to the unit and are connected to
the bridge circuit by a three-wire scheme. In this case a matching resistor is
placed in each conductor of the communication line with the resistance thermometer
and the total resistor of the conductor and of the matching resistor should be
equal to that indicated on the resistor label.
The signals of the resistance thermometers are :io~malized by the bridge circuit.
All bridge components are arranged in the BE 362. The number of bridge components
is determined by the gradation and measurement range of the resistance thermomenter.
The number of BE 362 used in a single BNV depends on the version of the BNV.
The total number of BE 351 and BE 361 in the BNV is equal to 16 in any combination.
The power supply to the bridge circuits is individual. Sixteen insulated circuits
of a single-stage parametric DC stabilizer arranged in groups of four each on in-
dividual printed-circuit cards (BE 389) is provided for this in the BP 121 power
supply unit.
The unit is made in the form df a special structure designed for suspended installa-
tion and is enclosed in a housing in whose side walls are openings for the input and
output cables. The openings in the rear wall of the housing are intended for sus-
pended installation.
The individual compensation wires from the thermoelectric thermometers are led in-
to the BNV from below through the central opening in the housing. Type KPKS-11
receptacles are provided for attaching them.
The analog signal inp ut device (WA) is designed for input and conversi~~~ of L~
voltages to a parallel 12-digit binary code from the facility sensors and a~so to
- receive control signals from the common bus interface and to transmit the results
of conversion to the common bus.
Depending on the use of the apparatus for tying to the common bus (the presence of
BKI-AV) and of controlling the WA measuring channel (the presence of BKU-AV) and
also the use of contact (BKK1) or contactless (BKTC2) commutator, there is a numuer
of versions of the analog signal input device of the international small computer
system (Table 5.3).
A block diagram of the device is presented in Figure 5.6. Signals are fed from
the sensors in thE form of DC voltages to the inputs of the distributing frame
panels based on two cards witl: metal-coated openings. Wires from the sensors and
1B8
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
~ :IAL USE ONLY
Table 5.3.
Nd. Versions
of
Item WA-0 WA-1 WA-2 WA-3 WA-4 WA-5
1 Plug-in interface unit (BKI-AV) 1 1 - - - -
2 Plug-in control unit (BKU-AV) 1 1 1 1 - -
3 Plug-in expansion unit (BI~t) 1 1 1 1 1 1
4 Plug-ln relay switching unit 2 - 2 - 2 -
(BKK-1)
5 Plug-in contactless switching - 2 - 2 - 2
unit (BKK-2)
The number of input channels in each of the WA versions is 64.
normalizing resistors of type 55-5 (1 watt, 1 kohm, + 0.05 percent) that convert
current signals (ira. the range of -5-0 to +5 mA) to voltage signals (in the range
of -5-0 to +5 V) a:ce soldered to the cards.
The distributing frame panel prov;.des connection of 64 two-wire analog signal
sources.
Signals from the out~,ut of the distributing frame panel are fed to the inputs of
two-plug switching rzits (BKK1 or BIQC2). The input signals are filtered to the
- BKK by a symmetrica?. RC filters and two-wire two-stage switching of them is ac-
complished on RES43 relays (BKKl) or contactless switches of series K190 (BKK2).
The signal is fed from the BKK output to the input of the scaling amplifier made
in the form of a plug-in expansion unit (BKR). The scaling amplifier amplifies the
input analog signals and provides a standard signal at its output (i:i the range of
-5-0 to +5 V) regardless of the range of inp+~t signals since its amplification
factor is controlled by the program method by signals coming from the BKU-AV unit.
Besides emission of control signals, the BKU-AV unit receives the format of the
~ control word from the BKI-AV, it decodes the numbers of the channel, group, unit
and amplification factor of the amplifier and carries out analog-digital conversion
of the DC voltages in the range oF 0-~5 V.
The exchange of control signals, addresses and data with the processor through the
common bus is carried out by the plug-in interface unit (BKI-AV). At the same
time (see Figure 5.6), one BKI-AV unit provides the capability of working with
sets of analog signal input devices in four directioas, thus permitting operation
of a processor with 1,024 analog input channels.
189
FOR OFFIi IAL USE O1~fLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-40850R040400044032-8
FOR OFFICIAL USE ONLY
CM-3 ~
cM-an ;
ui .
/yB9 0 -7 ' ,
~ ~ 6MN-AB / ~ ' ,
/ /
%
~ ~2~ 1 j 3 4 .
/ ynpaBneH:.-e / r - - - - - =
/ 6M.Y-AB (3' . I ' ' y9q-2~
k 6A'P-3 u 6h'P-4 6Ky-HB I�
~
I (~aH- ti ~ ~Ii - - . , ~
yeA-~ ~ I
I 6KP-1 I I I 6h'P=2 ,
I I I II I ~ i i 6KP , ~
I I DMh~-1 I I I I 6n'M- I I I
I 6Mn~-~ 2 FjKK-~ I
I ~ i ~ I ~ 6^~M'~ 6kk-l
~ I' ~ I~ I ~
I ~ ' 37 3` ~ I ~ 32 3P � I
~anccn n~ naHenb ~ nocco os /7pHeqb I
j koocca o� noHenb �
I ~ ~ ~ I 4 II I ~ I . ~
' oT oo I I ~
L=- aarvNK (5) 6~ I~~_ _Or aorvuKaB _ 64
J L~ Or dor~u~roB 64
_ - - - . - J
Figure 5.6. Block Diagram of Analog Signal Input Device: _>--control
circuits
Key:
- 1. Common bus 4. Distributing frame panel
2. Control 5. From sensors
3. To BIQ2-3 and BKR-4
The characteristic feature of the WA-1 compared to WA-0 is the use of contactless
switches BKK2 instead of contact switches BKK1. Components to protect the MOP-keys
based on stabilitrons are introduced into the contactless switch.
The main structure of the analog signal input device is a self-contained complete
unit havinn two modifications in height as a function of the equipment composition:
8U and 6U (U = 44.45 cm). Thus, the WA-0, WA-1, WA-2 and WA-3 have dimensions
of 8U and the WA-4 and WA-5 have dimensions of 6U. These complete units have
everything necessary for self-contained operation of the device, including power
supply sources, blowers and distributing frame panel for connecting the wires from
the sensors. Each self-contained complete unit contains (depending on the number
of the modification) a set of.plug-in units, each of which is a complete functional
assembly.
190
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
1
The analog signal input device has its own power supply system. The primary power
supply is a single-phase AC system (220 V and 50 + 1.0 Hz with deviations from the
nominal voltage by +10 percent and -15 percent). The power supply system of the
analog signal input device contains two power supply units: a standardized power
supply unit BP113 and power supply unit BP123.
'1'h~ ~~owPr c:on5umea Lrom the system by each analog signal input device is no more
than 150 V�A, including power to the plug-in interface block BKI-AV located in one
of the processor bays.
The digital signal input-output device (WD) is intended to receive signals from
the digital sensors and to send digital and analog control actions to different
mechanisms and the terminal devices.
The WD has 12 modifications (Table 5.4).
The digital input-output function and also the analog output functions are real-
ized by a set of functional modules: a digital signal input module (MVD)~ an in-
itiating signal input module (MVI), a pulse signal input-output module (MWI), a
digital output module (MVD) and an analog output module (MAV).
Each of these modules, when installed in the plug-in control unit (BKU), has an
output to the intraunit interface of the WD which provides the efficiency of the
modules in an arbitrary set in each BKU.
Table 5.4.
H~NMCHOBOHH2 H NOANyCCTBO ~YHKIIMOHaADH617I 6JIOKUO /'Z) ~ ~
~
p CV l+l 7 h
~1) ~ m (7)
MoaYBx,4Keuxo a a a a a a a -(6) ~
S ,,~pe, ~ T s. a `l
3)~ 4Y' 5~� w c~a m ~ m Y ~6
Y8~�0 I 1 I 4 - - - - - 1 1
YB1!-I 1 1 - 4 - - - - 1~ 1
YB'1�2 1 1 - - 4 - - - 1 1
YB;~�3 1 1 - - - 4 - - 1 l.
YB;1�4 1 1 ~ - 1 1
YB11�5 l 1 [ 1 - l - 1 ~ 1
Ye~l-6 - 1 4 - - " _ 1 1
YB1-7 - 1 - 4 - - - -
Y8~-8 - 1 - - 4 - - _ - 1 1
Y811-9 - 1 - - - 4 - - 1 1
YB11-10 - 1 - - - - 4. - 1 1
YB11� l t 1 l t - 1 - 1 . 1 1
- Key:
1. WD modification S. BKU-DV
2. Name and number of functic,nal 6. IQt
units ~ � Bxi"1
3. BK-DV 8� ~
~ 4. 9KR-DV
191
FOR OFFIC[AL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
FOR OFFIC'IAI. USE: O~NI,Y
The WD has the ::ollowing specifications.
Through the digital signal input channels (MVD):
the maximum number of digital input channels in one self-contained complete
_ unit is 256;
the input signal is a two-position type of positive or negative polarity;
there is optron galvanic isolation through each channel;
the input signal levels (logic "0"/logic "1") are, V: from 0 to 1.2/6 + 1.2,
from 0 to 2.4/12 + 2.4, from 0 to 4.8/24 + 4.8 and from 0 to 9.6/48 + 9.6j
the maximum noise of general type is 100 V.
Through the initiating signal input channels (MVI):
the maximum number of initiating signal input channels in one self-contained
complete unit is 128;
the type of input signal is a turo-position ini.tiating of positive or negative
polarity (an interrupt signal is emitted with the sensor in a state from "0" to
"1" or from "1" to "0")�
~
the search of the module address that caused interruption is autonomous;
the maximum search time is 20 microseconds;
there is galvanic optron isolation through each channel;
the input signal levels are the same as through the digital signal input
channels;
the maximum noise of general type is 100 V.
.
_ Through the number-pulse signal input-output channels (MWI):
the maxi.mum number of input-output channels in one self-contained complete
unit is 16;
the maximum frequency of the input pulses is 15 kHz; ~
the length of the input pulses is not less than 10 microseconds;
the length of the output pulses is regulated in the range fr~m 50 microseconds
to 1 second with one-off time ratio of 2;
the maximum output voltage is 48 V~
the maximum load current is 0.2 A;
~ 192
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400440040032-8
FOR OFFICIAL USE ONLY
the capacitance of the counter is 16 digits (15 digits plus the sign);
the input-output operating modes are controlled by special jumpers.
_ Through the digital signal output channels (MDV):
the maximum ritunber of digital output channels in one self-contained complete
unit i~ 256=
the maximum output v~oltage is 48 Vj
the maximum load current is 0.2 A:
Through the analog signal output channels (MAV):
the maximum number of analog signal output channels in one self-contained
complete unit is 16;
~ the range of the output signal is 0-5 V and 0-5 mA;
the time required to establish an output signal with error of 0.1 percent is
not more than 1 millisecondj
- the nonlinearity error is not more than 0.2 percent.
There is a number of BKU modifications with different composition of functional
modules:
BKU-DV-O--four functional digital signal input modules. It provides input of
64 parameters;
BKU-DV-1--four functional initiating signal input modules. The total number
of input channels is 32;
BDK-DV-2--four functional pulse signal input-output modules. The total number
of input-output channels is fourf
BKU-DV-3--four functional digital signal output modules. The total number of
output channels is 64j
BKU-DV-4p-four functional analog signal output modules. The total number of
output channels is fourt
BKU-DV-5--two functional analog signal otitput modules and two functional
pulse signal input-output modules.
The WD also contains two plug-in units: BKI-DV and BKR-DV. The BKI-DV provides
information exchange between the WD and the processor through the common bus and
also automatic search of the initiating channel address (the channel that requires
servicing); the BKR-DV realizes the capability of building up the digital input-
output channels in the syst~m.
193
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2047102109: CIA-RDP82-00850R400404040032-8
FOR OFFICIAL USF ONI,Y ~
Communications plug and socket units are installed in the BKR which can be used to
- connect the expanding modification of the WD (WD-6--UVD-11) by means of a flat
1.5 meter communications cable located in the set of installation accessories of
the WD. The input-output system is further expanded by connection to the second
' third of the WD device (in version WD-6 and WD-11) by a similar flat cable
through the same communications plug and socket units.
Besides two plug and socket units, there are four BIat-BKU communications plug and
socket units for external communications in the BIQt by means of which the WD bus
is isolated to the BK'~ units.
The external cables of the user axe connected by soldering to the functional input-
output modules through a distributing fram~e device aontained in the WD. Each
circuit should be completed by means of a wound pa~.r of wires connected to the
corresponding distributing frame co,~tacts. The distributing frame consists of four
distributing-frame cards with the capability of connecting 64 input-output channels
to each one. The cards have continuous marking of channels.
Power is supplied to the device from a single-phase AC system with voltage of 220 V
and frequency of 50 Hz. Ztao BP113 and BP123 power supply units are used in the
device. Current consumption at the level of 5 V by all plug-in unit~ of the de-
vice does not exceed 15 A for all versions of the device.
The main structure of the WD is a self-contained complete unit (height of 9U)
and a distributing frame panel (height of lU).
The self-contained complete unit includes BP113 and BP123 power suppJ.y sources,
blower units, a bus pack and network filter.
The distributing frame panels are connected by flat cables to the BKU-DV units
(each card has one BKU unit).
A block diagram of the input-output system based on the UVD is presented in Figure
5.7.
Software of the Device for Communicating With the Facility (USO)
The software of the device for communicating with the facility (PO USO) is a set of
programs to solve information gathering and processing problems from analog sensors
and digital input-output signals, to check the efficiency and metrological char-
acteristics of the analog signal input device (WA), to check the efficiency of the
digital signal input-output devicas (WD) and to localize malfunctions of USO hard-
ware in automated production process and scientific experiment control systems
operating in the control computer complex.
The programs for the PO USO are written in Assembler and operate under the control
of the PLOS-RV operating system (except for the tests contained in the PO USO,
which operate without an operating system),
The software contains:
194
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
1~()R ()I~NIC'IA1. II~F: ()NI.Y
cM-3n
(1) cM-an
06ryaA uir, ~o
seq-a=s~
~ ~ ~ . 6/rN-QB ~
, ~ ,
l Z 3 4 . ' ~
. ~ I
~ 6KP -,qB ' yB,Q-6a11
i I r 6A'P-,QB yB,Q-6�1f~ ~
1 I
. 1 5~r~ -G8 J-- _ ~011 l 6Ky-Lte a=l ~
I
i ' E^':�-:13 ~ aa~ll 6K.v-Q.4 -ool~
~ I ;K�~ ,,~3 n a�I~ I 6Md-=:S - o� i~ ~
- h 2 Z ti ~ I I
I - 6K~-tie oal~ ~ ~,,~y-,~le - ~ c, I
I rJVlll r al I
~J
---------~L ---------ll
- _ ~
yeq-6:1~ yB,q-6~i~ ya,q-s+� ~yeq-s-�
. ~ (4)
, r ~oaekiy
Figure 5.7. Block Diagram of Input-Output System Based on Digital Signal
Input-Output Device
Key :
1. Common bus 3. To sensors and actuating members
2. Distributing frame 4. To facility
the program "Metrology of the WA of the international small computer systemi"
the program "Test VK1"--a test of the WD controllerj
test of the WD modules~
user program LNMAS (linearization of nonlinear characteristics of sensors);
user program USRED (averaging of parameters);
user program USTAV (comparison of parameters to settings);
auxiliary programs;
WA driver;
control problem of WA driver;
WD driver; ~
195
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000400040032-8
FOR OFFICIAL USE ONLY
control problem of WD driver;
standard user problem.
The program "Metrology of WA of international small computer system" is designed
to check the analog signal input devices for func~ioning after they are installed
at the manufacturing plant, to check the efficiency and metrological characteris-
tics, to localize malfunctions of the analog signal input systems duri.ng acceptance-
turnover and periodic trials and also for preventive che~ks during operation of
the system. The program consists of four basic subroutines independent of each
other which provide:
input and storage of input data in the memory to execute the programs
determination of the reliability of the measurement results with issue of the
results of evaluationj
determination of the main error of the WA measuring channel--(y~) with issue
~ of the results o~ analysiss
determinatior~ of changes of the WA readings with variation of external fac-
- tors (y) and temperature (Yt) with issue of the results of analysis.
The program "Test VK1" checks the efficiency of the WD controllsr for all func-
tions performed by it.
The test of the UVL modules checks the efficiency of all varieties of functional
modules of the WD.
The set of software for the WA and WD is delivered to the user together with the
equipment.
Configuration of Devices for Communicating With the Facility
The maximum possible composition of the apparatus of devices for communicating
with the facility, serviced by a si.zgle digi*al input-output plug-in intsrface
unit (BKI-DV) and a single plug-i^ analog input interface unit (BKI-AV), is shown
in Figure 5.8.
The BKI-AV and BKI-DV units are located in the ,taizdard complete installation unit
having its own po~~er supply source of +5 V--BP113 and blowers and are installed in
the processor b�y or in the bay designed to include the interface units of the
peripheral device~ contained in the system.
Each of the BKI is designed to service up to four directions (four bays) (see
Figure 5.8).
Since the WG-O--WD-S modifications include a BKI-DV unit, only one of these mod-
ifications of the WD is required for the entire digital signal input-output sys-
tem. In similar fashion, the U'cTA-0 and WA-1 contain a BKI-DV and therefore only
one unit of these modifications is requ~.red in the analog signal input sys~tem.
196
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2407/02109: CIA-RDP82-00854R000400040032-8
- N'()R ()F'H'1('IA1. iltil~: ()Nl.ti'
~ f , .u ~ u. ~
~ ~ ' ,
yH~ U-S , - . . y9/j-6-11 i' yBq-6-17 .YBQ-6-1! '
~ ~ ~ L ~ , .
,4BA-6-l~ 9BQ-6-l1 ~ ,YBQ-6-J! i 9Bq-6-11 i
L~7' ~i .
yB,Q-6-11 , yBA-6-11 yB~f-6-11 9B~J-6-JJ ~ i ,
~ ~ ~ ~
' , .
a tuUNO 3~ MQ62n
K
aQT4UMOH U!/CRDQ- ~
~ _ HUTCqbtiO/.N' MCXO-
jMN�,l~B 4 H(13MO.H
fKN-AB . � ,
~ 3 . ,
. . ~ . Pc~aw :.:.1~n ' . . ' ' ,
~ \ ` � . ~ .
' L , o . m
~
, ,
'JtlA-0:l ~ , ydB-1.J 'JBA-2~3 ~ .yBN-?t3 ~ .
Q_r:.,"'I~ - ~
I~ ~ j
yBn-4.3 yBN-~~S yBN-4:5 yBN-4;5 . '
yBN-4;5 'I~ ~ Jd/7-4~5 . ~ yBR-4,5 YBl1-4~5 i~ '
+ I~ ~
'JB~~~ yBH-4:3 � '?8~4-4:5 I '?BN-4;J' ~
� I
, . ~ ~s A'0 206 1 ,
~ 4 ~ r ,s 1 .
~ ~
~
6NB~ 6NB~5 (5) Ka6enu o~ darvuKO~ 3,QC u rOKa
� i ' .
-r---- ~ .
` OT repMO.,e~cnB conporuBneduu ~ . � ~ ,
u ~epr~onao ~ '
Figure 5.8. Design and Configuration of Devices for Communicating With
Facility of SM-3 and SM-4 Control Computer Complex:
logic communications; --analog or digital input signals
Key:
1. Disi:ri.buting frame 4. Cable 1
2. Common bus 5. Cables from EN~ and current sensors
3. Cables to sensors and acutating 6. From resistance thermometers and
mechanisms thermocouples
Each additional analog input bay of the WA should contain either a WA-2 or WA-3
modification since these modules contain the analog-digital converter that services
WA-4 and WA-5 modifications (containing only commutators and an amplifier). �
The cables from the sensors approach from the pedestal and are attached along the
lateral wall of the bays. The cable wires are then soldered to the distributing-
frame cards.
Normalizing resistors for the current signals, additional filter capacitors (for
example, for additional smoothing of rattles of the contacts from the digital sen-
sors),fuses for the analog and digital output and so on may be located on the
- distributing frame cards.
197
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
FOR OFFI('IAI.. USH: ONI.Y
:.i.nce ~~act? uVA and uVD modification is structurally and electrically independent,
tYiey can be joined to each other in different combinations and can also be located
in a single bay with any other peripheral devices. However, onE should strive to
arrange the units that perform analog signal input functions and also digital sig-
nal input-output functions close to each other.
_ The signal normalization units of the resistance thermometers and thermoelectric
thermometers should be located at points of concentration of sensors, but not fur-
ther than 300 meters from the WA. Each BNV unit is designed to normalize signals
from 16 sensors and consequently a maximum of four BNV may be connected to each WA
unit.
It sizould be noted that the bay does not contain any WA and WD modifications;
therefore, any number of USO units is supplied in independent bays in specified
SM-3 or SM-4 control computer complexes.
USO Configuration Based on Devices Having Output to Junction 2K
The presence of a common bus interface matching device and 2K-USS OSh/2K interface
in the SM-3 and SM-4 nomenclature permits the use of the entire nomenclature of
ASVT-M (M-400, M-6000 and M-7000) and SM-1 and SM-2 devices and modules having
output to the 2K interface as devices for communicating with the facility.
The nomenclature contains:
low- and medium-level analog signal input devices (noise-protected WAS-2 and
s high-speed WAS-1);
digital signal input-output device (WVDS);
relay output device (WR);
high-speed analog signal input device (WB-100);
a set of modules from the SM-1 and SM-2 nomenclature.
The set of modules for the SM-1 and SM-2 includes analog-digital converter modules,
commutators, sampling and storage circuit modules, normalization modules, filtra-
tion and galvanic isolation modules, initiating and number-pulse signal input
modules and digita.l and pulse-signal output modules.
Systems for communicating with the facility, different by the number and type of
channels, can be configu.r.ed from the USO modules connected through the USS-OSh/2K
junction matching device.
The interface unit (USS BI) provides installaLion in it of up to 16 USO modules
and interface cards of external devices. Each location on the 2K junction in the
USS-BI is equivalent to independent connection of the module to the common bus of
the complex with servicing through the program channel and through the direct ac-
cess channels to the memory of the complex.
198
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8

APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400040032-8
1~()it ()I~I~I('IAI. Ittil~: (1NI.Y
't�ho nuuJ~r<