JPRS ID: 9766 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY

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• Content Type: REPORTS

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JPRS L/9766 -
1 June 1981
~
~
= USSR R~ ort
p
CY~ERNE`TICS, COMPUTERS AND
AUTOMATION TECHNOIOGY
(FOUO 14/8 i )
~ -
F~IS FOREIGN BROADCAST INFORMATION ~ERVICE �
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,
- JPRS L/9766
1 June 1981
USSR REPORT
CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY~
(FOUO 14%81)
CONTENTS
MICROCOMPUTERS
'Elektronika SS' Microcomputers and Their Application 1
~ ROBOTS
Programmable Robots 74
Classification of Robot Control Methoda and $ystems ..............o.,. 77
Robot Sensor Systems 80
Human Oper~tor-Robot Communications Systems g6
'Bars' A lgorithm System ........................................o..... 99
~
SOFTWARE
Abstracts From the Journal 'Programming' 100
I.anguages for Computer Graphics 103
APPLICATIONS
New Book on Computer Applications in Local Industry 116
Use of Keyboard Computers in Local Industr3~ Reviewed 118
Descriptiou and Recognition of Objects in Artificial Intelligence
Systems 120
Microcomputers for Investigation of Communications Channels 126
- a- [III - USSR - 21.C S&T FOU4]
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- CO:IFERENCES, ORGANIZATIONS
Conference Held on Problems of Developing and Using Computers ~
With High Throughput 127
The School of Computer Mathematics and Cybernetics on the Watershed
of ~`wo Five-Year Plans ................~...............e....,........ 12�
PUBLICATIONS
- New Textbook on Work of Computing Installations 135
~ Identification of Magnetic Componenta for Autumation and 139
Computer Technology �~~��~~~~~r~~~~~~��~r��~~~~~~~~��~~��~����~~��~�
142 '
New Book on Control Computer Complexes
Automated Control Systems for Machine Building Enterprises 144
156 ~
Date Transmission and Processing Methods
~
New Book Considers Early Stages of Designing Industrial Control
Systems .............................................o.............. i58
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MICROCOMPUTERS
UAC 681,32-181.48(47+57)
'ELEKTRONIKA SS' MICROCOMPUTERS AND THEZR A'PPL~CAT~ON
Moscow MIKRO-EVM "ELEKTRONIKA S5 " I IKH PRI~ENENTYE in Russian 1980 (signed to
press 3 Nov 80) pp 2-63, 73-84, 154-157
[Annotation, editor's foreword, introduction, chapters 1 and l, sections 4.1 and
4.2, hibliography and table of contents ~rom book "'Elektronika S5' Microcomputers
and Their Application", by Mark Petrovich Gal'perin, Vladimir Yakovlevich Kuznetsov,
Yuriy Aleksandrovich Masienikov, Vladimir Yefimovich Pankin, Viktor Panteleycwnovich
Tsvetov and Aleksandr Ivanovich Borovskoy, Izdatel'stvo "Sovetskoye radio",
35,000 copies, 160 pages]
[Text] The design principle and the hardware and sof'tware of a series of domestic
microcomputers are discussed. An analysis is made of ways of solving questions
arising in the application of nii.crocompuzers in instruments, equipment and~ control
systems; practical recotmnendations are given, as well as examples of the use of
microcomputers of the "Elektronika SS" series.
Intended for specialists involved in the development and introduction in various
sectors of the national economy of control and data processing and transmission
equipment based on computer technology facilities.
Editor's Foreword
A broad range of problems associated with the development, series production and
application of microprocessors and microcamputers has evoked the steadily growing
interest of engineers, scientists and technical managers at vaxious levels working
not only in the area of radio electronics, but also in other areas of the nat-ional
economy. This interest has been occasioned by considerable success achieved in
recent years iii our country and abroad in using m~croprocessors and microcomputers
as universal progratmried logic devices as part o~ the atr~~cture of ineasuring in-
struments, machine tools, industrial and marine automation equipment, in equipment
- for light industry, the ~ood, oil and gas ~ndustr~es, in medical equipptent and in
- agricultural machinery and units.
The use of micropzocessors and ~qicrocamputers has ~ade ~ossible the appearance of
fundamentall}r new consumer properties Por products; in ~qany ~ields o,~ engineering
their use is a necessar}r and important condition ~or competition in the world
market. At the same time, the use o~ ~uicropxocesaors and ~icrocomputers has made
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, the following possible: a dxasttc i~s~~xo~e~e~t o~ ope~c$t3~g xe],1$bi~,t.~y az~d the
possibi7,ity o~ se],~-di,~~~os.~s o~ ~1,~uz~ctions, a red~xc~inz~ ir~ ~oWex consu~nption, ,
a reduction in the titqe requixed for and the laboz 3,nter~siveness o~ de~Yelo~ing new
~ kinds og equiptqent an.d n~odexntztng it! and a reductfon in weight and o~exa~.1 size.
At the present time domestic industxy~ is ~roducing an extensive .list o~ micropro-
~ cessors, memory and input/output ~arge-scale tntegrated ctrcuits (LSIC's), as well
~ as completed models o,f mfcrocomputers. As an example can be named such LSIC series
as the following:
The K-580 series cantaining an eight~bit single-chip microprocessor, a RA,M [random
access memory) and lt~^ii [read-only memory] LSTC, as well as a para11e1 and serial
interface LSIC, fabricated according to the n-channel bSOS [metal oxide semic~nduc-
, tor] technology.
' The K-589 series, the basis oP which is the so-called "microprocessor sections"
~ executed wi::h TTL [transistor-transfstor logicj circuits and Schottky diodes.
The K-587 series constructed an the basis of the complementary MOS technology.
The K-584 series, executed with circuits with injection logic, etc.
' Among microcomputers being produced can be named the "Elektronika-NTs," "Elektron-
ika SS" and "Elektronika-60," etc., models. A number of c~mputers are in the con-
cluding stages of development and organization ol series production. Software and
debugging facilities, which are being improved constantl}~, have been created for
a11 computer models. SuPficfent know-how has been gained in using these computers
- in various fields of science, engineering and agriculture. ,
Computers of the "Elektronika SS" series occupy a merited position. The first
model of this series--the "Elektronika SS-O1" multiboard micracomputer--was created
~ in 1975, and in 1976 began the production of the "Elektronika SS-11" single-board
mic:rocomputer. Several more models ~f microcomputers of this series are being
produced at the present time.
Some distinctive features characteristic of the "Elektronika SS" microcomputer
series can be mentioned:
The presence in the series' structure o~ single-board microcomputers and additional
modules (memory and in~ut/output), as well as multiboard microcomputers with uni-
_ fied software and debugging facilities, unified circuitry an~ design and technolo-
- gical solutions, and a uni~ied production and metrological base.
The simul~aneous and eyen advance cxeation o~ so#twaxe, in xe].aCion zo the develop-
ment and staz~ o~ the pzoduction o~ the microco~qputex's themsel,ry~e~,,
- Broadly comprehensive work on fitle creation o~ ~nodels o~ ~quipp~ent, instruments and
- systems based on ~i.cxocomputers concomitantly~witl~ the dev~l~o~ment of ti~e computers
- themselves.
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- The design pxinciples o~ the iqost populax mode7.a o~ the "~~ektxor~ika S5'~ sexies
' of microcomputeTs, [heix soEtwax'~ and debt~gging ~;aci~ities, as we],7~ as ~uesttons of
, procedure and ex~erience gainezl ~n creat~n g equipment based on ~tfcxocrnqputers ~ox _
various seckoxs o~ ~he nationa~ ~conomy, are descx~,l~ed tn this hook~ ~uxzhexmore,
all questions are discussed by the authors as tneeparable paxts o~' the overall
_ problem.
~ Introduction
" In recent years micropxocessors and mi.crocomputers have evoked great interest among
a broad ranbe o~ special.ists. Conduc~,~re :to a great extent to satis~action of this
_ interest havP been a great nu~lier of publications in scienti~ic and technical perio-
dicals and a number of books by domestic and foreign authors discussing the funda-
- mental pr.inciples of the design of foreign microprocessors and microcomputers and
of their application. However, the work of apeciali!~ts has been complicated by the
lack of necessary information on domestfc models of microcomputers, since ~ournal
publications as a rule have not made:i.t possible to form a complete idea of a spe-
- cific microcomputer or, even more so, of an en~.ire series. _
The authors o� this book have endeavored to fill in this gap with regard to only
- one series ~f microcomputers produced 'by domestic industry, the "Elektronika S5."
The first chapter of the book is introductory and cdntains general ideas relating to
the application of microcomputers and fundamental concepts without which it is
- difficult to read the material following it.
~ The second chapter is devoted to a description of the first generation of the
- "Elektronika S5" series of microcomputers, designed according to the p-channel
MOS technology (p-riOS) .
In the third chapter. are discussed the key principles of tne design of the "Elek-
tronika S5-21" microcomputer, designed on the basis of a single-chip 16-tit micro-
processor, according to the n-channel MOS technology (n-MOS). The brevity of the
- exposition was determined firstly by the succession of many fundamental soluti~ns
discussed in ch 2 and, secondly, by the fact that the development of the n-channel -
generation of the microcomputer series is still continuing.
The fourth chapter is devoted to questions relating to microcomputer software and
contains a number of practical recommendatiox~s relating to the development of
~ software for specific applications.
In ch 5 know-how gained in the application of microcomputezs in vaxious ~ields of
engineering ~s generalized, a nusqber o~ standard technical so7.utions axe proposed
and a descripti,on is gi~en o~f know-hoW gafned in organizing woxk xela~ing to the
application o~ micxocoWputexs.
In this book the authoxs have endeavored to show that the si~qu~.taneous cxeation _
oz microprocessoxs and taicxocom~uters, their #ntzoductio~ in v~axioua instruments -
ans systems, and the organization o~ the sertes production o~ micracamputers and
equipment based on them re~resent work suan2t$esrient princi~le~ w~11ch. m~ke it possible
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to solve highly itqpqx'tant technfcal atnd eco~omfc probletqe ~d to achie~s the ;
enormous nat3;ona7, econotqic sa~ing h?}~ich. ppCent~a7.1y~ ~n the Y'~xy idea o~
microprocessox engineering. ~
The authors wi11 be grateRul ,for a11 ca~nents wh~,ch read~xs o~ thts book deew I~
necessary. ~t ~,s requested that sugge~tions and co~ts be~sent to the ~ollowing
address: Moscow, Glavpochtamt, a/`ya 693,.Tzdatel~stvo "~o~Yetskoye radio".
Chapter 1. Microprocessox Technol.ogy and Tts Application
1.1. Mi~roprocessors--a Revolutton in Engf.neering
The appearance o~ microprocessors, ~emorp and input/output LSTC's, as we11 as �
microcomputers among electronic engineering product~ which ha~ve been developed and
series produced has been evaluated by man}r experta in the ~ield o~ radio electronics
as a revolutionary phenomenon cot~ensur3te in signiffcance with the appearance in
the 50's of the first series-produced semiconductor devices.
These declarations were made five to seven pears ago, and today the time has begun
to determine the first results of woxk re'!ating to the applica~ion of micxoprocess- -
ors and microcomguters and further ways o# developing this new trend in engineering,
as well as to evaluate the revolutioniz~ig influence of microprocessor technology
on various sectors oP the nat3onal economy.
Among the majority of specialists in the field of classical computer technology
the appearance of microprocsss~rs and microcomputers, especially in the first few
years, did not evok~ notable enthusiasm. In fac:t, the simplicity of structural
solutinns, the not-too-developed instruction sets, the short word length and slow
speed could be considered a betrayal of the main idea of computer technology-- -
the creation of computers with the maximum possible computing resources. A certain
amount of time was necessary to understand that microcomputers represent the most ,
mass-con~umption-oriented and most inexpensive class of camputers and that thPi.r
appearance has paved the way for comguter technology to ~nter those areas of ;~sman
activity for which two barriers--cost and ready availabiliCy--earlier seemed o be
insurmountable. '
In. order to evaluate the value of the appearance of micraprocessors for spec:-''_sts,
scientific teams and entire branches o~ industry involved in the developmen` ind -
series production of semiconductor technology produets, it is necessary to c~ .~ider
two fundamental ~eatures o,~ tY~is new cl.ass o~ electronic engineering product::.
The first feature is the univexsality of the application o~ a microprocess~~ -nd a
- mi crocouiputer. With an fncrea~e in the degree of integxation to a~ew ~b ~~z - a d
' elements on a chip it would have been necessary ~o de~Vel.o~ an integxat~e ~~~:�.~it =
(TC) nomencJ.~tuxe exceeding by hundxeds o~ timea the nomencla~u7ce pzo~.;' ; ~~day _
for circuits wi,th a mediutq 7,e~e7. o~ integxation, in oxder to sup~oxt '~~~~~,~~nd of
_ a11 branches o~ industxy. ~ wicxocomputer conatructed with znfexopz-.c c,?':- and
especially a micxocom~utex on a single chip, ~.s the most uni~vel =reviously
known electronic logical components, c~hich ~ar~ pex~oxm the ~'ur~ct..~z-. pec~.fic _
piece of equipment de~ending on ~he in~ax't4atton entexed in ~its p~�~.;;: .~V~~ -aemory.
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There~ore, the appeaxance o,~ ~q~cTOp~oc~~~axs u~de tt p~saible not on~y~ not fio
increase the ZC no~qenclatuxe� bu~ e~rezl to xeduce ~.t as co~axed With. pxe~yious
generations.
The second feature. cl,o~el.p a1~.~ed to the ~~,~c~t, ~.s the exce~t~oz~a~l,~y ht.gh system
� design properties o~ this class o~ el.ectronic coiqpon.ents. ~11 pxev~.ous generations
of compenents designed for use tn compufiexs, d~gttal auto~tton equipment and
control systems were tied to decis~ons sqade !or tAe system as a whole with regard
to such parameters as suppl}r voltagas and ~echanfcal and clitqa,tic tn~luences, since =
they represented too sma11 a"buildtng block" ~oT construcring these products. A ~
- microprocessor and a microcomputer tn manp fnstances constitute the basic part of
the system directly tied to controlled spstems and infoz'~aation sources and carrying
in their so~tware an algorithm for operat~on of the enttre syste~n. This feature
has forc~d developers oP LSTC's .for �rhicroprocessora tc~ pose and solve problems
relating to selection of the type of interface, to implement the possibility of
- linking with various information sources and receivers and to create software which
~ is not inferior in complexity to the sof tware of minicomputers. And, finally, in
all its magnitude has appeared the problem of setting up a well reasoned procedure
for interaction with microcomputer users making poseible the required dynamics
for the increase in demand ~or and the production of theee products.
A detailed discussion of what a microproceasor and microcomputer is has been pre-
_ sented at the present time in a number of books and periodicals published here at
_ home and abroad [1-5]. Having availed ourselves of these~ let u~ give only some
concise definitions. -
_ A microprocessor (MP) is a functionally complete unit with a fixed interface, con-
structed with LSIC's and consisting of an arithmetic-logic unit (ALU), internal
registers and a control unit and designed for implementation of a specified in- -
- struction set [1].
Ay an interface is meant a system of address, inforniation and ~ontral lines which
is designed for coupling units and for which a time chart has been specified for
the flow of inf ormation.
- A microprocessor set (MPK) is a combination of microprocessor and other IC's com-
_ patible with respect to structural design and fabrication technology and designed
for use in microprocessors and microcomputers.
= A microcomputer (microelectronic computer) is a co~putez consisting of a micropro- -
cessor, a semiconductor memory~ and means ~or coupling with peripherals.
_ 1.2. Economic E~.~iciency o~ the Use of Microcaa~puters
A national econotqic saying fx'om the use o~ tqicroco'n~uters fs achi,e~ed pximari~:,y
~ on account o~ a d~castic ~ceducti;on in the labox ~,ntens~:V~nesB a~d co$~ o~ products
_ constructed on their basfs, im~rovement o~ the auf;tab~7,tt~r o~ thes~ pxoducts for _
quantity productian and o~ thei~c ~uneticn~ng xeliabf~tty, as w~7.1 as on account of
the endowmet�t o~ these products wfth ~undamentall~ ne~,r consu~e~ a4vantages, Tn
addition to the mass consumptfon pxopextfes and lva coat ehaxactexist~c oi' .
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tq~cracomputers, as We~,~, as. ~he~ un~~~xsa~ft}r and the~ pxaSxa~uaab;~1~..~~* p~ the~;x ;
functions, th~y a~sa ~ossess the pxopex~y~ af~ tncoxporalat~f;ty, A n;~cxocotqputex ,
is designed pximarily~ ~or use dixe~t~.y p~x~ o~ d~~~ex.ert~ k~,nd~ o,~ equ~,~ment--^ ;
units, instxuments, mach~ne tool.s, da~t~t tran~a~.tes3on~ equtpmetlt, t~~t; med~cal and
$gricultura~ equipm~nt~ etc, ~n connection w~i.th th~s, ~t t~ ~`ea~~fiiJ.e to div~.de
~ a11 microcomputexa in~o thzee grou~s, . '
Multib oard Microcomputer ~
A multiboard microcomputer is a co~puter in which th~ pro~essoz, ~torage deuices
and input/output units are implemented as indeper.dent bo~rds joined in a single
structure together with control and dtsplay units and the power supply and designed
for use as an incorporable unit ox as an ~ndependent tnstrument. Tt can be said
that a multiboard microcomputer repre~ents a readily avaf.lable and inexpensive
minicomputer constructed fxom micropTOCessor set LSTC's.
Single-Board Microcomputer
This is a computer in which the processor and storage and input/output units are
executed on a single board, a~ a rule not having ita own power supply and control
and display units, and desi.gned for use prfmari~.y as an incorporable piece of
equipment.
Single-Chip Microcomputer
This is an LSIC containing a processor, a working storage, input/output channels
and, as a rule, a permanent (semi-permanent) storage. In other words, it is a
microcomputer executed as a single LSIC and used only as an incorporable unit.
The incorporation of single-b~ard, single-chip and, in individual instances, multi- '
board multicomputers, too, in user's equipment is not only not primarily a problem
of the structural arrangement of this eqnipmenC.
It is primarily the replacement of electronic, electromechanical and mechanical
- units ("hard logic") with a universal unit (a microcomputer) whose operating
routine unambiguously determines the operating algorithm of the entire equipment
as a whole. This solution of the problem ~,~aeu ~~::es it possible to achieve a
quite high level of standardization and uni~ication a~ engineering solt~tipns and a
drastic reduction in the labor intensiveness o� and of the time required for de-
veloping and modernizing equipment based on microcomputers. It can be said that
- from the management viewpoint the use o~� microcomputers is one method o~ resolving
the contradiction between the voluute of pxo~ect wozk and liiqited labor resources.
' It is also the intzoduction o~ ca~~uting pxoceduxes and da,ta ~xoces.$ing into
equipment, infoxi~ation sources and t~anipul.atoxs, endowing thepi with new consumer
advantages. Zt is a~.sq simp].i~icat3,on, xeduction o� the coaC $nd i~{pxoyez~ent o~
the reliabil,i.ty p~ the hardwaze and so~twaxe interface not on~,y p,f computers, but
also of the entixe no~{e~~~,atuxe o.~ data reception and tr~napqi;~sion e~uipzqent,
measuring instrcuqents, as we1~, a~ equiQment whose co~qbination into ~ uni~ied
~ system was exceedingly di~~icu],t in connectton Frith the 1a,ck oi` computing equipment
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- accessib~e in te~;p~~ o~ cp~t a~d quan~i~p~ produc~ion which. Gou~,d be inco~'pox'~ted
inzo equip~ent~
The cha~ge ~rom desig~ing equip~en~ b~~ed on fntegxate.d crnqponesl~~ (:'~ha7rd '7.ogic")
to design#ng even sitq~l.e unifis based on micxoco~qpu~exs x~p~Te~ents a ch$nge ~o
- designing a"systetq in z~inia.ture~" ~ri add~:tion ~o im~xove,~4ent o.f an engineerFs
_ labor productivity, this change certainly ~equ~xee an itqpxaPe~ment o~ professional
mastery and involves the ~ppearance ot` new interesting aspects in everqday design
work, which is the goal o,E each eng~nee~.
A reduction in the cost and labor intensfveness oP equigment is achieved no~ only
~ on account o~ using LSIC's with a high 1eve1 0~ integration and 1~ow cost. Single-
board and multiboard microco~pu~ters pxoduced under condtttons o,f large-1ot pro-
duction and designed ~or use in various er.gineering fields aze economicall~ more
advan.tageous than specfal-purpo~e electrontc units developed for each kind of
- equipment and produced in sma11 lots. Thts is especiall~ important for branches
of industry which traditionally have not had sufffcient ~,nowhow~ in th~ development
and production of radio electronic components and units but have been forced to
create modern models o~f equipment uttlizing electronics. An example 9f such
enterprises is plants of the machine tool building indugtry and of the machine
buildi~ng industry for light industry and the food industry, agriculture and the
- like. It is extremely important that the conversion of a specific type of equipment
to microcamputers make possible further i~~provement of the economic parameters of
this equipment in proportion to improvement of production technology practically
without additional expenditures of time and labor on the part of the manufacturers
- of the equipment. It can be said that the application of microcomputers represents
a method of "transferring" the latest ach3.evements in modern microelect.ronics
characteristic of its technological and organizational approaches into other non-
electronic branches of industry.
However, a great national economic savings, which is the basis o~ the very idea of
- microprocessors and microcomputers, remains only potentially achievable until
equipment based on it passes through all stages of development, mastery in series
- production and introduction into everyday practice. All these problems are ex-
ceedingly complicated and they call for preparation not only of the phyaical base,
bt~t also the training oP speci&lista fn a specific field of knowledge, who com-
pletely have mastered their basic profession and simultaneously have a profound
understanding of the possibilities o~ micxoprocessor equipment, their programming
_ and the principles o~ designing systems based~on microcomputers.
If attention is paid to the exceptionally r~p~d progress in semiconductor technolo-
gy, which has made it possible to replace generations o# micxopxocessors every two
_ to three years, then it becomes underatandable that a s~,tuation couZd be created
whereby the cycle of the czeation and series-pxoduction ~stezy v,~ a new model of
an instrument or Qthex kind ofl equipment whp5e pa~'a,~netexs are direG~ly. dependent on
the technical and economic chaxactexistics o~ the nti.exocomputeX~.inc].uded in it
proves to be consi,deXably Zongex than the ~exiod ~or the xe~p~,acep~ent o~ generations
- of technology, and, consequently, the ec~ui~~ent wou],d tuxn out to be obsolete even
before the start o~ series pzoduction. The re~olu~ion o~ this conXradiction has
proven po~sible only upon ~u1fi11~aent o~ ~~e ~ollowing conditions.
. 7
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~
~
Condition ~
- This is the co~prehensive si.~q~tltaneous sol.ctlC~;on o~ a1,1, pxob~ex4a as�soctazed, on the ~
one hand, wi.th the cxeatiozZ o~ the entixe satcxoprocessvx aet o~ T~S~C~s and o~
microcomputers I~ased on th.eut and with tY~e pxe$ar~tio~ ~ox and organtzation of their
series production, and on the othex, with the cxeation o~ a bxoad nomenclature of !
uni.ts, instruments and s}*stems based on m~crocamputers fn various fields of engi-
~ neering and with the ox~ganizatfon o� their series production. FuT~illment o~ this _
condition is made pos~~ble on the bai~is o~ longterm inteTindnstrial programs which
regard as a uni~ied whole the entire proceas ~rozn the developmen~ of microprocessors
to the serie~ production of equipment based fln them.
.
- Condition 2.
This is the creation at a new technological }.evel of new models o~ microprocessors
, and microcomputers which are compatible to the maximum possible extent w~ith com-
- puters developed eariier with regard to sof tware, external interf ace and design,
because of which the user's changeover to new models of microcomputers does not
cause insurmountable dif:ficulties and makes possible improvement of the charac- C
teristics of equ~.pment.
A series of Lzodels of microcamputers united by common softw~re, principles cf inter-
face organization and designs, we wi11 ca11 a microcomp~iter series. The co~.:cept of
. a series calls ~or, simultaneously writh the ensurance of succession, also the
definite improv ement of all technical and economic characteristics when changing to
new improved technological and circuitry solutions.
At the present time domestic industry is producing a sufficient number of models
and s~ries of microcomputers which vary in terms of characterj.stics [6] and which
diffei from one another in speed, word length, memory and interface caFacity and
principles of organization, utili~ation characteristics and areas of application. ~
These include the "Elektronika-60" and "Elektronika K1-10" microcomputers and the
"Elektronika NTs" and "Elektronika S5" microcomputer ser.ies [7-9].
1.3. Composition of the "Elektronika S5" Microcomputer Series
- The following are the key components of this microcomputer series: a microprocessor _
set of LSZC's, single-board microcomputer~, a sEt nf microprocessor ~unctienal
modules (MFM's), single-chip microcomputers, multi-board microcomputers, seftware
and software debugging facilities. A methodology for the application o.f micracom- _
puters in equipment and systems has been developed for this series.
By microprocessor functional modules of ~he "Elekxoniica S5" series is to be under-
- stood electronic units constructed with ZSZC~s o~ the micxopx'ocessox set and de-
signed to broaden the kunctional capabilities o~ a sing7,e~boaxd ~n~,cxocomputer with
respect to n4emoxy ~a~~city~ and cptq~osftion and num,bex o~ in~ut/aut~ut channels.
- Up to the pre~Pnt tit~e the "~~.ektxonika S5" microco~pixtez sexies h.as. included
three generations: single-board and mu~tiboard t~icxocomputexs constructed on the
basis of a microprocessor set of LSICFS e~p].c~ying the p-M4S technology; single-boaxd
~t
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and cquJ,tib~+ard n~i,cxacozriputexs aAd I~}~ c(]i1~�txucted on Xhe ba~i~ o~ ~ micxo~zo--
cessor set o;~ ~,~~C~s ~~pJ,oying xhe ~~0~ t~ectul~~~~y; a~d .s.i~~x~~ch~~p J~icxacomputexs
_ employing the n-chan~e~ ~echnp],ogy~. `
' The following chapters o~ this book are ��de^~o~~d to a descx~~rioz~ oR thr~ ~izst two _
generations o.� u~icroco~puker~ and to ex~erience gsfned in thei.x app~,ication. The
third generatfon represents fihe l,ogical development o~ the zqain line of this ser-
ies--the endeavor toward maxfmally 5ma11 c~nfigurat~.ons; nevertheless it h~as a
number of specific ~eatures as compared with Che two previous generations of the -
series which are such that a descr~ption o~ the ~tructure of single-chip microcom-
puters and their areas application f~ worthy~ o~ beco~ing the subject o.f a
sep
I fP b ~ ~P
4 S
- 3'tS
PAB
3 ~ ' 8 ~ o ~e KoNCm~n
~a� ~
(~/HM ,?ORPOC
1~
4>PCM l~~n~ ~
~Za .
ycK Q~nrudoNUe 13 )
- 14 ) Ta~7~ep cdpoa -
Figure 2.3. Diagram of MPU LSIC
Key:
1. Address of word in MROM 8. Control actions
2. RBM [microinstruction base 9. Constant decoder
- register] 10. Interrogation
3. ShIM [microinstruction informa~ 11. MPA [microprogxam automaton]
tion line] 12. Start -
4. RSM [next microinstruction 13. Wait
register; ~ 14. Reset timer
5. RAV [return address register]
6. RTA [current address register]
7. Condition line (fram ALU)
The MPU LSIC consists of two sections: The ~ixst ~orms a mi.cxoin~tx'uction address
and contains a ~qicxoin~truction base register (RB~I), a curxent addxess register
(RTA), a next t~icroinstruc~iqn xegi,ste~ (RSM), a return addxesa xegister (RA,y) and
_ a constant decodex (pSh.), and the second contains a ~qtcxo~~pgz~q auto~aton (MPA)
- which deterniines the o~exating mod~s.o� the M~'U ~nd o~ Ehe entixe MP (start, stop,
- wait and forming a signa7. Por interrog$ting the I~O~M) .
11 -
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~
The c~nten~s o~ Che RBI~ and ~t~A are ~especti;~r~7,y the h~;gh~o~xdex a,nd l.oW~ox'der ~
bits of the miGxoinst~xuc~ioi~''s addx~ss ~~ux~h~~loxe, ai'x addxQ~~ bi,~s a7re ~ce~ j
gistered in the RTA in the execufifion o~ each 'micra$nsCxucx~on dt.x~~~~.y' ~xom xhe ;
MROM, taking ~nt,a account the in~ox'~tion entexing thxough t'h@ condit~,on 1ine. ;
Changing the contents o~ ~he RB~ xequi;xea the executien oR speci.a~. anicroinstruc�- i
tions and is per~ormed wi.th a~re~en~xy in the RSM. ~hu~, ~he addxess ~ie~d o~ ~
the MROM is divided into pages o! 7.28 words each. xhe microinstxuction set has. '
six microinstructions with two o~ which ("Operation" and "Conditioi~al Transfer") ,
' the address changes only within the limits o~ ~ page, and with ~our ("Unconditional
_ Tr~nsfer~~(BP) and Storage," "Unconditional Transfer W~thout Storage," "Enter
Constant and Execute Constant ) the contents of both the RBM and RTA change.
The microinstruction decoder controls all operations. The RAV aerves the purpose _
, of storing the return address when going to anotlier pmge o~ the 'MROM. The micro- _
instruction "Operation" is a microinstruction of2 the I~fPU with which the ALU
- performs the semantic processing of information.
- All procedures for forming addresses are executed only when the MPA is in the act{ve I
~ state and is executing the clocked MRO'M interrogation problem. The MPA entArs ,
this state after executing the "Reset" and "Stazt'~ pxocedures and remains in it
until error or stop signals arrive or a stgnal for ~nticipation of a response
- signal from external sources.
- Single-Bit RAM LSIC (K535RU2)
This has a capacity of 1024 X 1 bit, an internal regeneration circuit and a working
frequency of up to 400 kHz (cP . fig 2.4) .
7paN.tucmcpci
npedoapumenn-
Noto ~opada
4 ~ YtlCqOBO/,f MO(!/(!N
1~ 9 10)
BxoJ
, ewurypamqnx 6!l~epNa~e HaKOnumenr CxeMa'anucu yucno
,4 KocKader 51~pt4x1 cvume~BaNUA
B^blAfOd
~ PO7f1Rd0/ -
Koda adpeca 6~ .
2 ~ 6yqirpNOrc
KccKada
Aewu~pamop .
. 7, r
$ ~ � Pa~pnBa .
Koda uBpeca
Figure 2.4. Circuit of RAM LSIC -
[Key on following page]
12
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- Key:
1. X decodex 7~ X a~codex
2. Addresa code biXs Add7Cess cod~ bits
- 3~ Bu#,~er stage.s 9~ R~adi.ng entxy ci.xcuit
4. Transistors ~or precharging 7,0~ ~ngut
numeric machines 11 ~ .ytuqbez
5. 1024 R 1 storage 12, OutQut
6. Bu~fer stages
Byte RAM LSIC (1:535RU3)
This has a capacity o~ 64 X 8 b~,ts, an tntexnal regeneration circuit and an operat-
ing frequency o~ up to 400 kHz. The circvit is~ the saflue, but the storage has a
' 64 Y 8 structure.
R0~1 LSIC (K535RYe2)
This has an information capacity o~ 1024 X 8 bits and an operating frequency of
up to 400 kHz (cf . fig 2.5) .
1 2 J 4
_ l~ 2~
Cxena 3~
/1emu~pamofw 6y~epNat ~vume~9aNUa
X!-X31 KacKada clno4po~pAd
4 ~ Mompuya ~ )
1024 X a
' Cxeha
numaNUa
1
_ ,q
5
j~pomop ADp. 7... ADp.10
8 caeNa
numaNUa
Mampuya 1
1014 x 4
6 Alp.f'
Qemu~pam 6y�epNeie CxrMa
xJd - X64 KOCROD01 CVU/71Dl40N(!A
c,fnodpoapRB
5678
Adp.1... AdP. 7
Figure 2.5. ROM I,SIC Circuit
Key :
1. X1 to X32 decodexs 3. ;:ixcui~ ~or reading ou~ bits from
2. Bu~fer stages ~ to 4
4, 1024 X 4 array
[Continued on ~ollowing page]
13
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i
5t X Aecad~r 7~ ~ow~r c~,x~uit i
6. Cir~ui,X ~or readit~g o~.tk t~its 8, ,l~dd7;ess 7 to addxesS~ ].0
;
5 through 8 ~
Tn~ormation is xegistexed in the it0'M ~,S2C in the ~xocees o~ ,~abr3,cating the LS~C. I L_
The existence oP a transi.stox at a specific ~1a,ce tn the nlatxix corxesponds to a !
"l." When an RO'M LSIC with dif~exent in~ormarion fs ~abxicated, a single mask
bearing this in~o~rmation is substituted. The remaining three masks are permanent ~
and do not depend on the in~ormation being changec~. -
Information I/0 LSTC's are r~presented rather fu11y~ in tlze p~channel MPK [micro-
processor set] o~ the "Elektronika S5." Let us bx~,e~1y d~sr;uss their ~unctional
desi.gn .
Input/Output Central Control (TsUW) LSIC (K535IK3)
'Phis LSIC contains the following circuits (fig 2.6): a state byte register; pro-
cessor lines (ShVM's), input/output lines (Sh'W's) and a 16-output address decoder;
condition lines controlling the operating modes of the decoder; readin and readout '
control circuits which control the modes of information exchange between ShVM's and ;
ShVV's; and buffer flip-flops for the glags of the LS [logical adder] and LU [logical
multiplier], whose purpose will become clear in discussing the next LSIC. !
_ - - - - I'
(lUBB) 5 ~ 1
,qll/0 ,qrlf5
6~ ~ . 1~~ '
Hronynec ,
r.vumoiBoHUa Qeuru~pa- jP n~ rp ny
1) mnp o peca 12
CxeNa
ynpoBneNUA -0"
~ ~anucea u
~yumb~BaHUeM 9~ ~
I Pezucmp !
- 3 4 ) d d'auma '
Nnnynac Cdpoc ~o~moAHnu '
Jonucu
H) [uuHO ~ ~ ~BM ~ lO)
ycnoBr~u
- .
Figuie 2.6. Input/Gutput Central Control LSIC Circuit
Key:
1. Readout ~ulse 5. Shyy
2. Readin and Xeadout c~ontxol, 6. AShQ [~'0'~ d~cod~x]
- circuit 7~ ~,ddxess decodex'
3. ~eadin pulse 8. Condition ~ine
4, Reset 9. State hyte 7cegistex
[Key continued on .~ollowing page]
14
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10. ShV'k~ ~2, T.U ~1,ip~~,op
11. I~S ,~lip~~],op
The I,SIC o~ezates in the ~01,1,ow~ng thxe~ tqodes : nu~eFical, exchang~ bez~aee~n the
ShW and ShVM; oxd~naxy dec:oding, when the addx@ss wx~.tfien ~.n the statF byte -
register is decoded; and rapid decoding, when th.e addxess in ~he Shy'V' is decoded,
without storage, bypassing the state bpte xeg~ster. Selection of the decodin~ -
mode is cont-rolled ~,r the c~ndition lines.
Digital Input/Output LSTC (K536TR1)
This is designed ~or the inputfoutput o~ digital, signals ox for the reception and
processing of interrupt signals. The cixcuit of tlie TsW [digital input/outtput]
- LSIC is presented in fIg 2.7. _
_ _ -
a�
~ ? ~ 1~ ~ Opu~NaKu
1~ 5 3~aP ~ nc nq
V h - I
r I
1 -
I
3nJ ~N.1 3~ 2 �.BN.4 11 CdpoC; -
,Qemuq~p~mnp 5 6
odpau~eMUri
'
Perucmp 1 12 ~ ~By ~
= 1~ Petucm02 CxeMa
, ~ nopar~ppD- ,
Horo~opno-;
Cv.7 ~ poBaNU,r
15 Hn neCa
IIOMNfI-
14) mamop
~ C4.1
BN. ? BN.3 1~ CXCMC 17
po~QndMOrn
notuvec,roto i
HarteNUA PtaruN ~
exoda ~1~~ ;
, , , . exaa om ay
9 ~ `l(
By /1/!M 2 0> ~
19) CutHan -
npepaBaNU~(KSd6HPQ
Figure 2,7. Circuit of Digital Tnput/Output LSIC
Key:
1. Readout 5, Wx'iteiz~
2. Readin 6~ Gate 1,
3. Address 7, Regis~ex
4. Address decoder 8, Readout 2
[Key continued on ~ol,lowing ~ageJ
15
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9. To W[pexipherals] ~,5~ D~gita~. pul,ae aha~?ing cixcuit ;
10. LS and I,U f~.~ga 7.6, A~.g~ta~, ~.ogica~ tquJ.t~p~,ication '
11. Reset ci7CCUiC ~
12. Fro~ co~t~uter 17. ~nput v4ode :
_ 13. From 'Sl[T 7,8. ~nput ,fxo~ 'W ! -
- i4 . Commut ator ].9. OR i-
20. Snterxu~t signal (K536IR1)
2],. ~n~axmati.on line '
i
Basic communication between the LSTC and tha pxocessox is accomplished through a ;
bidirectional in~orniation 1ine. Tn~ormation is entexed either into register 1
through gates Vn. 1 or in register 2 through Vn. 4. Furtherrcore, depending on the
combination of the values of the LS and LU flags (which arrive from the individual -
flip-flops of the TsWV LSTC diacussed above), is entered either new information,
or the logical sum or logical product of the n~w code value and of that recorded
earlier in the registers. Ti~is capabillty is quite convenient when desi~ning
various input/output sections. Entry into a specific register, ~.ust as the transfer
of information to the procesaor (through gates Vn. 2 or Vn. 3),-is deter~mined by =
signals from the address decoder. Information to peripherals arrives from register
1 without additionai gating; consequently, this register is a digital output with
storage; the capability of taking back into the computer information previously
read out makes it possible to economize on the storage register and, an important
consideration, to conduct tests of the section. '
Digital information is received in the information line through Vn. 3, dep~ending on
the "Input Mode" signal controlling the commutator (from pulse information sources--
in register 2 via pulse shaping circ~uit, and from sources of the level type--di-
rectly thro~}gh the commutator).
Before discussing the operation of the LSIC in the interrupt system, let us recall ;
the basic steps of the interruption procedure regardless of whether they are imple-
mented by means of hardware or software: ,
1) Recording the reasons for interruption; 2) masking interrupt signals; 3) with ,
the existence of unmaske~ aignals--the generation of a general interrupt signal; ~
4) analysis of the reason for permitted interxuption; 5) selection of the interrupt
with the highest priority; 6) development o� the interrupt signal; 7) signal reset;
8) return to interrupted routine. _
The TsVV LSIC enables the haxdware implementation of steps 1, 2, 3 and 7 in the
following manner. The recording of interrupt signals is made possible by the digi-
tal entry of interrupt signals in register 2, i.e., the inputs from the peripherals ,
(W) are used as the inputa o~ the interxupt spStezn. Masking o,f signals is per-
formed by the digital logical mulxip].ication cix~uit, whexeby the ~ask code is
entered ~rom the processor and ~s stored fn xegi,stex The genezal interxupt
signal, is genex~t~d by the OR ~~.x~u~t ~
After the generation o~ a speciPic i~~erxupfi ~~;gna7, it can be reaet, ~or exa~uple,
b}r entering in registier =2 �xom the comQtatex a code w~it$ "0~' in the appropriate
location with a logical multipl,icati,on ~1ag. -
- 16 ;
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Thus, depending on the connection arrangemen~, digtta7, in~ux~output I,SIC's can be
used eithex' a~ digi.taJ, channel,s ox as~ intex~xupt cixcu~ts. NoteWOxthy also axe -
the capabil.i.ties o.f the ~ogica~ pzocessirig o~ output ~,r~~p7Ctqattotl, Which axe accom-
plished througt~ the logica~ addition and ~ogical ~nu~,t~.plicat~on ~~.ags~ ~ dis--
advantage of the cixcuit is the ~a,ct that ~n it is no~ utilized the capability o~
redistributing the LS~C~s contacts among the two dixec~ions oi' fn~oxmation flow--
for reception and ~or xeadout.
Serial Interface LS~C (K536IK4)
Th is makes possible the following: the con~rersion o~ a serial code into a parallel
ei ght-bit code and the conversion qf a para11e1 eight--bit code into a serial. _
Accordingly, this LSIC can operate in �he reception mode (~M) with the identifica-
tion of the codes of the sequence of data received wi:th one eiyht-bit code assigned
in advance (through software), and in the transfer mode (PD). The rate of conver-
sion in the reception-trans~er modes is a maximum of 12K bits/s.
The circuit of the serial interface LSIC is presented in fig 2.8 and contains the -
- fo llowing: RgBuf--an eight-bit buffer register; RgUst--an eight-bit control point
re gister; RgRezh--a two-bit mode register; SkhSr--a comparison circuit; DSh--an
address decoder for "Write" (Zp) and "Read" (Sch) instructions from the microcom-
p uter; Upr--LSIC operation control; and Sch--a three-bit counter.
1~!/A 2 n 3 Cv !l/N
) 8~ ~
4 ~ -
5 ) P~9cr
npe
6) 1~ ~p
ynp ~ n,q~nM _
r CBB
12)
P~ 6yrp
~ ~Pr Penr 13
cy 14 ) 15 ) TN
Figure 2.8, Cizcuit of Seria]. Zntex~ace LSZC
- [Key on tollowinR page]
17
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- Key:
1. Addxess 7,ine 7.0, CoxRp~7Ci~on ci;xcui~
2~ Wycite 5~1~~~ ~~gfs~tex
3. Read 12, ~D/`~'M
4. Decod~x ~.3. ~u~Rex xegiatex
5. Interrupt pu],se 14, Counter
- 6. Control 7.5. C7.ock pulses
7. Mode register
8. Tnforn~atfon ltne
- 9. Control point register
The mode for the processing of data in the ~'M or ~A ~odes~is detexm~ned by a two-bit
code arriving ~xom the processor through the in~o7emation 11ne, according to table
2.2.
Table 2.2.
Code in mode register LSIC operationa
00 Tnitial state: A11 registers are in the reset state and the
operation of the LSZC is inhibited.
O1 Search in the sequence of PM signals received for a code
equal to the code combination stored in the control point
register; output of an interrupt si~r?al upon identification
of this code
10 All sequences of bytes received (with reference to the over-
flow signal o~ the three-bit counter, Sch) are converted
into parallel bytes and transferred to the computer.
~ 11 From the sequence of data received, code combinations not
- equal to the code of the byte s tored in the control point
register are converted into bytes and transferred to the
- computer.
In the PM mode the serial code entering the input of the shift register, RgSdv,
fills it in relation to shift clock pulses, TI's, moving from the zeroth to the
seventh bit. Each state of the shift register is compared with the control point
code of the control point register and can be rewritten or not rewritten in the
buffer register for subsequent trans~er to the processor, depending on the code in
the mode register.
In the PD mode the code enters the trans~er out~ut seXial,J.y, beginning with the
high-order bit, ~xom the shi~t register in keeping with the c],ock pulses; upon
completion o~ the ei.p,hth shi~t cyc~,e, the con~txol ci7CCUit thxough a signa~. ~rom the
output o~ the caunter ~ez~oxms a xeFrr~te ~zom the bu~~ex reg~ster into the shi~t
register and ger~ezates an.intezrup~ pulse; ~te7C ~his the new tx'ans~ez cycle
begins. ~f fn the interval between interrupt pul;ses a n~Wbyte ~.s not written
18
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into the bu~~er zegistex, then the code ~'roiq th.e. contx0~. ~o~n~ xegistez will be
- rewritten in the bu~~ex 7regf.ster~
Tirner LSIC (K536zK5)
This LSZC serves the puxpose o,f ~orming t~~me intex'va7.s, delaps, and sequences of
pulses of various frequenctes and has fi~ve Qpexating modes: dit~ider, delay, dis-
~ tributor, modulator and ~.nterpolatox.
~n the "Elektronika S5" microcrnaputer the timex LSZC is used only in the first two
_ modes. The circuit consists oP four channels, each of which contain3 a f~ur-bit
counter, a control point register and a cotaparison circuit. The ~irr.zt two identical
~ channels have in a3ditfon two two-input d~coders each, and the second two, circuits
f or reading the current code from tYie counter. The circuita of~~the first and
third channels of the LSIC are presented tn ~tg 2.9.
~
P~ 3 ~ Pr ~
1~ b tl 5
v~ . k2
G~ VO
y 4
_ V ` (
1
Cy BbIXOd ~4 BDl1fDd
2~ 4)
r r -
emv~pamop CxeMa ~
cvumeiBaNUa
qamu~pomop 3-~(4-ri)KaHan
1-u (2-n KaNC.~
I~igure 2.9. Circuits of Z`wo Channels of Timer LSTC
- Key:
1. Register 5, Aecodex
2. Counter 6, Readout circuf.t .
- 3, Com~atxi.son ci.xcuit 7, ~~,rst (secoz~d) chanz~e~,
4, Output 8. ~'h.f,xd (~ouxzh) channe7,
zn the "divider" mode a div~sion factox (~xom 1 to ].6) ~ox the ~,z~put frequency can
Ue registered in each regi,ster thxough pxog]cam4~ng~ By exte~~1 switchi,ng o,f the
~ 19
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LSIC's channels iz is possib~e. to obta~n div~is~on #actolCS ec~ua~, to ~he pxoduct o~
the factors which are xegistexed in the ~registers o~ e~ch. a~ x~e char~nels. ~,'he
maximum value o~ the inpuz ~xequancy ts ~ F 20 kHz .
= In the 11di~tributor" p4ode values of control points axe not entexed in xhe registers.
The first and second channels opexate fn the mode oz a di.stxibutor o~ pul~es in the
- outputs o~ each decodez, and the thf~d o7c ~aux~R fn the ~qade o~ div~.ding the i~put
frequency by 10. In ettRer~mode in the th~,rd and ~octxth. channels the current value
of the counter can be read out b}* programmfng.
ADC Control LS~C (K536TK6)
This circuit is desfgned for constructing an analog-digital converter (ADC) which
- operates according to a two-step integration circuit. The ADC LSTC forms control
- signals for a11 ADC units, ~orms the value of the output code--the result o~ analog-
digital conversion of the input signal--and makes possitsle interfacing of the ADC
with a microcomputer. A circuit o~ the ADC LSTC and its operating princip les are
presented in the discussion of the operation of the ADC functional module (cf.
"'Elektronika 55-121' Microprocessor guncttonal Module
Keyboard Coder LSIC (K536IV1)
- This LSIC makes possible the coding (in keeping wiLh GOST [All-Union State Standard]
13052-74) and input of data from a keyboard containing up to 90 keys of the contact-
switch type. The circuit of this LSIC and its operating principle are presented
in discussing the operation of the system's operator's console.
2.2. Microprocessor '
The microprocessor (MP) (f ig 2.10) performs arithmetic and logic operations on
16-bit numbers with a fixed point expressed in complement form. The microprogram
principle of control is implemented in the microprocessor; a 32-bit microinstruction
makes possible the simultaneous cont~rol of all units of the MP in the synchronous
mode. The time for executing a single microinstruction is 10 us (one cycle of
phased power). The same circuit for designing the MP is used in all p-channel
microcomputers of the "Elektronika S5" series.
The 16-bit microprocessor consists of three basic sections: an arithmetic-logic
unit, a microprogram control unit and a micro~rogram storage ~mit.
The ALU makes possible the storage and processing of inf ormation, the forming of
addresses o~ instxuctions and numbexs, and the forming, storage and output of
conditions ~or trans~er to the micxoprog7cam.
Six eight-bit microcix'cuits (K536zK9), gxouped in twos, ~orm thxee identical 16-bit
ALU~s. The ~irst is designed ,fox' storing and processing i.nstrucriqn in,formation
(~LUK), the seCOnd ~OZ stoxing and processing numerical ~n~qxfiation (AI~UCh} and
the third--a supp~ementax'y (ALUD)--is us~ed w~en woxki,ng with bytes, as well as for
speeding up the operation o~ the ~icroprocessor.
20
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- - - -
(UA(B-14J 1~ I
U/A (0- 71 '
. . . . . I
3!I
A/1S11 A/Iy2 AQy3 AAy4 A/IyS A/ly6
3)
. 4)
u~n~oa)
mn~�u)
5) ~y
[Uy
/l3y !U/1N 7 M/ly lOdpoC
6 ~ fUAM n~IM~
Figure 2.10. Diagram o# Micropxo.cessox Eiqploying p-Channel LSZC~s
Key :
1. Address line 7. Microinstruction information line
2. ALU 8. Microinstruction address line
- 3. Storage 9. MPU
4. Information line 10. Reset
5. Con~ition line 11. Start
6. MROM
- The MPU makes possible the formation of addresses and accessing of microinstructions
from the MROM, accomplishes branching in keeping with conditions arriving from the
ALU and from outside, and enables an asynchronous mode of operation with I/0 units.
The microprograiu storage unit With a c~~$cit~ o~ 1024 32--bit words is designed
for storing microprograms o~ the instruction set, console modes and other functions
such as micropx~ogxama.:,EG~- controlling peripherals. The ALU, MPU and storage unit
(7.U) are interconnected by means af multibit lines: address lines, bidirectional
- information lines (ShI's), condition lines (ShU's), L;i^ro~nstruction address lines
(ShAM's) and microinstruction information lines (ShZM's).
The informati,on line unites the in~orn~at~on ~nputa (outputs) o~ the ~I.,U, R0~
and of ~he inpu~/output contxo], unit.
A four-bit cond3,tion 7,ine serves the puxpose o~ txans~mitting ~eedback signals from
the ALU and M~U, which together wlth other contxol s~;gna7,s det~xmine the seqiience
for accessing nicroinstructions ~rom tAe 1~OM. Tt~e 10-bit Sh~M znakes possible the
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transfer of az~ addxess ~ro~ xhe i~U Xo ~tie T~O~'I, and ~he. 32~?~~t Sh.~ ~x~n&kexs ~
contzo~ in~ortqa,t;ion ~Xo~4 1:he 1`'~O~i t~o Ghe ~I,U as~d ~'~'U, ~'he add~eSa ~,nd i:n~oxxqaticn !
lines repxe.sen~ the cot~!~nicatin~s ~,i;ne ~~etwe~~ th~ m~cxop~o~es~sox ~1d '~esqox~ and
_ i.nput/outp~st uni,t~
2.3. "El.ektronika, SS--~2" M~,cxocoz~u~~~
The "Elektronika 55-12" (ftg 2.11) [photogxa~h not xepxoduced] is a single-board
model of the "Elektronika SS" ~microcomputer seTies . The ~vain purpose of creating '
this microcomputer model was the endeavor to achieve mi~nimum cost for a universal
programmable computing facility desfgned tor mass application in 1oca1 monitoring
and control spstems.
In connection with this, in developing the structu~e o~ the "Elektronika S5~12"
single-board microcomputer, the Pollowing require~ments were used as the raw data:*
The microcomputer must be soPtware compatible with other s4odels o~ the "~lektxonika
SS" series.
The number o� LSTC's and external TTL circuits on the board must be zuinin~al. For
this purpose the size of the internal storage uni.t and input/output units was
restricted and the basic set of I,SIC's was supplemented with mesuory circuits with
byte (numeric) structural organization and the static method of stor~,ng inf ormation '
in the RAM.
The number of interconnections on the board must be minimal on account of the line
organization for linking the processor, memory and I/0 units through information
and address circuits.
'I'?Ze asynchronous principle for operation of the processor with the memory and I/0
units was employed in order to speed up and simplify operation with I/0 units,
to make it possible to connect an auxiliary storage and I/0 units with different
speed parameters, and to make possible identity of the storage and I/0 unit inter- ,
f ace.
For the purpose of operating in real time, the possibility of receiving and pro-
cessing interrupt signals must be provided and timers must be introduced into the
computer's structure.
The single-board microcomputer must be used as a unit built into the system, whereby
power supplies and controls represent equipment of the system itself.
, For the purpose o~ broadening fts range o~ appl.ication, the ~ossibi~.~ty~ is ~royided
o~" increasing the auxil,iaxy stoxage and Z/0 uni,ts by connect~ng stoxage and
*This model, was pxeceded by the "~~.ektzonika 55-11" n~:Ecrocomputer, wh~,ch has twice
as less ROI~ capac~,ty and the abi].ity~ to 1ink, on~,y with. ROM MFM~S w~th electrical
t.ranscrtption of information.
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_ input/output u~icXqproce.s.sox ~u~ctfonal, ~iodu~ea i~dfcaXad iR xab~,e 2.4~ ~ descrip-
ci,on of ~qicroprueessox, RunG~~,ona~ u~odu~,~.s ~s ~x~~ent~d ~,n ~ec 2,4,
Theae require~qents., ~oxt~ing the dssign bas~.~, axe xQ~1,e~c~~d ~;t~ the sXxuc~ura7.
diagram of the "EJ.ektxonika SS-1,2" m~crocontputer (~ig 2~ 12
~J'J I11y ~ 1135/ /13y OJ9 039 03y OJy
1~ l014~B f024~B 1016xB lOP4+8 64+B 64X0 64xg 64+i
i mN(0-7) 3 ~ 2 ~
u~~~~s-rsJ Mn
- 4 -
5) ~
,~emurppamop Peruemp
ee 6 ~ odMeNe
~ yBB 0 yBB 1 yBB 2 yBB J launep yQ~mameP
- A B C
Figure 2.12. Diagram of "Elektronika S5-12" Microcomputer -
Key:
1. ROM 6. Exchange register ,
- Z� RAM 7. I/0 units
3. Information line 8. Timer
4 � 9 . Oscillator
5. I/0 decoder
The main functional component of the microcomputer is the 16-bit multichip MP.
The microprocessor, memory and the input/output control unit are coupled by a
- common line which includes address and information lines. Control of the transfer -
of information through the line and the ensurance of the required load parameters
of lines are accomplished by means o~ information~storing amplifiers (a K535IK5 -
microcircuit).
The microcomputer's i,nteXnal storage. consi~ts o~ an RA~ with a capaciky o~ 128
16-bit words and an RON~ with a capacfty o~ 2048 J,6~bit woFds, The R~M with the
sratic method o~ stox.i.ng in~ox~zqation i,s ex~cuted ~~th ~oux type .~C535~U2 LS~C~s~
each of whfch contai~ns 64 eight-bit regzsters. The ROM 3,s executed with ~our type
K535RYe2 LSIC~s, each o.f which h~as a capacitp~o~ ~024 eight~bit xegistexs. Record-
ing of information in the ROM fs per~oxwed in the pxocess o~ ~abricating the LSZC'S.
The microcomputer is linked with pex~,pherals through four di.gital. T/'O.I~STC's
y
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;
;
(K536ZR1) , each o~ which. makes pos~s~;b~.e tRe x~cept~on a~d autpuX o~ ~ight di.gital.
_ signals. One o~ the. d~,g~ta1, ~/'0: T~SfiC~'~. Cau b~ u~~d ~o~ xece~;~~4ng i,r~t~x7CuQt s~gna~.s !
and generat~ng a xou~i,ne-i;ntexxupt s~.gna9,. p~g~ta1. ~~'0. I~$~C f a. ea~ch~tnge ~n~axtqation i_
with peripheral,s thxough speci,a~ bu~~ex~ ~c~~ccuits whos~e inpuCs a,t~d Quxpufis a7:e
matched w~th the le~e7.s o~ T~'T.~ c~xcutts. .
_ Three type K536IK3 LS~C~s ~oru~ the ftrat tngu~foutnut.addxess de~ ;
coding stage (the second I/'0 address decod~ng stage ts imple~qented in the digital ,
I LSTC's . The structure o~ tfie c~xcu~t �ox contxo~.~.�~~~ the x/0 un~.t also
/0 )
includes logic circuits whi;ch axrange ~ox~ the contxol. o~ the exchange o~ in~ornia- ;
tion between the I/0 unit and extexnal channe3.s o~ tt~e ~n~'.cxocomputex, and the
generation o~ an access stgnal (SOZh), a signal i'or response ~xom the I/0 unit, and i
a signal for division of the clock ~requencp. A~~.mex executed with a type
K536IK5 LSIC is used for the purpose of Porming time intex'a~als.~or three channels
(channels A, B and C).
'T_'he microcomputer includes a clock pulse generator (a K535GG1 microcircuit) which
f orms nhas~~ ~upply voltage pulses for the logic circuits. Voltage pulses for _
supplying the memory LSIC's are formed in type K592GF1 microcircuits.
The "Elektron-ika S5-12" is software compatible with other models of "Elektronika S5"
_ series microcomputers. In addition to certain advantages in utilizing software,
- this property o� tihe microcomputer makes it possible to solve the problem of debugg=
ing specific problems by means of a single-board microcomputer of this series--the
"Elektronika 55-02." This model has sufficient working storage capacity and in- ,
formation input and documentation facilities, as well as a programmer's console,
- which makes it possible to fulfill the required conditions for the debugging of
programs and for display in the "microcomputer - controlled system" system. '
Structurally the "Elektronika SS-12" microcomputer is in the form of a two-sided
printed circuit board measuring 250 X 280 X 2 mm, on which on both sides are
mounted microcircuits and discrete elements. Type GRPM-61 output connectors are ~
- mounted on the two opposite ends of the board measuring 280 mm. It has a metal ;
frame for the purpose of making possible the required rigidity. The assembled
board is covered on both sides with covers. On the side walls of the covers there -
are four threaded holes each, making it possible f or the user to attach guides,
taking into account the distinctive features of the specific equipment into which
the microcomputer is to be built. The key technical data of the "Elektronika 55-12"
microcomputer are presented in table 2.3. '
Table 2.3. ~
Word length, bits 16 ,
Operating principle ~'axal.lel .
Control principle Micxo~xogram
Speed 10,000 opexations/s
Number ok basic ~nstructions 31 ,
Capacity o~ ~qetqo7Cy, bits:
g~ ~.2 8 X 16
goM 2048 X 16
[Continued on .~ol,].ow~.ng page]
_ ~
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Ability to incx~ease addresses Up to 32K
Number of singl.e~t~it dig~tal input/'
output channels ~xom 24 to 32
Number of intezzupt signals U~ to 8
The microcomputer picks up an external
signal wi~~ a.fz'equency o~ not greatex
than 10 kHz and makes ~oss#1~1e the
following: division of ~fxequenc~,es '
from 1 to 16 through two channels
and f rom 1 to 256 through cn~
channel
'I'he microcomputer provides electrical
compatibility with r~icroprocessor
functional modules
Parameters of output si.gnals:
For digital outputs yoltage o~ lo~ical 0 not less than
+4 'V; voltage o~ logical 1 not ~
greater than +0.4 V
For timer out~uts yoltage o� logical 0 not greater
than -N0.4 y; voltage of logical
1 not less than +4 V
Parameters of input signals Voltage of logical 0 from 2.4 to
~ 5.0 V; voltage of logical 1 from
0 to+0.4V
Maximum permissible load current 16 mA
- Overall dimensions 284 X 298 X 30 mm
Weight Not greater than 1.5 kg
External connectors Type GRPM-61 (four units)
_ Operating conditions:
Ambient air temperature, �C From -10 to +50
Relative humidity.of air To 95 percent at +35 �C
Atmospheric pressure, mm Hg From 630 to 800
Supply voltage + 5 V+ 5 percent, + 24 V+ 5 per-
cent, + 1.5 V+ 10 percent
Power consumption Not greater than 30 W
2.4. t4icroprocessor Functional Modules
The set of microprocessor functional modules (ME~'s) presented in fig 2.13 [photo-
_ graph not reproduced] [10.13] [as publishedJ has been developed on the basis of
p-MOS LSIC's for the purpose of constructing on the basis o~ the "Elektronika S5-12"
microcomputer systems with broadened ~unct~,ona1 capabilities. The key character-
istics of Mk'M~s are pzesented in table 2,4.
Table 2.4.
Designation o~ ~P~1 ~urpose and key~ ch~~~actex~sti.es
"Clektronika S5-121" Fifteen-channe]. ADC ~ox d.c~ input vol,ta,ges from -10
to +10 conVez~sion errox not gxeatex than 0.4 pexcent;
converston ti~e not longer than 0.1 s
[Continued on following page]
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"Elektronika SS�-~.22" Digital #nput/auC~ut~ wh.os~~ voXtage 1,e~e~.s tqatch the
out~ut 1,eve7,~a oa~ xx'~ c~xcuf~~; ;
Number o~ inputs~-k bytes
Nua~ber o~ outputs~-4 bytes ~
I,
- "Elektronika 55-123" zn~ex~aci,ng wi,th punehed tape Z/0 units, such as the
~~-1501 photoelectxf.c papex tape output unit and the ~
~L--80 or ~L-150 punchea :
- "Elektronika 55-124" ~nter~ac~ng with type RTA~6 (RTA-7, RTA-60, T-63, '
STA-2M) teletype
"Elektronika S5�-125A" RAM with a capacity o~ 2048 16-bit words '
"Elektronika SS-125B" RAM with a capacity oP 4096 16-bit words
"Elektronika S5-126" Display adapter for output to a"Kvant-M" television-
type vfdeo monitor o~ i.nformation from the microcom-
puter's storage ,
System operator's
console Enablea interaction of the operator with a system
~ontrolled by the microcomputer in data card language �
":~vant-M" VKU [video
monitor] Television-type video monitor based on a 16LK2B CRT ~
[cathode ray tube] and designed for compatible opera- '
tion with the SS-126 module in displaying information
- from the microcomputer ~
"Elektronika P5-PPZU" Reprogrammable ROM with electrical replacement of '
information and with an information capacity of 1024
16-bit words
_ Note: The operating conditions of MFM's are identical to the operating conditions ~
of the "Elektronika SS-12" microcomputer. All modules are executed in the f orm of ;
single-board constructions (the printed circuit boards have dimensions of 280 X 160 X
- X 2 mm or 140 X 160 X 2 mm) and have an external frame and protective covers.
"Elektroni~.a S5-121" ~unctional Module
This makes possible the commutation, analog-digital conversion and entxy into the
microcomputer o~ direct-current ana~.og stgna7.s. ~h~,s module has the ~ollpwing key
characteristics: numbex o~ input voltage channe~.s---16; xange o~ vaxiation of input
voltage ~rom -].0 to -i~1,0 V; convers~on erxax' at noxmal tempexatuxe not gxeater than ~
0.4 percent; convexs,ion ti.me not l,ongex than 0.1 s; ~npuz ~.~n4pedauce~-1.00 kSt.
The module ~s powe.x,ed ~ratq i-24 y-h 5 percent and ^24 y-h 5 percent d. c~ power
supplies; the power required by the supplie.s is no~ g~e~tex than 2 W~oz --24 and
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not greater than 3 W for +24 V. The overall dimensions of the module are
295 X 165 X 25 mm and it weighs not more than 0.7 kg.
A diagram of the "Elektronika SS-121" module is presented in fig 2.14.
' Aar � ' �
1 ~ H3T KMJ ~ .
K
2) 5
H/ �
N3 R/ Ka4
Oy! 0!/2
MIS R2 KMS
3~a~r~-ia) . ~
K~
IUA (0-J, 6- f0)
lUll(1, 2) N1 !
el e2 e3 e5 e4
' 6NC 9
KS3B NR6 1 9RpKa31. IK 10 ~
1 12> 1 TtC ~DJN ~KO `
f7M
. NZ 13 cy 14~ 152 .
16 ) Cv eN cv `
- 18) m~ 19) ~
- ~~n m3 21~ Nx Kn 20~
- ~4
~igure 2,14. Diagram of "Elektz'onika 55-121" ADC Module
Key:
� 1. Comparison circuits 9. UprK1ET [reference current switch
2. Co~nutator control]
_ 3. Address line 10. Commutator flip-flop
4. Condition line 11. f_ _
tl [el~ck pulses]
5. ZET [re~erence current source]
6. OU1 [operational amplifier] 12. Tss [start-stop flip-flopJ
7. K536IK6 LSIC 13. Sch [counter]
8. Flip-flop 14. FZn [circuit for forming sign bit of
output code]
[Key continued on following page]
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~
15. FKP [circuit for forming 18. GTI [clock pulse generator] ;
pulse for termination of 19. NX [output code sign bit] ~
conversion] 20. KY [convereion termination pulse] '
16. Counter 21. Shapers
17. Counter gate
~
Conversion of the input signal (I1 to I15) is accomplished by the two-step inte- ,
gration method. iie ke; advantage of analog-digital conversion (ADC) of this type
- is its high noise rejection. Noise fram alternating current sources whose period
is equal to or a whole number of times less than the duration of the f irst integra- _
tion step is suppressed completely, i.e., does not influence the result of analog-
digital conversion. The switching of ADC into operation is accomplished with the
simultaneous arrival of signals through the following lines: ShA (11 to 14)--a ,
f our-bit channel address code; ShA (0 to 3 and 6 to 10)--a nine-bit ADC address
code; ShU (1, 2)--two control signals ("Interrogate Storage," "Store/Count"). '
A signal from the output of a camparison circuit, I1, turns on the input s~gnal '
commutator (Kml) and the digital control automaton (K5361K6 LSTC). In the LSIC _
this signal through the start-stop flip-flop, Tss, and comparison circuit I2 -
enables the entry of pulses, ~fT (100 kHz) , in the input of the 12-bit counter
- (Sch) and through flip-flop TkI picks up signal e5 ("Correction"), turning off �
commutator KmS. In addition, this signal drives i::to the initial state circuit
FZn--for forming the output code sign bi~ (in keeping with the polarity of the
measured voltage); circuit Upr K1ET--for controlling reference current switches;
and (through Tss) circuit FKP--for forming a pulse for the termination of conver- ,
sion (KP). Fro:n the same signal flip-flop Tx sends out signal el for the purpose ,
of connecting the channel selected through commutator Km4 to the input of the in-
tegrator, which contains an operational amplif ier, OU1 , with a capacitor, C, in _
- a negative feedback loop. As a result the first step in integration begins--in-
tegration of the input signa.l from the chaanel selected. The duratian of the ;
f irst integration step equa:.s the time for the arrival of 2048 pulses from the
clock pulse generator (GTI) (a K536GG1 LSIC). A signal from the output of the ;
llth bit of the counter returns flip-flop Tx to the initial state (at the same time
~urning o~f commutator Km4), forms (f~~,~ ~I~na~ e4 ,arriving fr~~a output of ;
_ null detector OU2 ) the output code sign bit, N, in circuit FZn, prepares circuit
FKP and turns on circuit Upr K1ET, which sends out one of signals e2 or e3
(depending on the golarity of the voltage of the channel selected). As a result,
in the second integration step to the input of the integrator through commutator
Km3 or Km4 from the reference current source (IET) will be supplied a reference
current whose polarity is opposite the polarity of the input signal and discharging
of the capacitor will take place. At the instant when the capacitor :tn the second
integration step is discharged to zero from signal e4 , circuit FKP forms signal '
KP, which through f lip-flop Tk turns on commutator Km5 for correction of the in- ~
- tegrator's zero drift, picks up signal e2 (or e3) through circuit Upr K1ET and ~
through flip-flop Tss closes the input of the counter, Sch. The result of analog-
digital conversion--the state of circuit FZn and the number of pulses arriving in _
Sch in the second integration step--is read with reference to the Sch signal from
the outputs of gates Vn sch.
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"Llektronika S5-122" Digital Input/Output Functional Module =
This module makes possible the following: the reception, storage and transfer of
four bytes of level or pulsed digital information in levels of TTL circuits from
peripherals to the computer; the output and storage of four bytes of digital in-
- formation from the computer to peripherals in TTL circuit levels; and the organiza-
- tion of a routine-interrupt system. A diagram of the "Elektronika S5-122" function-
al module is presented in fig 2.15.
. - _ _ . . - _
' 1 N,vmrpq~eu! JIBI FlYA,lUN,!!/y)
2 3 7)
9n Cv lUA lUN(QJ AC ~9 /m/
> s) 6 a)
i - - - - - -
' ~ ,Q!!I 6NCQBQN~1 N�2 N�3 ~N~4 I
~ ~ 10) I
1 ~
~ Pr 1 1], Pz 2 ~
~
: I i
~ 12) (BI
I ~
Cx.conp Cx.conp i
MO/I 1TA MO/J 77/I
13> L- - - - - ~ _
E114 ~I~ el Py~ � fl (B1 (8J E2 (8 (B) E3 (g~ (d)
. K B9 ~~'1 16 ~ Om By ~ /lpBf ~pe,~ liped
noHZ nphd npN4
Figure 2.15. Diagram of "Elektronika 55-122 " Digital Input/Output Module
Key:
l. Input/output unit interface 10. Digital I/0 LSIC No 1
(address line, information 11. Register 1
line, condition line) 12. MOS TT~ interface
Readin 13. E [voltage]
3. Count 14. To peripherals -
4. Address line 15. Output Prvl -
5. Information line 16. Input Prll
6. Logical adder 17. From peripherals
7. Logical multiplier
8. Response
9. Decoder
The module contains four channels, each of which incZudes a digital I/0 LSIC
(K536IR1) and circuits �or matching MOS TTL levels for eight digital outputs and
for eight digital inputs. Control characters of the LS and LU establish the type
of readin from the computer into Rgl (and Rg2) in keeping with table 2.5. These
control characters make it possible to accomplish the aelective readin of a"1"
_ and "0" in the desired positions of Rgl (and Rg2) and accordingly selective
_ switching on and off of peripherals.
29
FOR OFFICIAL USE ONLY
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APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000400020005-0
FOR OFFICIAL USE ONLY ~
- i
_ '
Table 2.5. I
- LS LU Type of entry !
1 1 Ordinary entry !
. 0 0 " ~
1 0 Logical summation
p 1 Logica~ wui~ipiication !
i_
The collectors of the output transistors of the matchin~ circuits in the outputs of
each channel are connected via 10 1cSZ load resistors to the voltage source (Ei not
greater than +40 V). The maximum value of the current through the open output
- transistor (total current from E and peripheral connected to the collector of the
output transistor) is 20 mA. ~
~ The signal in input Prli is established according to the kind of input signal:
"1" (0 V) in input PrI for making possible the reception of pulsed input signals
from the peripheral (w~th their storage in Rg2 of LSIC TsW ) and "0" (24 V) in
input Prli with level input signals f rom the peripheral (en~ry is accomplished by ~
bypassing Rg2 of LSIC TsWi).
~
When the channel operates in the routine-interrupt signal reception mode, for input
PrIi is establiehed a"0" level, output register Rgl of LSIC TsWi is used for
reception from the computer and for storing the interrupt mask, register Rg2 is used
for receiving and storing interrupt signals, and through output Prvi a signal
regarding the presence of permitted interrupt signals enters the computer.
Register R~2 is reset aftpr readout when readout takes place from register Rg2 -
with the presence of a"1" LU eontrol character. The module is powered f rom a
-24 V+ 5 percer~t d.c. power supply, its power requirement is not greater than ,
4 W and its overall dimensions are 298 X 165 X 25 mm.
"Elektronika ~5-123" Functional Module for Interfacing with Punched Tape I/0 Units
This module is designed for implementing a hardware-software algorithm for controll-
ing a photoelectric papertape output unit of one of the "Ridmom R40B" and "Ridmom _
ER40B" types, the FS-1501 when reading information into a microcomputer from
punched tape, and for controlling one of the "Perfomom R35," "Perfomom YeR35,"
PL-150 or PL-80 punches when reading information out of a microcomputer onto
punched tape. ~
- The circuit of a functional module for the exchange of information with a tape
punch (PL) and a photoelectric papertape output unit (FSU)--of a PL F~U--is pre-
sented in fig 2.16 and contains the following: a synchronizer which makes possible
switching on and off of the electromagnets (EM's) of the punches upon an instruc-
- tion from the microcomputer ("Line") and by means of synchronization pulses from
the punch; digital input/output channels TsVVl and TsW2 (K536IR1 LSIC's), per-
forming the functions of buffer registers for the input/output of digital informa-
tion in the microcomputer via an I/0 unit interface; an interrupt signal input i
channel--TsW3 (a K536IR1 LSIC); a timer (a K536IK5 LSIC); amplifiers (U1 to U14);
- 30 ~
1~OR OFFICIAL USE ONLY ~ '
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APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400020005-0
FOR OFFiCIAL USE ONLY
commutators (K1 to K3); shapera F1 and F2; Coder Shl; gates Vnl to Vn8; and
logical gathering circuits ILIl and ILZ2 [OR1 and OR2].
_ -
1~ a~, nn-rsn,n~-e~ Om P3S, fP.iS ,5)
� 2~ /'omoB /IK NQ /lpama.xraA PcmoB/1
3) 4) 6~ -
K mapNalH. 3M s~ ~1 ~ Pa~oma _
J ~'uHxpoNU~omop
q1 ,35) 36) nps
K 3M rlpbmA,w,ru .
1 14 9anpoBKa
Pc~pe~utMUt 13~ Ha~arTn~ N
K 3M mp. Jnpo~~! Podoma ' KH. Onrped R
M~1N1 KN. Na~aB R
' 19 )
8 3H K~1 Na70d II 3
15> _
Om xaBose~x ? ~ a 3N Ro~t , Q~l n Ka mp.do~$g )
~aC9CK ~ ~ B -
D� ui6 a 3N irod ! 4 93 b Cnnpuxa,tnp~'a
_ cmo~ fs 20~ . ~~~39)
IQ� BOQOMKC IU,Q Y~II~Q J~ltlQ Cmapvn FJ ~ KJ . Cv. MlBAlH. ~ O~
PomoBHOCme 23 2 9) ) 44) ~ 41)
� ~ ~ ~I � Tp. dapaw,ra
KH. Pneped R 24~ ~mM~ 42~ ,
h�N.HO~aaa 25) 28) taunrp Ysac
/leMma 2 u8B1 ~mp,ran �
/(OH!!(qtNl7)0/ ya~, 43~ 45)
Kr nM~vss,ecy myae 46~ .
a 33~ .
b /lum
nnisopa~ _
� r 1t0 -
Figure 2."16. Diagram of "Elektronika 55-123" PL FSU Module
Key:
1. From PL-150, PL-80 16. TsWl
2. Ready 17. Vnl to Vn8 _
3. Code reception 18. U4 to U11
4. Beginning of cycle 19. Electromagnet codes
5. From R35, YeR35 20. FS stop
6. Punch advance 21. F1
7. Punch ready 22. Transport track
8. To brake electromagnet 23. Readiness
9. To advance electromagnet 24. R forward button
10. To transport track EM 25. R reverse button
11. Synchronizer 26. Tape _
12. Pern~it operation 27. End of tape -
13. Punch reverse 28. TsW2
14. OR2 2~. Stepper motor phase 1 _
15. From k'SU code tracks 30. Line
[Key continued on ~ollowing page]
31
FOR OFFICIAL USE ^v
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APPROVED FOR RELEASE: 2007/02149: CIA-RDP82-44850R000400024405-4
rOR OFF'ICI.AI. USE ONLY i
i
31. Reverse 41. Slow readout ~
32. PL-150 (-80) power 42. Transport track ~
33. R35, FSU power 43. Timer
34. + 12 V 44. TaW3
_ 35. Operation 45. 25 ma '
36. Interrupt input 46. ShUW [coding I/0 unit] ~
37. Punch reverse 47. FS start '
38. Transport track punching 48. Servicing ;
39. Continuous punching 49. Shl [coder] ~
40. 1 Hz ~
From PL-150 and PL-80 punches synchronization signals enter the module's inputs-- '
PL readiness, code reception (PK) and start of cpcle (NTs), as well as state sig-
nals--servicing of tape, breaking of tape ("Tape"), and end of tape.
The f ollowing signals enter the tape punch from the functional module: turning on
~f code electromagnets for punching code holes ("EM Code 1" to "EM Code 8");
turning on the electromagnet for punching a transport hole ("EM Transport Track");
and turning on the advance electromagnet ("EM Advance").
The operation of the microcomputer's punch is software-contr~l.led via an I/0 unit ~
interface. The tape punch'^ power is turned on through TsW2 and commptator K1. ~
For the purpose of turning un the microcomputer's tape punching mode it is suffi-
cient in the absence of "Tape" and "End of Tape" signal~s to produce a"L3.ne" signal
' and then with the absence of a"Operation" signal to output new values of the code
for punching. With the "Servicing" signal (without the participation of th~ micro-
computer) is accomplished initial servi~ing of the tape with the punching of only
transport holes.
f When working with the "Perfomom R:,:~" and "Perfomom YeR35" punches, the following ;
signals ~nter the module'.s inputs: ~:,-achronization signals--"Punch Ready" and
_ "Advance Punch;" state signals--tap::~~roken and end of tape; and the signals
"Punch Track," "Continuous Punching," and "Punch Reverse."
~ The f ollowing signals enter punches from the module: for turning on code electro-
magnets for punching code holes ("EM Code 1" to "Em Code 8"); for turning on tihe
electromagnet for punching a transport hole ("EM Transport Track") and the advance
electromagnet ("EM Advance"); and for turning on the brake electromagnet ("Brake
- EM").
The punch's operatian is soit~aare-controlled via an I/0 unit interface. The tape
punch's power is turned on through TsW2 and commutator K2, and for turning on the
microcomputer's tape punching mode it is sufficient in the absence of "Tape,"
"End of Tape," and "Reverse" signals to produce a"Line" signal and then with the '
absence of an "Operation" signal *.o output new values of the code for punching.
One of the following three signals enters the input of coder Shl: "Reverse Punch,"
- "Punch Transport Track," and "Continuous Punching," which are coded in two-bit
code which is transPerred to the input of TsW2; the gathering of these signals
acts on input 6 of TsW3, causing fihe software implementation of the required
32
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400020005-0

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FOR OFFICIAL USE ONLY
function. Punching is stopped upon removal of voltage from the "Line"
signal.
The following signals enter the module's inputs from FSU's of the "Ridmom R40B"
and "Ridmom ER40B" type: from the transport track ("Transport Track"); for the
presence of a serviced tape ("Readiness"); from FSU code tracks; and from the
"R Forward" and "R Reverse" button.
The following signals ent~r an R40B and ER40B FSU from the module: from TsW2 _
through K2 for powering the FSU (+12 V); and fxom TsW2 through amplifiers U12,
U13 and U14, a voltage of +12 V to the windings of the stepper drive motc,r.
Advancing of the tape is software-controlled by changing signals in the inputs of
U12, U13 and U14 in the following sequence (simultaneous presence of "1" signals
in the inputs of stepper motor amplifiers): ~
r, , - - _ . - -
- a~' rev~erse l~ . fr.~rw.ard
. .
, -~2 -~3 -3 -3~ ~
With the interlacing of sequences accord3ng to arrow a) the tape moves in reverse,
and according to arrow b), forward. The "Transport Track" acts on the interrupt
input of TsW3 for the purpose of running the code readout routine and for forming
the next step, which is delayed 25 ms (from a signal from the timer) in relation
to the preceding. _
The following signals enter the module's inputs from the FS-1501: from the trans-
- port track ("Transport Track"); the presence of a serviced tape ("Readiness"); and
from FSU code tracks.
The following signals enter the FS-1501 from the module: "Start FS" and "Stop FS."
The "Start FS" signal is formed by circuit F2 with any change (increase or decrease)
in the total number of "1's" (from one to three) entering its input from TsW2.
The "Stop FS" signal is formed by circuit F1 in the absence of a"Readiness" signal !
or with the presence of a"Transport Track" signal (start-stop operating mode).
Simultaneously the "Transpart Track" signal acts on the interrupt input of TsW3
for the purpose of running the code readout routine and for fornting the next step. _
The module is powered ~ro~ a-24 V+ 5 percent power supply. The power requirement
is not greater than 3 W. Peripherals a:~ ~.Gwtr~d by the user's equipment. The
module's dimensions are 298 X 165 X 25 ffin.
"Elektronika S5-124" TA Module--Functional Module for Interfacing with Telegraph
Equipment (TA)
33
FOR OFFICIAL USE ONLY
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APPR~VED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400020005-0
_ i-
FOR OFF[CIAL USE ONLY
~
-
This module makes possible the exchange of information between a microcomputer and ~
a five-element-code telegraph set (RTA-S, RTA-60, STA-2M, etc.). �
:
The nominal data rate ia 50 bite/s and the code is five-element MTK-2 code; the line ~
voltage is 110 + 20 V and the electromagnet's current is 40 to 50 mA. A diagr~at of
the TA functional module is pr~sented in fig 2.17. j
i
_ . . - _
. _ - 1~ K TA- 2~ � Om TA '
3) y~ 4) ~ ~~ry '
5) ~K~y 6) N NnH i
. np~ caN n~ e~ Kc c H nM
c12g eKnZ3~ 14) 15) nM cNN nN
n,q
6NC n,q 6NC na '
(A' �3� )NK4~ 17 tK 5db NRi) ~ 3~ ,
16
NH~ ,24)
18) N"~ 20) 22rpOna
- Om13y (N BK~rJ,I, ' KaNm N~~ K 3~ )
) Zl
25) .vz
27) Bxn,Q ~K6S
6~uIBB nP~ 32)
BKn A' ~s T BNKn,!( 1~~ -
BKnQ 28~
BaKnK . ~R ~3) . , -
BarrnQ2 ~pa ~34~pe nN ~
Figure 2.17. Diagram of "Elektronika S5-124" TA Module
Key:
_ 1. To TA 15. Reception
2. From TA 16. Data trans~er LSIC (K536IK4)
3. U1 17. Data reception LSZC (K536IK4)
4. F [shaper] 18. Readin
5. Data transfer interrupt 19. Fronn co~uputer
6. 1 kHz 20. Information
7, ~ 21. TA on _
8. OR 22. Data transfer interrupt _
9. Data transfer synchronizer 23. Readout
10. KS 24. Information
11. Data reception synchronizer 25. "On" button, motor ori
12. Data transfer synchronizatj~~n 26. "Off" button, motor off
13. On 27. Motor on
14. Transfer 28. Motor off
[Key continued on following page] '
34 -
FOR OFFICIAL USE ONLY
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FOR OFFICIAL USE ONLY
29. TsW LSIC (K536IR1) 33. Data transfer interrupt
30. Information 34. Data reception interrupt
31. Read.in
- 32. Interrupt
The telegraph set`s motor is turned on and off via flip-flop T and amplif ier U2
either from buttons ("On Button," "Off Button91), or upon an instruction from the
computer via the TsW LSIC ("Motor On," "Motor Off" signals).
In the mode of the transfer of data (PD) from the computer to the TA, a byte of
information from the computer enters the input of the PD LSIC (K5361K4 microcir-
- cuit) and at the "Readin" (Zp) signal is entered in the~buffer register of the
PD LISC, and at the same time the circuit for controlling zhe PD LSIC is turned
~ on, which makes possible the copying of information from the buffer into the ,
shift register of the PD LSIC and the output of an "On" signal to the input of the
data transfer synchronization circuit (SZNT PD) .
With the "On" signal the distributor (from ~TI ~clor~k pulse~ - 1 kHz ) is ~urned
~ on, forming Prv PD [data transfer interrupt] s gna s a a d b. ar~d SIN PD
signals. The Prv PD signal, via the TsW LSIC operating in the mode of the
reception of pulsed interrupt signals, forms in its output a Prv [interrupt]
signal, which through a routine-interrupt system ena6]:es transfer of the new byte
of information.
- Signals a and b, acting on the combination circuit (KS), ma.ke possible the
formation oi start and stop bits of the MTK-2 code. The STN PD signals corres-
pond to the beginnin g of each MTK-2~code and represent clock pulsea for the PD
LSIC shift register.
Upon the completion of the formation of all elements of a single MTK-2 pulse
(a single character) the circuit for controlling the PD LSIC (from the reaults of
, counting SIN PD signals) accomplishes the copying of the new byte (actually a
five-digit code) from the PD LSIC buffer register to its shift register and sends
- an "On" signal to the SIN PD circuit.
In the mode of receiving information from the TA, shaper F converts the signal
from the line into a TTL circuit level signal. By means of th~ start pulse from
the TA the data reception synchronizer (SIPl PM) is turned on, from whose distribu-
_ tor is formed a SIN PM signal at instants correspending to the middle of each
MTK-2 code pulse. The PM signal enters the input of the PM LSIC's shift register,
the clocking shift signal for which is the SIN PM signal. Upon completion of the
reception of the last element of the MTK-2 code, it is automatically copied in
the PM LSIC from the shift register into the buffer register and a Prv PM [data
reception interrupt] signal is sent out, which via the TsW LSTC acts on the
routzne-interrupt system, enabling the readout of infoimation from the PM LSIC.
The module is power ed from a-24 V+ 5 percent d.c. power supply and the power
requirement is not greater than 3 W. The telegraph set is powered ~row the user's
_ equipment. The overalY dimensions of the module are 298 X 16,5 X 25
35
_ FOR Ol~'FICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400020005-0

APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400020005-0
FCR OFFICIAL USE ONLY ~
~
"Elektronika S5-125" 1~M gunctional Module
This module has a single baard (measuring 140 X 160 mm) with an informat3.on capaci- i
ty of 2048 16-bit words.
"Elektronika SS-125B" RAM Functional M~~ule
'i'his module has two boards of this kind. Each board contains 32 type K535RU2
microcircuits (RAM LSIC's). The information capacity of each microcircuit is ,
10'L5 X 1 bit. All LSIC's are divided into two zones having a common circuit--for
enabling a specific zone. One zone is designed for entering, stOring and reading
out information for addresses 0 to 1023, and the other for addresses 1024 to 2047.
- Accessing of a specific location is accomplished by means of a 10-bit address code.
= The circuits for entering and reading out information of like bits of the two zones
are united.
The board's structure includes a two-stage zone d~coder executed with circuits of
the KT-902 type. The first stage of the decoder makes it possible to access a
specific RAM module from the entire memory field. The second stage is used for
accessing one of the two RAM zones.
Four clock amplifiers are used for the purgose of converting and amplifying pulse
signals of the master oscillator. Forming the basis of the amplifier's operation
is the principle of charging a Zoad capacitor through a low-reaistance loop and
rapidly discharging it through a high-current switch.
Eighteen readout amplifiers are employed for the purpose of amplifying readout
signals and for making possible reliable operation of the microprocessor's input _
circuits.
The RAM board is powered by -24 V+ S pe~cen~, +3 V+ 5 percent and +5 V+ 5 per-
cent d.c. power ~upplies with a total consumption of not more than 3.2 W.
"Elektronika SS-126" Display Adapter (DA) Functional Module
This module in combination with the "Kvant M" video monitor (VKU) makes it
possible to display, on the VKU's screen (a 16LK2B CRT) with a working f ield of
" 110 X 90 mm, a specific zone of the storage of a microcomputer with a capacity of
256 bytes (cha~acters) in 14 lines. The height of a character is 4.4 mm and its
width is 4 mm. On the 9KU's screen are displayed 128 types of characters in
keeping with KOI-7 code (GOST 13052-74) witho~t lower-case characters (only
capitals): 31 in Cyrillic script, 27 in Roman, 38 numbers and symbols and 32
- auxiliary char~cters.
- A diagram of the DA module is presented in fig 2.18, where BU is a buffer re-
- gister, BZU is the bu.f~er R~I, PZU is the character generato~'s ROM, Rg Sdv
is a shift regi~~er, GTT is the c1o~k. pulse generator and BULpr ZU is the unit .
f or controlling access to the microcomputer'g storage.
36 -
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400020005-0

APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400020005-0
~ ~
FOR OFFICIAL USE ONLY
Tax: . ~ rnxc . _
1 ~o.rc ~OXK ~7M a ~
!UN(0-IS) _ 5 ~ K SuBeo-
KaHOny BKSI
6J~n 63y /139,1i Pr Cq6
' Toxc 3 4) � 10) ,
2)
N r ~
11~ N ~%~12 ~ .
f/~/ `
x3~ I'TN CuNx oNUaamop Hd cuitxpoHU,wyua
NN~ Kogp. pc30epm. 6Ky
Ao n 3n , ~__T_~],~
////~~0-~~ ~ 15~ HCCLNXf1pNUJQy(/l0
~nxc ~arTe~,rT~n NHC cmpovH. po~Bepm. BR9 lg~
_ AdpeC 3921 NMo Z4) 1 ~ ' ~
3unpoC 3 6y .~np 3Y ~Z 2~ ~ 19 ) ~
KTn ~n 26~
- . 23 T.rn .
= Figure 2.18. Diagram of "Elektronika. SS-126" Display Adapter
= Key :
- 1. Information lines 15. I [vertical scanning pulsPSJ
k [horizontal scanning 16. Ink [horizontal scanning pulses]
2. faI~stime] 17. For synchronization of VKU vertical
- 3. BU scan~.ning
- ZP 18. For synchronization of VKU hori-
4. BZU
~ 5. T~S [horizontal scanning , 19. T ntal acanning
$ [ readin time ]
6. PZUe time] 20. ApZPA Zp [readin]
7. T khZg [vertical scanning 21. Address stora,s~,e -
fa�IIktime] 22� Enable storage -
8. f 23. BUZprZU
TI [clock pulse] 24. I
9. Rg Sdv 25. F~s[phase 2]
10. To VKiJ video channel 26. KT [ end of text J A"On"
11. N zn/st [number of character .
in line]
12. N ts/zn [number of televisicn
line of character]
13. GTI
14. Synchranizer
Time di ~grams of the a~chrvnizer ~ s operation are presented in ~ig 2.19 .
37
FGic ur r"SCIA~. USE ONLY
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APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-44850R000400024405-4
_
FOR OFFICIAL USE ONLY
i
~
i
_ - - - . _
U cmpovNOU pa~OepmKUBK9 1~ ~ � ~ _
~ ~
~ . ~ ' .
~nxc�SIMKC Toxe=1YMKC Z
x~ 3> 4~ I
,
- a~ . . e ~
U~QdpoBan paa/e~m,ru BA'y i
1
1 ~ ~ '
Tnxr. ~ 1~MC T xK= 2 NC ~
NNK 6~ � H~ � ' j
t
Figure 2.19. Time Diagrams of Synchronizer's Operation
Key: ~ ;
_ 1. U, VKU horizontal scan 6. Ink
_ 2' Ins Tpkhk ~ 18 ~~vertical scan rise
3. TPkhs � 52 us 1,
time]
4. Tokhs = 12 us 8. Tokhk = 2 ms
5. U, VKU vertical scan '
The DA module is switched into c~peration with the arrival from the microcomputer's
digital outputs of an eight-bit code for the initial address (A~) of the zone of ,
the storage to be displayed and of a single-bit Zp [entry] signal. The display
adapter makes it possible to form on the VKU's screen characters in ~i~e same _
sequence in which they are arranged in the storage. After readout and display of
the last character in the last line, the cycles are automatically repeated with -
a frequency of 50 Hz. I� in the same sequence of bytes (characters) to be read
out from the microcomputer's storage a code appears corresponding to the symbol
KT [end of text], then further information (to the last character in the last line)
is not displayed on the 'VKU's screen from the 256-character zone indi:.~te~ ~n
AO .
When the signal "Inversion of Brightening" arrives from the microcomputer through
the single-bit digital output, bytes read out from the computex's storage and
having a"1" in the eighth posit~on are converted into characters in keeping with
KOI-7 code with the inversion o~ brightening.
The dispZay adapter rzYre~~n*_s a selector channel with direct access to the com-
puter's storage, making possible the conversion of para11e1 codes read out from
38
FOR OFFdCIAL USE ONLY
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APPR~VED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400020005-0
FOR OFFICIAI, USE ONLY
the computer's storage into a serial code for the purpose of modulating the
brlghtness of the beam through the video channel and the output of pulses for
synchronizing the horizontal (In ) and verical (Ink) scanning of the VKLT in
acr_ordance with the television s~andard.
Direct access to the computer's storage has been arranged for in the DA by taking
into account the fact that access of the processor to the stora~e takes place
always in the second half-cycle of the clock pulse for powering the micracomputer's
dynamic logic, whereas the unit for forming interrogations of the storage (the
BUZ ZU) of the DA module accesses the microcomputer's memory only in the first
haI~rcycle (in phase F2). -
For the purpose of matching the slow rate of readout from the microcomputer`s
~ storage with the high rate of horizontal scanning, a buffer storage (BZU) has
been added, executed on the basis of a K536RU3 LSIC and making it possible to -
store characters for two character lines of the VKU. -
The circuit for synchronizing the operation of�the DA contains a quartz oscillator
for clock pulsps with a frequency of f = 2.7 MHz (a GTI) and a counter-divider -
. with decoders {"synchronizer"). TI
_ The formation of each character on the VKU's screen is accomplished by the method
of a character matrix with a 5 X 7 arrangement, whereby two television lines are
used for a single character string of the matrix and six television lines are
used for forming a space between character lines (a total of 20 television lines
. for a single character line and the space).
With I and F2 pulses and the presence of KT , Vkl ["On"] and T
signalsn~he BU ZU [as published] unit requests in each television li~ie~aeadin]
byte of inf orma~~on from the computer's storage, whereby the high-order bits of
the address code correspond to A, entering from the microcomputer, and the low-
order to the current number of. the television line (No ts).
This byte of information from the computer's storage is stored in the buffer re- _
gister of the readin control unit (BU ) during the torward movement of the
television line and is copied ir.to thepBZU with an address corresponding to the
current number of the character's television line (N ts/zn) during the line's
return movement. The higher bits of the PZU 's address code are read out from
the BZU according to the N zn/st [number of c~aracter in the line] address during
the forward horizontal scanning stroke. The low-order bits of the PZU 's _
address code correspond to the number of the character's television lin~ (N ts/zn).
Information read out from the PZU (a K536RYe2 LSIC) enters the shift register
(Rg Sdv), from whose output with agfrequency of fT (with the absence of Tokhs
and T h signals) is formed a signal for control~ing brightening for the -
VKU's �v~deo channel.
The module is powered by -24 V+ 5 percent, -I-3 V-~ 5 percent and -h5 V+ 5 percent
d.c. power sup~7iPs. The total consumption is not great2r than 10 W. The overall
dimensions of the DA module are 298 X 165 X~5 mm and it weighs no more than 0.7 kg.
39
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APPROVED FOR RELEASE: 2007/02149: CIA-RDP82-44850R000400024405-4
FOR OFFICIAL USE ONLY ;
~
- "Kvant-M" 'Pype Information Di~play Video Monitor (VKU) !
This module makes possible in combined operation with the DA the output on the ;
screen of a cathode ray tube (CRT) in alphanumeric form the contents of the !
memory of a microcomputer with a capacity of 256 characters. The "Kvant-M" !
type VKU is a unit for the pasaive display of information stored in a storage. ~
- A photograph of the "Kvant M" VKU is presented in fig 2.20 [photograph not re- ~
produced] and a diagram of it in fig 2.21. The VKU contains the following: !
= A type 16LK2B CRT; a horizontal scanning driver (gsr); a vertical scanning
_ driver (Fkr); a video channel br3ghtness intensif 3er (W); and a high-voltage .
transformer (PV).
+9KB 2)
.,~ooe 3) ,
ne .sae 4)
1) ~
~
~ ~cp 5 ~ ;
,
, 't ~Kp 6 ,
i 169Kf6
7)
BC yB ~ Q)
9) ~
�ApKOCma"
Figure 2.2~. Ai$gram o~ '~Kvant-M" yRU
Key:
1. Transformer 6, Vertical acanning driver
2. +9 kV 7. VS [video aignal]
3. +300 V 8. Brightneas intensi~ier
4. "Focus" 9. "Brightness"
5. Horizontal scanning driver 10. 16LK1B [as published]
The method of forming an image on the CRT's screen is the television method. The
frequency of horizontal and vertical scanning is respectively 15,625 and 50 Hz.
Since in the reproduction of alphanumeric information on a screen nonlinearity of
scanning is especially noticeatile to the eye, for the purpose o.~ reducing this
distort~.on dr~.vers k'sr and glcr have been c~nstructed on the basis of integrated
operational ampli~iers with ~eedback,
40
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FOR OFFICIAL USE ONLY
Siiice the information to be read out on the screen has only two gradations of
brightness, the brightness intensifier has been executed in the form o~ gating
stages. The volume of information read out can be varied over a~ride range--
from a single character to complefie filling of the screen. Therefore in the _
bri;htness intensifier aection have been eliminated bypass'and interatage capaci-
tors whose transient processes of charging and diacharging would cause a change
in brightness.
The high-voltage source has been executed by means of an electronically stabilized
voltage multiplier circuit and is synchronized by meana of horizontal scanning
pulses for the purpose of reducing noise. Electronic stabilization makes it _
possible with a change in load current from 0 to 100 uA to change the 9 kV voltage
over a wide range. The transformer (PV) also forms a+300 V acceleration voltage
and a+50 V voltage for focusing.
The "Kvant-M" VKU is powered by a+12.6 V+ 10 percent d.c. power supply. The
- load current is not greater than 1.5 A. The overall dimensions of the VKU are
190 X 180 X 250 mm.
Th~ structural design of the "Kvant-M" VKU makes it possible to use it both as _
a self-contained desktop instrument (in its plastic case) and as an instrument
built into the system's console (in this case the plastic case is removed). -
"Elektronika P5-PPZU" RROM Functional Module
This module is designed for storage, in the absence o� a power suppJ.y, o~ period-
ically changed information.
Key technical data: information capacity--1024 16-bit words; information access
time not greater than 5 us; length of storage of information with power cut off-- -
_ 2000 h; number of rerecording cycles not less than 104 ; power supplies--+5 V+
+ 10 percent, +24 V+ 5 percent and -12 V+ 10 percent; total power requirement
= not greater than 5 W; overall dimensions 300 X 188 X 30 mm.
It is reco~nended that the working changing of information in the PS-PPZU module
be performed Frith the "Elektronika P5-ZP PPZU" unit. _
System Operator's Console -
This unit makes it possible to control the order of executing the system's tasks,
t~ enter new information into the microcomputer and to read out the results of
computations to displays and audible signalling systems.
A diagram of the console is presented in fig 2.22 and contains the following:
_ a keyboard unit (BK); a display unit (BT); a dyn.amic loudspeaker (ZD); a keyboard
coder (ShK); a digital output channel (TsWl); amplifiers (U1 to U9); and a
phase voltage generator (P1 to F4). The exchange of information between the
console and the microcomputer is carried out through software and hardware via an -
input/output interface.
41
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FOR OFFIC[AL USE ONLY '
i
i
. _ . . - ~ i
6A' j,~ f t 10 6N 2) i
, ~ . 4 ,
z a~ 3 ~ ~~,4
. .
K~ . ~
y 6) ;
. ~
- . ' ~
5) � ,
- . lUK
- � 7) a~P~ ,
~ . . . B
PZ V1
~ 9 .~n=ye 14) y9
- ~ 12 n~y~ 1
ary , e ~ s,4 ;
io> i3 '
6!I n~yt '
~pQ a:,Nx
~ ' 11) d BMJ g~ R1 -
15) �19~ , '
OJy C,~L'pt ~t ~ frNepamop � -
17) 21)
16)
eMz oz mi ~4
- ~ 22)
Figure 2.22. Diagram of Operator's Console ~
Key: '
1. Keyboard unit ~2. Contxo7, point xeg~.stex
2. Display unit X3~ '
3. Lamp 1 7.4. U1 to U8
4. Dynamic Loudspeaker ].5. Gate 1
5. Keyboard coder 16. RAM
6. Switch 17. Register 1
7. Comparison circuit 1 18. Output reg3ster -
- 8. Distxibutox 2 19. TsWl
9. F4 20. Dynamic loudspeaker input
10. Intexrupt 21. ~hase voltage generator
11. Control 22. Phases
~ 42
FOR OFFICIAL UcF ~NLY -
APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400020005-0

APPR~VED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400020005-0
w
FOR OFFICIAL USE ONLY
The keyboard coder (K536TV1 LSTC) makes possible the entry o~ data ~rom alpha-
numeric (maximum of 60 ke~~s) and function (maximum of 30 keys) keyboards.
- The keyboard unit of the system console contains the following: 4 X 4 alpha-
numeric keys and 4 X 2 function keys (VR [expansion unknown], NR [expansion
unknown], Uprl [Control 1], Upr2 [Control 2], etc.). ~
The keyboard coder performs the continuous scanning of keys (K1's) of the keyboard
unit with a frequency of 200 Hz. Furthermore, through its 10 outputs distributor
I'cl sequentially excites the vertical lines of the keyboard matrix (only one verti-
cal line is excited at each instant). When any key is pressed this excitation is
transferred (in the appropriate operating cycle of R1) to a certain horizontal
line of the matrix. Tn each operating cycle of R1 is performed the comparison by
means of SkhSrl of a nine-bit code from the horizontal lines of the matrix with
the state code of the nine-bit distributor (shift register), R2. During one
complete switching cycle of distributor R1 a pulse is formed for carry to the input
of distributor R2. The codes for the states of distributors R1 and R2 represent
the address code for ROM 1.
When any key is pressed, from the output of SkhSrl is formed a signal through
which occurs the formation of a key code in the following order; If one of the
function keys (VR, NR, Uprl, Upr2, etc.) was pressed, then the code for this
key is copied from ROM 1 into register Rg Ust [control point register]; if a key
from the 4 X 4 field ~is pressed, then its code is read out from ROM 1 and, taking
into account the code in Rg Ust, recoding is performed by means o~ ROM 2 for the
purpose of producing in register Rg 1 a code corresponding to the KOI-7 (KOT-8)
code of the key pressed.
From a signal from the BU [control unit] is performed a comparison of the code
entered in Rg 1 with the codes in the five locations of the RAM; if comparison _
circuit SkhSr2 then does not produce a signal for equality of the codes, then
in unit BU a circuit is switched on for forming a delay for the duration of the
"chatter" of the contacts (from S to 40 ms), depending on the three-bit control
point code, N. The working cycle concludes with a repeated check of the re-
pressed key and the formation of suppression signals in Rg 1 and information
readiness signals (Prv) with which the microcomputer issues a request for readout
and an address. When information is read out from Rg 1, at the same time it is
entered in the RAM in the microcomputer.
After removal of the request for readout, suppression for entry into Rg 1 is
switched off and the keyboard coder LSTC i~ ready for the reception and transfer
of the next information. ~f in the first cycle after the removal of the suppres-
sion of Rg 1 a pressed key is detected, and if the code for this key is stored
in the RAM, then its transfer to the microcomputer will be suppressed; and if
this is a new code, then it will be transferred to the microcomputer and be
entered in the RAM. As a result, in the RAM wi11 be stored up to five "simul-
~ taneously" pressed keys, which makes it possible for the keyboard coder LSIC to -
enable sntry fz~m five "simultaneouslp" pressed keys.
If during a complete scanning cycle a pressed key is not detected, then the erasure
of information takes place in the RAM.
43
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APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000400020005-0
~
FOR QFFiCIAI. USE ONLY
Information enters indicators L1 to Z8 ~rom the ~3.crocatqputer through output
register TsWl and ampliPiers U1 to U8. The input atgnal enters the dynamic
loudspeaker (ZD) through volume control R1 and amplit~.~r U9.
Interfacing the "Elektronika SS-12" Microcompu~er with MFM~s
Functional modules can be used together with a single-board microcomputer in any _
combination desired.
The nucleus of these systems is the "Elek~ronika 55-12" micr~com~~ter, whose inter~
face is in common with modules connected from~ the outsi.de. fihe microcomputer forms
all signals for accessing these unfts and does not require additional interfacing
circuits when connecting any module. At the same time it is necessary to impose
a number of restr:tctions in order that the capability of an arbitrary arrangement -
will not result in a number of cases in the creation of technically and economic-�
ally unfeasible configurations and, in connection with this, in discrediting the
idea of the use of single-board microcomputers and MFM's. Let us discuss these
restrictions.
The first restriction relates to the capacity of the working storage. The address
line system provides the capability of accessing a memory with a maximum capacity
- of 32K words. However, the construction of large capacities from modules with a
capacity of 4K words is unfeasible if only because the chief advantage of the
"Elektronika SS" microcomputer series is the implementation of advanced I/0
functions in a single-board model. It is recouunended that no more than two RAM _
modules be connected. It is obvious that when it is necessary to create large
RAM storage capaci~ies in a specific system another microcomputer model should be
used, e.g., the "Elektronika 60" microcomputer.
The use of more than one ROM MFM is also not recommended.
Restrictions on the number of I/0 modules are similar. The connection to the
microcomputer of~more than three parallel interface MFM's, more than one module
for communicating with a teletype and more than one ADC module is not recommended.
The connection of more than one DA MFM is not permitted. It must also be taken
into account that its use is possible only together with a RAM module, since the
output to a display of information from the internal storage is not provided for.
Let us discuss some configurations of computing facilities constructed with a
single-board microcomputer and MFM's, and the key goals which are achieved by
means of a specif ic configuration.
"Elektronika SS-12" Microcomputer + RAM
- This most obvious configuration is intended primarily for those users who totally
suppor t the concepts o~ small con~igu~ations and single-board microcomputers, but
- for whom the capacities o~ the RAM's of today's microcomputer models aze not
sufficient �or their tasks.
44
F~
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APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000400020005-0
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"Elektronika S5-12" Microcomputer -i~ RROM _
Tkis configuration can be recotmnended for a number of cases. ~'irstly, for the
development of experimental models of equipment prior to the fabrication of
ROM LSIC's. Secondly, for putting together equfpment to be produced in small
quantities, for which the fabrication of ROM LSIC's is not ~ustified economically.
Thirdly, for the creation of equipment in which the main part of the control or _
data processing algorittun is unchanged an d can be realized with ROM LSIC's in- _
stalled directly in the microcomputer, and a certain part requires changing only
when going from one modification of equipment to another, or in the process of _
use of each equipment unit.
"Elektronika S5-12" Microcomputer + ADC _
This configuration can be used in quite varied fields o~ engineering. For example, -
on its basis can be constructed complete measuring instruments or sections for
measuring technological parameters within the structure of an ASUTP [automated
system for controlling technological proceases], whereby the results of ineasurements
can be displayed or documented by one of the methods discussed below. This con-
figuratior. can also serve as a basic digital servo system in which control of the _
drive is accomplished by the pulse width modulation method by means of timer
circuits included in the structure of~the "Elektronika S5-12" microcomputers, or
by means of digital-analog converter circuits, e.g., of the K572PA-1 type, which
are to be interfaced with the microcomputer and built into user's equipment.
"Elektronika S5-12" Microcomputer + TsW [Digital I/0 Unit~
This configuration quantitatively broadens the capabili~y oi a,~?~:.rocomputer's
parallel interface for the purpose of connecting information sources and receivers
and control units and displays, as well as for the software formation of special
interfaces.
- "Elektronika S5-12" Microcomputer + RAM + Displa}r + Video Monitor
The purpose of this configuration is the display of the results o~ computations
made by the microcomputer, and more precisely of figures whose display is required
- by the operation of the equipment into which the microcomputer is built. A dis-
play section of this kind can be regarded in two ways. It can be regarded as a
"poor display," making it possible to read out only alphanumeric information, and -
to an extent of less than 300 characters. However, it can be regarded as a unit
capable of uniting information ordinarily read out on separate digital displays
and capable of accompanying this in~ormation with the required text, ~acilitating
its understanding by the operator, warning o~ tl~e origin of a critical si*_uation,
etc. Furrhermore, it must not be feared that the filling of even such a small
display will be incomplete in a specific application: Tn the configuration dis-
cussed the DA MFM replaces several boarda o~ the para11e1 interface even with 50-
percent utilization o~ its capabilities with respect to the amount o~ in~ormation
displayed.
45
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"Elektronika SS-12" Microcomputer -1~ Operatorts Console ~
This configuration makes possible the manual entry of information into the micro- !
computer. Tn combination with the preceding conf iguration it represente the
technical basis ~or arranging for a dialog between the operator and equipment ,
constructed on the basis of a m3crocomputer. '
"Elektronika 55-12" Microcomputer + Telegraph Set (TA)
The purpose of this configuration is to enable documentation, the working entry
of data files fram punched tape and individual numbers from a keyboard, and the
readout of information onto punched tape.
In addition, this configuration can be a means of interfacing remote microcomputers
with one another or with a computer of a higher level wh~en working in a hierarchi-
cal system.
With the additional connection of a working storage ("Elektronika S5-12" micro-
computer + TA + RAM configuration} a teleprinter veraion of a supervisory system ,
(TVDS) can be employed.
Let us discuss a configuration which can be used as a facility for debugging pro- ~
grams for users for whom the purchase of a multiboard machine for debugging prob-
lems is unacceptable for one reason or another. A minimal conf iguration can serve
as a program debugging facility: a microcomputer, one or two RAM modules and a
TA moduZe. The number of RAM modules is determined by the volume of problems to
be debugged. ~
A teleprinter version of a supervisory system (a TVDS) with a capacity of 1024 ;
words, which is located in the microcomputer's ROM, serves the purpose of controll-
ing the operation of this system. The debugging system affords the user with
facilities for working interaction with the supervisory system and the microcom-
puter's specific software. The debugging of user's problems is performed from the
TA by entering information of any kind--new routines or numbers--into the micro-
computer's working storage, by communicating to the supervisor the parameters of
problems and the initiation of problems, and the output of information from the
microcomputer's storage to the TA [11].
2.5. Multimachine Systems Based on~the "Elektronika 55-12" Microcomputer
The small overall dimensions and low cost of "Elektronika S5-12" microcomputers ~ _
have been responsible ~or their use as a multipurpose module to be built into
various kinds of terminal equipment, such as regulators, measuring instruments,
bench equipment, machine tool equipment, data processing equipment, consoles and
the like.
Microcomputers built into terminal equipment contain a set o~ prog7rams ~or con--
trolling this equipment (~or its various operating modes) and through their input/
output channels have an interface both with this equipment's data transmitters and
with its actuators. In the construction of systems using term3.na1 equipment of
46
FOR OFFICIAL USE 4NLY
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APPR~VED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400020005-0
FOR OFFICIAL USE ONLY -
this type and a centxal computer w~?ich pex~ox'ms supex~r~,aoxy functions with xegard
to this terminal equipment on the basis of the results o~ solving a major problem
of the system, the problem arises of arranging for the combined operation of
several microcomputers.
In org~nizing the combined operation of microcosaputera in a system of this sort
the necessity arises of transmitting from the central microcomputer to a peripheral
microcomputer located in the terminal equipment messages of tita ~ollowing types:
switch on, switch off, transfer a new setting, sw~.tch to the execution of the task
_ required, interrogate the state of equipment and the like.
In turn, the per ipheral microcomputer must have the ability to transmit to the
central microcomputer �~aessages of the following types: the state o~ equipment, the
results of data processing, campletion of the execution of a task and the like,
i.e., signals tranemitted from one microcomputer to another represent (for a system
of this type) short messages with a low repetition rate. It is advisabZe to inter-
change information~,rith these characteristics through multiplex channelr.
In fig 2.23 is p resented a structural diagram for the connection of two microcom-
puters of the "Elektronika SS-12" type, making possible the interchange of informa-
tion byte by byte, I1 and I2, through registers Rgl and Rg2 0~ the TsWl channels
of both microcomputers. The TsW3 channel of microcomputer No 1 and the TsW2 of -
microcomputer No 2 operate in the mode of the reception of interrupt signals: PD1 -
is the signal for advising of the transfer of byte Il; OTV2 is the signal for a
response regarding the reception of byte T1; PD2 is the signal advising of the
tzansfer of byte I2; and OTV1 is the signal for a response regarding the reception
of byte I2.
The microcomputer's operating sequence in transferring a single byte o~ information _
from computer No 1 to computer No 2 must be as follows:
I. In computer No 1.
1. Information I1 is entered in TsWl.
2. PD1 = 1 is entered in TsW2.
3. PD1 = 0 is entered in TsW2.
II. In computer No 2.
1. Interrupt signal PrV2 (PD1) is processed.
2. Information Il is read out from TsSTV1. -
- 3. OTV2 = 1 is entered in TsW3.
4. OTV2 = 0 is tntered in TsW3.
III. In computer No 1.
1. Interrupt signal PrVl (OTV2) is processed.
In this algorithm the serial entry into the same output register location of first
a"1" and then a"0" makes it possible to form a pulsed output signal. -
With a similar algorithm it is possible to arrange ~or the combined operation o~ a
single (central) microcomputer ~rith several pertpheral micxoco~tputers, using ~ox
this purpose, as iliustrated in fig 2.24, 3n addition a digital input/output mo-
dule for every three peripheral microcomputers. The exchange o~ in~oxmation byte
47
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FOR OFFICIAL tJSE ONLY ~
_ by byte (I12, I21, T13 and T31) is acco~aplish~d thxough twQ channels (Ts'Wl and
TsW2) of the digital input/output module, and signals PD12, OTV12, ~D13 and ;
OTV13 enter the peripheral microcamputers (into their interrupt input/outputs) ;
via channel TsVp3. Signals PD21, OTV21, ~'D31 and OTV31 enter from the peripheral
microcomputers via channe~ TsW4, operating in the interrupt signal reception mode.
CS-!1 Nq . CS-12 N�Z
2 ~ qBBI 1(8B1
- .'4 ~ Ni(B) -
3 ~ 'Pt 1 Pt2 ,
N?(B)
Pr2 Prl
4Be2 n,4~f11 S) ueaz
~eJ ~P�~6~
Pzl OIB1(i) 6 PZ1
(BJ Ptt Pz I ~pBi ~ ~ ~
.
1
!(QB3 nQ?~~I ;:(BB3 ~
~pB~6J (6) � a
~ PY 2 OTBt (11 Pt 1 ~ ,
a u
~ n e~ ~8J ~
P Pr1 . Pr2 ~
o , -
~
qeB4 :(riB4 ,
r8~ Ptl (8, -
Pt! �
~8J Pr Z (B)
Pr1
8) ,
~M-7y N�1 ~M-yBB X'1 ~M-9yN'2 ~M-9B8n�Y
Figure 2.23. Diagram of System o~ ltao Microcomputers Linked via TsVV's
- [Digital I/0 Units]
Key:
1. To system No 1 6. OTV1 =
2 . TsWl 7 ; ~ry [ intex'rupt ]
3. Rgl 8. Storage ~unctional module No 1
4. I1 9, ~nput/output unit functional
- 5. PD1 module No 1
48
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. .
' CS-1t N.~ . . � ' ,
IJoDyne yu~poBux. SxoDos-se~xo~os �
, ~ ~ 2)
1) ~ ~ qBBf yeBt~ QOBd QBB4
i .
Cf-11 N�2
~ ~
m Ht I
4) ~ ~
~ . ^
n,Q11 ,o /1pB1 v ~4tz: ~ ~
OTB?1 ~ ~ ~ OTB1Y
5)
CS-1T N�3 � .
N1J '
^ Hdf
~ ~ i
R4.~~ nQ~~ ~ " � .
npea w
_ OIB3I d m 01813 .
~
Figure 2.2~+. Diagram of System of ~'hree Microcomputers Linked via TsW's
Key: 4. PD21
1. TsW's
2. Digital input/ouput module 5. OTV21
3. I12 6. Pr'~12
The permitted interrupt signal enters the interrupt input of the central microcom-
puter f rom the output of channel TsW4 of the digital input/output module.
It mus t be mentioned that it is possible to connect two more peripheral microcom-
puters to the central microcomputer i~ its digital input/output channels are used
- ! for this purpose.
i
49
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The structural diagxauls o~ mu~ti~rlachi~ne syste,~ p7cesented ~n 2. z3 and 2.24 :
are realized on the basis o~ ~uncti.ona~, modul~,s, but w~,th an incxease in the .
number of peripheral micxocomputers fs zequired a gxeat numbex o~ centra7. micro- ~
_ computer digital input/output channels and communication links. Tn fig 2.25 is i
presented the structural diagram o~ a mu1timachine syetem of the trunk line type
- which minimizes the amount of equipment for arranging for intn20haVn02,bVn30hich 1
= requires the user to connect eight-digit gates (Vn10, VnU1, V , -
Vn03, to systems.
The following design.ations are used in fig 2.25: TsW represents an eight-bit
information input/output channel; PrVi is the interrup~ signal of the i-th com-
puter; OIi represents eight-bit infarmation entering from the common trunk line
into the 3-th microcomputer; IO representa eight-bit information entering from
the i-th computer into the common trunk 1ine; PAii represents a single-bit signal
for advising the j-th com~esentsf atsingleabit signaleforft~e reaponse of theci-th
puter No 1; anci OTVi~ rep
computer to the j-tFi. _
- The operating sequence of the microcomputers when transmitting a byte of informa-
tion from microcomputer No 2 to microcomputer No 1 must be as follows:
I. In computer No 2. ,
1. Information I20 is entered.into TsWl.
2. PD21 = 1 is entered into TsW3.
- 3. PD21 = 0 is entered into TsW2.
II. In computer No 1.
1. Interrunr signal PrVl (FD2l.) is processed.
2. Gates Vn01 are opened via TsW3.
3. Signal OTV12 = 1 is entered into TsVV3.
4. Signal OTV12 = 0 is entered into TaW3. _
ITI. In computer No 2.
1. Interrupt signal PrV2 (OTV12) is processed.
2. Gates Vn20 are opened via TsW3.
- 3. Signal OTV21 = 1 is sent out via TsW3.
4. Signal OTV21 = 0 is sent out via TsW3.
IV. In computer No 1.
1. Interrupt signal PrVl (OTV21) is ~rocessed. _
2. Information I01 is read out from TsWl.
3. Gatps Vn01 are closed via TsW3.
4. Signal OTV12 = 1 is sent out via Ts'W3.
5. Signal OTV12 = 0 is sent out via TsW3. _
V. In computer No 2.
1. Interrupt signal PrVl (OTV21) is processed.
2. Gates Vn20 are closed via TsW3.
3. Signal OTV21 = 1 is sent out via TsW3.
4. Signal OTV21 = 0 i~ sent out via Ts'W3.
VI. In computer No 3. -
1. Tnterrupt signal PrV'1 (OTV21) is pxoaessed.
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, (1-8) 0~~21 ,
' . ( 7-9) O,Q?l
~ OTB f2'
`-r--~ '
n,qu _
uee4 uee.~ ,
- ,
ppBl 4 jS-11:Y�7 QBB4 I~BB.~
I~FBI [~8B2 . /1pB2 CS-1Z N�Z -
N1D ~ H01 QBBP uBBI -
5 fl-B) (1-8J
H02 NZO
BMw~ b ayo~ a (~-a1 . {t-el
6~ By02 a BdPO b -
� OTB 31
~ ~ . n,4,~~
~ OTB Jd '~1
I
nQ~a
7)
~ _
b u~e4 uBe.~
E
; . ,
i ~ ~ /lpBJ 1 CS-12 N~d
� ueBt !(BB1
o ~
:
. ~~d~ (1-8)
6WO9 ~a BHJO b L
Figure 2.25. Diagram of a Multimachine System Linked via a~arallel Inter- _
f ace =
(Key on follow~ng page]
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,
Key : 1. OTV21 5, ~~.0 i
2. PA21 6. 'V`~i~0 ;
3. TsW4 7. Comwon txunk line ~
4. PrVl '
With great relative distances between microcomputers, for the purpose o~ lowerin~' 1
the cost of the communication channel it is ~iossib1e to arrange for the ~oint ,
operation of microcomputers by includtng a TA functional module in the structure ;
- of each microcomputer. This makes it possible to arrange for exchange by means of ~
a serial code. ~
A diagram for the connection of two microcomputers of the ~'Elektronika 55-12" type ;
_ by means of TA modules is presented in fig 2.26, where ~D r~presents a single- i
wire line for the transmission of data ~ro~ microcomputer~o i to microcomputer ;
No j. With this type of connection, for each microcomputer the other microcom- ;
' puter is regarded as a te].eprinter and the operating algorithm for this system ;
is similar to the operating algoritYun for a microcomputer with a teleprinter e~-
ploying a TA module (whereby exchange can be performed in the duplex mode). ;
~
_ . - : _ i
. ' I
CS-11 T~ ;
N'l ~N'1 ,
1
~ n,q~2 nqY1 ,
' CS-12 2 ~ TA ,
N~p ~ N~i ,
Figure 2.26. Connection Diagram for a System of Two Microcomputers Linked
via a Telegraph Set ~
Key: 2. PD12
- 1. TA [telegraph set] ,
The connection of additional computers to one o~ the computers shown in f ig 2.26 ,
car be accomplished through one of the circuits pre~ented in 2.23 t4.�2.25.
= 2..6. "Elektronika 55-02~' Microcomputer ;
The "Elektronika S5-02" is a multiboaxd model o~ the "El.ektxonika SS" m~crocomputer
series and represents a 16--bit cozpputex w~th evo~.Red atorage and input/outpt:t
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systems. This microcomputex's external. appear$nce is shown in ~ig 2.27 [photo-
graph not reproduced].
_ The following are the main features of the "Elektxonika SS-02" micxocomputer:
large capacity of its internal storage (up~to 20K 15-bit words); an extensive set
of equipment for can~rolling external spstems; the presence of a built-in control
console designed for starting, stopping and indicaCing the state of the micro-
computer and for executing program debugging routines; the presence of a built-in
secondary power supply; and total structural completion (a unified chassis and
case).
The "Elektronika S5-02" microcomputer's design includes the following: a micro-
processor, a storage, an input/output unit, a control coneole, a clock pulse
_ generator and a power supply.
- - - - - - - .
lUA
lly~em . Z~ M~ y~p, nazucmpar.s y3y tOf,~x16 OJ9 /i3y /i9y
1 IOfEX16 4096X16 4096xJ6
- 4~ .
Modynb Mody~b i'~'od ne . ~
ma~tMepa np~ NBaNU~v y~~M
a~aoao~ 1Q)
ABB
l!/NG~B
, ~ ptlB/!!l~HdA j ~
NOt!/CTQOIIb BB
MoJpns MaByna Modyna NaJyne MWyrt1 Noaj~~
yBB 9BB �9BB nn pM ~ut~nnea Nodyna Mo9yne NoByne. _
~ 4 1 lfi 9~qn ~ nHC-z
13) .
- nep~o- nep~o- nM
_ 21) BBod 2 Oe~Ood 2 koHCye 24 ucnn ~ 5 TA 2 6 M10o ~ -
)
Figure 2.28. Diagram of "Elektronika SS-d2" Microcomputer
Key:
1. Cons~le 8~ Timex module
2. Microprocessor 9. xnterxupt ~todule
3. Address line 1.0, z/0 contx'ol module
4. Control line 11. z/0 address 13ne
5. Storage control (UZU) 12. T/0 in~ozv~tton line
6� RAM 13. T/0 unit module
7. ROM 14. ~P [punch converter] module
[Key continued on following page] � -
,
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_ 15 . PM [ loading mach~r.~] wodu~.e. 22 ~~'unch output ;
_ 16. Display module 23. "Consu~" ].pad~ng ~qa,chine ;
17. TA module 24, Aisp~,ay~
- 18. Controlled Z/0 line 25, TA [tel.egraph set] ~
19. ADC module 26, "Modem-200" ~
20. PTS-2 module '
21. Punch input '
Functionally the 16~bit microprocessor does not differ from processors of all i
models of the "Elektronika S5" series designed on the basis of a un3fied p-cb.annel
set of LSIC's. ~
The storage consists of a RAM and a R~ wrlth a total capacity o~ 20K 16-bit words ,
and a control unit which forms storage control signals (a UZU). The ROM includes
individual functional ROM modules, each of which represents a storage with a
capacity of 2048 16-bit storage locations. The information storage principle is
the static one. A RAM module includes also an addreas decoder, RAM clock pulse
- amplifiers and readout amplifiers.
The ROM is made up of indivi~~.~al ROM modules, each of which represents a storage ,
with a capacity of 4096 16-bit storage locations and includes an address decoder,
clock pulse amplif iers and readout amplifiera. Blocking of the ROI~I with an identi- ,
cal RAM and ROM address is provided for. The structure and number of RAM and ROM _
modules in the microcomputer can be changed depending on the specific application. ;
The microcomputer'~ input/output unit makes possible the following: the operation
of a set of input/output peripherals, a multilevel interrupt system including
program-controlled timer channels, and the operation of a microcomputer control -
console. ~
The following are the key functional components of the "Elektronika S5-02" micro-
comps~ter input/output unit: a digital input/output unit; a routine-interrupt
signal input unit; a punch control unit and an FSU; an analog-digital converter;
- a TA control unit; a display adapter; a"Consul-260.1" EPM [electrical loading
machine] control unit; a unit for interfacing with the "Modem-200" and UPSTG
[clack signal conversion unit]; and a program-controlled eight-channel timer;
a unit for the reception and output of information to the microcomputer's control
console; and an input/output control unit which includes an information exchange
circuit and an address decoder.
The f irst six units have electrical circuits which are identical with the circuits
of the corresponding functional modules.
- In the "Elektronika SS-02" microcomputer has been implemented the program-con-.
trolled hardware method of controlling peripherals. Therefore, the peripheral
cont~ol units included in the microcomputer's structure represent a set of input
and output registexs with circuits ~ox matching 1evels mak~ing possible the opera-
- tion of peripherals, and the algorfthm for their operation ~s implemented through
programs (microprograms). The addresses o~ T/0 cY~annels, the RAM and ROM are
- located in a uni~ied memory ~ie1d and are coded in speci~ic bita of the 16-bit
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address code, :i.e. , addressing o~ Che x/0 uni~ takes p7.ace ,juat as the addzessing
of the storage does~ There~oxe, the, input/ouz~nt contxo7. un~,t generates a set
of signals whir_h foxm an input/output inter~`dce and wnich c~;atxo~. the exchange
of informatior. between pexf,pherals and the ~nfcropxocessor tn the async:hronous mode. -
Three groups of lines ~orm Che input/output inter~ace: 16 input/output information
lines, 36 T/0 unit address predecoder lines and eight control lines.
All input;~~~*_g,~t interface and power lines are 1ed out to the microcomputer's
external connectors for the purpose of making it possible to connect additional
units for controlling peripherals.
A three-level interrupt system is used in the "Elektronika SS-02" microcomputer.
- The higher interrupt level represents a digital input of the 1eve1 type. The
~?ighar-1?vel interrupt signal enters the microprocessor. The higher-level inputs
are represented by signals entering fram the second-level interrupt regisCer, which
includes a routine-interrupt register, a computer console interrupt register and
an input/output interrupt register. Routine-interrupt signals and signals for
interruption from the console enter the digital pulse inputs and the interrup t i
signal from the input/ouput unit enters the digital level inputs. _
The third level of the interrupt system is represented by the r:,utin?-interrupt
preregister and input/output peripheral interrupt registers. The digital inputs,
functioning as interrupt registers, depend3ng on the type o~ signal entering, can
operate either in the pulse or in the level mode. The possibil~ty of further ex-
panding the interrupt system is provided for. _
The control console included in the structure of the "Elektronika SS-~J2" micro-
computer is designed for starting and stopping the computer, for entering and =
reading out storage and input/output unit information and f or displaying it, and
for executing program debugging routines.
Console operations are implemented at the microprogram level. The control console
is connected via digital input/output channels through which upon an interrup t
signal from the console the microprocessor shifts to the microprogram implementa-
tion of one of the console operations.
- The machine cycle power generator is included in the microcomputer's structure as
an individual module and makes possible the formation of synchronization puls es
for machine cycle powering of the microprocessor, storage and input/output units.
The power supply in the microcomputer's structure makes it po~asible for it to
operate from a single-phase 220 V 50 Hz industrial network.
The microcomputer's structure includes a chassis on which are mounted printed
circuit boards with connectors of the GRPMT-61 type. Ths power supply is executed
as an independent unit, The control console is in the fox~tn of an individual unit
fastened to the fx'ont wa11 of the frame and is connected with other units o~ the
_ microcomputer via a connector, W3.rfng between boar,ds is accomplished by means o.f
a printed distribution board. The external connectors of the "Elektronika S5 -02"
microcomputer are of the RP~15-5UG type. The microcomputer can be executed in two
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1i
i
vaztants: desFctop and buil~~i,n. The key~ techn~.ca~ chnxactex~,at~,ce o~ the micro- ~
computer are p~'~sented fn table 2.6.
e
~ Table 2.6. '
i-
~ I
Word length 16 btts '
Operating principle Para11e1
Control principle Micropxogram ;
Speed 10,000 operat~,ons/s '
Number of basic instructions 31 '
Maximum capacity of 3nternal stoxage
(RAM and ROM) 20K words
Address augmentation capacity To 32K ~
The microcomputer makes possible the
input and output of information to ~
peripherals as fc~~~~.:~s for the
following models:
"Elektronika SS-02A" 9 single-byte digital 3nputs and 7 sin-
; gle-byte digital outputs; 4 two-byte di-
gital inputs and 4 two-byte digital out-
puta; a PL-80 and PL-150 punch; an FSU -
of the FS-1501 type and a teleprinter,
video monitor and ADC
"Elektronika SS-20B" One single-byte digital input and one
single-byte digital output; four two-
byte digital inputs and four two-byte ,
digital outputs; a PL-80 or PL-150 punch, ,
an PSU~of the FS-1501 type, and a tele- :
printer i_
Interrupt system Three-level ;
The microcomputer generates signals Through four 12-bit channels and four ;
four-bit channels of a program-controlled ~
timer ~
The microcamputer has a quartz
oscillator by which are formed the~ ~
= following frequencies 100, 10 and 1 kHz and 100, 10 and 1 Hz
Levels of input and output signals for
communication with peripherals Correspond to standard levels of TTL
circuits
Power required from 220 V 50 Hz in-
, dustrial network Not greater than 100 W
Overall dimensions 460 X 412 X 243 mm
Weight of microcomputer Not greater than 23 kg
Operating conditions:
Ambient temperature, �C Fro~m -10 to +50
Relative tiumidity of air To 95 percent at +35 �C _
Atmospheric pressure, mm Hg ~'xom 630 to 800
r
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Chapter 4. Microco~pnputer So~twa~e
The quality of modern com~uters, ~,ncluding a~cxocomputexs, and the possibilities of
using them for controlli.ng, processfng and tra~smttting data (U0~'D) are determined
to a great extent by their degree of equfpment ~,rith facilities ~or automation of
, the development of programs~ with operating systems, with librar~es of standard
programs, and with facilitfes for the program check and diagnosis of the state of
the computing system. The reason for this is the steadily growing, and hav_ing
become essential, amount of software design in the process of creatin~ informa-
tion controlling systems.
For such a mass-produced e}.emant~base of equipment.for con~rolling, processin~ arld
transmitting data as microcomputers are, the general software should be united
from an organizational and technical viewpoint with the computer-aided design of
LSIC`s, since RO'M LSTC's are the basic medium for specific routines in information
controlling systems based on microcomputers.
A description of the various elements of the software (PO) of the "Elektronika S5"
microcomputers, as well as certain questions relating to i~s design, represents
the content of this chapter. Here the ma~or emphasis is placed on what standard
software gives the microcomputer user and what typical prob].ems must be solved
by the user in the process of developing apecific routines.
4.1. Instruction Set
_ The structure of the "Elektronika SS" microcomputer series meets the requirements
of universality for performing the most common tasks in the creation of differsnt
kinds of equipment, instruments and systems for controlling, processing and trans-
_ mitting data. The presence in the instruction set's structure of the majority of
arithmetic-logic operations, the evolved addressing system and the ability to
work with words and files makes it possible to develop programs which are effective
- in terms of productivity c.riteria and the storage capacity occupied and which im-
plement various algorithms for industrial automation and the processing and trans-
_ mission of data and algorithms for controllers and terminals.
The presence in the instruction set of special operations making it possible to
control the process of the transmission of routine and peripheral interrupts makes
it possible to arrange for a mulciprogramming mode and the performance of specific
tasks in real time. All this, taking into account the available hardware, makes
- it possible to define microcomputers of the "Elektronika 55" series as broad-
application multipurpose control computers.
The instruction set represents a microcomputer of the "Elektronika SS" series as
a 16-bit computer ~rtth an address field with a maximum of 32K 16-bit words [13].
_ Included in this address field are input/output addresses with which interaction
is carried out by the same operatfons as interaction with the storage. This
solution, which basically does not complicate the structu~e, substantia'i1y extends
~he ability to work w~th peripherals.
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The computer's structuxe inc].udes the ~o1l.owi,ng (~ig 4,1) : a 16-bit ALU [a~ith-
metic-logic untt] with a stngle-bit co~nunicatton xegistex (RS~ and a two~bit
result flag (F), a general address fteld with a capac~ty o~ 2~ bptes, an RgK
[instruction register], and a four-bit problem nualber registex (RNZ) which serves
the purpose of indicating the location of genera'~ registers in the atorage. ;
Sixteen locations are set aside in the storage for each problem in correspondence
with the RNZ and these are used as program-accessible general registers (OR's).
Of these sixteen OR's the first three (the zerofih, ~irat and ~econd) are used for
the microprocessor's operation and are engaged respecttvely by the instruction
c4unter (Sc:~K), the interrupted task register (RPZ), aad fihe protection register. .
The remaining 13 OR's (the third to g) are considered program registers. The
basic unit of tn�ormation in the computer is an eight-bit byte.
Z~ 1 MucCUB adpecyeaou nae+amu u BOaEa-OeiBal� � ~
.o A Honep polp~do0 Ad ec
i (~Bcrc e0eiu 6aum /lpaBa~u daum 6 nP
aBoto PH3 ~
~ darFina) p~ 1 3 4 S 6 7 B 9 10 11 12 1J 14/S �~uma 8~
0 0 '
! 0 0 �J 0 ,
1 0 04 ' 00 S
f 0~1 E ~
0 00 ~
D ~
Z 00 4 0 S 1
f D 0~3 �3 F
0 O1fD O1�1
1 D/E1 O1EJ f.
Z O1 E4 O,I.ES
f 0 1 f� 0 1~F f ,
02 0 1
0 0
DffE ' DffF
1 1~
- ' 9~ . KaNane~ SOOOa 12~ 13~ prK
EFff
;F KaNanai BaiBoBa /ly ~B 1 PHJ
�14)
�
Figure 4.1. Structural Aiagrata of riicrocomputer from the Programmer~s
- Viewpoint
Key:
1. Addressable storage and 4. Number o~ bit
I/0 file 5. Left byte
2. Number. of general register 6. Right byte
3. Address o~ word (left byte) 7. Address of right byte
[Key continued or~ follow3ng page]
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8. Problem number registex ~,2. ~U
9. Tnput channels 7.3. ~esult ~1$g
10. Output channels 14. Cot~4unicat~,on regi.ster
- 11. Instruction register 15. ~xoli7.em number xegister
The instruction set makes pos~ible the execution o~ operations with two kinds of
data formats: a byte and a word. A word consfsts of two bytes--a left and right.
The numbering of bits in a word goes from left to right, beginning with zero.
The zeroth bit of the numtier fn the storage is used as the sign (fig 4.2a). -
Numbers in the computer's storage are represented in complement, and in computa-
- tions, in modif ied complement code with a fixed point after the sign (zeroth) bit.
The range of the representation of numbers in the computer is -1 ~ x< 1. -
Taking into account the representation of numbers 3n the com~uter in complement
code, the maximum positive number (1-2 15) is written as 7F'F~', the maximum negative
number (-2 15) as gFFF, and the mini~mum positive number (0) is written as 0000 and
- the minimum negative (-1) as 8000.
Three instruction formats (fig 4.2'b) are used in the instruction set. Al1 formats
have a half-byte field size. ~
Instructions of format I include the operations of addition, subtraction, non-
destructive comparison, logical addition and multiplication, modulo-2 addition,
search for a right-hand "1," accessing from the storage to general registers, -
loading the contents of the general registers into the storage, logical shifts to
the right and left, ~ump to a subroutine and storage of the return address, and
cycle organization. Mention should be made of the distinctive feature of employ-
ing the "accessing" and "loading" operations, the first of which makes it possi'~le
to directly assign a constant, and the second an unconditional jump to any address
of the storage field.
Instructions of format II are used for making a jump with refer.ence to the state
of a flag and with reference to i.nformation specified in the "mask." Ones in
individual bits indicate the condition for a~ump in accordance with the appropri-
_ ate flag. A forward jump takes place by no more than 12810 addresses with re-
ference to the instruction counter, and a reverse 3ump by no more than ???10
addresses. When it is necessary to transfer control by a greater number of in-
_ structions it is necessary to emplay in addition an appropriate modif~~cation of
the "loading" opzration.
Typical of format III are special instructions. They include working with the
communication register and gener~l registers, attendance to a new problem and
= return to an interrupted problem, accessing a problem number, substitution of a
higher-level mask, working wfth the interrupt system and working with ~lags. Also
belonging to this format are the operations o~ loading the OR [general register]
file into the RAM and o.~ copying the RATrI`s file into the OR, shifts with the
direct indication af the number of shifts--arithmetic to the right and logical to
the left and right, as we11 as 3umps to a mfcroprogram 1eve1 and a halt. Tt should
be mentioned that also included in the basic set oi~ inatructions supplied in all
modifications o~ microcomputers axe tfie multiplication and divis3,on o~ 16~bit
numbers without rounding o.~~ (fig 4.3). ~
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i
~
;
. . _ ~
. _ . - - - - - _ - - - i
a~MamuHNe,u Koa 1} . . . . ;
AeeWU boum 2) OpaOe~ri daum ' 3~ i
- McMmucca 4j ~ _
~
0 l 1 9 4 S~ 6 7'd 9 10 11 f2 1J 14.15 ,
5) 3HCKOBn,u paJpRa , . ~
b) KonaHaei 6) ,
7 ) 1 ~papr+am . _ ~
8) 1-ri nony6aum 2-ri aarydcrrm .~-u nanydarim k-u nonydadm
9) -
cnrpaN u(KOJ B I~M R1 RP
0 1 1 3 4 S 6 7 B 9 f0 11 lt lJ 14 15
~ ~ Y- ! �
If0=1-D /1pu~+oKU MoNJ= NOMtp OP HOMtp OP ;
q~uKayuu a0peca (neO0a0cnepaxd~ (Bmopod onepaNBj ~
10) onepaNAa 11,) 12)
13) 11 �~opMOm . ~ .
- 1-ri noayda6m Z-a ncnydaGm ' 3-u, 4-r3 nonydaume~
KoB MucKa ~pupari{eHUe ;
onepayuu I5 ) ,
14
p 1 2 3 4 S 6 7 8 9 10 11 f1. 13 /4 1S
~ .
_ KO = f �
16) !II ~popMVm -
I-u nonydodm 2-n no~ydaum ~ a nonydaum 4-u nvnybarim
One~ Nd~
adpec on~ilfr06-
KOB BuB I.~ 0/!E QHOD URU Q~ UN 0 MG-
- cnepaquu onepayuu 80y CfIBOMQC ) y RP _
i
_ 0 1 2 3 4 S 6' 7 8 9 10 fl 11 lJ 14 15 -
i
r._--r---"
- , If0=0
i-
Figure 4.2. Representation o~ Numbers and ~nstructions~in Microcomputers
Key: 8. ~~.x~X ha~,~ b ~e
1. Machine code ^ Y
2. Lef t byte 9~ Qpe7Cat~;AA code -
3. Right byte ~.0. Opexand addxees ~riodi,~icatiqn ~l.ag
4, Man~issa 1],. Nwribex n~ general xegister (~irst
5. Sign b~:t operand)
6. Instructians ~.2. Second opexand
7. ~ormat I 13. ~'or~mat I~
[Ke~? t:ontinued on ~o1.lowing page] .
60 ~
FOR OFFICIAL USE 4NLY
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~ FOR OFFiCIAL USE ON~.Y
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- Figure 2.19. Control console of "Retab" industrial robot
~ (a) and selector field of "Matbac" robot (b).
The target control systems for remote-
controlled robots should be developed on the
basis of scanning TV robot systems. A TV
target indication system, developed by
~ ~-t;~ OKB TK [Special Design Office of Engineering
> ~ Cybernetics], and a general view of which
s{ ~
`1 is shown in Figure 2.21, will be described
~ .
below.
~ Voice command systems enable the operator
, to give a robot instructions in the most
natural way. Here the operator can use
standard oral voice communications syster~s
~ for remote transmission of instructions to
_ the robot, which is particularly important
` r for the joint completion of tasks by people
~ and robots. Voice control of robots still
does not enjoy extensive application in
~~a connection with the considerable complexity
~ of speech pattern recognition problems.
There are only a few of such systems with
- - - a dictionary, limited to two-three hundreds
of words, and operated by one-two speakers.
Figure 2.20. General view of master A general view of a 200-command voice
manipulator of LPI-2 robot. command system, developed at OKB TK for
~ robot contr.ol, is shown in Figure 2.22.
[n addition to the master systems described above, standard computer terminals
teletypes, console typewriters, displays, etc., may be used for human operator-
- robot cammunications.
Information display systems are divided into mechanical, visual and acoustic.
Mechznical display systems are used for the most complete and natural involvement
of the neuromotor system of a human operator in the robot control process by means
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- of active dynamic display of information
about the interaction of a robot and
surrounding objects, ancl about its spatial
_
~ orientation. Examples of the use o suc
. systems are tactile displays [75), manipu-
_ lators with force display [36J, a mobile
operator console that displays the spatial
, orientation of underwater work [79].
Visual information display systems c~mprise
the largest group, including information
A; consoles, plotters, scanning robot TV
systems and other sources of information of
visual feedback, and also standard computer
terminals.
~ Acoustic display systems act upon the human
Figure 2.21. General view of target hearing organs. In the simplest case
indication system. acoustic feedback (in the form of
individual signals) can be used for
attracting the operator's attentior~ or for
- signaling a danger. In more comglex cases
. Y a sound signal can carry information about
~,ie interaction of a robot with the
�Y environment or about the condition of its
Y_i;:: subsystems; for instance, the frequency of
- an acoustic signal can carry information
about the force developed by the tool of
the manipulator. The best form of acoustic
communic~tions is oral voice communications
between a robot and human operator. Voice
communications can be achieved through
speech synthesizers or with voice acknuw-
ledgement systems. One variety of such a
~ system will be described below.
Figure 2.22. General view of voi.ce
command ;ystem. The above classification by type and
physical attributes does not reflect the
classi.ficat.ion of tllese systems by utilization on different levels of the control
s~~stem. Such an hierarchical structure of man-robot communications systems is
given in Table 2.3.
As can be seen in the table, on low robot control levels (I-III) man-robot and
robot-man communications systems exhibit a considerable difference. On control
levels IV and V the communications systems tend to be more alike and the languages
approach natural human language. At the s4me time the master systems and informa-
tion display systems, which on level V blend into a single control system, show
the same tendency.
; We will proceed to a more detailed examination of some standard man-robot communi-
cations, developed by OKB TK.
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Table 2.3. Structure of Man-Robot Communicatians Systems ~
Control Master systems Display systems Language
level
I Command buttons; potentiometers TV; telemetry indication
systems
II Master manipulators; master arms TV; telemetry indication ~
systems and force di.s-
play systems
III Target indication and instruc- TV; generalized informa-
tion systems tion display systems
IV Teletypes; typewriters; dis-. Teletypes; typewriters; Task-oriented
- plays; voice command systems displays; speech
synthesizers; speech
reply systems _
V Same Same Limite~i i~atural
TV Target Indication S ystem. Shown in Figure 2.23 is a structural diagram of a TV
target indication system, used in underwater work with supervisory control [69].
Let us examine the oper~.tian of the system. The operator, by looking at an image =
of the robot's working zone on the TV screen, selects the object-target in which he
is interested a;~d guts an electronic mark on it. The position of the mark is con-
trolled with a two-st~.ge master lever, connected to two orthogonal potentiometers.
The line and frame voltages Ulin and Ufr, taken from the potentiometer, go to
coincidence circuits. The other inpu*s of these circuits receive the appropriate
line and frame scannin g voltages. As soon as thess systems are actuated the logic
system that generates a marker video pulse is started, and this pulse is sent to
the input of the video channel of the TV receiver, where it is mixed with the video
signal of the image. The position of the mark relative to the beginning of a frame _
- and line is determined uniquely by voltages Ufr and Ulin' selected by the operator.
The image brightness of the mark is controlled by the amplitude of the video pulse. -
= By changing the polarity of the video pulse it is possib le to make a bright or dark
image of the mark.
Voltages Ulin and Ufr are fed into an angular coordinate computer (an electronic
digital computer), wlnich computes angular coordinates at and ~t. These angles are
computed by formulas (2.80). As was already mentioned in �2.2, additional ydnge
~ finding systems or automatic optical focusing can be used for determining the third
- target coordinate range. "
The described target indication system can also be used in a stereoscopic TV
system. In this case the operator must indicate the object on the screen two
times for images, translated alternately by each TV camera. A general view of a
supervisory control console for controlling the manipulator of a mobile robot, and
" c~ntaining t~:e examined target indication system, is shown in Figure 2.24.
90
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reneeHaHOxMaa '
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.
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.
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1 ~ ~
:
'J~ CxeMi Cxawa Asyxcsenexxu
opasxexiu epaoxewu 9~~A~owu
. pyuoenca '
11~~ ' ~Ku
Figure 2.23. Structural diagram of TV target indication
system.
1. Logic system generates 6. Operator
mark video pulse 7. Comparator
2. Transmitting TV camera 8. Comparator
3. TV receiver 9. 'I~vo-stage master arm
4. Line scanning generator
S. Frame scanning generator [cTp=lin; Ka,q=fr]
Voice Command System (VCS). Work is done basically in two directions by automatic
speech recognition [25]. One of these directions phoneme recognition, is aimed
at the global solution of the problem of automatic speech recognition. The second
direction is the search for methods of automatic recognition af a limited set of
instructions. The solution of the first problem naturally will be the solution of
the second. However, automatic phoneme recognition encounters considerable diffi-
culties and necessitates the construction of extremely complicated systems. In
addition it is necessary in many cases to use systems that react to a comparatively
small set of commands. It would be uneconomical in this case to use methods based
on phoneme recogni2ion. A more intelligent approach is to find a simple and
inexpensive way of solving a given specific problem.
Many systems have already been developed that solve the problem of the recognition
_ of a limited vocabulary. However, it is important to point out that most works on
voice command recognition are more theoretical than applied in character. The use
of large computers, which model certain recognition algorithms, can hardly be
assumed acceptable in practice. Recognition algorithms of this kind are based on
spectral band, formant, correlation and certain other methods.
91
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A structural diagram of a voice command
system for controlling a robot, developed
, at OKB TK by V. A. Novikov, et al, [67], _
is shown in Figure 2.25.
A speech signal (command) goes into a
compressor system, which is used for com- "
pressing the dynamic range of the speech
signal by 30 dB. The compressed signal
_ goes into a filter unit, which consists of
11 identical narrow-band envelope shapers
(Figure 2.26). Each envelope shaper con-
tains a bandpass filter F, detector D, low-
~ pass filter LPF a_nd zero level hold ZLH.
.L, i I The bandpass filters are active filters
Ili ~ ~
~~s~~~+, if~~~ with a steepness of not Iess than 40 dB/dec.
~ The passband of the first filter on the 0.7
level is 100 Hz and increases by the llth
to 600 Hz. The signals fram the filters
go into adders for making the envelopes of
, the first half of the first formant, the
second half of the fir~t formant, etc. The
_ signals from the adders go to detectors,
Figure 2.24. General view of supervi- which are HF limiters with a 40 dB linearity
sory control console. range. The detected signals pass through
low-~ass filters with an 80 dB/dec falloff
steepness and a cutoff frequency (at the 0.7 level) of 10 Hz. To eliminate the
DC v~ltage from the LPF output due to the instability of previous elements and the
existence of noise at the tnicrophone output (motor, fan and other like noises), the
zero level holds are used. The tolerable noise in terms of voltage is 0.3 of the
maximum useful signal. The speech signal, aft~r undergoing preprocessing in the
compressor and filter unit, goes into the attributes unit (Fig~sre 2.27), where
characteristic features (attributes) of the received speech envelopes are identi- .
fied. Attributes are sorted out in accordance with the following criteria: a)
invariance to rat~; b) invariance to speaker; c) invariance to loudness; d) simpli-
city. _
The following attributes were selected as the result of an analvsis: 1) number of
segments of an envelope with larger than a given area, lying aUove a certain
tlireshold; 2) number of the segment with the largest area; 3) amplitude ratio of
the first three signals; 4) amplitude of the initial segment.
t-~ive channels must be used in VCS for the described attributes, and to the input of
each of them may be fed any envelope from the filter unit. _
The most informative envelopes in the frequency bands given below were se'_~cted on
the basis of the results of experimental investigations: 1) the envel~pe in the -
entire frequency range; 2) the envelope corresponding to the second half of the
first formant; 3) the first and second halves of the second formant; 4) the second
formant.
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1~ 6noK Z 6no~c 3~SnoK ~6naK Knao bnoK
Kon+npeccop~ ~Hnerpoe npw~NaKOO CN~NK~TOP7 NHAHKeUHH
Figure 2, 25. Structural diagram of voice command system. ~
Key: 1. Compressor un~t 4. Classifier unit .
2. Filter unit S. Indication uiiit
3. Attributes unit
mo ~ mH4 mHY ' .
-
~ mi 1 A mH4 mHY ' -
~
, ~ i
~ i
~ I i.
i mi 2 ,q ~DH4 mllY ~
i L.~_J ~ ~
~ t
i m~ 3 . A mH4 mHY ,
i ~ _ i
i . i
~ � . ~
i m^ 4 A mH4 mHY , -
I ~ ~ . . i
i i
_ l ~ t i
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: ~
~ ~
i
~ ~ - ~
~ 3 ~
~ 4 E A mH~I mHY ~
i i
~ ] ~ -
~ i .
- i ' E ,q' mH9 ~HY ~
, ~ .
~ ~ ~3 '
i 1 4 �i
i
_ i I ~opn+atrta .
~
r------ � � F_~.
i .
~ 1 ,
. ~ ,
i II ~opMaHta
L______"_'_________~'______~_~_~_~~~__ .
____~~.~~_~_~_~~~~..~~~~~~~~~~~~~~~s~_~~~~~~~~~~~.~
r------
i ' r--?
1l _
i III c~opMaHta ~
L_'_____"'___'______'_.'___~________.______
Figure 2.26. Structural diagram of filter unit.
Key: 1. Formant
[d~=F; ~,=D; ~Hy=LPF; ~HY=ZLH]
The se lected attributes of the speech signal go into a classifier (Figure 2. 28) ,
- whose functions include logic processing of information about the speech signal for
the purpose of identifying a speech signal with a command stored in tt~e robot's
merr~ory. The signals are classified in accordance with an attribute processing
algorithm, based on the processing of ,tatistical material. Hyperplanes, separat~
ing commands in the space of attributes, were plotted as the result of this pro-
cessing. The "delete" method, the essence of which is explained below, was
developed on the basis of the processing algorithm used in the VCS classifier. _
We will examine an m-dimensional space of a*tributes, characterizing N commands.
F.ach command is represented in the space of attributes by an m-dimensional
- 93
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� f -------~---------~'----~-~--~--~--------------------1
I ' ' f-0
fl 1
m j l " H--0
y ~i I
H-0
o
Figure 2.27. Structural diagram of attributes unit. ;
Key: 1. Selection of segments by 8. Selection of segments by area
area 9. Counter
2. Counter 10. Identification of maximum seg-
3. Measurement of word length ment
4. Analog-digital converter 11. Word envelope integrator
5. Syllabl~ generator 12. An alog-digital converter
6. Word generator 13. "Form" matrix
_ 7. Control system
94
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hyperparallelegiped, the sides of which are parallel to the coordinate axes. Edge
length is Zi~ = 2k6i~, where i is the number of command, j is the number of _
attribute, ~i~ is the mean square deviation of the values of an attribute, k is a
constant.
- - - - - = - - _
. ~
1) rPm~. -
cMwcnoerix _
cnoe
m 3~ Cpynna
- ~ ~ w+~P ~
n ia
c ~ -
c �
o S
y 4~ ~PYn~
0
e NcnonHNrene� 5 ~
~ Hwx Ko~+axtt
2~
7) CX2M8 ~
6) Cxen+a ~ y~p~neHHn
Y~P~enewu N~+stwcauNei+
Figure 2.28. Structural diagram of classifier.
Key: 1. Semantic vocabulary 5. Indicator
2. From attributes i.;nit 6. Control system
3. Group of numbers 7. Indicator control sys-
4. Execution command grotip tem
For recognition probability P= 0.95 and average number of attributes n= 4 we
have k~ 2(the hypothesis that the probabilities of the attributes have a normal
distribution is accepted).
In order to solve the problem of classification at the lowest equipment cost it is -
necessary to draw dividing hyperplanes that minimize the number of attributes _
necessary for the recognition of a given co;nmand with the fewest total attributes
utilized for recognizing all commands of the vocabulary. We introduce quality
functions F~, characterizing t}ie average number of commands "deleted" by the j-th
attribute. These functicns are
' _ N - ~ N -
F1= jy" Li F~l~ Ft! - N- 1~ pUk, ~2. $S)
k~l
?
_ where pi~k expresses the number of att-ributes, on the basis of which a given
command k is separated from investigated command i:
(~t, if the j-t1~ attribute separates command i from k;
P~1k-t o- otherwise.
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~~OR OFHiC'IAL USF, ONLY
{
'I'h~~ u~e oi functions f~. is based on the assumption that coefficients F. . are
J i~ '
s~if't ici_ently close for different con~mands. To find the minimum number of attri- ~
butes necessary for recognizing each i-th command it is necessary to solve the ;
l inear j~rogr.imming problem j
min CX, AX >B, ,
r 1.~ w I I�.~ U) �rl 1 N �~-I I Ul 1~1 I~"., N d-1 N
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~
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~
~
. '
- Table 10. Display Characteristics
. ~
I Models
! Technical Characteristics
i YeS-7064 YeS-7066 YeS-7061 Y~S-7063
- Screen diagonai, mm 430 430 250 250 ,
~
Working field, mm 250x250 320X180 150x200 150X200 I
Character height 3.5 3.5 2.5 3.6 2.4 3.6 2.4
- I (dimension), mm I i
1 ~
I Number of simultaneous ly 1,400, 960 240, 480, 960 960, 1,024 960, 1024
. ' reproduced characters :
Number of functional keys 32 16 18 22
Working (buffer) memory _
~ volume, bytes 4,096 4,096 1,024 1,024
jNumber of symbols per -
Iset 94 94 64, 96 64, 96
Maximum data trans-
mission rate, kbytes/sec 500 500 100 100 ,
Light stylus available Yes No No No
Printer availab le No Yes No No ,
- 150
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N FOR OFFICIAL USE ONLY
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152
FOR OFFICIAL USE ONLY
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~
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Table 13. Basic Raw Data Used in Computation of the Technical, Industrial,
and Financial Plan '
~
No . Data Group Name Subsystem in Which F'ornEed I
~
" ~ I~File of labor standards and summary labor NSI ;
' ~standards per article ~
i II IMaterial standards file NSI ,
~ ~ NS I
, III ~Equipment file
~ iV IFile of article composition and usability
i ~ ~og par ts and assembly units in articles NSI
~ V ~Resource limitations TE~'
! ' [technical-economic
' planning]
I VI iData from OPP [operational production ~PP -
I '~planning] subsystem.(calendar plan
I ~standards, number of parts required for -
( iincomplete production, etc.)
~ VII iPrice list for finished products NSI
I VIII IProduct release, unloading, and sales Product marketing and
- ~accounting data (finished products re- sales control
~ ~maining at warehouse, and unsold pro-
; 1 ducts) _
i !
I IX ~Service norm file NSI
X'File of labor standards for jobs in Auxiliary production
I ~auxiliary shops control
i XI ,Norms of material outlays per jobs and
~ ~services associated with repair and ~
~ ~ I
~ Ioperation I
. t
_ ~ XII Services of auxiliary and other shops, ,
i {in relation to outlay items
XIII ~Norms for expenditure of different forms NSI
1 ~of energy (electric energy, steam, air,
et~.,
XIV ICost of fixed capital and the norms of ~P -
_ ,its depreciation deductions
.
~ XV ~ Data from the technical development and TEP -
' I ~production effectiveness growth plan
XVI ( Personnel schedule ~EP
XVII Personnel file Personnel accounting
XVIII Volume of jobs performed by auxiliary Auxiliary production
workers control
154
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equipment intallation to introduction of the system (3-5 years); from introduction
- to the time of full compensation of capital investments in the t~SUP (2-6 years).
Unfortunately we often encounter cases in which enterprises install computers and
other hardware without preparing the approgriate software and informaticn support,
- with the hope that all of this could be done later on. Neglect of the preparatory
stage leads subsequently to operation of the computer below its capacity, which
results in large losses and raises doubts as to the feasibility of creating the
ASUP.
The following sample values of operational outlay items to be used in summary
computations are recommended in the procedure for determi.ning the economic
effectiveness of an ASUP: cost of data storage media (punchcards, paper tape,
paper, magnetic tape, etc.) and auxiliary materials--1-2 percent of the cost of
the hardware; outlays on current and preventive equipment repairs--2.5-5 percent
of the cost of the computer; outlays on maintaining the computer rooms--2-2.5
percent of the cost of the buildings; outlays on computer room lighting, heating,
security, and janitorial services--0.2-0.5 percent of the cost of the buildings;
other outlays--0.25-0.5 percent o� the cost of the computer.
COPYRIGHT: Izdatel'stvo Leningradskogo universiteta, 1980
_ 11004
CSO: 1863/144
,
- 155
- FOR OFFICIAL USE ONLY
a
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DATA TRANSMISSION AND PROCESSING METHODS
Moscow METODY PEREDACHI I OBRABOTKI INFORMATSII in Russian 1980
(s iGned to press 2 Sep 80) pp 2, 115
[Annotation and table of contents from book "Data Transmission and Processitig
Methods", edited by M. S. Pinsker and V. A. Garmash, Izdatel'stvo "Nauka",
2950 copies, 120 pages]
~ [Text] Annotation
This collection is devoted to statistical and probability methods of solving
problems in the theory of data transmission and processing, Estimates of the
- correcting capacity of concatenated codes are studied, the areas of acceptable
data rates for a channel with many users are found, and methods of statistical
information processing are investigated,
The book is intended for scientific and engineering/technical workers.
_ Tab1e of Contents
E, L. Blokh, V. V. Zyablov. Potential and realizable r.orrecting p�ronerties
- of aae class of generalized concatenated codes . . . . . . . . . . . . . . . . 3
G. Sh. Poltyrev. Throughput capacities for certain broadcas chann.els 22
M. S. Pinsker, G. Sh. Poltyrev. Throughput capacity of stationary
Gaussian broadcast channel . . . . . . . . . . . . . . . . . . . . . . . . . . 27
G. K. Golubev, Frequency estimation Uy multi-channel receiver 45
S. Yu, Yefroymovich, M. S. Pinsker. Toward the problem of asymptotically
sufficient statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Ye. K, Trish.chenko. P.sympotic behavior of risk of Bayesian estimate
for multidimensional Gaussian observations . . . . . . . . . . . . . . . . . . 73 -
156
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E. Kh, Mustafayev. Convergence of one continuous mo~iification of
Robbins-Monro in the multidi~nensional case . . . . . . . . . . . . . . . . . $0
A. G. D'yachkov, M. B. Ma lyutov. On weakly-dividing plans [of screening
exper iment s ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
- A. B. Tsybakov. Accuracy of estimation of minimum of average-risk type
functional by finite set . . . . . , . . , , , ~ , ~ , . ~ , , ~ ~ ~ , ~ ~ , 105
V. A. Mikhaylov. Adaptive random access in broadcast channel. 109
COPYRIGHT: Izdatel'stvo "Nauka', 1980
6900
CSO: 1863/143
157
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T,1DC 519.95
NEW BOOK CONSIDERS EARLY STAGES OF DESIGNING INDUSTRIAL CONTROL SYSTEMS
Moscow ASU TP. PREDPROYEKTNAYA RAZRABOTKA ALGORITMOV UPRAVLENIYA in
- Russian 1980 (signed to press 13 Dec 79) pp 2, 294-295 ~
[Annotation and table of contents of book "Automated Control Systems for
Industrial Processes. Predesign Development of Control Algorithms" by
Vladimir I1'ich Skurikhin, Vladimir Vasil'yevich Dubrovskiy, and Vladimir
Borisovich Shifrin, Ukrainian SSR Academy of Sciences, Izdatel'stvo
"Naukova dumka", 2,450 copies, 296 pages]
[Excerpts] Annotation -
This book considers the methodology of synthesizing control algorithms,
- testing them, and selecting the best ones in the predesign stage of set-
ting up automated control systems for industrial processes by using a -
- block-type mathematical model of the industrial ob~ect of control to simu-
late the work of the control system under regular and emergency conditions. _
The authors describe ways to simulate an industrial object of control with
- continuous production, control algorithms for deterministic and random
influences, modules to simulate the hardware of the automated control sys- _
tem, and techniques of optimizing design decisions using the simula~ion
model.
The book is intended for scientific workers and engineers who are develop-
ing control systems and f.or graduate students and advanced undergraduates.
The book has 52 illustrations, seven tables, and 100 bibliographi c entries. ,
Table of Contents Page
List of Basic Symbols and Abbreviations . . . . . . . . . . . . . . . . 3 -
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1. Methodology of Predesign Development of the
Automated Control System for T.^.~~as*_rial Processes 10 _
1.1. The Structure and Interdependence of Work in the ~
Predesign Stage . . . . . . . . . . . . . . . . . . . . . 10
1.2. Normative Algorithmic Models of the Industrial _
Object of Control as the Basis of Predesign Investigation . 18
158
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- Page
1.3. Evaluation of the Efficiency of Control Algorithms
by Means of a Normative Control Algorithm 33
1.4. Optimization of the Parameters and Structures of
~ the Automated Control System for Industrial Processes 41
Chapter 2. Normative Algorithmic Models o~ Industrial Objects
of Control . . . . . . . . . . . . . . . . . . . . . . . . 53
2.1. Development and Structure of the Model of the Controlled
System . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.2. Simulation of Industrial Systems with Multiple Flows 62
2.3. Moduli for Simulating Heat Physics Processes 77
2.4. Model~-ng External Influences and Change in the
States of the System . . . . . . , . . . � . � � � � � � � 87
Chapter 3. Modelling Dynamic Controlled Ob~ects . . . . . . . . . . . 110
3.1. Structure of Algorithms for Simulation Modeling 110
3.2. Description of the Controlled Dynamic Object by
Equations of State . . . . . . . . . . . . . . . . . . . . 118
' 3.3. Iteration A~gorithms for Calculating the State of
the Ob j ect of Control . . . . . . . . . . . . . . . . . . . 12$
Chapter 4. Normai:ive Algorithmic Models of Automated Control
Systems for Industrial Processes and Moduli of
Control Aigorithms . . . . . . . . . . . . � � � � . . . . 142
4.1. Moduli for Simulating Monitoring and Measuring Instruments. 142
4.2. Normative Algorithms of a Model of Actuating Devices 150
4.3. Algorithms of Primary Data Processing and Local Control 160
4.4. Algorithms of Optimal Control of Dynamic Objects 185
Chapter 5. Software for Predesign Development Work . . . . . . . . . . 204
- 5.1. Purpose and Structure of Support Subsystems 204
5.2. Moduli for Statistical Processing of Simulated Data 218
5.3. Methods and Algorithms f.or Optimizing the Parameters
of Control Systems Usin~ a Normative Alporithmic
Model of the Industrial Object of Control and the
Automated (:ontrol System for Industrial Processes 231
5.4. Selecting the Best Structures f~~r the Control System
Based on Modelling Results . . . . . . . . . . . . . . . . 242
_ Chapter 6. Investigating and Optimizing the Structure and Algorithms
of Industrial Automated Control Systems for Industrial
Processes . . . . . . . . . . . . . . . . . . . . . . . . 253
- 6.1. The Industrial Object of Control "Branching Gas
Distribution System" . . . . . . . . . . . . . . . . . . . 253
6.2. Library of Simulation Moduli of Gas Industry
Objects of Controi . . . . . . . . . . . . . . . . . . . . 257
6.3. Analysis of Algorithms for Control of Gas Transportation
in Multielement Systems . . . . . . . . . . . . . . . . . . 266
' 6.4. Simulating the Processes of the Industrial Objects
of Control "Cement Furnace" . . . . . . . . . . . . . . . . 270
159
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Page ~
6.5. Predesign Analysis of Variations of Algorithms for
= Controlling the Preparation of Cement Raw
Material Mixtures . . . . . . . . . . . . � . � � � � � � � 28d ~
i _
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
COPYRIGHT: Izdatel'stvo "Naukova dumka", 1980 ,
11,176 _
CS 0: 1863 /115
- END - -
160
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