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JPRS ID: 9675 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY

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APPROVED FOR RELEASE: 2047/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY , JPRS L/9675 21 April 1981 U55R Re ~rt p CYBERNETICS, C01v1PUTERS AND AIJTOMATION TECHNOLOGY (FOU~ 1 1 /81) - FBIS FOREIGN BROADCAST INFORMATION SERVICE - FOR OFFiC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2047/02/08: CIA-RDP82-00850R000300100038-6 NOTE ,7PRS publications contain information primarily from foreign newspapers, periodicals and books, but also from news agency transmissions and broadcasts. Materials from foreign-language ~ sources are translated; those from English-language sources are transcribed or reprinted, with the original phrasin~ and other characteristics retained. _ Headlines, editorial reports, and material enclosed in brackets - are supplied by JPRS. Processing indicators such as [Text] or [Excerpt~ in the first line of each item, or following the last line uf a brief, indicate how the original ir_formation was - processed. Where no processing indicator is given, the infor- mation was summarized or extracted. Unfamiliar names rendered phonetically or transliterated are _ enclosed in parentheses. Words or names preceded by a ques- tion mark and enclosed in parentheses were not clear in the original but have been supplied as appropriate in context. Other unattributed parenth etical notes with in the body of an item originate with the source. Times within items are as - given by source. The conCencs of this publication in no way represEnt the poli- cies, views or attitudes of c~~e U.S. Government. COPYRICHT LAWS AND REGULATIONS GOVERNING OWiVERSHIP OF MATERIALS REPRODUCED HEREIN REQUIRE THAT DISSEMINATION : OF THIS PUBLIC~,TION BE RESTRICTFD FOR OFFICIAL USE O~~TLY. APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY - JPRS L/9675 - ?1 April 1981 USSR REPORT CYBERNETICS, COMPUTERS AND AtJTOMATION TECHNOLOGY (FOUO 11/81.) - CONTENTS SM COMPUTERS Small Computers and The~r Applic~,tion 1 r - a- (III - USSR - 21.C S&T FOUO] APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 _ FOR OFFICIAL USE ONLY SM COMPUTERS St1ALL COMPUTERS AND THE?R APPLICATION Mos-cow DIALIYE EVbi I IKI-? PRIMENENIYE in Russian 1�80 (siqried to nress 14 Aug SQ) pp 2-49, f39-94, 147, 172-183, 190-195, 210, 212-213, 230 - 231 [Annotation, table of contents, introduction and e.xcerpts from book "S~nall Com- puters and Their PpP].ication," edited by A. N. Naumov, Izdatel'stvo'StatistiY.a", 34,000 copies, 232 pages] - [Text~ The SM-3 and SM-4 control computer complexes (UVK) developed within the family of small computers (SM EV1~1) are considered. The conf iguratinn characteris-- - � tics of WK, the input-output systems interface, the hardware of SM EVM f~r devel- apment of complexes and the software are described. Examples of confiquration of problem-oriented complexes are presented. The book is intended for specialists in the field of computer technology and auto- mated control systems. Contents Fage Intr~duction 3 Chapter 1. Sy~tems Engineering Characteristics and Configuration of SM- 3 and SM-4 IJVK 5 1.1. Systems Engineering Characteristics of SM-3 and SM-4 5 1.2. General Data on Configuration of SM-3 and SM-4 UVK 11 1.3. Addressinq Modes 19 1.4. Instruction Set 24 , 1.5. Characteristics of Organizing Work With Memory in the SM-4 U~'K 45 Chapter 2. The "Common Bus" Input-Output Systems Interface 50 2.1. Characteristics of Operation an~ Orc~anization of the Interface 50 . ?..2. Control of Feripherals of the Complex 54 2.3. The "Common r:xs" Main Lines 57 2.4. The Functional-Time Characteristics of the Interface 65 2.5. ~lrbitration of Priorities. Procedures for Routine Interrupt 69 ~ 2.6. Operatina Algorithms of the Interfaces of the Devices 73 2.7. Physical Realization of Interfaces 7~ _ Chapter 3, Hardware of the SM EVM for Creation of Developed Complexes 95 1 , FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY , 3.1. The Znterface Expander ~6 - 3.2. The Interface Segmenter 103 3.3. A Programmable Timer 105 3.4. Computer Integration Device 107 3.5. Common Bus Switch ].13 ~ 3.6. Interprocessor and Rer.x~te Communications Adapters 119 3.7. Arithmetic Expander 135 Chapter 4. Software of the SM EVPi 142 4.1. Cnmposition of Software 142 4.2. Structure and Main Characteristics of Operating Systems 143 4.3. Designation and Field of Application of Onerating Systems 148 4,4. Applied Proaram Packs 159 Chapter 5. Design of Control Computer Complexes 1~2 5.1. Classification of Complexes ' 1~2 ~ 5.2. Principles af Configuration of User Complexes of SM EVM 183 5.3. Devices for Communicating With Object 199 5.4. Operating Conditions of the Complex 212 . Chapter 6. Problem-Oriented Complexes Based on the SM EVM 215 = 6.1. Measuring Computer Complexes 215 6.2. Automated Operators Positions 224 230 Bibliography - Introduction Development and serial output of a new family of productive and economical small computers (SD1 EVP~1) open wide opportunities for introduction of autcMatic informa- tion processing and control systems in new and traditional f ields of application of computer eguipment. S~lution of prablems of qualitative improvement of the structure of computer complexes, development of the component and design-production ~ base ensured large-series production of SM EVM. Oriented toward a wide range of appli.cations (complex automation of production processes, automation of monitoring and measurements, automation of scientific research, automation of teaching, mes - sage switching, automation of scientific and engineering calcul.ations and process- - ing econamic and statistical information), SM EVM become accessible to a large number of users. F1t t}ie present tir~e the SM EVM includes 'SM-1P, SM-2P, SM-3P and SM-4P basic proc- ~ essors with productivity from 200,000 (SM-1 and SM-3) to 400,000 (SM-2) and 500,000 operatiAns per second (SP4-a). SM-1P and SM-2P processors continue the line of domestic r4-6000 and P-'.-7000 computers . Therefore, the S:d-1 and Sbi-2 computers are oriented primarily toward application in those systems where there is alrpady - sufficient completion of the software for the M-6000 and M-7000 computers. The SP4-3 and SM-4 computers, continuing the line of domestic ri-400 computers, in- d clude a large number of essentially new structural solutions directed toward simplification of programming, desian of various com}~uter, control, information and measuring com~~lexes and arranged in an optimum manner to work under specific conditions. 2 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY - The main features of the St4-3 and SM-4 are a wide range of productivity under spe- _ cific conditions of application, major structure of the interface with apparatus realization ~~f most input-output information systems functions, simple realization of multiprocessor and multimachine systems, high speed of processing interrupt and capability with formats of different length. The nomenclature of devices (input-output, communicating with objects, external magnetic carrier memory and s4 on), traditionai for small control computPr complex- es, is supplemented by devices for expansion of the intermachine and interprocessor communications complexes. Because of this, realization of computer systems with ` common and separate field of peripherals and complexes with variable structure is - provided. The software of the SM-3 and SM-4 is constructed on the basis of multi- user real-time systems, time sharing, remote processing, dialogue systems and so _ on, with a large number o� procedure-oriented routines. The book offered to the reader is the first in a series of books devoted to SM EVM. The main characteristics of SM EVP1 (SM-3 and SM-4) are considered in it. The book provides specialists in the field of computer technology and automated control sys- tems the main reference data which permit one to select the appropriate computer and to evaluate the capabilities of the hardware and software of the SM-3 and SM-4 - and also examples of configuration of SM-3 and SM-4 complexes. The following books will be devoted to detailed consideration of programming prob- ` . lems on the SM-3 and SM-4 computers, description of hardware and analysis of the principles of configuration of complexes of different designation, problems of joint operation of SM EVM with ~ther families of computers and design of automated control and information proce~sing systems based on the SM-3 and SM-4 WK. The wishes and comments of the Institute of Cybernetics of the Ukrainian SSR Academy of Sciences, the Central Economic and Mathematics Institute of the USSR Academy of Sciences and a number ~f plant organizations were taken into ~ccount _ during preparation of the book. The comments of the book raviewer, 3octor of t echnical s ciences, Professor A. G. . Shigin were especially useful. ; 3 FOR O~FICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOF. OFFICIAL USE ONLY _ Chapter 1. - SYSTEPIS ENGIi1EERING CHA.RACTERTSTICS AND CO'.VFI ~URATIOPd OF SM-3 AtID SM-4 COPI`I'ROL COMPUTER COMPLEXFS 1.1. Systems Engineering Characteristics of SM-3 and S}~i-4 [Text] ~ystems engineerina characteristics are determined bv parameters of both individual devices and modules of the SM-3 and SM-4 and by generalized indicator~ of productivity, ef�iciency and structural characteristics of the St9-3 and SM-4 complexes. These characteristics permit one to refine the field of effective ap- plication of the 5~4-3 and ~P'.-4 and to nrovide a general idea of the capabilities of designing systems based on the St1-3 and SR!-4. The nomenclature of the SM-3 and SM-4 hardware is constructed on the basis ~f 16-digit processors (SM-3P and SM-4P) ~ and includes internal storage modules and a set of external devices aiid interproces- sor and intermachine communications devices. The systems characteristics (speed of information inout-output, processing speed, _ functional capabilities, set of external devices, operatinq efficiencY of multiproc- essor complexes and so on) of the SP4-3 are 2 to 10 times qreater than the corre- soonding charactpristics of microprocessor computers (for example, the Elektronika- 60). The use of new structural and design-engineering solutions in the SM-4 com- puter made it possible to increase approximately fourfold the productivity of this processor compared to the SP~-3 and to bring it up to a level close to the product~v- itv of inedium-sized computers (for example, the YeS-1~93). The instruction set of the ~ri-3 computer is the instruction subsPt of the ~M-4 computer anR therefore all thc routines written for the SM-3 can be processed on the SM-4 without any change. tlost operating systems are common to the SM-3 an~i ST4-4. . One of the most imn~rtant problems of wide application of modern computers is re- - duction of expenditures for programming and primarily for the more laborious s.ystems _ programminq, which rec{uires hic7hly qualified programmers. The new structural solu- tions used in the S"-3 ~nd SP4-4 provide apparatus realizati.on of a large number of systems functions in the followi.ng typical modes: - real time (system of. priorities of requests for interruPt, processing of in- terrupts, register and cartridge (stack) memory, information storaqe system and - problem restart syster~o:ith Y,rief cutoff of power and hard~�~are-software monitoring); time-sharing (Means of security and dynamic redistribution of inemory, hard- ~vare-software for dynamic change of pri~rities); solution of inf.ormation retrieval problems, construction and m~nagement of data bases: different format information processing (byte, bit, word and double ~ _ ~ FOR OFF[CIAL USE ONLY , APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY word) with floating and fixed decimal, processing and transmis~ion of information files, an effective instruction set which provides simple realization of different data structures (lists, tables and files). Apparatus execution of complex systems functions in a process~r occurs on the aver- - ~~ge an order faster than e:cecution of routine modules with similar systems charac- teristirs. This in turn significantly expands the boundaries of. application of the sr~-3 and Sr1-4. Stzucturally, these coMplexes can be made in the form of a set of several modules (processor, memory, object communica tions device--USO) built into the control ob- ~ iect. Single-column versions of configuration may also include Magnetic disc _ stores, punch tape input-o~~tput modules or internal storaqe expansion blocks. Two-column and multicolumn versions oF confiauration, dependinq on designation, may include USn expansion modules (from several hundreds to several thousand input and output signals, with given metrological and dynamic characteristics), maqnetic car- rier nc~nvolatile meroory expansion modules, modules for design of two-processor - systems (hierarchic~l, distributed, with variable structure, 4~ith se.parate and com- r.ion field and so on). The capabilities of using the SM-3 and SM-4 are expanded due to the devices for communicating with other com.puter families. The capabilitv o� connecting r,?icropr.ocessor computers to the SM-3 and SP4-4 provides design of distrib- uted information, contro~. and measuring systems in which the St~-3 and STi-4 perform the �unctions of a central comouter. During joint operation with the YeS EVM [Qnified computer system], the SM-3 and SM-4 WK are used as a remote intellectizal terminal; an input-output processor which provides communications with the ohject in real time with high dynamic characteristics; a message concentrator in network struetures; a peripheral orocessor. ?1n important desic~n feature of the SP9-3 and S"4-4 is execution of individual modules in the form of self-container~ structural blocks wi~h their own power supply sources and so on. They are connected to the complex bv the standard method usinq cables. 'r'his permits the user to configure SM-3 and SA?-4 complexes ~vith regard to specif;.c conditions and to carry out simple pre-assmebly of systems during operation to provide new �uncti~nal capahilities. The ~.xternal devic~~~ of the SM F.VM can be connect~d both to th~ SM-3 and SM-4 hy the sa^~e integrat~cessor and inter~;achine convnunications devices) . The - software corresponcls to the basic complex an~ is sup~lemented by drivers of con- nected devices; problem-oriented complexes. They are ~3evelop?d f~r a specific set of applica- - tions combineci by t~ie un.ity of information processing technoloqy. mhese complexes . are constructed on tlie i~asis of specified complexes and may include additional non- standard modules, devices from the nomenclature of other families of coMputers, - ;;~odules of operatinq systems and applied probler.t packs which provide infor.mati~n processing in specific given modes for a specific set of objects.* * . The principles of configurat�ion of SP~-3 and Sr2-4 complexes are considered in more ' detail in Chapter 5. , 9 ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL US~, ONLY The systems eng~neerinq characteristics ~f complexes are deterMined to a signifi- cant deqree by computer configuration. � 1.2. General Data on the Confiquration of the 5M-3 and Gr1-4 WK Computer confiquration is understood as everything that the machine offers to the - program working at the level of machine i.nstructions: the. structure of the memory, _ addressing mechanisms, functional diagram of the .processor, instruction f.ormats, _ means of controlling periptieral devices, interrupt system and so on [3]. The - efficiency of executing different tasks depends on thP specific configuration prop- _ erties of computers. The configuration of the SM-3 and SM-4 UVK considered in this chapter pr~vides the highest efficiency when solving problems of processing large information filPs structurally organized in the form of stacks, tables and queues, information gather- - ing and processing and control in thF real-time mode with high response of the sys- ~ te:n to interrupts from external devices , byte processing and information transmis- sion. These .problems are tynical for many areas of application of camputer equip- ment and primarily for svstems where automation of scienti�ic experiments and production processes and for automated production control systems and information- measuring systems. The SM-3 and SP~1-4 L'VK have Linified confiquration* and are coripatible "from bottom to top." This compatibility means that an arbitrary routine in machine code exe- cuted on the SM-3 can also be executed on the SM-4 since all the configuration characteristics of the SI1-3 are re~~ained in the SF1-4 WK, which has more complete = productivity achieved by use of additional configurational capabilities of the central pracessor of the sr1-4 (compared to the SM-3) and also higher spee~i in the main instruction set (similar to the SM-3) . Henceforth, when describing the con- fiyurational properties of the St~?-3 WK, it will mean that these properties are also related to the Sr9-4 UVK. The additional capabilities of the SM-4 complex will be especially stipulated. ilie configuration of the SPt-3 and sr~-4 WK differs significantly from that of mast ~ s,:iall. computers . One of the typical features o~ any comp~iter is the method of ad- - d ressinq the internal storage device (OZU) . There is the problem of addressinq a large volume of C~ZU for small computers, which usually have a 16-digit instruc- tion forrtat. This ~roblem is solved in many small computers k~y means of indirect addressing throuqh the "zero" merm~ry page [1] . The capak~ility of direct access to addresses of the "zero" paqe is Provided in the instruction format since its ca- ~acity is usually small (256-2,~48 words). The disadvantages of this method are obvious: two access cyr.les to ttie OZU are essentially required for each access to the operand; moreover, even with a sma11 volume of the zero page in 16-~3igit in- struction format, douhle-address instructions reR~iired to perform two-place opera- tions of the addition, comparison and other types cannot be realized.. Of course, th~se instructions are realized in computers which utilize the "zero" page prin- ciple. However, an internal register-storage device in ~~~hich the result of the * This family may also include tne Elek.tr~nika-60 computer and the previoizsly pro- duced h1-400 complex. - 10 FOR OFFICIAL U~E ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300104438-6 ~ FOR OFFICIAL USE ONLY operation is stored i~: u~~~ as the second operand in this case. An additional in- _ - struction is used to refer to ~he contents of this reqister in the OZU. Another method of addressi.n~ is used in the SM-3 UVK: addressing throiagh one of the general purpose reqisters (RON) of the nrocessor. Ttie number of this reqister ~ - is indicated in the instruction format and essentially no time is expended on ac- cess to it when executing the instruction. The contents of the reqister are inter- preted as a function of the addressinq mode which is also given in the instruction ~ format. There are eight of these registers and three digits are required for ad- dressinq any of them. This pravides the capability of realizing single- and double- address instructions with 16-digit instruction format, which considerably facili- tates proqramming at the machine instruction level. = Another characteri_stic feature of the sr1-3 L*vh is the use of a unified ''Common bus" ~nterface in which info miation exchan ge (addresses, data and control signals) be- tween the processor and memory is accomplished by the same principle as between the processor and external device (VU). Beca~ase of using this interface, special input-output instructions of_ the processor. ' are no longer necessary; direct access to the OZU is simply realized, i.e., infor- mation exchange occurs without the parti~ipation of the processor between the VU and ~nemory Llock or hetween two W; the operating flexibility of the ~~rocessor with the VU is enhanced sinc~ all the address instrur_tions can be used to transmit and process information in the W registers. A total of 4,096 old words of the ad- _ - dressed memory is allocated for addressing the VU registers, addressed the same as OZU cells. Thus, the configuration of the WK (if the physical restrictions of _ the load capability of the "Common bus" lines are not taken into account) permits connection of a practically unlimited number of W to the processor. - General~Purpose Registers of the Processor _ The processor has eiqht 16-digit universal qeneral-purpose registers (RON): RO-R7. These registPrs can be used both as storage devices, index registers, address dis- . plays, table displays, list displavs and so on and also as memory range displays for temporar~ storage of d~ta (stack). The specific use o� the registers depends on the selected ad~ressinc mo~3e. I~mong these r~gistPrs should especially be allocated R7 and R6 reqisters. The R7 register is used as ar~ instruction counter, i.e., it contains the address of the next instruction to }~e ~xecuted, which permits sever~l additional addressing modes to be achievec3. Z'he processor utilizes thc~ R6 register as a stack display during execution of some instructions wliich requir~ temporary storage of data (for examnle, the return a~l- 1 6 5 D , ' �PE,7M FE~ PE31C PE~ ~ ~ _ _ _ - ti __i\ ` _ _ ~ ..(11 h'o;~ anepauuu (S) NCTO'IHUK I~PJBMHU/i bl Figure 1.4. Formats of Sir~gle- (a) and Two-Address Instructions (b) Key: 1. Operating code 4. Receiver 2. Mode 5. Source 3. Reqister To use the contents of the register as an address (or the address of ~n address in indirect modes) of the operand, this address (or the ad~ress of the address) must 17 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 ~OF OFFIC[AL USE ONLY first be entered in the given reyister. Since additiun~l time is required for this, the indicated method is used only when proccssinq information files when the set r~gister can once serve nultioly to address sequential memory cells. In this - case the work is carried out with automatic increase or decrease of the r.egister co~itents by one or two after execution of each instruction with access to a qiven regis*er. ~1'Yius, the address o� the next byte (with an automatic increase or de- crease by one) or of a word (with automatic increase or decrease by two) is pre- pared in the register. It should be noted that an automatic~increase (or decrease) is always by two when using indirect modes 3 and 5 since the r.egister contairs the _ address which is always a 16-digit (two byte) word rather than the operand in this _ case. Table 1.1. Main Addressing Modes _----r-- - ~ Indirect Modes ~ Direct Modes (Address of the ! ~ - (Operand Address Operand Address ~ , Is Formed) Is Formed) j Description of Mode ~ umber of P4nemonic Number of Mnemonic~ r^.ode Code - t�Iode Code ~ - - _ ' 0 ~`RI.1 ~ 1 @ R n ~ The contents of the register are the oper- ; and in mode 0 and the address of thF oper- I and in mode 1 2 (Rn)+ 3 @(Rn)+ ; The contents of the rPgister are used as I , the address (or the address of the address) I of the operana and is then incre~~sed by ~ ~ ~ one or taro (in mode 2) and is always in- I I i creased by two in mode 3 _ 4 -(Rn) ~ 5 @-(Rn) ~ The content~; of the register are reduced _ I ~ by one or two (in mode 4) and are always ; i reduced h~~ two in mode 3; it is then used { I as the address (or the address of the ad- ~ ~iress) of the operand 6 X(Rn) i 7 ' C~X(Rp) The contents c~f the register are added to J ~ those of cell Y, f.ollowinq the instruction; I I the sum is used as the address (or the ad-l i ~ I I dress of the address) of the operand _ ote. n is the number of the selected register. Examples of using addressinq modes in the instructions of the SM-3 and GM-4 EVK are presented in Table 1.2. Register R7 (the instruction counter), which we will subsequently denote by SK, is used as the RON for working with individual cells of the OZU. This counter always - contains the address of the cell following the executed instruction. Thus, if the _ SK is used as an RON in the addressing field, preliminary setting of the register (SK in the giver~ case) is not required. Although the SK can be used in any of the main addressing modes, work with the SK is practically feasible in only four of these modes. From the programmer's viewpoint, four additional addressing modes 18 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFF'I~IAL USE ONLY . ~ (direct, absolute, relative and indirect-relative) are possible, although these ~ modes in no H~~y diff.~~r with respect to apparatus from the corresponding modes with use of. other registers. Address~.n~ modes using the SK as a general-purpose regis- 1 ter are presented in Table 1.3. a ~ _ ^r N O ~F Os ~Q' p ' O O Oc'~7 O 00 v M ~~a . M ~A O ~ N O ~ O O O O p g 0 $ p p O O v II tl U u p p II . Y 1 u u ~ o ~ o ~-Ci ~ R O O N O CVp ~D O cQG~ O ~D O~ O O O O e c O O~ O~ O~~ p0~ ~00 Ov 0~QMf'~7~ ri ("1 rl OO M ~ = e m O O... 0.... - ~ ~v O"' O O Vv OM vc'~7 ~ V ~.....v ri r-1 r1 C r-I M ~ u O o O O p vp M O O ~ r--1 r-1 r-I lfl rl N ~ O O O O O O S ~ ~ ~ N U1 ~ N a ~ ~ d m a ~ n ~ e r u ~ u u ~ u ~ o v a ~ a z � a z ac a r~x~ ca a . w ~ ~ w a~i ~ a ~ O 0 0 U 0 U = N N N W N W � ~ ~ ~ ~ G ~ � ~ ~ ~ R~ R'. s ~ ~ �o o o otn $ co �o~o ~ ~ ~ G q G = e o c�~ o r'~ o �o c o c~ o c~ op C 0 O S~ ~ 0~ U) a o O ~ oo ~ o O ~00 U U U~ 1~ U 47 ~.1 U a � � o0 0 �oo 0 o goo N N .1~ u~i O+~ t~n O = p II 9 Y U d g U G II p il N ~ v�~ ~ , ~ u o �o ~ o a cc o ic o ca o v~ ro N b N~ b~ ~o 0 0�0 �oo o�oo o�oo o�o�o oM~c�o pe~7MN N O~ O~ N oi N o�~ o-- o o r~~n o ' a o - o "u> r~ ~ ~"o " r~ U U td rd b td m � o � o �o �o �o �o �o o ~ 9+ N~~ O 3a l~ O N .�r u II tl A ' N N II p H A Ca ~i E+ W E-~ W _ ~ a a a a a a z z a o4 . . . . Ol O rl N f+1 d' N O ~ ~ ~ ~ ~ - ~ S ~ S S S ~ c7 O ~ ~ G. CL G C1 S O y~ � c'~ r" C1 el a) E1 Y ~fJ X N ~ ~ ~i a ~ a bc .s N v u . u u s ~ v~ x O 1-i ~ � C T a ^ 7 ~ �e. V' a ~ ~ v v~ v o cV a ~O ~ x 'U ~ s ~ y y x x ~ ~ d ~ a ~ S~ tT~ r.i; ~ s s � s s x ~ R1 ~1.~ N - ~ ~ a aai v aai �J . o. ~ a~�'i ~ N 4-t O . �i c, O ��~1 4-+ ~ z z ~ m o v o N O u ~r ~i u - ~3 ) c~ o 0 o a p a o ~ - D a o o a- ~ u tn p o N - s~ =o +o rM ma r mH ~ b~ +i 4a ~ ~ ~ z S Y ~ Y a,x ~ z u a~i ~ u N N Z1 f-1 U ~ ~ d~asi ' a+ ~v a~ ~ a a v a ~ ~''d 0 U1 ~ 1.~ G O U C.' W r-I ~C O ~ ' ' T n. 7~ Q A a J~ o~e C m O C m O U O O.-I ~ 0 U U M M MN p.-+Np d~ CV W ~�~-1 N �rl dl N ~ v NifMd COV N N O ~ e~ O5~ ~ ~ V ~i ~1 fA C) X~ ~ _ ~ �~uo YoN S S 8 8 ~ 8 0 25 8 ~ ~ ~ .u 'a N ~ ~ ~ a~i ~ ~ 'd' A E N U+~ O O~i N s.+ A -4- a _ ~ ca .r " w ai o a~i ~ w~ M ~ v; M a~ a a a a ~~oQ~~a�~~He~ _ x ~ ~ a C~9 U ~ ~ > . (d~ > ~ ri c.i M ~r ~ri ~o ~ o0 U U ~ z- z Z Q ~ ~ ~ U ~r H r-ITu/n p~ ~ ev eo ~ ~n ~o -t~ ao ~ 19 FOR OFFICIAL U5E ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY Lat us consider tre features of absol~ite and relative addressing. Relative ad- dressing is used mainly wh~n writing so-called position-independent routines (which are not dependent on position in the OZU). If the routir,e is designed for transfer _ in the memory, abs~lute addressing cannot be used in most cases since the ciirect address of the operand, whi~h changes its value upon transfer of the routine, is contained in the second word of the instruction. The difference between the cur- rent position of the instruction (i.e., the contents of the SK) and the actual ad- dress of the operand is stored in the second word with relative addressing. If the entire routine is transferred to another position of the OZL~, this di.f.ference is stored and consequently the operation will be e:cecuted correctly. However, there are special cells which have f ixed addresses not dependent on the position of the routine (for example, addresses of interrupt vectors and regi.sters of devices) . Absolute addressing must be used upon access to these cells, atherwise access to these cells will be incorrectly executed when the routine is transferred. Table 1. 3. Addressinq Dtodes iJs~ ng SK as General-Purpose Register Number of Mnemonic Addressing P4ode Addressinq Code Description Direct 2 ~r1 Contents of N cell follo~vinq the first word of instruction is the onerand Absolute 3 ~#A Contents of A cell following the first word of instruction is address of operand Relative 6 A C:ontents of cell following the first word instruction is added to contents of SK; the sum A is address of the operand Indirect- 7 A Contents of cell following the first word relative of instruction is added to contents of SK; sum A is address of address of operand Examples of using a~'dressing modes with the instruction counter as the general-pur- pose reqister are presented in Table 1.4. When executing the instruction presented in example 1(the direct addressing moc3e) , the followinq occurs. ~fter the instruction is sampled, the SK in the .processor is always automatically increased by two. Then, since mode 2 is being use~i, the con- , tents of the SK are interpreted as the address (2002 in the given case) of the oper.- and, i.e., the operand is the second ~vord of the instruction. Thus, this mode per- mits one to be given constants in the routine by storage of this constant in the second word of the instruction and by usinq the register mode ~aith automatic in- crease of reqister SK. An automatic increase is necessary since otherwise the constant is interpreted as the next instruction. The operations are executed similar to the previous mode in the absolute addressing mode (exaMple 2). Ho~vever, th e contents of the SY. are interpreted as the address of the operand address, i.e. , the address of the onerand is the second word of the - instruction. The processor again turns to the memory for the index word by the address contained in the SK in the re].ative addressing mode (example 3) after selecting thP instruc- tion and increasing the contents of SK by tcao, after which it again increases the 20 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300104438-6 FOR OFFICIAI. USE ONLY . a o o o ti~ ~ c�o �o o � tD ~ o o - o ~�n �o q O O O tG O ~ O O ~ O O O ~ O O O O ~ a o 0 0�n i u n q U II CV O O N ~ ~ ~ ~ ~ O O ~ O O O O u ~ ~O c'v O O v v v N ~ v v y s R ~ ~ ~ - �t ~ y' y~ 'd' O O G p O O 0 O iJ, ~ GV N O O ~ T --g o d ' u ~ . �e 0 a ~ .y~j c ~ U U U U V o ~ ~ " - ~ = ~ Y N ~ n ~ p P eh ~ H � ~ � cc+v ~ � ~ O O o o ~ o ~ M d M ~ Q ~ N O O 3 ~ O ~ ~ ~ O O O O O O O 'y ~ ~ ~ 0 O O O O ~ o o~ ~II o o � II tl p II U p ~ ~ Y ~ N O N ~ O N O O N u llls O O f~ N G~V N N v N CV M v ~ ~ v~ ~.N RS . v ~ c O 0 Q N N ~ _ ~ N N O O ~ p ~ p O ~ O ~ ~ ~ . . ~ M N a V. U U , U N 'd m . u O M ~ p o ~ �o 0o r-I ~ b, ch r�~ ,=x, 'n ~ ~-i ~ ~ 5 sTC a~i s U G ~ U U7 s ~s d � O a ~ � �/v x ~ O a � S-1 S~ ~ v~ ~ a ~ A rn~ o, ~ F ~ o o~ ~ o ~ oo ~ ~ x~ x a~ m ~n E t~ ~ ~ Q, m z w n. r ~LJ N~ N C~J ~ C c,~ O ~ ~i ~ b�~~-I ~L ~ A id a tn W G~ U W ~ pp MO t~Df~ NC ~ O�~ O QI p h M O M N O ~ 0 .N j.~" ~41 O .l-~i � ~yY NO o0 0�0 ' oo tn 0 O M ~ d~ � � � � ~ ~ ~ ~ ~ d ~ ~-1 N ~ ~ 0 N O ~ O ,-I � Ul U 3-~ ~ ~ ~ U 0 O O v U~~-I A r-1 ,q S . ~ o $ �rl �ri N r- i r- 1 r~ � r~ U+~ ~ tn 0 k~ N N N - C-~~ ^ o ~ � ~ �rl U R~ N~r1 U UI U ri s - � Z ~ � . v ~ C: ~ . . . ~ ~ ~ .Vl ~ ~ ~~dt rd ~ rtf ."'e, U V ~ H A U W~ E-~ W H W ~ ni ri ~r ~n ~o r ao ai o ~ a~ ~ 21 ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2047102108: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY contents of SK by two. Since the addressinq mode is index type, the processor adds the index word to the contents of the selected register, which the SK regis- ter is in the relative mode. The sum (74 + 204 = 300 in the given example) is the - address of the operand. The indirect-relative addressinq mode (example 4) is similar to the previous one, only the sum of the index word and the contents of the SK are interpreted as the address of the operand address. 1.4. The Instruction Set All the instructions contained in the instruction set of the SM-3 and SM-4 UVK are separated into grouos (single-address, two-address, transfer instructions and so on) and into subgroups. This separation is purely arbitrary in some cases and is -nade for purposes of convenience of outline. Formal description of the instructions is given in Tables 1.5-1.10. The name, mnemonic notation (used in writing routines in Assembler language), the form~l al- gorithm and the verhal description are presented in these descriptions. The follow- ing notations are used in formal description of the instructions: (XXX) --contents of YXX --"becomes" ist --source address T --selection from stack prm --receiver address y --recordinq to stack ~ & --"AND" function (logic Z --digit of zero character in multiplication) word of state ! --"OR" function (logic N --digit of minus character in addition) 4~ord of state O! --"EXCLUDING OR" function C --digit of transfer character (addition modulo 2) in wrrd of statc - --featur e from top--"NOT" V --digit of overflow character functi on (inversion) in w~rd of state This formal descr iption is quite adequate to understand the word of some instruc- tions. Ho~~ever, let us consider more instructions in more detail. Special atten- tion should be turned toward methods of setting the conditional codes. In the general case conditional codes are set according to the definitions qiven i~ 1.1. - However, when executing some instructions, the conditional codes are set in a special manner. In these cases the method of setting the conditional codes is stipulated especial].y in ttie description of the instruction. Single-Address In structions Formal descriptio n of sinqle-address instructions is presented in Table 1.5. Their forMat is shown in Figure 1.4, a. Six ciigits of the instrucLi~n code are allocated for the address f ield, which contains the number of the addressing mode and the number of one of the RON which determines the address of the operand according to the rules considered in 1.3. '?'he remaining 10 digits in the instruction format are - allocated for the operating code. Special attention should be turned tow~rd the rules for setting the transfer and overflow digits in the arithmetic instructions (understanding of this problem is also important when using two-addre ss instructions and transfer instructions). 22 FOR OFF'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAI. USE ONLY - - Let us consider methods of displaying numerical information in the Std-3 UVK. Numbers can be displayed in two forms in the SM- 3: with and wi thout a sign. Num- bers with a sign are displayed in a supplementary code and have ranges of -2~-2~-1 (when operating cvith bytes) and -215_215_1 (in operations with words). If the re- sult of the operation goes beyond this range when executing arithmetic instructions, the overflow digit V is set in the SSP. Display of numbers wi thout a sign has ranges of 0-2a-1 (in operations with bytes) and 0-216-1 (in operations with words). If the result of the operations goes beyond this range dura.ng execution of arithme- _ tic instructions, the transfer digit C is set in the SSP. Thus, ~ahen executing arithmetic instructions, the transfer digit is actually the ov erflow index for - representation of numbers without a sign. Single-address instructions can execute operations both with bytes and with words. An exception are SWAB and SXT instruc- tions (the SXT instruction is realized only in the SM-4 UVK), for which operations with bytes are meaningless. ThF feature of byte operation is a one in digit 15 of the instruction code. The letter B is added in the mnemonic notation of the in- struction in this case. Arithmetic instructions. There are three single-address arithmetic instructions INCREMENT (INC), DECREMEt~T (DEC) and CLEAR (CLR) in the instruction set of the SM-3 WK. - The operand always contains a zero after execution of the CLP. instruction. There- fore, digit Z is set to one and digit N is dropped to zero. Digits V and C are _ also dropped to zero. ~ The INC instruction adds one to the contents of the operand. Let us consider the case when the operar.d contains the number 077777 (or 177 for onerations with bytes), ..~rhich is the mahimum positive integer in character representation of numbers, prior to execution of this instruction. As a result of adding one to this number, ti:~ number 10000~ is found, which is negative (i.e., overflow occurs). Therefore, ' digit V is set to one in this case. _ The DEC instructio:~ subtracts a one from the contents of the op erand. The condi- tion of res e t when usinq this instruction occurs if the number 100000 (or 200 for byte operations) is cont.ained in the operand, which is the maximum negative number. _ It is natural that subtraction of a one from this number leads to the siqn repr~- sentation of the numbers leaving the range and digit V is set to one. . The INC and DEC instructions do not change the status of digit C even if a~rry oc- curs (i.e., arithmetic overflow with display of numbers without a sign). This is determined by the fact that the lowest (or highest ciigit of the sh ifted word (byte) ~ which should be used in the next shift cycle is recorded to digit C in the instruc- tions of the cyclic shift. Thus, instructions (for organization of program cycles) - which do not change the state of digit C are required when organizing a multinle cyclic stiift. Logic instructions. Only the corresponding setting of digits Z and N occurs as a result of executing the TEST (TST) instruction. Digits V and C are dropped to zero. the contents of the operand do not change in this case. This instruction is usual- - _ ly employed to determine thp carry conditions at points of program branching. - 23 FOR OFFICIAL USE aNLY - APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02108: CIA-RDP82-00850R000300100038-6 - FOR OFFICIAL USE ONLY ! I N ' ~~I l~ I 1 W ~ I q ' ~ ~ C~ I rti D q 0 1�~ ~ { ~ ~ 0 E b ~ rt S I U J ' S~ D�rl ' w v'd �ri t~ ~ s~ a~ ~ U S-i 0 ~-1 N~ l~ I N N N U N N N ~l ?a N ~ N N~ 0 U1 N S-~ N ~d i~ U q i D U N I~ ~ O S-~ 'J 9.~. r~l ~ - N~ 4-+ N C~ I 0 ~ O N.~ 0 ~ p�-1 w+~ ~6 ��-I ~I O rtf -~-I ~ 0 0 ~ U~-? : N S~ � r i ' C 1 ~ N N O U N N ~'0 0 a rr t~ v, ro~ rn u o I , u~ x u~ a ~s o 0 v~ a~ ~u G s~ m~ a~ A~ w�.~ ^ N A r. ~ A ^ ~O O 0 a.` , w b N ; 0 'c7 ~ - .u ~ o , ro o I y~~ w ~ a~ ~d a zf�~+ p,tww or w~+~~ ~y..~ owww~ ~ - O N~ v S~ tn 0 0 N G) O 0�r1 ~ 0�,~ 4+ 3~ rt?a O O�~ tP U 1~ t~ N.C ~ U tn ~ I U I b~ 0 ~ ~l O U a1 0 U ~V O'Lf ~ A~ i+~ ~ W O UI f0 1~ �.i 'O " N N rl N O N N~1 U1 ~n a+~ b l~ a~ I G a~ > s~ ~ ro v cn ~ N rtl w u1 ~ a) ~U 0 s~ I.,~ N p u~ �~1 u~ 0~'~ r~ N O ~ A U'U O U ~ ~C N W tn ! iT i~ 0 la .-I tT 1~ 1~ ~-I b~ U~ - i N N N I N O'~ i N~ N U O d�rl C. 1~1 i-1 ~�rl q ~1 b~ �r-~ f.' ~n ~ s~ v~ a, cr!~o a~ a~ ~s .u ro a, a~ I~o a~ .u .u ~ a~ . a~ a~ ~ ~ c ~ N ~ ~ .4., y U 23 I t r-I p N~ N N U'~ ~ tr~ b~ cd i r-I ~ CP tr~ td .-I ~ tr~ Ln �r? r-I ~ tr tr+ tr I r-1 ~1 t.' N[: N' r-I �rl O 4-~ I�rl ,L' r1 O�rl W tA �rl S+~ ~ O�rl �r-I 4) ~ O I�-~ 0�rl �rl �rl , a:~o ~c+~ ~,;~c�~Q~ o:cn c~(~ ~~s o�.~A ~a~ro�o ~�.~+~i~ ~broro _ ' ~ ' - , - ~ ~ I~ ~ i I ~ I + ~ . I ~ ~ ~ o ! la ~ ~ ,a ; ~ ~+~i ~ y ~ I~ I~ , , ( - s ~ ~ ~ ~ ~ I~ ~ I~ ~ i - N ~ a a~a Ig ~ a I ~ F-~i I ~ ' ; v I ~ - - - ~ j ~ ; N ~ , i ~ ~ , ~ C ~ ~ ~ I b m o ~ N i M r c~ M o ~3 b ~n ~ u~ ; u~ ~ u~ u~ ~~n ~o I`fl a ro o o lo :c o 0 0 ~ o � ;o ~ ac~ I o o ;o io ~o lo ~o o i i I I j ~ O ~ I i ; ~ ~ I ~ ~ ~ i ~ T'_~__~._-. "i' . " _ r-� - V ~ i i ~ ~ I i I ~ ~i ~i o~ ~ a z '~w ~o ~N ~w ~N o ~ ~ U~ U H 'Ca U !H i~ r�C r~ ia ~ _ i ~ I ~ A~ ~ i ' ' ~ F I i ; I ~ f ~ ' ~ E+ ~ H ' C ~ i ' I I~ I H H U~ O .x ;x ' v ~ - 0 i ; ` ~ u~ ' H ~ ~ ~ ~ ~ i H O U iH ~ I H H x ~ w ' ~ ~ a ~ ~ ~ ~ x H ~ o - ~n ~ o i o c~ ~ ; ~ H ~ ~a I~ a N~ ;H a IH a ~cai ~ y~ ~a ~ w w,w iw i x o ~a~ o 'r H ~ c, H ~ ca z H i z ~~c H ~c F ~ a o.~ ~ ~ ~ ~ ~ ~ b o , ; , t u o ~ ~ a~ ~ ! ' i ~ ~ ~ ~ r~i ,-i ro , ri cr I ~n io ~ r ~ i q rt ; I I I " H z o ~ ~ j * 2L~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR UFFIC[AL USE ONLY ~ - ~ o = w I i m I ~ I s~ A b~ ~ b a~ ~ O 4-+ b~, ~ a~ ~ z~ s~ ~ ro~ ~ ~n ~ a~ o w~ ro a~ ~ o ~ a~ .r~ ~n ~ cn z ~rl N �.-I f-I v J~ N C) N'J ~ �~-I O U j~+~ i~+ N �~I U I�~I a-? C 0+~ ~ U W i~ SJ ~ u1 b~ N i ~ N C1 U O�~-I �rl .0 N v1 I U �~1 W td U N' U U N.1~ N ~1-~ tr~ ` al u v 21 ~ a~ 3 a ~ I ~-1 - N ~ U 1~ ~ W ! ~ ~ O O i~ ~ 'Ll rt N v�.-i 0�~ O'��I r-1 U m w�ri ~ a f o a~ o�~ a~ ~ ~r ~ a~ ~ a~ 0 3~~ s~ > I m;�~ o ~a ~ ~ o N i c.~ cn b c.~ b ro+~ ~ ro~ a~ b u, b b ~ ' s~ t~.~ ~u ~ ~ cn ~ ~ w a~i ~u-~ ~ ~n ~ ~ A.~ ~ .~i cn ~ A ~ a~ a~ cr o o u o~ I 0 b.?.~ a~ ~ b~-+ ~ ai a~ b a~ o a~ ~ a~i aNi a~i a~ b w u~ ~ a~wro b�~~o~~~~+~.a~a o u o a~ rn~+ c, cr b~+ a~ a~ a or+ o~w�~+ ro v, m o ro~, a�~+w.~~ s~ a~x o ~x ~ o o ~s ~ ~ , ~ ~ x o o ~ ro N ~ ~ ~ I i ` i�� o ~ IU U II ~ I I+ II ~ ~ ~ ~ I I ~ ~ .l ~ ~ ~ i ~ 0 ~ a ' 0; ~ ` I I ~ I ~ ~ iy ~ ~ i ~ ~ ~ ~ i la Iw ' w w� - ~ z ~ i ~ ~ I ~ I ~ ~ { �~i ~ I I.-1 tf1 ~0 M 1~ 1~ Z7 I I ~O u1 u1 O ~D ~ v I I o� I�o `O �o �o ` 0. f I ~ � ~ ~ ~ ~ a i ~ ~ ~ I i W c~i o '�a' ~ ' cpn 3 ~ c~p 41 ~ U ~ ~ I ~ I a ~ - ~ ~ ~ � I ~ ~z ~ ~ - - ~ ~ 'H w H .u o ~ x I o H ~ ~ ~ ~ E H RC ~O-q{ I.~ ~ I c~�~i.' 2 I H ~ ~ ~ - - v N Iv ~~U a A a ~ H i a N H a;~ ~~w z ~ u; !~a a u~u~i c~ ~a~o n I.u ,-i ~ ~ ~ ~ - a~ .-~i a~i ~ i o - i ~ ~ w e-G-1 r~-I !~-1 ri r~I ~ H H I z o I I* 25 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007102/48: CIA-RDP82-00850R000300144438-6 FOR OFFICIAI. USE ONLY - The NFGATIODI (NEG) instruction changes the sign of the operand, i.e., the operation of conversion of the number to supplementary code is carried out. If the operand is equal to 100000, digit V is set to one upon execution of. this instruction. This ~ occurs because the num~er 100000 (-215) is the maxi.mum negative number to which no positive number corresponds (modulo) in t.he supplementary code. This means that - the result of the operation goes beyond the range of the sign representation of the numbers. Digit C is always set to one with the exception of t?~e case whPn the oper- and contains zero. The negation operation carried out on any number (except zero) means an attempt to find a negative number which does not exist in r~presentation _ without a sign. " The INVERSION (CO~t) instruction executes digit by digit inversion of the operand, ~ i.e,, the operation of transfer to rever:ae codes. In this case digit V is always - dropped to zero and digit C is set to one. Shift instructions. The arithmetic shift instructions ASR (ASL) accomplish the oper- ation of shifting the operand by one digit to the right (or to the left). In this case the "expelled" lowest (highest) digit of the operand is written in digit C. Upon a shift to the right, the highest. digit of the operand retains its value which it would have prior to execution after ex~cution of the operation. Upon a shift to the left, a zero is written in the lowest digit of the operand. The operation of the arithmetic shift instructions is illustrated by Figure 1.5. CnoBo ~ ~ ~ c ~s o _ 6au T ) ~ ~ ~ I i ~ I ~ ~ ~s � HeverHeui aapec ~3) 8 0~ 4erHniu ar7pec ~ CnaBo ~ ~ I i ~ I i i I ~ ~ I i i I ~ ~ ~ 6pur _ L=1 , I~ ~ I ~ ~ ~ ~ I ~ ~ I ~ f ~ 15 He4erHaru oBpec yerHOiu ar7pec - Figure 1.5. F,xecution of Format Shift to Riqht (a) and to Left (h) - Key: 1. ~~~TOrd 3. Odd address 2. Byte 4. Even address The cyclic shift instructions FtOR (ROL) also accomplish the operation of shift of the operand by one digit to the right (or left). In this case the contents of digit C are recorded in th~ highest (lo~,~est) digit of the o~erand. The "expelled" lowest (highest) digit of the operar.d is written the same as in the arithmetic shif t. Thus, the cycl.ic shi.ft of a 17-digit (or nine-digit with byte operations) register consistirig of an operand and digit C is accomplished. When organizing 26 FOR OFFICiAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02108: CIA-RDP82-00850R000300100038-6 FOLt OFFICIAI. 1JSE ONLY a multiple cyclic shift of the operand, the programmer should not use ins~ructions which change the state of digit C. The work of cyclic shift instructions is il- lustrated by Figure 1.6. CnoBo Cl) ' ~ c ' 15 , � ' . 0' . ~ � ' . 6aur ` � ~ ' Neve7Hbi 3) ~ yerHa~c3 (Y . !5 0 7 ' 0 ~ ~ . C _ a) ~ ~ CnoBv ~ ` . � ~ ~ ~ - 15 ~ 0 - 6aur ' 15 8 7 . ' ' Q . C C ~ ~ Figure 1.6. Execution of Cyclic Shift Instruc~ions to the Left (a) and to the Right (b) Kev: , 1. Word 3. Odd 2. Byte 4. .Even , Instructions for 4!orking with increased accuracy. The 16-diqit format of a machine word places restrictions on the range of represented numbers. If this range must be expanded, the operands are represented in the form of several words (or bytes). Arithmetic operations are executed separately on the hiqhest and lowest parts of _ the operands. If a diqit C is set above the lowest parts during the operation, this means that the result exceeds the range of the lowest part of the operand and this should not be ta}:en into account during operation on the highest parts of the ~ operand. The AllDITION I4ITH CP.RRY (ADC) and SUBTRACTION WITH CARRY (SBC) instruc- tions are used for this purpose. - For e:cample, ii- tH~o numbers with double accuracy, one ot which is recorded in registers R.1 and R2 and thc~ second of which is recorded in reqistars R3 and R4 must be added, th? following sequ~nce can be used: 11DD R1 AND R3; add the smallest parts; _ = ADC R4; add the value of carry to the highest part; _ I 27 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300104438-6 FOR OF'FICIAI, USE ONLY ADD R2 AND R4; acld the highest parts. The SIGN DISTRIBU`1'IOP1 (5XT) instruction is used to facilitate working with negative numbers. It permits transfer of the number contained in the word to an equivalent word with double accuracy (with regard to sign), cunsisting of two words. Digit Z is set to one if the initial word is positive (since the second word is filled k~ith zeroes in this case). Digits N, V and C are dropped to zero. This ~nstruction is realized only in tre SM-4 U~~K and does not execut~ operations with bytes. The S[aAB instruction. The highest and lowest bytes in the word change places as a result of executing the BYTE PFRrtUTATION (SWAB) instruction. For example, if the number 1234568 was in register RO prior to execution of the Sc~JAB RO instruction, the number 027247g will be contained in it after execution. Conditional codes Z and ~I are set according to the contents of the lowest byte of the result. Digits V and C are dropped to zero. This instruction i.s convenient in packing (or unpack- ing) of data which rPpresent a byte file entered (or read) from the. VU. It is ob- vious that this instruction does not perform operations on hytes. \ Two--Address Instructions Arithmetic-logic instructions. Formal description of thes? instructions is pre- sented ~in Table 1.6. ThP format is shown in Ficiure 1.~, b. As can be seen from the fiyure, the instruction code consists of two address fields and an operating code field. ~ach address field is formed the sam~ as the address field of single- address instructions. The ~ddress formed in diqits 5-11 is called the source ad- dr~ss ar~;' tnat for~e~l in diqits 0-5 is called the receiver address. The result of the operation is always transmitted through the receiver address. Digits 12-15 of the instruction codP are allocated for the operating code field. Two-address arith- metic-logic instructions can perfarm operations both on words and on bytes. An ex- ception are ADD (ADD) and ~UBTRIICT (SUB) instructions. The feature of byte opera- tion is a one in dictit 15 of thA instruction code, the same as in single-address instructions. The letter B is ad~ied in the mnemonic notation of the instruction. The TRANSMISSION (t40V) instruction is found more frequently than others in programs written in the instruction codes of the SP~-3 UVK. The conditional code digits Z and N are sPt according to the contents of the operand-source during its execution. This permits one to avoid in s~r?e cases the use of the supplementary test instruc- tion (TST) at points of program branching. Digit V is dronped to zero and the con- tents of digit C do not cl~ange. 'I'he operation is performed in similar fashion dur- ing byte transmission. Recor~i*~g is performed in the lowest bvte of the regis~er upon transmissi.on of. a hyte from the memory to the register of the processor, which has a 16-diait format, while the sign of the onerand-source is "distributed" in the highest byt~. For examPle, if tY1P number 350g is containe~i in the byte by address 10~1, the number 177750g will be recorded in register R3 after execution of the instruction MOVB 10!~1, R3. When executing the instructions ADD (ADDITION) and SUB (SURTRACTION), the result of the operation is stored by the address of the second operand, i.e., the receiver. The previous contents of the receiver are lost. These instructions do not perform operations or, bytes. Settinq the conditional caies corresponds completel_y to stan- dard defi.nitions of these codes. This means that digit ~J is set to one if the - 28 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL U5E ONLY ' N U) ~ 1 W N }1 Q) I R TJ N ^1 ~I1~ S~~/ 1^~ I O-: 0 4~+J i(~~ N`. OJ N W`, W` , V ^M, I O N M W f7 M ~1 ~~y~ W`, J^y, 1"1 M ~ W M ~ ~'f'~ ~ I~ O ~ W r ~ M W ro i~+ .u a~ ~ a o~ ro u u~o ~~s ~ - - x ~a~~a oa~a~ ,o o ~+s~a~ ~ a a, ~ > o o a, I.~+ a j u a~+ a, ~ x a~ z~ ~ a~ o o �~u rr;~+~>o ow aoa~oa~o~ s~ o a, x~;~o I a~ s~ o N ~ ro~~ ~ s~ u&+~ ro ~ ~ o a~ .c ~ ~ zy N N u~ a o x ~n a~ o~.~ ~ u+~ ~ s~ .u ~ w�~ o ro o 0 �rl N+~ tn I}.~ U~ r-I 47 0~ ~�rl ~ O 0 cA m 1.~ ~ N, W R, 1~ W 0 N tr~ N~ S-I 41 4a U 4-1 T~+ i W ~41 �rl Cl IA ~�ri 1~ 1~ N N W y.~ ~ 4-I ~1 N 0 a1 'd ' 0 Ri O,~ >~O rtf ~ 0~ t+~ D O~d 1 O'd N N b G: N~~ 0~ ~.C i 4+ 0 TJ ~�ri N~ Q N~ Rf N+~ U ~ ~d ~L+ UI O O ts U R7 N~ m f~ tn J~ �~I ~J �.~I .I.I u O 6~ G) ~ rt1 ~J U i~ N 1~ U N a e~ a ro'~ro o a,+~+~ m ~ a~ rt u vv~a,a~~o ~�~+u~o+~~bwr~os~a~�~+a~~+a~ ~ > ~ .u u, m ~ ~ u a ~d a y ~ ~ a~ s~ ~ ~ ~ ~s a~ ~s ~ a~ a+ ~ ~ ~a'~i ~o' a ~ o ~i o ~ o~ c~~o ~w a~p o x o�~+ - N U+~ U j U N O rtf I~l C) N N~p) A~ N U ~-7 O~d U S~j U cn O ~ ~ ' ~ ' O ~ I i ; ~ ` c73 t i 1 ~ 1,-i ~ ~ S.~i I Ra i~ E ~ ~v.~ ~ ~ ' R ~ R+ R R~ ~ Oa i ~ H ~ I I~ I^ v v J.~I ,1.1 i11~ N U a' F-. ' 1~ ~ F.. ~ ~ ~ rl ~ �ri Y~1 ~ N ; y.l N N S-1 ~?~1 S~ I v i a l;= v +f a ~ ~ ~ ~ ~ u --..~-_..__-4---_.--- ---r - - _.-_y--_; ! i ~ , i ~ N j ~ ; ~ j ~ ~ o c ~o ~o ~o 0 0 ~ ~ ~ U I I i ; ~ U~ ~ ; ! i I a i ~ ~ ! ~ ~ ~ ; ~ ; i , , ; ~ O'd C H ' H ~H ~ A ~ ~ N U ~ ` U P U : O q ~ 0 0 ~ U l ~ ~ I~ I ; ' ; + ; ~ i - - ~ ~ ' i ~ I I ~ I ~ , t ~ ~ ; c~ ~ ~ I �.~i H ~ z ~ V ~ EE-, H ~ U~!� Ix IU '~W!] O,U H H U , I I ~ _ I ~ ~ u~i I~ e, ~ E-+ ~ E-+ + EH+ - _ ~ ~ ~ p~, + ~ H ~ H ~ H I Aq ~ - ~ H H ~ U G] ~ A ~ A I rC ~ j__ _ - i I ~ - + ~ ~ i I ~ ~ i ~ ~ H r-1 N M ~ t11 l0 ~ l~ 4-I z o ~ I 29 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300104438-6 FOR OFFICIAI, IJSE UNLY a~ i a~ ~ m ~ I a~ ~ o a, ~ ~ ~ ~ a, .u ~ + ~ v u~ a~ , s~ c~ ~ a a~ ~ w o cn 3 �a .C t~ tr~ ~ rts w a a w ~~.a ~ro ~ cr o 0 O OR~ O O N i~~ v�~ O'd 0+~~~ ~ m G G 'b G ~ ~ 4-~ 27 i a cn a, rr b N a, .u la a z tr rt a~ x.~ o o a, ~ a~ N ~ ~ .C O .C " Z .a~ ~ N N ' U O ~ 3-1 C.' 11 .V rl C.. ~'.y (S.1 1~ Ul rl G: C: f-I '~i U1 N U�rl v a~ v, a a~ a-- a~ w+ a~ a o rn+: r~ u a~ ~ w�~+ ~n w~- I~ o.c o 3 ~n ~ o~n a a ~a o ~ u, a o~ ~n ~ o a~ ~ u~ v~ o m+~ x a~ ro a, o a~ ~n o ro~~ m~ N~, ~ a~ w b+~ ~ ro N � a~ u+~ ~ a~ a~ ~ tr u, s~ ~ a~ u~ o~~ b a~ a~ ~ o v w ~ o o o ~ o ~ a, w a~ ~ a ~ ~n a~ b~�~ a~ ~ ~n ~ o ~d �rl ,C N �rl �rl .f: tl) �.-I 0~ k �rt ~ C 0 X ~l �-i 1~ W 1~ N CP i-~ N N �ri i~ N�.1 'b b~ `~i ~ C+ ��-1 fA Q1 ~ i~ ~L , U O S~ 'C7 ~p+ N 'Ci 0'd u1 ~ S~ ~ O N w d N.4 ~J 3~ S~ N S~ v' N Z+~ O~ U~ N A^.~ O~�~ O C] ~ ~ O 4+ ~ G~I+~ Y~1 W O Ei ~ 1~ �rl ~ N UI V' ~~Ci ~ ~ Q ZS H + C ~ Y~ tr ~ d O'G O 1~ 0 N I N N tn r-1 a1 cn C{ N.A O N 0~ 4-+ w Rf ~ I �rl .t2 tn Zti L4 Id-~ C tn ,fi tp +1 � O ~.I 'C1 'i7 ~ Il~ C ri ~ U' +,^J 1~ �rl � UI t C R7 ^ rl �1~ W'I-~ ^ Ul N 4J N fA 'CS c a a~ o a~ m�.~ a~ o a~ e ~ a~ o~�,~ o�~ m a~~ a~ ~ w ~ a�~+ r~ ~ a~ u u~ a b.~ Ts a.c o~ o s~ b I O i N~ ~'L7 C I w V m+~ V z�~ U N v1 ( ~ A 0�~ ~.~~C 0 m O~~~~ Z ~ O w ~ O u1 N 2 w�~ X~~~ C~ E-+ ~ U) ~ rt1 E-~ U�.-I U1 ~N rd I~ U1 ~ w O~ U��a r-I " O'd E~ U1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ j ~--i m t'+ ~ S-i + + �rl ' U I ~ R' ~ R: ~ ~ I~ ~ ~ v ~ , ~ i 1 tT j ~ I � ~ i_ . _ - 1 ~ I�~ d) O ~~-I ~`7 I M ~ ~ ~ ~ ~ I ~ I~ c~i o 0 o I o 0 ~ ~ j ~ ~ ` ~ I _ _ ~ ; ~ I ~ I rt ~ O ro ~ H cn x ~ O Qa I N(~j A FC I a I;ti ~ ~ ~ ~ I _ - - .v _ ~ - - ~ ~ C w w ia O H ~ x x ~O ~ i i U ~ tA ~ j C7 H I ~ ~7 O i-wl W~W-7 I H I ~ H UJ H H H ~'J - I ~ a ~ a ~ a ~ H ~ IQ ~ U ~ IW ( - ~ 6 I N ~ H rl N M d~ U1 W z o 30 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE O1VLY result of addi tion (or subtraction) goes beyond the range -215_215_1. Digit C is . set if the result c;oes l;eyond the range of a representation without a sign. Over- flow can also be detarmined by another method. During addition, digit V is set to one if both operands had identical signs and the result had an opposite sign. Dur- ing subtraction, digit V is set to one if the onerands had different signs and if the sign of the result coincides with that of the source. Digit C is set to one if the result goes beyond the ranqe of the represPntation without a sign. In other words, during addition, digit C is set to one if there was carry from the highest digit of the res ult and during subtraction digit C is set to one if this carry o~as not present. The instruction C0~?PAP.ISON (COt~!P) subtracts the contents of the receiver from those of the source. In this case the contents of the source and receiver do not change since the result of subtraction is not stored anywhere. Therefore, the only result of this operati on is setting the digits of the conditional codes. These digits are set the same as when executing instructions SUB if the difference in setting the . _ overflow digit V is not considered. Since the contents of the receiver are sub- tracted fr~m tho se of. the source when executinq the instruction CMP (the contents of the source a re subtracte~3 from those of the receiver when executinq the instruc- tion SUB), diai t V is set to one if the operands had different siqns and if the sign of the res u lt coincides with that of the receiver rather than the source. The instruction CP-1P is used to compare the contents of two elements (registers or Mem- ory cells) at t he points of proqram branching. The instruction DZ~IT SET:IPIG (BIS) executes the operation of logic addition of the contents of the sc~urce and receiver. This instructi~n is used to set a specif- ic combination o f cliqits (indicated in the source) in the receiver. All the digits previously set i n the receiver remain in the same state. Digit V is dropped to zero and the va 1 ue of digit C does not change. The instruction DI~IT CLEAR (B7C) executes the operation of logic multiplication of the contents of the receiver and of the inverted contents of the source. This in- ~ struction is us ed to drop the specific combination of digits (indicated in the source) in the receiver to zero. All the digits previously set in the receiver re- main in the same position, Digit V is dropped to zero and the value of digit C does not change. The operation o f logic multiplication of the contents of the source and receiver oc- curs by the instruction DiGIT TEST (BIT). Only the conditionai codes are set as a result. The con tents of thP source and receiver do not chanqe. The instruction is = u5ed to check tYie setting of a specific combination of digits (indicated in the _ source) in the receiver. This check is usually accomnlished at the points of. nro- qrammer branchin g, Diqit V is dropped to zero while the value of digit C does not change. Supp].ementary arithmetic-logic instructions of the SM-4. Formal description of t}iese instructions is presente~i in Table 1.7. These instructions are also related to the group of two-addrass instructions, but have a different format (Figure 1.7). As can be seen f rom the figure, the proc~ssor register is ~lways indicated as one of the operands_ The source-operand is formed by the same rules as the operand in single-address instructions. 31 . FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02108: CIA-RDP82-00850R000300100038-6 FOF OFFICIAI, USE ONLY 15 ~ 9 8 '6 5 ~ 0 PEr F2�) tPE.7IC ~ 3) PEr ~-v----' (1) Koa onepauuu (4 ) ~epBa,u Bropoci onepaHa onepaHa Figure 1.7. Format of Supplementary Arithmetic-Logic Instructions of Shi-4 UVK Key: 1. Operating code 4. First operand 2. Register 5. Second operand 3. Mode i~hen executing the instruction MULTIPLICATION (MUL), the register indicated in the instruction code is used as the receiver-operand. Since 32 binary digits are re- quired to represent the results of multiplication of two 16-d iqit numbers, this result is carried to two registers: indicated in the instruc tion code and in the one following it by number. For example, if register 4 is indicated in the instruc- tion code, the result will be found in registers R4 and R5 after execution of in- struction t,4tTL. If the number of the reqister oi the receiver is odd, only the low- est part of the result in this register. is stored. The digit is dropped to zero and ~igit C is set to one if the result of the operation goes beyond the range -215-21-15-1. Two registers are also used in execution of the instruction DIVISION (DIV). Thus, _ the 32-digit di~~idend contair.ed in registers Rn and Rn+l is d ivided by the 16-digit divisor which is found in the source-operand. The result of division is transmitted to register Rn (the quotient) and to register Rn+l (the remai nder). The number of register Rn should be even. Digit V is set to one in two cas es: if the divisor is equal to zero and if the absolute value of the highest part o f the dividend (i.e., the contents of the register) is greater than the absolute va lue of the divisor. In this case the instruction is not executed since more than 15 digits are required to represent the absolute value of the quotient. Digit C is set to one if the divisor is equal to zero. The instruction MULTIPLE SNIFT (ASH) shifts the sele.cted reg ister to the right or left by K positions. The number of K positions is stored in the supplementary code in the six lowest diyits of the source. If capital K is les s than zero, a shift to the right is mac~e and if K is greater than zero, a shift to the lef.t is made. - Thus, the contents of the register can be shifted by 32 posi t ions to the right and by 31 positions to the left when executing a single instruct i on ASIi. If K is equal to zero, the contents of the register. Digit V is set to one if the sign of the digit of the selected register changes durinq the shift. Th e value of digit 15 (F~ith a shift to tl:e left) or zero (with a shift to the right), which was in the reqister prior to the last shi�t, is carried to digit C. The instruction CONtBINED MULTIPLE SHIFT (ASHC) is used when working with double accuracy. The double word consisting of the register indicat ed in the instruction and the register following it by number is shifted when executing this instruction. 32 - FOR OFFICIAL USE ONLY ~ APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FUR OFFIC[AL USE ONLY The number of shifts and setting of digits V and C are determined the same as in ] the instruction ASFI. Th~ instruction EY.CLUDING OR (XOR) fulfills digit by digit addition modulo 2 (other~vise the o~eration "EYCLUDING OR") of the source and receiver operands is executed. Digit V is dropped to zero and the value of digit C does not chanqe. - Floating arithmetic instructions of the SM-4 WK. Instructions for executing all _ four arithmetic operatious over numbers with floating decimal (floatinq arithmetic instructions) are provided in the SM-4 UVK. Formal description of these instruc- tions is presented in Table 1.8. - The exponent (eight digits) separates the mantissa from the sign of the mantissa. Tha mantissa is always normalized, i.e., the decimal poicit is locatPd to the left of the most significant digit. The most significant digit of the normalized mantissa - is not stored in the memory since it is always equal to one in positive numbers and ~ it is always equal to zero in negative numbers. The exponent changes accordingly _ upon normalization of the number. The exponent is stored by a value increased by 200g (12810). The sign of the exponent is stored in the 14th digit of the highest half of the number and is considered as a one for a positive exponent and as a zero for a negative exponent. Thus, the exponent may vary from -128 to +12"/. The re- sult of the operation with floating decimal is always distinct from zero. If the ~ exponent is equal to zero, the number is considered equal to zero regardless of the sign digit and value of the mantissa. In this case zeroes are formed by apparatus ~ in all 32 digits of the number. Table 1.8. Floating Arithmetic Instructions of ~M-4 WK (1 (2) ~3~ ~(4 (5) ~ KowoHne ~ . � = A11'OPHTY - � ~ ~ s Y a . 1 CJION(E� FADD 0750U ((R)~-4, (R)+6]�-[(R)+4, (R)+6]-f-[(R), (R)+~ H{�1E +2 , ecnH erar~2-1�, ~uiaye [(R)-f-4, (R1+ +6~+-0 (11) 2 [3b14NTA- FSUB U7501 [(R)+4, (R)+6)�-[(R)+4, (R)+6)-[(R), (R)� IibIE (7) +6~~--O~H~lO~nsraT~'L-~~e yt~~,,~ ~~R~+4, (R)+ ~t 3 YD1FIO~CE- FMUL 07502 ((R)+4, (R)+6]+=~(R)+4, (R)+6]X~(R), (R).-F. II}~iE ~8~_ +2 , ecni~ pe3yn~~aT~2-tT�, Nua4e [(12 -I-4, (R)-~� +6~--0 (10) (11) . ~ 1lGIlEH6iE fDIV U7aU3 [(R)+4, (R)+6]--[~R)+4, (R)+6]/[(R), (R)+ ~9~ +2 , ecn~~ pe3ynbrar~2-'~8, ?~fiaye [(R)-4-9, (R}-t- +6~~-U (10) (lI) , Key: 1. riuml-~er of item 3. Mnemonic codP 2. Instruction 4. Operating code [Key continued on follo~~~ing paqe] 33 FOR OFFI~CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFIC[AL USE ONLY [Key continued from precPding paqe] 5. Algorithm 9. DIVISION 6. ADDITION 10. If the result 7. SUBTRACTION 11. Otherwise S. MULTIPLICATION - Digits 3-16 are shifted under the operating code in the floating arithmetic instruc-- tion format. The three lowest digits indicate the register which se rves as the op- ' erand stack. The operands in the stack are arranged i:, the following manner (the addresses of the memory cells are indicated from the left): (R)--highest half of operand B; (R)+2--lowest half of operand B; (R)+4--highest half of operand A; (R)+6--lowest half of operand A. The result of the operation is stored in cells (R)=4 and (R)+6. The stack index contains the address of the first word of the result after execution of the instruc- tion. Digits V and C are dropped to zero. Carry Instructions Formal description of. the carry instructions is presented in Table 1.9. The highest byte of the instriiction contains the operating code and the lowest byte contains the eight-digit shift, which i5 a nuinber with sign which determines the carry address. This address is calculared by the processor in the following manner: the sign digit of thP shift byte is copied in digits 8-15; the result is multiplied by two; the result is added to the value of the instruction counter to find the carry ~ address. ~e assembler carries out reverse conversion of the carry address to form the shift byte. The eight-digit shift permits carry by 200g words (or 400g bytes} of relatively current value CK backward and by 177g words (376g bytes) forward. When executing thP carry instructians, the processor analyzes the logic expression in which digits of the conditional code of the SSP are used as the Boolean variables. Transfer of control by the address determined by the shift value stored in the in- struction COCIP or carried to the following instruction is accomplished on the basis of this analysis. _ All carry instructions can be conditionally divided into fotir groups.. The first group includes a single instruction--UNCONDITIONAL CARRY (BR). Transfer of control 34 FOR OFF'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL U5E ONLY Table 1.9. Carry Instructions Number ~ Tinemonic Operating Carry I of Item rlame of Carry Code Code Condition 1 UNCONDITIONP.L BR 0004 2 EY INEQUALITY TO ZERO BNE 0010 7, = 0 3 BY EQUALITY TO ZERO BEQ 0014 Z= 1 - 4 BY PLUS BPL 1000 td = 0 5 EY AIINUS BMI 1004 N= 1 6 BY ABSENCE OF OVERFLOt�1 BVC 1020 V= 0 7 BY OVERFIA4T BVS 1024 V= 1 8 BY ABSEt~1CF OF CAFtP,Y BCC 1030 C= 0 9 BY CARRY BCS 1034 C= 1 10 BY "GREATEft THP1I OR EQUAL TO ~ 'L~RO" I BGE 0020 N C$ V= 0 11 BY "LESS THAN ZERO" BLT 0024 N~ V= 1 12 AY "GREATER THAN ZERO" ( BGT 0030 Z!(N ~ V) = 0 13 BY "LESS THA?~1 OR EQUAL TO ~ ZERO" BLE 0034 Z! (N ~V) = 1 14 SIGNLESS EY "GREATER THAN ZERO" BHI 1010 C!Z = 0 15 SIGNLBSS BY "LESS THAN OR ' EQUAL TO ZERO" ~ BLOS 1014 C!Z = 1 16 SIGNLESS PY "GRFATER THAP1 OR , EQUAL TO ZERO" I BHI 1030 C= 0 17 SIGNLESS BY "L~SS THAN ZERO" BLO 1034 C= 1 ~ is always made when executing this instruction regardless of the staze of th'e con- ditional code diqits. The second group comprises "simple" conditional carry ~nstructions. This name is ~ related to the fact that the operatinq algori~hm of these instructions depends on . "simple" conditions. For example, when executing the BEQ instruction, transfer of control occurs if the digit Z= 1 and when executing the BRL instruction transfer is made if diqit N= 0. The third qroup cont~;ins instructions of sign conditional carries. 'Phey 3re uaed when workinq with numbers in the ranqe -215-215-1 (or -2~-2~-1 for operations with - bytes). In this case transfer of control depends on a more complex logic funct.ion. For example, transfer of control by the BLT instruction is made if the condition r1~ V= 1, where ~ is the operation "excludinq OR," is fulfilled. The instructions of the fourth group are similar to those o� the third group. How- ever they are usec~ only w}len working wi.th numbers in the signless range of 0-2I~-1 (or 0-28-1 For operation with bytes). Let us consider an e:~ample to understand the difference between the instructions of the third and fourth groups. Let us assume that the number 1777778 is located in _ regisi.er P.0 and that the number 000001 is located in register R1. In this case, ~ - upon ~~x~:cuti.on of the routine fragment _ 35 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICI~+I. USE ONLY CMP R0, R1 ; compare the contents of F.0 and R1, BHI A; carry by greater than Transfer of control by address A does not occur since the number 177777 correspbnde to -1 in sign representation, which is naturally less than +1. If BHI instruction is used, the routine f.raqment is written in the following mann er: CMP R0, R1 ; compare the contents of RO and R1, IIHI A; carry by greater than. In t}lis case transfer of control is made by address A since the number 177777g is c~reater than +1 in si.gnless renresentatio:~. Remaining Instructions The instructions, each of which has its own features and is unrelated to any of the groups described ahove. are described in this section. Formal description of the se instructions is presented in Table 1.10. The instruction of absolute ~inconditional carry (J,1P) is intended for unconditional transfer of control ~rithin the program. The instruction format is similar to that of single-address instructions (see Figure 1.4, a). The control transfer address is determined by the same rules as the address of the operand in single-address i n- structions. Thus, tran~fer of control to any memory cell is possible (unlike the BR instruction). It is obvious that mo~ie zero loses meaning upon formation of the address. Therefore, internal interrupt bY vector 10 occurs in the given case. Instructions reversion (JSR) and return from subroutines (RTS). The following main operations must be executed when orqanizing work with subroutines: transfer af - control to the subroutine, storage of the return address in the main routine and return of control to the main routine. These operations are executed in the folloo~ing manner in tr.e SN!-3 and SM-4 UVK: a) the control transfer addrPSS is formed in the subroutine reversion in- struction (JSR) by the samP rules as the addrPSS of the operand in arithmetic-logic instructions. The same as for the JNlP instruction, the use of mode zero in forma- tion of the address is meaningless and causes internal interruption by vector 10. The format of the instruction is similar to that of the supplementary instruction s of the SM-4 WK (see Figure 1.7), but the register does not contain the operand but the return address (see paragraph b); b) when executing the JSR instruction, the return address, i.e., the current value of the instruction counter, is stored in one of the RON (the programmer se- lects the register anc~ indicates it in the instruction code), the contents of wh ich are in turn stored in the stack (the contents of the US are first reduced by one- half); c) when executing the subroutine return instruction (RT~), a procedure in- verse to that described above is carried out and namely: the contents of the 36 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FUR OFFICIAI. USE ONLY � i ~ ~ I ~ ~ i ~ ~ a~ ~ i i i i c ~ i z i a~ i o u~ a~i ~ i ~ ~ j G.~ ~~~s ~ ' 43 Z7 1 i �~-I 'U � 'CJ U.C u1 I S~1 N.~ Ul k N i�r~i N~ Q1 td ! tl+ ~ N ~d ~ ~ .k JC N ~ a ~ U ~ N .C ~ O ~I ! tT ~ N N O~+ ~ G~ P G U ~C7 S~ rt1 O+~ M.~ !~u a~a~ ~ bN~,+~~~,ls~oro H t� ;a~'ia v3v - .A a~~b .n~, oNOa,~Ub ~ N uo ~a o s~ I I a~ s~ H~ , a, a~ ~n I~ u a~, ~ A ~a .u H ~~n ~a ~ a , v I ro.~ rt o ~ a~ w m~ - w H-- ~cn v~ ; a+ a~ ~ u ~ a~ ~n ~n a~ s~ ~n o a~ ~d ~o a u~ ~ s~ a~ �a .c b a~ a+ s~ .a .a a~ I o ~u a~ o�.~ ~ ~ ~.~G S~ I LI CT Q~ 1~ N 3~ .G ~ GJ I W N i~ N~ j~ N ~.~C ~~1, ~ O.~ ~ N ~ N � U N 41 N U N 1~ 0a ~ O N �~1 ~ z ~d U~ O O O U1 = d-~ i 4-I i~1I W~1 L! b N ~4-1 ~1 S-1 ~'.7 ~ 'Jr Ul i'd ~ !1) ~ O d-~ �ri ~�rl C'.. ~ ~ UI N I N Ql N 1~ �rl I N 0'C7 ~ W'~ ?,I i~ O A.C ~ C.' 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"J " E~ � 3~1 rl �ri U �r1 N L: ~ N S~1 N 3-I 1-1 'Ly W~ N S-1 C.' 11 U7 b~ N R7 N~1 W N W~ rd 11 }J �rl A;�~-I rI ~~i1 !�~I O N 0.~G �~-I v1 N td ~ N N 4-i N�.I 1~ J-> ~t' PO N I~ ~d m+~ Rf N~1-~ ~ u-~ ' ~ w b � ~ ~ .u ro s~ ~ .c ~n ~ ~n ~ a ~ M ~ ~u o+ s, a s~ a c i.~ o o v!~ m~ m b z�~ o ar ~n a�~ a ~ aui a~ ~ a% o : o ~ o z~ a+~ o o a~ a+ o o: ro ro~~r ~d ~ cn a+~ a~ .u ~ ; S-~ tA 1-t In tn N S~+ N I f-1 tA U S..I N N�r1 1-~ ~ r1 S-~ ~ 1~ N�~� r-1 O ~ O ~I O = - , ; m ~ ~ tA ~I T1 ~ �~-I ~ 1~ m 11 'd ~ ~j �rl ~ ~1 ~ N ~ N 1~ E+ i H ~ Q1 ~ N C S~ 1~ tT' N N N N O~1 i i~ O i~ 1A >C 'CS i N tA , H~ O d-~ r-I O I ' O S~ O Ya N C C) Ul ~ O la 1~ ~�~-1 ~~�~-I t11 N�~ N~~ U GJ ~ I.~ N~ 2( ~-I 3a ~ 3~+ d , i c,~ ~o o~~, I U ro~ rts ~ 3��~ ~n ~ a+~ ro 3 H~-- ro i F~, , H i,~ u-~ ~a w.~e . ~ I ~ i I I ; - ~ - --~--1-t----~ ~ ~ ~ i ~ I 1 I I~ j ~ U ' I , I~ ' r-1 ~ U~Ul ~ ta!] N If- f~ ' I m ~ ~ 4 ~ { ~ ~ ~ N !�'y' 2IU ~I ~ I O I I~' .~i ~.~j ~ U U z u1 U N.~Ci V Z I.~ " ~ I I I I r^ U 0. D>C L1; p f~ N U>C y 1 ~ 1 1 ~ 1.~ ~ ~ V .r ~ ~ ~ U U ~ Q+ I ~ ~ I i U ~ ~ i~' I'J y' y' ~ N O N 'J U i.`!i U i , ~ ~ D 4 1`-' ~ G 4 ~ a 4 u1 ~ W C~ U; U U I I ~ i ~ : U i-~ ~ U ~ U P4 ~ + U ~Y j ~ �r1 ~I?. + ~ I ~ ~ N ; i ~ i ~ i i ~ i i ~ ; - - r- - - ~ . , . . _ _ . . - I i i ' ~ ~ ~ �rl j�ri N~ r-1 J~J' ~ N [N l~ ' V' d' V' f'~ N l0 ! lf1 r-I O ~ ~ R3 O , O ~ O I~0 1~ ~ O V' O O O O O O O �rl I Rf O'O IO j0 O O I~--I O O 00 OI00 ,O ~ U' O ~ f0 O ~ ~ O O O ~IO O ,O , v ~a I ooooloo ,o , , ~ n, , o , � ; , ; _ I-------._._.----~----~---- - ~ - ~ ; ~ i a,':a ~a ~~n ~4 a~ HaHFHE~ wH la ri i o~ ~ cn ! E+ 04 ~ o I~ o a E+ E~ cn r.~ I ~ ;~~~h Ih ~a ~ ~n ~w~Hmaar~~ ~ ; ~ , I . - - . - ; ~ ~ ~ ( ~ ~ - H i i a i-- I z u ! , H j i I O Iw IH H E ' ~ I I I ~ H z p~/1 ~ f~ ~j ~ ~ N ~ H I H ' O O I ~ K+ I ~ i O~ A ~ c~0 paq O I W ~ W E-~ i C*.~ I ; a.~i ' O I n~G ~ t~!) vai t7 2 ~ H ~ O ~ I ' ~;r' Icn ;�a ~x ~ Iwa ~ H i ~ , a HH ; ~n ; w jp w w r~ o o w ~c a i ~i' z z j~ E-~ I U ~ I W ~ I H~ I i O >a+I i~ fZ x ~ C7 UW f pZ i W FI W W i u~ 4Y~~ iH ~ H ~ I~ O H z H Q H c~!~ j a~ ~ 3 ~ ~ a ~ a I~ a ~C ~ I~n ~ ~ ~ - ' ~---I a~ ~ ~ H' rl N I rl I tf') i lfl I~ i CO Ol I O ~ ~ I I ~ ~ I I ~ I ~ ~ ~ ~ ' I i ~ i ~ ~ ~ ~1---- _ 37 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 "r0[? OFFICIAL USE Or.'..":! sel~cted register are carried to the instruction counter and then its initi~l con- tents are carried to this register from the stack. After this the stack index is increased by two, i.e., it is returned to the state in which it was prior to sub- routine reversion. The format of the RTS instruction consists of the field of the operating code _ (digits 4-15 ) and the field in which the niuaber of the comanunications register (digits O-3) is indicated. The same register should be used in the RTS instruction as in the JSR instruction, by which reversion to the given subroutine is executed. I�`. register SK is used as the communications register, the return address (the cur- r:~~.t: contents oP the SK) will be stored in the stack upon reversion to the subrou- tine and this address will be restored from tYie stack upon return from the subrou- tine by the RTS instruction. The use of other registers simplifies the task of - the subroutine independent variables . _ The described structure of warking with subr.~~utines provides an essentially unlim- - ited depth of embedding of subroutines intc each other (it is limited only by the size of the memory zone shifted t~ the stack), repeated entry of subroutines and convenience of assigning the subroutine independent variables. An example of workinq with the routines is presented in Table 1.11. The subroutine independent variables ar e arranged directly beh~_nd the JSR instruc- _ tio~ code in the given example. Therefore, the address of the first of the inde- - pendent variables rather than the return address is stored in register R5. The subroutine should be written in the following manner to use the independent vari- ables.(for example, to registers R1 and R2): SUBR: MOV (R5 ) Rl - MOV (R5) R2 PT S R5 ~ Thus, the independent vzriables are transferred to registers R1 and R2 inside the subroutine while register R5 contair~s the return address as a result of execution of two instructions in the autoauymentation mode. - The subroutine return with stack clear instruction (rtAP,K) is realized only in the _ Sri-4 WK. It permits automatic return of the stack index to the initial state if - the independent variable of the subroutine is transmitted through the stack. Let us consider an example of using the MARK instruction. Reversion to subroutine is written thusly: h10V R5, -(SP) ; the contents of RS are recorded in the stack; MOV ARGl, -(SP) ; iv independent variables which should be transferred to the subroutine are recorded in the stack; MOV ARGN, - ( SP ) MOV # NIAPKN -(SP) ; the MAP.K instruction is recorded in the stack; = MOV SP, R5; the address of the MARKN instruction is carried to R5; - JSP PC , SUBP.; carry to subroutine . The contents of the stack at this moment have the form: 38 FOR OFFICIAL 'iJSE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 ~ FOR OFFtCIAI. USE ONLY I a � N ~v j LY. t.~ ' P~0 ~ O ~ 1 p $ 1 A 9 w ~ a �o � o 0 0. N Y~i ~ '1 ti a' o � o 0 0 ~ O ~1 ~ � c~ v cV t �ri U�~-I 0 ~ v x � , . ~ . ~ N YI o� 3 ~ ~ CG . 0~.C ~ N ~ ~ t~d ~ O ~ ~ o o~ N ~ 4-i W ~ ~ ~ ~ r ~n ~ o ~n o y A � ~n U SL . 4 a cA N N ~ o x v U _ � ' ~F+ ~1 !n �ri N ~ p ~ ~ ~-i . . ~ N m R7 O ~s ~ ` ~ ~ ~ ~ . O O p N ~ Cla C7 U LI �tT fd ~ ,1-I 0 0 O 5 fY CL' s~ o q o 0 o a a a a~ a, ~ b " = 1 ~ p 0 U il N~~ ~ ~ 4 ~ 6 ~ y n O O O O O " ~1 O Rj ~ N ~ _ ~ ~ ~ ~ m ~ ro _ = o 0 o cn ~ t� a, a~i 0 ~ a ~ o ~ ~ � ~ ~ ~ ~ ~ ~ ~ m o 0 0 ~,~y, ~u U d 0 N U N C. (~!1 �r~'-I a ~ ~ t3 ~ ~ - . ' ~ O .C �O �N N - _ y..~ 0 6, u v m _ U H 1~ ~-1 S.~ ~ O ~�,u~a " . ~ . ~ � o o m.T~ , c~ TJ ~ * ~ ~ Y , ~ " . , ~ ~y~~S ri - ~ ~ . a S x . " . . . , . , ' . . = y q0 s =C~" ~ . . . � � R~'a W u ^ G.U O 'S ~ ~ ~ . . ' . � . � , ~ Fl; 7 ~ C ~ C Q~. l~0 ~ . I ' ' . . � ~ ' ~ ~ - M ~ vyCQ m a O~ . . ~ 0 C~. ~ S ~ N u 'a L~ ' � �rl ~0 xtna w ~ ~ ~ r-I G ai q 1S O. � ~ ' U ~ - m~~WOr ~ 'L1 ~ � ~ � c a~ ~ ~ ~ , " O c~U .1-~ a~~xMa. _ ~ ~n u-~ ~ o ro - ~ H ~ _ . a~, � wawenor roN ~ N " O Ul O O N N ' ~ O a1 ~ O O y . ~ U ~I 1A N ~1-~ tA '-I s ~ d � O O O 0~ N O U ~ 'v Y : - N . .t{ ~ �rl N S-1 ~ , ~ , . . . _ . U U Ra U ~i-~ U ~ R3 a _ x ' ~3jQ � - , _ ~ ~ ~ �ri ~ ~ ~ rtf o ' N 1-1 N~I ~I SJ ~I I - _ ~ri 0 � . � ~ U ~ O O N I ~ ~ ~ a . . . ~n ~n u~ ~ ~ ~n a N3 _ ?-~i H A c~i ~ a ~ ~ rl N M d' ~fl l0 N ~ 0 a~ z 39 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 ~ FOR OFF(CIAL USE ONLY ~ , (1) ColtepHU~Mae RS ARG1 . ~ ARG2 � , , - ARGN MARK (2) AQpec BosepaTa , (3~Hasarenb cTeKa \ ~ Key: 1. Contents of P.5 3. Stack index 2. ~2eturn address Control is transferred to the subroutine SUBR, which should be completed by execu- _ tion of RTS instruction of R5. The return address is carried to reqister R5 and the address of the P~IARKN instruction, which will also be executed in the next step of the routine, is carried t~ register CK. The stack is reduced by r1 cells after its execution and then the contents of R5, i.e., the return address, enter CK from R5, while the current cell of the stacY. in which the old value of register RS is stored enters R5. Thus, complete exit from the subroutine is accomplished with _ restoration of the contents of RS and of the initi~l value of the stack index. The processor change of statP instructions (EMT, TRAP, SOT and BPT) are actually interrupts which are induced by the proqrammer himself inside the routine and have their own interrupt vectors. When executing these instructions, a procedure is _ accomplished similar to that described above for interrupt processing from external devices. The operating code of the EMT anci TRAP instructions occupies the top byte of the instruction code. 7~he lowest bytes of the Ec~T and TRAP instructions can be used by the programmer to enter any code. Tlius, a routine which will analyze the lowest byte of the instruc- tion and ~ahich will transfer control ta one of 256 p:~ssible subroutines can be entered in the cell to which control is transferred upon execution of the instruction. Compared to the J~n.instruction, the EfdT and TRAP instructions have the following � advantages: they alcvays occupy one cell of the OZU ~ahile the JSR instruction usu- ally occupies two cells. Using these instructions, the programmer can establish the word of state (the priority of. the processor is especially important in this case) cahich is required when executing the subroutine. This capability may be sig- nificant when writing real-time r~utines. , However, a disadvantage of these instruc.*_ions is the significantly greater time of execution. tdote. The EMT instruction is used extensively in standard software systems. There- fore, use of it in user routines is not recommended since corract execution of sys- tems routines is not quaranteed. 40 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY The values of the lowest bytes are not given in the IOT and BPT instructions; therefore, they are used for access to a single subroutine. Like the EMT instruc- tion, they are reserved for systems use. The interrupt return instructions (RTI and RTT) accomplish a procedure oppositF with respect to that which was described above for interrupt processing. There- ~ fore, the interrupt processina subroutines induced by external devices and internal , factors and also tr~e subroutines, control to which is transferred after exec ution of. EMP, TFZRP, IoT and BPT instructions, should be terminated with these instructions. The difference betk~een RTI and RTT instructions includes the following: RTT pro- hibits interrupt throuqh the following digit of the SSP. This interrupt can be ~ realized only after execution of the first instruction following the RTT and upon - execution of the RTI instruction this interrupt is possible irunediately after com- pletion o` execution of the RTI instruction. The format of the RTI and FTT in- structions consists only of the field of the operating code. rJote. The RTT instruction is used only in SM-4 UVK. The RTI inst ruction is exe- cuted in the SM-3 u'~IK the same as the RTT instruction in the S^9-4 tTVK. The counter carry instruction (SOB) is realized only in the SM-4 UVK. It is con- venient for orqanization of cycles. When it is executed, the contents of one of the registers RO-RS (the proqrammer selects the register) is reduced by one. If thP valuP of the reqister is not equal to zero, control is transf.erred by the ad- - dress which is determineci by the value of shift in the six lowest diqits of the instructian. If the value of the register is equal to zero, then control is trans- ferred to the next instruction. Thus, to orqanize the cycle, the programmer has - only to enter the number of renetitions of the cycle in the register and to place the S0~ instruction at the end of the cycle. Note. The SOB instruction is usAd to transfer control only ~aith a reduction of the addresses, i.e., the shift i~ always subtracted from the instruction counter. The conditional code set-reset instructions have the f~rmat shown in Figure 1.8. Digit 4 indicates that the following should be executed by the instruction: set- ting (one) or reset (zero) of the conditional code. The digits 0-3 indicate ~Nhich of the digits of the ~,Jord of state should be set to one or reset (ones are caritten in the corresnondinq instruction digits and zeroes are written in the diq- = its for which no a.ction is necessary). 15 5 k 3~ �2 .1 D ~ 0~1 N Z V C . ~ . ~ _ (1) Koa onepac{uu ~ I riqure 1.8. rormat of Conditional Code 5et-Reset Instructions Key: 1. Onerating code 1~1 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OTFICIAI. USE ONI.Y The mnemonic notations of these instructions are presented in Table 1.12. Table 1.12. (1) (2) I ~3~ ~ - MHlNOHNK~ KoH~e~td I UnepRUN~ Koa oneptuxa CLC C6poc C ~4 ) 000241 CLV C6poc V ~5) 000242 CLZ C6poc Z.( 6). 000244 CLN C6poc N (7 ) 000250 . . . SEC YcTaNOexa eAHHHua B ~~8~ 000261 SEV YcraHOeKa eAxNxuw e V(9) ' ' Q00262 ~ '$CZ YCTBNOBKB' eANHHUd 8 Z (1~) ~6264 SEN YcTac+oeKa euH~~Nud e N(11) 000270 _ . C6poc ecex pa3pAAox KoAa yC1109N~ ~~.2~~~025~ _ Yrrat+oeKa eAuaeuW ou ece paspAAd Koua 000277 , ycnoeNti (13) . Hynb�onepauee (14) . 000240, 000260~ Key: 1. Inscructiom m~emonic code 9. Setting of one in V 2. Operation 10. Setting of one in Z 3. Operating code 11. Setting of one in N 4. Reset C 12. Reset of all digits of conditional - 5. Reset V code 6. Reset Z 13. Setting of one in all digits of con- 7. Reset N ditional code . 8. Setting of one in C 14. Zero operation The RESET (RESET) instruction. [~hen executing this instruction, a common reset signal is formed on the INIT line of the "Common bus" interface which can be used to set the W to the initial state. This signal is completely similar to that which was generated when the "Start" key on the processor console was pressed. The INTERRUPT anticipation (WAIT) instruction stops execution of all operations by the processor. A way out of this state is possible only upon interrupt from the W. The address of the instruction following WAIT is stored in the stack upon in- terrupt and execution of the main routine is restored after completion of work of the interrupt pro cessing routine. Since the processor has na access to the "Comrnon bus" interface during execution of the WAIT instruction, the interrupt from the W is serviced at maximum speed. The STOP (HALT) instruction also stops execution of all onerations by the proces~or. Interrupts from the W are prohibited. The "Con- tinuation" key on the processor console is pressed to get out of this state. 1.5. Characteristics of Organizing Work With t�4emory in the SP9-4 WK The Stack Limiter One of the confiqurational characteristics of the SM-3 and SP~-4 UVI: is the apparat- us canabilities of organizing the stack memory. The programmer usually sets the stack index to the beqi.nning of its ro utine. The lower bound of the stack con.- - stantly changes value and may be below the permissible value during access to sub- routines, during interrupt processing and when using the stack by the programmer 42 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 1~0E OFFICIAI. 11SE ONLY i7imself for temporary storage. of information since the lowest addresses of the memory in the developed prograinriing systems have been shifted to the interrupt vec- tors. Therefore, equinment security of the interrupt vector zone is provided in the SP~[-3 and SM-4 ~JVK. If the value of the stack index (R6) is eRual to or less than 400, int ernal interrupt by vector 4 occurs. � If the stac}: must be arranged in an arbitrary memory zone rather than in the ini- tial zone, distribution of the stack to another memory zone in which the routines ~ are located is nossible. The apparatus stack limiter, which sets the lower bound of the stack by the routine , permits one to avoid this in the SP4-4 WK. An inter- nal interrupt occurs if this boundary is violated. The lower stack boundary can vary with discreteness of 200g words and the informa- tion about it is recorded in a special reaister of the stack lir.?iter. Access to this register can be gained from the routine by the address 777774. - Digits 8-15 of this register contain information about the stack boundary. These digits are dropped by pressing the "start" key on the processor console or by the ` RESET instruction. The eight lowest digits are not used. If_ access by the stack address, which exceeds (becomes less than) the boundary set in the register of the stack limiter (OS),is executed in the instructions, the vio- lation of the stack houndary is recorded. A so-called "yellow" zone of 16 taords - located below the stack boundary exist.s. Violation of it is recorded upon access to this zone. In this case all operatiaris in this zone are prohibited and inter- rupt of the routine by vector 4 is then induced. This interrupt in itself uses the stack, automatically leadinq to a second violation of the boundary, but it is exe- cuted witheut recording of the additional violation if only the stack address did not indicate the "red" zone. _ Violation of the "red" zor.e is prohibited during access to the stack (an odd stack address or nonexistent address are other uncorrectable stack errors). The opera- tion which induced this violation is rejected and interrupt is executed by vector 4. The contents of the stack limiter register are compared to the stack address to determine violation of the stack boundary. ~ The "red" and "yellow" zones are determined in the following manner: the "red" zone < (OS) + (337)8 and the "yellow" zone = (OS) + (from 340 to 377)8. If the contents of the stack limiter register are equal to zero, the "yellow" zone - occu~ies cells with addresses from 340 to 377, while the "rPd" zone occupies cells from 000 to 377. The ?~emory Dispatcher Another ~~iece of equipment of the SM-4 WK is the memory dispatcher, which is used to increase the vo].ume of OZU up to 124K words. The 16-digit format of the word does not nermit ac?dressing of the memory with volume greater than 32K words. Therefore, expansion of t?~e memory is intended mainly for internal storage and to , execute several tasks, each of which occupies no more than 32K words, rather than for storage and Qxecution of a sinqle task with volume greater than 32K words 43 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02108: CIA-RDP82-00850R000300100038-6 FOR OFF[CIAL USE ONLY (although this capahility exists). The control routine which distributes the _ " memory among tasks and which performs dispatcher functions upon transfer of control of one or another task is required to perform several tasks. Therefore, two oper- ating modes--user and systems--are provided in the SM-4 UVK. The mode in which the processor is at a current moment is determined by digits 14 and 15 of the SSP. S�]hen the mode changPS, it may become necessary to exchange information between the current routine and that ~ahich was executed prior to the change of mode. This ex- , change can be accamplished through the stack memory zone. There are two stack equipment indexes in the SM-4 WK. One of them operates in the systems mode and _ the other operates in the user mode. Moreover, the index is denoted by R6 both in _ - the systems routine and in all user routines. One of the indexes is selected dur- ing execution of the routine as a function of the current mode. Thus, two stack zones--systems and one of the user zones--exist simultaneously. The stack limiter can be used to Prevent intersection of these zones. Special instructions: TRANS- MISSION FROM D2BMORY ZnNE OF PREVIOIIS fdODE (MF'PI) and TR~iNSMISSION TO r4EMORY ZONE OF PREVIOUS tlODE (t�1TPI) are used to exchange information between these zones. The principle of inemory expansion includes addition of the value of the address formed by the instruction to a specific 18-digit shift. The extent of the shift varies upon transition to another problem. Thus, several routines encoded in the same addresses may be located in the memory simultaneously. Any 16-diqit address coming from the processor is first entered in the memory dispatcher., where it i.s converted to the actual 18-digit address of the OZU which prints it out to the address lines of ttie "Con~non bus" interface. Let us subsequently call the addres- ses formed by the Arocessor instructions virtual addresses and the addresses issued by the memory di.spatcher to the address lines of the "Common bus" interface physi- cal addresses. A virtual address is converted to a physical address in the following manner. The _ three highest digits 13-15 of the virtual address are interpreted as the number of one of eight shift registers, The contents of digits 6-12 of the virtual address - are added to the contents of digits 0-11 of the selected shift mode. The derived - 12-digit sum and the remaining six digits of the virtual address (0-5) form the physic~;l address. The entire field of virtual addresses is divided into eight pages, each of whir_h can be arranged at any point of the memorv. Formation of the physical arldress is illustrated by Ficrure 1.9. The ~hift reqister contains the 12-diqit field of the nage address. f?owever, this field can be re- garded as an 18-dicrit field in which the lowest six digits are equal to zero. Thus, one can control the position of the page in the memory wit}~ discr.ete.ness of 32 words. This file of 32 wor.ds is c~lled a block. Therefore, dioits 6-1'l of the virtual address ma~~ be regarded as a number while digits 0-5 may be regarded as a shift inside the block. The sum of the contents of the selected shift register and of digits 6-12 of the virtual address forms the numk+er of the physical block. A page description register, wrich contains information about the method of access to the page, lengtl~ of ttle paqe and the indicator of recording to the page, corre- sponds to each shift register of the page. The accessibility of the p~Zre is provided by corresc~onding setting of a two-digit code in the page cescription register. The pagP may be accessi~le for recording and readout, only For readout and completely inaccessible fnr both recording and a ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONI.Y - ~ (1) '~s 2 /s 1P s s o BupryanaHa~u Ilone aK~uB- yo,yep 6noka CHer~eHUe B aBpec HbIX CTppHf,/l~ 3~ 4 6noKe ' ~ ~ ~ 15 12 ff .D Peeucrp , ( 5 ) cMeweHUA . ( 6 ) /lone aa,oeca Crpa~uua~ � - ? � 6 5 0 ~~3eC ecKUU y`8~p ~u3uyeckoeo 6no,rQ - C~e ~noKe B P j ~4~ Figure 1.9. Diagram of Formation of Physical Address Key '1. Virtual address 5. Register of page shift 2. Field of active pages 6. Address field 3. Number of block 7. Physicai address 4. Shift in block 8. ?dumber of physical block readout. The latter means that the address field corresponding to this paqe cannot _ - be used in problem solving. This permits the memory to be protected against the - influence of one task on others. For example, if a storage capability equal to 20K words is allocated for the task, the access code which prohibits access to these pages will be set in the description registers of the sixth, seventh and eighth pages. If the task forms access to one of these pages through error of the programmer or due to the effect of external factors (in real object control tasks), this access is not executed ar.d internal interrupt occurs. If the system contains ~nformation which immediately uses several problems, a page _ (or part of it) is allocated to each problem in the address field, upon access to ~ahich the problem achieves ac~ess to the required information. Since this informa- - tion may be required after completion of work of the given problem and transition to the next problem, an access code corresponding to the mode in which only readout _ is possible is set in the page description register. The length of the page (in the blocks) is determined in the descri,ption register if a memory whose capacity is not a multiple of 4K is allocated for problem solv- ing. The length of. the paq~� varies from 1 to 128 blacks, i.e., fr~m 32 words to 4K words. - The page description register also contains the page recording indicator. The page recording indicator permits a saving of the time which may be expended on re- recording to the e:cternal memory of unmodified memory zones (from the ti.r,le of thei_r last callup to the internal storage) required for other purposes. Thi.s zone can be used immediately and the routine is not spoiled in this case since an exact copy of it is still available in the~external mernory. If at least one recording to the given page is made during problem solving, the indicator is set to one. 45 FOR OFFICIAL USE ONLY - APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007102/48: CIA-RDP82-00850R000300144438-6 FOR OFFICIAI. USE ONLY Still another set o� shift and page description registers is provided for working in the systems mode in the memory dispatcher. The memary dispatcher selects the required set of registers as a function of the code set in digits 14 and 15 0� the SSP. Thus, a systems routine may also be divided into pages and arranged in any point of the memory. The routine operating in the systems mode can utilize all capabilities of the sys- - tem. There are certain restrictions when working in the user mode. Use of one of the user routines which may affect the state of other routines is prohibited. The - user routine cannot execute some instructions (for example, HALT and RESET). If one of the impermissible instructions is encountered in the user routine, this ir~- struction is not executed and internal interrupt occurs. Moreover, it cannot per- form input-output operations, NThich is provided in the following manner. Access to the W is accomplished by addresses 160000-177776 (the hiqhest 4K of the address- able field) with the menory dispatcher switched off in the SM-3 and SP4-4 WK. Actually, the VU have addresses in the range of 760000-7677776. Therefore, upon _ access to the lowest addresses, the processor automatically displays ones on the - two lowest address lines of the "Common bus" interface. If the memory dispatcher is switched on in the SM-4 UVK, the state of these lines depends on the page shift r~gisters. P, value equal to 760000 is usually set in the eiqhth systems shift reg- ister. Thus, the systems routine permits access to the W. Upon transitian to the user task, the user set of shift registers is filled by the values which were determined during distribution of the memory for this task. If the total possible storage capacity (32K words) is not allocated for solution of - this problem, access to the virtual addresses is usually not possible in the range of 160000-177776. If the complete storage capacity is allocated for solution of _ the problem, the eiqhth shift register is loaded with a value which physicallv cor- responds to the beginning of some memory zone rather than to the beginning of the ~~i7 registers. _ [Excerpts] Characteristics of the line grouns. The level of the logic one in the active state on the lines of the first RP [Transfer authorization] [7:4] and RPD _ - (Direct access authorization] group corresponds to high voltage (+3, 4V), while they themselves are at a low level 8~) in the passive state, which corresponds - to a logic zero. The signals of the lines of the first group also terminate on the ends of the matching resistor dividers (see Figure 2.12, b). The resistor parameters are the - same as those of the lines of the third group. A schematic diagram of realizing the lines of the third group of the OSh [Common bus] is shown in Fiqure 2.12, a. The parameters of the matching resistors are the following: nl = 150 ohms + 2 per- ~ cent and R2 = 300 ohms + 7. percent. The output of the resistors is 0.25 watts each. The lines of the second group have one each matching resistor of 300 ohms + 2 per- cent (0.25 W) on the ends, connected in parallel to a 0.001 uF capacitor to voltage of +5 V. 46 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300104438-6 FOR OFN I~'IAI. USE ONLY The ASP [Fower sui:~ ly emerqency] (ACLO) and AIP [Power source emergency] (DCLO) - signals should maintain the correspondinq lines at the low level + 0.8 V) sven if the voltage in the device signallinq the loss of power supply completely disappears. The presence of matching dividers on the resistors on both ends and a certain num- ber of load units (up to 20 pairs of IST [Source] and PRM [?:eceiver] distributed along these line s, is typical for the lines of the third group (see Table 2.4). Arrangement of the PST and PAM along the lines can be arbitrary (cluster, uniform or mixed), dete rmined by the configuration of the system. The outer IST and P?2M can be arranyed behind the matching divider on resistors at a distance of not more than 60 cm. If the divider is located at the end of the line, no special recruire- ments are placed on the minimu.-n distance between the matching divider and the IST or PRM. The length of the lead connecting the IST or PRI~i to the bus line and exe- ~ cuted by printed circuit or a twisted pair should not exceed 60 cm. In this case the total capac itance cvhich shunts the line should not exceed 30 pF. All the matching resistors (with the exception of the resistors of qroup 1) are structurally ass em:~lPd on a printed circuit card, called a common bus choke (ZOSh). The ZOSh dividers are powered from the sources of. the devices in which they are installed. The RP and RPD lines of group 1 d~ not always nass from one physical end of the OSh to the other (the source is the processor arbitrator). Any of the lines of this group can be int errupted in each device located at a given level of priority on the OSh and propagat ion of an RP or RPD signal along it may proceed furtr~er if the given device is not a reguest source. Since the signals on the RP and F2PD lines are relayed in d evices having their oum power supply sources of +5 V, variation of the voltage of +5 V(within permissible limits) on the ZOSh resistors in no ~aay af- fects the state of the equilibrium levels on these lines. � To measure the equilibrium level of the voltage or to follo~v the shape or front of the pulse on th e RP and RPD lines, a check must be made at the specific points of interest of the nSh directly on the devices. Interface amplifiers specially desiqned for mainline transmission (sources--IST) and reception (r eceiverc--PRtd) of information are used to connect the devices to _ the "Common bus" lines. IS [Integrated circuits] of. series K559: K559 IP1--four - mainline transmi tters, K559 IP2--four mainline receivers and 1C559 IP3--four re- ceivers and four transmitters with common control, are used as the interface ampli- fiers in devices of the SM3 and Srt4 UVK. Integrated circuits with electrical and time parameters presented in Table 2.5 are used as the standard signal receivers from the "Common bus" which meet common requirements. Integrated circuits with electrical and time parameters no worse than those given in Table 2.6 ar e used as standard sources which meet the requirements of signal transfer through the "Common bus." The total value of the maximum output current of the loqic one for the source ~Ilvykh - 120 uA) and the maximum input current of the logic one for the receiver ~I kh 200 uA) connected to a line equal to 320 uA with capacitive lo~d not ex- ceed~ing 30 pF is taken as the load unit for direct current for a"Common bus" line. ~7 ~ FOR OFFICIAL i1SE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY 1 ~ ~ ~ ~ ~ (d N (d - ~ ~ O ~ O 9 a ~ . N ~ w ~ ~ ~ O id ~ ~ ~ ~ > ~ b~ ~ ~ ~ C N ~ tr+~ ~ ~ o a ~ o v~i ~ vai �b~ ~ 3 ~ 1~3 ~~~w~ . i U v U 0 3 H~ N i ~ ; ~ ~ v~ o o ~n ~n ~r o ~n o ~ o 0 . r1 N 1 N O O 00 M M ~ ri 1~ N ~ f~' L~. ~ ~ ~ 1d fd ~ ~ ~ I ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ a ~ a~ o~ aNi o a~'i v o 0 b w ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ u~i ~ � .u ~ ~ o I z� z� z 2 ~ z z� ~ z� z� i ~n ' ~ ~ ~ ~ ~ , - ~ ~ , , ~ ~ ~ ~ ~ ~ ~ ~ x ~ x ~ ~ S-1 U U O ~ ?G ~r ,!C ~ U U rtf ~ 3 .~e ~ D ~ 1~ a �a o ~ x ~ ~ o ~ o j'�i ~ N~ (3J1 ~ rl~ H D ] H ~ 1311 U31 _ ~ ~ S-I ~i N ~ O N ~ Gl 3.i C,' C. . ~ 4~-1 ~ 4~-+ N ~ ~ O N 0 N W Ri y.~ ~.-1 ~ rl O N U U U U ~ ~ tfl Cs U b~ U U �'i �.~I �rl N ~ . ~ ~d �rl r0 tT �r1 tT b~ b~ b~ E ~ N ~ ~ tT ~ tT b~ O O O O rl 0 O O .-1 r1 '-1 r-1 .~.t cn ~ ~v ~.�u w w o 0 0 o bz ~z a ' ~ ~ ~ ~ o ~ � � m a~ a~i i~ a~i ~ o~� o a~ cr rr ~ a z~ ~s b: I N.-1 S: ~ ~ ~ ~ t0 N Gl 'C! N N r-1 7 f!] N ~1 ~ ~ ~ 3d ~1 ~i N C ri - I f-1 Ny..~ r-1 S~ S-1 O 0 ~ ~ O O 0 ~ ~ 0 U U > D U U t~tl ~ ~ ~ ~ ro w b o I rr a~ a w w w wo a ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~w H 4a H 4..i H H O O O O W O a+ O M a~i .~�.i ~ cv c~ ~r ~n ~o r m rn o ,R H ~ ~ w z o 48 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02108: CIA-RDP82-00850R000300100038-6 ~ FOR OFFiCIAL USE ONLY - ~ _ . - o ~ b~ i ~ ~ ~ ~ ~ ~ s~ o Uf a.1 N r'~1 U ~ b ~ ~ O tr~ 3 ~ V p b ~ G~~i ~ A~ ~ ~ 3 O D ~ O 4~-i a~-1 ~ ~ ; U I ~ 3 3 0 ~ ~ c~i i o co o ~ ~n co o ~ ~ 41 S~1 ~ N O ~ ~I ch O r-1 ~ ~ ~ ~ - 41 ~�I ~ C i". ~ C f." C�. G". q j b v b ro ro ~ ro b b m ro ro ~ ~ ~ x ~ x ~ ~ ~ ~ x ~ b ~ ~ ~ ~ ~ ~ ~ ~ - ~ ~ rt u, a~ a, a~ cn a, a~ m al ~ ~ ~ a I v, s~ ~ 3~ N s~ 1~ cn i~ . ~ t6 N O 0 O ~ O O v 0 ~ ~ v~i b O ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ N ~i ~1 ~ ~1 ~-1 ~ ~ ~ ~ ' ~ 4-i 0 O 0 O O O O 0 0 ( ~ o z z z z z z z z z ~ ~ = N l o - A ~ ~ ~ ~ ~ ~ ~ I ~ ~ D r~C ~ ` a x x ~ x ~ ~ ~ - ~ ~ ~ ` ~ o~ ~ o~ a ~ 3 S ~ - ~ ~ I~ H H ~ O H O N UI ~ ~ N 1~-i ~ 3a ~ N ~ N ~ ~ O ~O I O N p N ~ N O N ~ ~ N N ~ U U U U �ri ~ �r1 �rl 41 N ~ ~ 1~ �ri �.I �.~I �ri (T O~ b~ (T ~ ~ O - N N tT tT tT b~ O O O 0 �~i ~-I ~ 0 O 0 O ~-I ~ ~-I r-I +i N H ~ w w w o 0 0 o ro b cn ~ w o 0 0 o a~ a ~ ~ z ~ z ~ . ro ~ a~i a~i ~ ~ ~ ~ ~ s~ a~ b~ I ( ~--I ~ ~ ~ O O ~ ~ ~ ~ ~ N I I ~ ~ ~ ~ U U N ~ .-I N I ~ ~ 1) ~ ~ ~ ~ (~d .-1 td ~ ~1 ~ ~ a ~ a a w a a+~ a s~ o ~ a a a a o o w ~u H H H H o 0 0 o a o a o o w J ~ ~ o U ~ i 41 .-1 N r1 d' u1 t~ l~ OD d1 O ~ H ~-1 I ~ ~ o I z ? - - - ? 49 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007102/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY ~ ~ A diagram of the load unit is shown in Figure 2.13. //uHUA o6u.terl muNai , ~1 ~ ' ~ ~ ~Qx. RPM +~Qax. uC7 Ncr.(2> nPM Figure 2.13. Diagram of Load Unit on OSh Key: 1. Common bus line 3. Receiver ` 2. Source Requirements on the main cable. The communications mainline which connects the de- vices to the system consists of a combination of series-connected segments of flat multiconductor cable and groups of wiring joints directly on the general wiring ~ panels of the bloc}:s and devices. The cable has printed cir.cuit pieces on the ends designed for installation in a standard interface disconnect and connects the contacts of the piec es of the same type. - Cable of different lenqth--0.6, 1.0, 1.5, 2.5, 3.3, S.0 and 8.3 meters--is used as a function of the location of the devices. When additional devices are connected, one should take into account that the total length of the mair. communications line should not exceed 15.0 meters (without using interface expander devices). Flat cable which m~ets the following requirements is suitable for realizati~n of the "Common bus": wave impedance should be 100 + 20/10 ohms, the signal propaga- tion delay time should not be more than 5.2 ns per meter and electr ic resistivity of each siqnal and shielding (ground)conductor should not Y~ more than 0.4 ohms per meter. The signal conductors should alternate in the cable wi~h the ground conductors to _ shield the signal conductors against crosstalk. The interface disconnect. A tvro-r~w disconnect of the. "Socket ~3.094.01.30.21" tlrae (TU-77/801-805/265) is used to install the printed circuit vieces of the "Com- - mon bus" cable in SD1-3 and SM-4 complexes. The Unitra-Eltra Company of the Polish ~ Peoples Republic is the manufacturer. The designation of the disconnect contacts in application to the "Comm~n bus" is presented in Table 2.7. The maximum permissible cable length (for all transmission lines) with regard to _ the permissible length of the leads from the lines to the source and receiver has ~ been established at 15.0 meters. This length was selected with re gard to the pa- rameters of the main amplifiers and realization of the main line by an exceptional- _ ly flat cable with parameters indicated above. 50 FOR OFFICIAL USE O1vILY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007102/48: CIA-RDP82-00850R000300144438-6 FOR OFFICIAL USE ONLY Table 2.7. Structure of "Common Bus" Disconnect , ~~~Obosn:+sen~e er;rx~aa . (1) Howep xoNt~K- 06o3uaqexrecnrn~aa . . - Ita x� cropoxe ~ ~ _ � . . paeroeMa~~ ~,Y~~QYCCKOY na ~xranqcro~ x~ pyce~coy H~ lHI'Aq0CY0Y ~ j: % 99hIK! ~2~ ~ L7HKQ ,t:~ b/~~ 7~tlKt . Y7W1f! Y ~ s- - 3~ 4 a s~ ~ . fINTAHNE-f-~~ POW~R~-5B 1 _ 1 fINTAHHE-}-9B ROWER-I-SB - ~ ~ PE3EPB (P)(6 ESERVE (R) 2 2. PE3EPB (P) F~ESEKVE (R~ : 3EMlIR (7~ GROU~ID 3 ~ 3EM.RSI ~GROUND OW ~ IIP P~ USINTR L' ' 4 .4 -OW IIOA~O BUS IN1? L ~ 3~MJIS1 (7) ~ROUND 5 5 ~EMASI ^vROUND -OW ,q00 (g) BUS DOOL 6 ~ 8-G'.II ,I~O1 (a) BUS DO1 L ,-OW ,q02 BUS D002 L 7 "-OW Zj03 BUS D03 L -OW A04 EiUS D04 L' 8 8-OW AOS BUS D05 L ~ -OW A06 BUS D06 L 9 9-Olli J~07 BUS D07 L 3EMJIA(7) GROUND ~ 10~ 10 9EMIISI~ GROUND -OW 1~08 BUS D08 L 11 I l -OllI ,II09 BUS D09 L - -0W ,q10 QUS D10L 12 12 -OW ,Q11 BUS b11L �-OW 1~112 BUS D12 L 13 13 -OIII A13 BUS D13 L -OLtI jjl4 OUS D14 L 14 14 -Oi(1 ~lb BUS A16 L�' 3EMJISI GROUND 18 15 3EMIISI GROUND -OW KO ~lp ~ BUS PAL 16 16 -OW K1~21 ~ BUS PBL -GllI TIB6 ~11 BUS SACKL 17 17 -OW 3AH (22 RUS BBSYL 3EMJiSI (;ROUND 18 18 3EMJI5~ GROUND OW Prl,q 12~ L~US NPG(IN)H . 19 19 Oll! PfI,q(12) BUS iNPG(OUT~H -OllI 3II,C~~1 $US G7(IN)H ,21 21 nIII PI77(1~ BUSE BG?(OUTjH ~ - OIlI PfI7 ~ ~ - PE3EPE3 ~F~" (~ESERVE (R ~ 22 -OW 3117~1 ~ BUS BR7 L OIi! PI16 ~ 8US BG6(1N;H 23 23 OW PII6 BUS BG6(OUT)H -OW 3n8(15) Bt~S BR6L 24 24 PE3EPB (PJ RF~ERVE (R) W I~IIS IiUS BG5(IN)H 25 25 OW P1I5 BUS BG5(OUT)H PE3EPB (p) RESERVE(R) ~6 26 OW 3IIS BUS BRSL OW PII4 ' BUSBG4(IN)H ' 27 27 OW PII4' I3US BG4(OVT1H --OIII 3II4 DUS BR4 L ~~�-R PE3EPB (PY ESERVE (Rl -OIII ACT[ (1 ~iUS ACLO L ~ Zy 29 --Olli AI~III ~23 US DCLOL ' -OL1I A00 ~17 ~ BUS A00 L 31 31 -OllI A01 US A01 L . -OtI1 A02 BUS A02 L ~'2 32 -OiII A03 BUS A03 L -OW A04. DUS A04 L 33 33 -OllI A05 , BU9 A05 L - -OIII A06 BUS A06 L~ 34 34 -Olli A07 OUS A07 -OW A08 BUS A08 L 35 35 -OllI A09 BU$ A09 L -OIII A10~ BUS A10 L 36 36 -OllI Al l ~ BUS Al l L -C:ll A12 nVLiS A12 b 37 3T -OW Al3 BUS A13 L -~LII A14 BUS A14 L 38 38 -Ol[I A15 BUS A15 L -OllI A16 . BUS A16 L 3y 39 -OllI A17 BUS A17 L PE3EPB (P) RESERVE R - 40 40 PH3EPB (Pj RESERVE (R PE3EPB (P) RESERVE~R~ 41 41 PE3EPB (P RESERVE (R PE3EPB (P) RESERVE(R~ 42 42 PE3EPB (P~ RESERVE (R -OLII YO (12) 4US COL �43 93 -Oili Y1 ~24~ BUS CI L 3EMJISI GROUirD 44 44 3EMJISi GROUND -OW CX3(1Q BUSMSYNL 45 45 -OI1I C}CIi(25 s~!S SSYNL ~ 3EMJlA GROUND 46 46 3EMJ1Si GROUND IP1:3EPB (PXS RESERVE(Rj 47 47 PE3EPB (P) RESERVE (R~ ~I7~:TAH~iE+58 POWER-}-5B 48 48 IINTAHHE-}-5B POWER-}-5B Note. The Latin letters "a" and "b" denote the series of _�~ntacts on the socket, while the numbers "100" and "200" denote the corresponding sides of the printed circuit pieces of the bus cables or interface cards installed in these sockets. Key : 1. Notation o` signal 3. In English language 2. In Russian lai,g~=g~ 4. Number of contact on side of disconnect [Key con~tinue~. nn following page] ~ 51 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY [KPy continued from preceding page] - 5. Power + 5V 16. Power system Emergency hus _ 6. Reserve (R) 17. Common bus A 7. Ground 18. Control bus 0 8. Common bus interrupt 19. Dispatcher synchronization bus 9. Common bus D 20. Preparation bus 10. Operating code bus 21. Checking bus K1 11. Selection confirmation bus 22. Engaged bus 12. Direct access authorization bus 23. Power source emergency bus 13. Direct access request bus 24. Operation control bus 14. Tz�ansfer authorization bus 25. ~xecutor synchronization bus 15. Transfer request bus _ The load capacity of the hus is limited to a maximum of 20 load units. This limit was established on the basis of the condition for providing an adequate noise re- serve at.the given source and receiver parameters. Means of expanding the interface capabilities. It is recommended that a special device--a signal relay (one or several), called an interface expander OSh SM EVI~t - (RIF S:~i)--be used when it is required to transmit signals over interface lines hy a distance exceeding the maximum permissible length of 15.0 meters or to increase the - load units above 20. Each of these devices loads the main segment of the bus with a single load unit, but provides the capability of additional connection o� up to _ 19 load units and a lenc~th up to 15.0 meters. The RIF SM can be used every 15.0 meters or less. Zt divides the entire main communications line of the complex into a number of independent segments (sections) with identical capabilities. The use of an expander circuit doi:s not affect the operating algorithm of the interface, but introduces an additional delay (not more than 350 nanoseconds per RIF) during - propagation of signals over series-connected segments of the bus. _ Each additional section of the bus should beqin and end with matching dividers on the resisters (located on the ZOSh), the eauivalent resistance of N~hich is equal to the wave impedance of tr.e interface cable. - Chapter 5. DFSIGI`1 OF Ct~t1TROL CC~NiPUTER COMPLEXES 5.1. Classification of Complexes _ SM-3 and SM-4 com~lexes are hardware complexes (KTS) of the Sr4 EVM11 with "Common bus" interface, the confiquration and software of which are determined by SM-3P and SM-4P processors. These complexes are program-compatihle "from bottom to top" and have a unified nomenclature of external devices. SM-3 and SP4-4 complexes are con- ditionally divided into basic, specific, standard and prohlem-oriented as a function _ of the makeup, consideration of user re quirements and so on. Basic complexes arF, hardware and standard software complexes of specific composi- tion (fixed, determined by specifications) designed for use as the computer nucleus 52 - ~'OR OE FTCIAL USE ONLY - APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 I~OR OFFICIA[. USE ONI.Y ~ ~ a~ ~ ~ ~ _ u~ ~ a ~ ~ ~ ~ a ca ~a a e�Ga ~ tT N e, ~ o Ol j4 - - ~ t~ f^ U O ~~C ~ R. " a "q ~ L( `r r~ G~ c~i ~ v'm Q E ~ ~ U G C F W GV W N C S-I L+ " ~ ? ~ � ~ ~ ~ :r d U ti a ...m tn O 1~1 U'' � a f ~ V ~ O` u o j4 �f c ~ x Mo ~ b'~ N N.k ~ o~, ~a �r' ~ r ~aQ ~ ~ rt ~II s x .u 1~ ~2 rt3 v' v UU~~~ ~ ~ c~ W ~ W ~ ~ a~ ttl Ul M 1-I S-~ U ~ ^a o o~ v~ m o~o ~ cu b~ a~ fZ ~ C., tn `n V -1 U �C r~ ~ `o ~ u a, a � m o a~i .a x a~i c.~ ~ 1~ C~ .4 U~ o vO },{~'^J N ~ O~ X U ~ dCS v N ~ V 0~1 ~~7 C O -V L. C O t~ W N>+ C G W M ~ t0 ~'i A. L~ I-I N Q~ N ~ ~C C ~.J Qi �r~-I �rl ~ ~ O p, ~ O ~O Q,~ ~ ~U ~ P'J t t. ~ U G d t0 -0 C/ f~l O�{-) ~ ~ ~ ~ 1 cp ~ C N Y U p U U~ ~ 4: rl rl ~1 _ a U U.t. .r~ ~ ~ m v LLI x 4] oo Q R ~j ~.~I ~ N~+ ~ s ^ ' ~ . oA -1- a Q rz x m o ~ p~ s ^o o.a cn a ae o~c ~ ~ ~ d~in r~ c o~ u a~ v~ m ' x a~i i-.. ~ . . . . - v "O � ~ = a ~ c; c- o m , m ~ ~a u a p x ~ ~C 1~ ~ d1 ~ 3 9 cD o0 oc~x~ s o ud cc ~ VU~- N O ~ O uW - F-~ S~. ~ N t'.g' C ~i _ �r'~ ~-1 5 ' CA ~ ~ Q1 ~ ~ " ~.4 0 ~ v ~ ~ v ~ ~1 ~ m c ~ 'D ~ ~ ~ u mt 'o $ e� ~u d 'L7 r. L X U ~ ~ ^ ~o,o ^ x ~ o ^`t) .r, (J O~ c~ � v p y a V o v~ M v ~ o~�G t- H a ~ v w d ~~o ~ ~ _ . _ U N ~ m u ~ ~;u8 N ~ ~ N ~ r z a ~ I~ ~ N _ b �v S U S.~ . ^G ~ �~I tT Ti ~7 ~ ~n lUV V c� y~ , M~O~., R1 ~ N~ 1~ ~ d U o = ~ ~ ao a o Y I ,~`v' c~d t+~d tn N N ~ ~ U.~.C ao O~, u Z Z_ 4 s~ �a tn tn - A -~--tff--- ~ u1 � U 4-+ N+~ ~ t~ N rd a~ ^ o~ o aroma a ~ { ^ v~ M e a v ~ v O O~1 '�-I b~ c~ r, N ~ N ~v 11 ~ ~ ~q ~ ~ ~ v ~ . s ~ ~ U 4-1 R~ ~ N ~ r m _ " v~ C: U C oo c~i O�c m u x ~ ~I m a ~ O 0~~ ~S ~ N tn N td p, ~ O v F., a~i E:. ' a 3~ �J ~ ~ N U N Sa O~I ~--1 , a x ce ~ ~ f� af M~ O ~ O N CP ~-i m ~ s = o~ a a a a, tr o 0 ~ d , ~ ~ ~ � ~ G ~ s ~ ~ ~ =r, ~n s~ o ~ ~ ~ ~o a~ -R _ ~ ~ o ~ � T a ~ M~ ~ ~r`~i w a~ ~ c: H = u cr . F_ v c N 75 o a o .,.~i ~ c~... ~ rl ~ ~ - s o v ~'z ~o .a o ~ N N~' ~,x C p a , rtf ~ 1 1~ 0 N _ `f.. A K m t~a m z(V 'CS p 7S y~C �rl 3~1 N r-I N rl '.3' ~-~-1 x s� o~ d/� z m~ s~*,. ~-s y x o x 3 rtf ~ rtf & ro ~ v 4y ~ F- p" O`~ m O ~ Q 7~ O OC ~~D O S'Z' ,L~' ~~�r~ �rl K ? os~ c~T~ aaic~f.r~x ~c~au+[ ~o.~o,~x : ~ U C7 L~ E+ L] ~ E-s � x~ ox~ oxW ro Z�'T ~ ~.x o~' r�1-OC O U ic r-I N M cp u1 ~ N ~4 u 53 - FOR OFFICiAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY [Key continued from nreceding P~9el 10. Real-time di~l~: operating system 25. Presence of multipgroram 11. Real-time o;~erating system 26. No 12. P~?ultiterminal time-:~haring 27. Yes dialogue operatin~ system 28. Number of simultansously executed - 13. Time-sharing disk operatinq routines system 29. 127 + 1 bacY.ground 14. Type of UVK 30. 1 operational + 1 backgr~und. 15. SM-3 31. 250 priority levels 16. SM-4 32. Presence of rP~note processing 17. System carrier facilities 18. Punch tape 33. Number of connected terminals 19. Piagnetic disc 34. Programming languages 20. ^linimum internal storage 35. Dialogue languaqe of dialogue caFacity, K wnrds system - 21. Maximum intPrnal storage 36. Assembler capacity, K words 37. Macroasspmbler and Fortran-IV 22. Servicing capability 38. DIAMS dialogue lanquage 23. Single-iise.r 39. Basic-plus 24. Niultiuser in design of information, measurinq, control and computer complexes of different comnosition and designation. Specific complexes are qeneral-purpose comolexes whose composition is determined by the customer's specifics accordi.ng to the coordinated technical assignment. The - composition of the delivered equipment usually includes a basic or standard complex supplemented by the necessary ecruipment from the KTG nomenclature of the SM EVt~ f,~evices, blocks an~~ modules). A specified complex is supplied with standard soft- ware an3 minimum gt~neral systems documentation developed by the manufacturing plant or user with the consultative assistance of the manufacturinq Plant. The complex - has no delivery sper.ifications and therefore the Manufacturinq plant (sup~lier) con- ducts no additional tests of the specified complex in assemblec3 form. All individual cievices and units ~re chec}:ed for conformity to specifications at the manufacturinq - plants; the given oneratinq system is crenerated to the corres.pondinq configuration of the complex by ti:e suppliPr. All the specifications included in the specified com~lex (addi~:ional devices, structural components, cables and so on) are nomenclature articles with a confirmed _ price. The sellinq price of a soecified complex is determined by agreement for de- livery by the total pricPS of the constituent parts. Standard complexes (standar~i specified complexes--TSK) occupy an intermediate posi- tion ~etween the basic and specified complexes. Documentation for them is worked out by the head ~rqani::ati.on for computer technoloqy and the manufacturer to sim- plify ordering and ~i~velopment of specified complexes by customer orders. The functional capabilities of TSI~ are considerahly wider than those o� basic complexes anci it is simpler to construct specified complexes for speci�ic applications on their hasis. - 54 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY n typical sj~ecifi~~l comr,lr.x, in ac~~iition to the selecte~7 basir_ cor~plex, incltt~ies cievicc~s, modules, dispatcflers and bavs. For examPle, interface matchinc~ Modules for connection of communications devices with the ohject are from cP4-1 ancl SP^.-2 nomenclature (USS ~Sh/2Y,) or for c~mmunicati.~ns with machines of series Ye5 ~~'~9 (USVP4) , Li~O bays ~~~i th varia.nts of sets of modules for desiqn o� c~ntrol complexes , common bus sk~itch (PSh) c]evices; interpracessor communications ad~pters (~1Mc) f~r creation of multiprocessor complexes and complexes with variable structure for sys- tems of enhanced viability and productivity, remote communications adapters (BS ADS) for rer.~ote processing complexes and so on. TSK are divided into standard specified computer complexes (TS VY.), standard speci- _ fied control computer complexes (TS UVK), standard specified nonprocessor complPxes or standard subcomplexes (parts of complexes) and standard bays (TSS) as a function of the composition of the hardware and standard software. The main ch~racteristics o� ~tandard specified complexes are presented in Tahle 5.1. Pirferent conf.igurztions of standard specified complexes base~3 on the Sbi-3 and SD~-4 are illustrated by Fiqures 5.1-5.3: remote processing TS VK with four remote terminals cvhich inclu~ies tcti-o r,iagnetic tape stores and two maqnetic disk stores fFigt.ire 5.1), TS U~'Y�. 1J~11C}1 utilizFS object communications devices with 2K interface con~iected through U~S OSti/2K communications-matching devices (Figure 5. 2) and TS ~VK which utili~es object communications devices (WA and UVD) with OSh inter- face (Figur.e 5.3). Problem-oriented complexFS of the SM EVM (POK SM EVr4) are sets of hardware, soft- ~ u~are, methodical, ~~lanninq an~3 organizing solutions on realization of a aiven set of problems of automation of a specific class of objects combined by a common in- formation nrocessing technology and unanimity of information processing modes and operating conditions. . NMQ NM11 NM/7 NM/! . N.'OI NJOr N30T N30T 1J7~ fJ70 5004 5004 ~1~ . - ~1lrale~rn OJy OJy N~~Nrd ~2 ~ -1'vN~NK~ ( 3 ~ CH-7704 CM�JJO? CN�3107 ~y 540T C~b-5.701 , ~ 0!U - , � 1 yBB /1 ~ yBA!{q.Y y(I:~ CN pytp-C~1 6C 17~fC 6C FAC 6C R,QC CH-61J? Crf-63U3 t'H-7105 ~a~ ~ "f !p. ~~~+n,~ Iep,yuNan ~ IepnuNOn ~'r-340 Bi-340 ~ BI-340 /tpnuNOn TepMUNan BT-3ti~~ BT-340 FiQure 5.1. ~tan~:3ard Specified r4ultiterminal Comnlex of SP4-4 Y.ey : 1. Frocessor 3. N*?L monitor 2. Nr~lD monitc~r 4. ?'erminal 55 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY Table 5.1. `~h NOCN� (L~ ~ OCHOBHEA I~P21(7BpMCTNHH ~ tldx pAY ' ~!NlPBIIHN . nporp~N. d9 0(~. MNUJ cpepcTe o o ~ ' W :m ~ ~1 ~ ~ 15 (1) Yc~oeuoe ~2 ~ 8 a �~H ~ 3 1 0 1~ U(0 ~i1841�UNQ UCHOOHU! I/Y3i184lHH! a al u q a+ = K u = NO>IfI.IC~C2 Y S I u 7I = a S~ ~ x ' ~ f x ~ ~ S u y * b Y * _ . als Qo a q q v~ a, V y a A m O m m m m 0 y a a S a ~ W w W 10 ~O a p= ~ ~ A H= 1~= r 5 (y Y O h q a (5 (6(7 = = o= o= ~ = o:. � a+ C + �F c:~~1�3~U7 TCI( paciu~~peuFimii � uGutcro ua3ue~ierinsi (uapuaurriWSi)~43~ + X ~:i~l�3-07.U1 X + + + + X + �F C,til�3 07.0'? ' X + + + + I X + + [Table continued on following pageJ 56 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 ~OR OFFICIAL USE ONLY Table 5.1. [Continued from preceding page] 06Q860TKN HH~OQN8llI1H OIIlQl4NOHH8Y CHC7lYt ~2L~ ~ I ( 4 pe~ i ~ noad. - ~ wexxoA 2~ ' lt~~~�o xeae~c� ~ ~ ~ ~ f10CTN O } _ ~ S p a ~.JS~ ~ d'� 21 (2 E ol 5 ~ Tipw+evanna y a a S V V Q tR ~ a a m s sa s V q ~ ~ q a�0. or 3~ 2~ 2El , 31 a o ~4~ a A~ s�~4 s z ~ o, oa v 3~ v m v a ~ o � a~ ~ s o' U V~ c`' p p~ ~ < ; o `o u~ a,3 O ~ ~ U m p' < U() U m ' = e^, �o _ �x S K O O O U S O O O 4 S = a c a m s C G ~ A O q ~i cl q l5 lh I7 18 l9 20 21 Y2 23 24 2b 26 27 2i 29 30 31 ` 2sK ~4 a~ nn, H~aA (2,4 M6a~r) + + X + X X Aoe croi~hEt (45 ) O~na croiiKa ~4~~ 16K cnoe, [TJl, F iM~i (2,4 M6atir). onua - � I-- � Y. + X X - croi~Ka (471 - ~ ~sK ~noo, nn, oAna + x - ---cTOi~xa (dR) , 8K csoe, CIJI, oAHa - � - croiiKa (4~) s2K ~?oe ~2sK>, nn, � � KHMn ~2X + x XI00. K6aAT) ~50) + X 16K cnoe (~1) 2sx cnoe, rtiM.q + (2X250 K6a~ir) (5?) -I-- + X + RJI, KHMJI (53) + + x ~ + + + x + Her yBBnn cs4~ . , 28K cnoe, HM,q ~ 55 ) ' (2X2,4 M6afir), + X + X HMJ] (2X20 M6ai+T), AL117Y. PA + it X t X + + + X X t X t+ ' [Table continued on follou~ing page] 57 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY Table 5.1. (Continued from preceding page] I TNn ~weN- Utuonn~n %lPBKTGQHC7HK8 TlJIY 4AN PlMtP~IINH nporpaw- , NPI~ � O O ~ epeacre = _ ~ R a ~a y - I A ae m n L y I q Q Ycioetioe a a~ c ~ Y ~ o6o~ue~~eNHe ~CN08H0t H6311~4CIIUt L 4� ~ ~ u-. x + s iv a = a s m ruMnae~cca $ ~ ~ � < q = ~ _ � : � a ~ 4 u o 10 ~ P. ~ G ~ ~ 2 = x ^ o' S 2 m a m m x ~ W ~ ~ ~ w w m v o ~ 2 v~ a q M~ Y S M Y G V O h~ b = S Z p S a0 , ~5., ~Y ~ V ~m O s O O ~ F ~ e 7 w S q y a~ . m- O _ _ a ~ Y P4 GL GR S q A a~! 5 a0 C'p C G G I a+ V = b C ~ E C Om Om OS m e OS O ~ q 4 5 ti 1 tl 9 10 Il 12 1:f 14 CM-:3-OS TCK c YCO-QW + + x+ � ~ (56) CM-3~08.01 x + + x + + _ _ X + _ _ CM�3�U8A'l ~c + + x + + _ X + _ C~~t-3~09 TCK c YCO�2K (ua- pnnuTUi,~ii) ~57~ + + X + CA1-3�09.O1 + + + t _ X + Ch1-3�09.02 + * t + x + _ CP1�3�0~~.03 + t + + X + ~ CA1-3�10 TCK (58~+~iororep~+~i- I - uan~nn~ti c reneu6Pa~ - - - Guri > + + + + + + + + (Table continued on following page] 58 FOR OFF[C[AL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR UFFICIAL USE ONLY , Table 5.1. [Continued from preceding page] ObQ3C0iKN NH~UpNlLLNH Oqep~uxoMHe� CnCLEYQ , ` ' I ~ plIICHM � noem� Y W ain01 - O M8IIC71C- ~ . , A HOCTM H a o . s = c b IIpxLevuu~a 0 * v; A ~ ~ a+ a - ~ ' o ~ u d 0' Q a ~j A = =a. = U ~ . ~ _ n n ~ x s - = o w o~, z a m a ~ T " S c o m ~i a c. "o a R ~ o. m V m V a �m n m u m s s U U 4' p ~ a -1- 4' � o o a y o O O D U ~G" a 6 U U:J o o,o o � o r ~ O O O U S O O 7 4 i a? a a i C C c( q 6 O ~I ~S ~1 , li lb l7 1.~ l9 _U 2l 22 23 24 25 26 27 YS 2y �0 + X 28K � cn~e 1~ H11~i,q - (2X2,4 hl6aiir), FI~1J1 - (2X20 M6aiiT), IIJI, t + x x X + + X - - (62) - - - - - - - - - - - - - BBPItclITfIOCTb YCO + ~ -f X :C X + + X --r - - - 28K cnoa~63~I,~tA i-I- - - - + X ` (2X2,4 M6aur), I1~1J1 (2X 100 M6aiir), lIJI r X X~C X 1.lse croiitcu YCO 64 i ~ r X:c X++ X OuHa croiitca YCO_~ + ~ X X X++ X + OAtta cTOt'iKa YCO -I- - , YB6-100 (66) 28K cnoo,(63)?~~'L~. _ - I ---I- - - - - - - - - - (2X2,4 M6aiiT), H~ti1Jl x+ ~lx ioo nsaar~T~, nn -i---i-- [3oceH~ yAaneiui~x - _I _ _ _ - _ _ _ Tepa~nHa.70D ~Fi7 ~ ~ - - - - - - 4ermpc y~a.~ciiuwx - ~ reps+i+Eiana (68 ) , + - - .t.~ - - + X - - 28K cnos, ~ HT1A (2X`l,4 M6aiir), HDiJ1 ~ (1X20 M6ai+r), f1JI, ~ rxM,q, AU,llY, 3I7[', ~ Ch1 (6~) ~ I + - - - + X x - - 28K cnoe, f]JI, HM,q , (2,4 M~aiirj, Aee ' CTOHKN ~70~ F - - - - - - - + X + X - - - - 32K cnoe, I7JI, HAt,q (2X2,4 ~16ai+r), Ase CTOf1KI1 ~71~ [Table continued on following page] 59 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 - FOR OFFIC[AL USE ONLY � Table 5.1. [Continued from preceding page) . , . ' � TH~ HOCH- OCHOBH~Y XlDOIftYQNC[NKS . T0.1Y IlAR reeepauen nporpaw- e, ?~xdx o � ~ . cpe ~cre ~ 9 ~ A d S q d S S W m n ~ ~ ~ = W Q O071o184eMNC OCIlOBMOE Hl3H848NH! d A�' Y K u = ~a = S.u 2 ~ IfONItACKCI ~ o * 3E Y 3E b s * s a~i ~ ~o u o u e d$ a a� c'" ca y b�' ~ `s - � o ma m pM a ~x a ~ ,y e q ~d ~O~ d a e~ 7 q m Y n ~a~. S f= f= 6 d O M~ q Y ~p Y ~ ~ d y I O S R$ N S y V S s1 ~ O r C( G~ Y p,y dY 4L F ti q a~' S ,e .p y ~O 6~O 6 a! Y S~O S e( G i~ c om om oo r m e os o 1 2 I 3 4 5 6 I i B 9 10 11 12 13 14 i CM�4�O'? 6a3oewii c h1J1 06� utcru Fia:~y~v~t{us -i- + + + + + + + + l ) CD1�a�u3 ~ia3onwii c hlJl 06� ' utcro uastia~~euu~ . + + + X + + ~72~ - - C,yl-4�U I 6aaoowi'i Mi~~uiManbno- ro cocraea (73) -F + �I- -H + + Ch1�4�05 TCK c ru6ici~MFi~~11 4) Ch1�4�05.01 + + + X + + + C~~-a-o5.o2 + + + + CM-4-06 TCK c YCO-2K ~75~ X++ + + X* CM�4-06.01 - - - - rM-4-OG.02 CM..~. r;r,.03 CM-4-O7 TCK MuororepHi?� - ~tan~Eiw~ c Teneu6- a6oTKOA AnA Mtioro- d~aw~+t+u~x KuninneK- CUB t CM�4 � 0'1.~ 1 -F -I- -I- -F -F i- -I- CM�4-07.02 + + + + + + + C61�4�07,U3 + + + X -F :C + [Table continued on following page] 60 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY 'I'ak~le 5.1. [Conti.nued from preceding page] o0pebor~~ HH~OPNlLLNN UaeputNOxx~o cxeteu~ , peHtu~ ( . a fIOBN� ` weHiiop ~ IIaDCNC- O HOCTN Y ~ ~ ~ s � ~ o ~ _ ~ _ * s e oa , IIQHYG4~HH0 a~+ na s G o a ~ L YE Q ~ S S a ~ m = _ _ ~ ~ = a u s C( = a m 0. ~ �v A y s u� = x m U m m O a s U V U i0 0 ~ n W o x o U U cL O �1 ~ n' 'C d~ d~ 0 'J U U ~A ~ < U U :J d s i 01ae cm S C C q q 8 O ct a a q IS lo li t`~ l9 2U 2l 22 23 24 25 26 21 48 29 30 31 32K cnoe, IIJ1, HM,ij + + + X + X (2X2,4 M6aHr), HMJI _ _ _ _ _ _ _ _ _ _ _ (20 M6ai+r) 64K cnoe, flJl, HM.Q + + X + X (2X2,4 M6aAT), f(MJI _ _ _ _ _ (20 M6aitr), AL1C1Y ( g ) 32K cnon, 17J1, HM,q + + X + X (2,4 M6a~iT), oA}~a ~ cTOHKa (79) ~ - - - - - - - - , 32K cnos, CHMA _ _ _ _ � (2X250 K6a~Sr) (80) - - --r-------- - + ~ x nn (si) + . - ~ x x x+ s2K cnoB, nn Nax _ . rruvcA (~2> _ _ HMA (2X2~4 M6a~ir) 83) - i{MJI (2X20 M6a~r) 84) ~ KHMA (2X 100 K6atiT), 03Y (85) 64K cnos - (8F) 64K cnoe, CIJI, HM,11 (2X0,4X2~4 M6at+r), ~ HMJI (2X20 M6aNr?, - - - - - - - - - - - - - - - NnH KHMJI (2X + + + + + X X100 K6a~r), qerd- - - - - _ _ _ _ pe - socemb repr~i+- , ! } + + X HanoB, conpAmeuF~e � c EC ~BM + + + X + ~ [Table continued on follotiing page] 61 FOR OF~ICIAL USE ONLY ~ APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FaR OFFICIAL USE ONLY Table 5.1. [Continued from preceding paqe] , Ten NocH- OcxosHeA ztpaerepxeTxK~- teea aaw reeepeuxx I nporpa~� a , � IIMNI ~ " O Y cpeane = _ S S q ~ O b m p~ Y 61 = O _ 6 Yceooifoe I Y Y Y y '.E M 4 = obo~uavenxe Ucn~ouoe Me3xevenae y: s ~ : ~ a s d = Ko,in.~eeca ~~E ~f o k a= 3E = a� a o a~�, o � y a$ c m m~ a o 01 �`i m " ~ . ~ C G ~ !1 ~ Y e~J W i M= F= F S 6 V O 1- 7 q 1+ ~o w .7 4+ r+ d C v ~ y O Q a~ m I O Z u S Y q r a�~ _ - ~ ~ q G 4 ~76 O 6 4 Y N 5'G F 'y C,' ~ ~G C O m O o O O N m b O= O ~ q q 5 6 7 A 9 10 I1 12 l~ 11 CM-4�08 TCK rpa~~ivecK~~~ AnA I ;eEtoroMawu~~Et~x Kon~nneKCOe (87) + X CM-4�08.01 + + + X + + - CM-4-08.02 - CM-4�09 TCK uey~npoueccop- u~t~ pesep~~ipoeaH- ~ ?~r~H c YCO�2K'(88) + + CM-4�09.O1 X + + + + + k + CM-9-09.02 X + + + + + X + Ch1-4�0~.03 ' x +r + + + X + CM-4~09.04 ~ X +r + + + X + CM-4�l0 TCK lieyxnpoueccop- ~im~+ c pe3e e~ipoea- NNCN~C YCO�~W ~8 ~ + - CM�4-10.01 X + + + + X X + CM-4-10.02 X + + ~ + X X + CM�4-10.03 � X +r + + + X X + CM�4-lO.Od +r +r + + X X + - (T~~le continued on following page] 62 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL USE ONLY Table 5.1. [Concluded] - o0peborsN xxi~op~iauxe OnepauxoHNao cHCreMa percxu ' � nouw- ~ x we~~noA � ' M ~ - ~ n.~ae*� � a iocrd Y ~ ~ ~ o = s � g fipxuevawfe ~ ~ a m ~ y - ri o a c d` y~= a ~ ' ' ~ s '?G U ~ a ~ u ~ s i a m~ = U ~ ' T s o a : ~ C( ao 4 ~ e < i s ~ < m V m U a U a 0 o c ~ ~ c= o V V a ~ ~ ~ i o o-`" O ~ U U~o S O~~ x x m g a~ x x O 'J 7 U = s.= ac om s a a e o a a a a i5 Iti li tN IS~ e0 21 23 'G~1 26 28 27 2d 29 80 :il snr cn~ 96K cnoe, I]Jl, I1D1~1 - (9n) - ~-I ' - - + X - + ~2X24 ~~lsariT)~ H,~IJI, A!1C YCBh1 ~171118 (nne uea 9(lf C~1), - 6C AAC (91) � (�2) ~ ~2s (~2a)K ~noo, nn, ------------H~~t1~ (2 ,116aiir)nnE~ + + + + x x + T't-IA11I, HMJI (2X - x'l0 M6aiir) r + X x + NnEt hH~ti1Jl (2X ' - --I---- - XI00 K6ai'iT) - + X x x + Bapiia~+ruocTb YCO _ ~03~ + + + x x x t (94) 32K c,noe, IIJI, IiMA _ - - - - - (2,4 h16ai~T) i+nn + + + x x + rHMA, HMJI (2X _ x20 M6aAT) u~u -r-------------I(HMJI . - + + + x x + (2X100 K6aiir) ~ CBA36 yepes fl W ~95 ~ X X x + Bapt+aaTt~ocTb J'CO I -t + x X ~ (96) Notations: +--used in the main version; X--use in different versions is possible; g--floppy and k--cassette [Key cn following pagel 63 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY [I~ey continued from preceding paqe] 1. Natation of complex ~l. Magnetic tape TSK (cassette, 2. r7ain designation minim�.im composition) 3. Type of carrier for software 42. Floppy magnetic disk TSK (variant) generation 43. Expanded general-purpose TSK 4. Main characteristics of information (variant) processing 44. 28K words, punch tape, magnetic 5. Punch tape disk storag2 (2.4 Dmytes) ' 6. D.agnetic disk 45. Two bays 7. Magnetic tape 46. One bay g, 47. 16K words, punch tape, magnetic 9. Real-ti.me processing disk storage (2.4 Nbytes) one bay 10. High-response real-time processing 48. 16K words, punch tape, one bay 11. Time-sharing processing 49. 8K words, punch tape, one bay 12. Remote data processir._q 50. 32K words (28K), punch tape, 13. Data base management multiple magnetic tape s~-orage - 14. Dialogue mode (2 Y 100 Kbytes) 15. Graphical information processinq 51. 16K words 16. Single-task mode 52. 28K words, floppy magnetic disk 17. Two-tasY, mode storage (2 X 250 Kbytes) 18. Multitask mode 53. Punch tape and multiple magnetic 19. Multiterminal processing tape storage 20. Increased reliability mode 54. No punch tape LTW 21. Processor redundancy 55. 28K words, magnetic disk storage 22. External device redundancy (2 X 2.4 Mbytes), magnetic tape 23. P~tultinachine processing storage (2 X 20 Nmytes), alpha- 24. Operating system numeric printer, arithmetic 25. Paper tape ope.rating system and expander dialogue prograr,iming system 56. TSK with USO 26. Time-sharing paper tape operating 57. TSK with USO-2 K(variant) ~ system 58. Multiterminal remote information - 27. Disk operating system processing TSK 28. Time-sharing di~k operating system 59. Graphical TSK 29. Basic real-time background-operat- 60. Basic disk ing system 61. 28K words, magnetic disk storage 30. Time-sharing operating system (2 X 2.4 Mbytes), magnetic tape 31. Multiterminal time-sharing dialogue storage (2 X 20 NIl~ytes), punch � operating system tape 32. Time-sharing disk operating system 62. USO variant 33. Disk operating system plus remote 63. 28K words, magnetic disk storage data processing system (2 X 2.4 Mbytes), magnetic tape 34. L~isk operating system of automated storage (2 X 100 Mbytes), punch operator's position tape 35. Comments 64. Two USO bays 36. Srt 65. One USO bay 37. General-purpose basic disk (variant) 66. One USO bay and WB-100 38. Minimum composition basic disk 67. Eight remote terminals 39. Minim~n-composition hasic ~isk 68. Four remote terminals 40. Pasic [Key continued on following page] 6L~ ~ EOR OFFICIAL USE ONLY ~ APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOit O~'F[CiAi. USE ONLY F,9. 2�3K words, magnetic di:~c storage 86. 64K words, PL, N~2D (2 X 0.4 X (NMD) {2 X 2.4 Mbytes), magnetic X 2.4 Mbytes), NML (2 Y> 20 Mbytes) tape storage (NM.L) (2 X 20 Nll~ytes), or IINML (2 X 100 Kbytes), 4-8 punch tape (PL), floppy magnetic terminals, integration with YeS disk storage (Gt1Nm), alphanumeric EVM printer (ATsPU), EPG and SM 87. Graphical TSK for multimachine 70. 28K words, PL, NNID (2.4 Mbytes), compiexes two bays 88. ~vo-processor redundant TSK with 71. 32K wr~rds, PL, NNID (2 X 2.4 i~ytes) , USO-2K two bays 89. ~ro-processor redundant TSK with 72. Basic general-purpose magnetic tape USO-OSh 73. Minimum composition ~asic 90. EPGSM, 96K words, PL, r1r~w 74. Floppy magnetic disl: TSK (2 X 2.4 Mhytes), NML and ADS 75. USO-2K TSK 91. USVM A71118 (or two EPG SM), 76. Multiterminal TSK with remote BS ADS processing f.or multimachine 92, - 128 (124;K ;~ords, PL, N1~2D ~ - complexes (2 Mbytes) or GNNII~, D1ML 77. 32K words, PI,, P1MD (2 { 2.4 Mbytes (2 X 20 NU~ytes ) or KNML NML (20 Mbytes) (2 K 100 Kbytes) 78. 64K words, PL, t1NID (2 X 2.4 Mbytes), 93. Variant of USO NML (20 Mbytes ATsPU 94. 32K wor~s, PL, P7MD (2.4 Mbytes ) 79. 32K words, PI:, NP~ID (2.4 Mbytes) , one or GIVMD, NML (2 X 20 Mbytes) or bay IQ~TM.L (2 X 100 Kbytes? 80. 32K words, GrII~~D (2 ?C 250 Kbytes) 95. Communications through PSh S1. Punch tape 96. Variant of tISO . 82. 32K words, FL or GNt~ , 83. NMD (2 X 2.4 !~~ytes ) 84. NML (2 X 20 L'mytes ) 85. KN1rID (2 X l0U Kbytes OZ[1 of 64K words These complexes have the following main features: ' besides standard faciZities of the SM EV!K, complexes, dFVices and software, ~ they include nonstandar~i dFVices, specially developec~ modules of. operating systems, applied routine pncks ancl so on; the complexes are usually developed by the leading systems organization with - participati~n of ~vT developer organizations with reqard to the characteristics of application of thF given complex in a specific set of objects; the composition of the r.arda~are and software of the POK is refined when de- signing a user complex for a specific object on the basis of the POK, generation of the applied proqram packs of the POK, parametric adjustment of the software - modules of the POi~ ~nd so on are fulfilled. A user complex based on n POK is de- ~ signed by its methodical materials. A multiple user c~r.~plex can be designed on the basis of several POK. Examples of POK are ARf~ [Automated operator's position] and NK [Measuring computer complex] _ 65 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 FOR OFFICIAL LJSE ONI,Y NM,Q HM~f NMl1 NM/l NJO/ 137D ~~JOI lJ70 JOt SOa4 u3oT 5004 ~ 1 oN r. ~ 3~ n~oN~n seAUny ~ Opn~rcrz U3!; 03y' 03y D3y NH 2 NH,~ H-: rp.; cM-JrU1 ~`!-JID2 tM-3102 CM-J102 n- cv M- CM-63D5 ~ OiU 0~, 5'~9 n~ yRNq 'JdOCN yC. YCC 'JCC yC :Pf-6102 C~1-e,700 CH-yZCS PN~ ~t~ ~ PHZk OW/7k O!U/Pd GpH2k . p... yco p p... aco ~ ~ ' ~ r ~ ~4~ K o6aeKry Figure 5.2. ~tandard Specified Complex of. SM-4 With CompletP Standard Aays of USC~ IIased on USO SM-1 and SM-2 Modules - - Key : 1. Processor 3. NML monitor - 2. NMD monitor 4. To object HM,Q NM,Q HM/1 HN~1 N30T 1370 N30,T 1370 N30T 5004 N30T 5004 _ 1 ' ~ 2 (3) /IOOueccnp 03y 03y KONT NM,Q yB HL(ry h'OHT NM/1 CM-?!03 CM-3107 CM-3102 ~M-540? CM-6305 CM-5301 ~ ` D JBB !7/1 y~Mn ~JBOCN yBq yBQ ~ ~`~-b'?U.' C~y-6300 CM-7Z05 _ Figure 5.3. ~tanda.r3 SP~cified Complex of SM-3 with i;c0 SP4 EVPt ~ KeX: 1. Processor 3. NML monitor 2. P1t~ID monit~r - - com~lexes (see Chapter 6) . A nonstandard opArating system SOD ARI~1 and applied pc�oqram pa~ks was developed during creation of the A?s; and connection of such non- _ standard devices as semiautomatic graphic:al information input devices, graph plut- _ ters and magnetic tape storage devices to the SM-3 and SM-4 u~as provi~ed. The C1~MAC dispatcher, a number of CAMAC modules, a CAMAC monitor and applied program packets, ASET disp3tcher and IVK-7 and IVK-8 monitor were developed during creation of the POK. IVK. 66 EOR OFFICIAL ~I~E ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 ~ I~OR C~FFICIAL IJSE QNLY ~ ~ Y M S x S q ao m fA ~ ~ ~ S pq ~ G' r ai Q Q ~ ~ ~ �U Q - x w E ~ x ~ w ~ U'~ u ~�o c. a u ~ m N ~ s O q ~p O, .~1 rr 2~ ~ S U S E" O~ UI � _ ~ _ ~ cc s o x ~ ~ !~1 t0 U u~ ^ ~ S~ V O ~ Y 3~ V F N U x mrc v ~ t~u~ ~am O N q x x _ ~ a.. m m`~ ` ~t u cc~~ u ~ u x ~^u ~ u~ p, ~ p~ C m ,Q ~ ifl ~'LJ G R ~`1 ^u ~ ti~ ^i u u�. o ~ a, ~ t- a ~ ~ V'I ro ro f ar~c'- oc'� ~ o,~ r~- �~u~ o u ~ ~ o+~ N v,�, r~ ~ s^ N. ~ u ~ r-I U � ~0 0 a ca 5,~ c~ s o o r o s z a�'i R~ ~ d' RJ _ q d W~ f:.: r, 41 U M in U c~7 ~ U~ ~ N ~ UI ~ T O R3 U 4-1 W c o ,-.`c1 ^c� o V rt N~~ rtf i., .~-I ` N 0~ N X dG R7 ^~oF ~ ~ O~ +'.U 1, ~ N~ ~ _ a ~ ~ ,_'~'j c N 'Q ~2 ~ ~ 4 'Q o ~ ~ i .~R ~ Cr 0a 0 0, ~ri7 q GO q C] CQ ~ s~ ~ ~ N~ ~d 0 0~' U ~~~-I~ U O - [ O~ O O ~ u~7 ~ M . N u n ~ ~ N(l~ ~O 1~ rl 4-i 3 ~ cn ~ ~ RC �ri u~ v b~ I . a. _ ~ z ~n N td ~1 O Q.+ �rl e i J a CV ~ f!) fA ~J FC Ul N O''d _ ~ ~ I , Q~ U r-I N~'''1 C u1 l0 - i m, M J ri ri '-1 ri r-I ~--I r-I rtis~ .r ~ ~"as ~u? ~ ~ ~ ~ X o� w cn ~o co ca co 7 ~ dv Q p .~om i.y~ ~u"c o: ~ . OOAv ~ ~ ~:C L~ LQ Y N ~ 5 , C z>' V ~ ~ cD U) N O S-~ 'CJ s ~ ~ ~ n' ,x m - ~ S a ~ a ~a � a~ ,.L~ .~Q.~ ~ u~i ~ ~ ~ ' x v S n. ~~~''3 x m m .s Y a ~ = C a~ ~-I ~ Rf UI ~ LI ~ fV Z m cc S r~- o x-~ ~~s ~ m Y~s [ m ~i �rl ~G A CQ �~-I ~ a - ~ Fu z"o s'$'f0,~ovc.sY Fuoo . o, 'cy ~ p- o, Y a r. ~ Lf1 'S R x F- O s Y x~ Y Q. Y ~ T m F" . . . . ` o~ x x o m s `v o~ o o=� x V cU O ~ a a~ o A a ~ o s,G u r'. a~�'o Y ~t~ U O .-I N m U 41 u~ q Ct Y= m.s o x d~o >.~o ~~'9' Y ,x,r~ ~N ~i' d~ 'a' _ A ~ x r�1-~ ~ x a ~ c. ~ (A~- 4`.' N H ~ ~ 7~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE ONLY � 4., +N tn ON N O ~ ~ N ~ 0 0 ~ ~ a~ ~ ' ~w ~ ~ ~ oo _ N N r-1 _ ~"x mu~+x~a ~cia of�i,K ~F-ma'u N~+1 ~ 00 O - I p ~�'c.z x� a S`s' m o a~ ~ o O+~ b~ ~ d' ag~ n~, o o�.~'c�o o`~ o. z ~9uz0.Y r-I t T N~ a= ~Qi'~n o�~ ~.o ~F, xc.ov F I ~O R X x~ x tA ~~-I ~ X~ a S oqxr~-, ~m~ ` ~mo v~a m R! tA ~tC ~ ~ I _XO o' o ~ ~d p o p Y~O ^ o m ca u$~N~ u~ m W~ ~Q~ r~l p rl fd ~ 5~ ~ xs ~ s x x= ~m ~G W Oa~ Sd N ~ ti y~ m u cD ca x~~$ ea q O � ma" ~v~~~ ~rxo�~y ^QmT F'u~d'm'A �ARZS r-1 0 N A NN o~ ~.~y . N~ r, f~ ~ 9 u a s c~ K 3 = m u ,Q 'C1 IA rl ~ M~ ~m co r w~ x`-� ~ ~ ~ a�7 o m s~o ~ Rf U~ N N ~ o~ESm ~ s ~`~r`~.u vs F u icm1� ~ms a fA N O w c~-( S 0.~ 1 O F~- ~ L' Om ~ p p ~1 'a' O~ Z W O u S ~ F v ~ ~ ~.C'+ ~ ~i . m s~ ~ c'o p ~ o m:o 7f w s o a a s cYa 'd .1 ~~-I N.-I uxN zy,;,YN;~_ ~ S a,~t .rawxu U mxF~ti Tl tT~--i ~ S~ ~ a. lfl o CO C1 ~ rt1 C'. r-I ~d A�r-1 ~I a~ av0 ~1 O Ir N 0 v-+ ~ ~ ~ 1-I ~ ~ 3a ~ ~ ~4 ~r; ~ ~ 4a N u1 ` a c ' ' Q ~ ~ X t~d ~ ~1' ~ ~ o 0 0 o z~~ w~+~' ~n c N N 41 n . ~ T A S o. ~ ~n ~ ^ ^ Lfl A~aO~i ' .1+ X L J = ~ 71~+F y T s u~y < ~ ~ 00 00 a0 b ~oq L f� ~ il~ ~1 _ ~ ~ ' ~ 3 tr' m 't3 O ~ ~ m � R~ R' o co ~a ~ ,a C b~ d A ~e x x p cV '4 ~ ~O ~O p A �r1 NJ T O ~ 1~ ~ U CJ U N~ rt1 W~ ro ~ a~ m w~� a~,, a~ ro s~ ~ o d . � ~ a, ~ ~ w c., T ~ _ ca ca w ca a�~ 3 ~D ~ ~ ? c X x :~4 x ,i2�' ~d r-I ~ ~1 N ~ _ ~ = a ~ 4 4 4 x X N Rf O O 4a - ~ U U N+~ s o s s " ~ ~ .G ~ ~ ~ ~w cO `y ' ~ R~ 0a U O ?C R~ ~-1 ~d O ~ U G 0 ~ ~ j ~ o~t o c"( apo n�a 6 p tr~ 0, .-I ,0 4a ~ _ v;% ��s~' mw ~ F w o A~ o o . o v ~d ~ ro _ U o ~ c~-1 ~ w m cv ~ ~ v 'd c'~1 U r-I r-I O RJ Z ~ a� b 0. f~ R+ CL A ~ s ~N m:i mca mu ~ Y^ ~ 1 y Ul rt3 a~ 7 m r~'- f~ m m~ 0� ~ .~rl a~i d ~rl ~'d A C7 (A x �~-i N Z a m~ m~ 04 r~K... t~ ~ m 4, ~ S +l S u/, u x ~ F ~ F GLC' ~ ~ ~ 1 ~ 'o a o~ ~'asi s q u O~ ~j u'~1 uNi U v o ~ ~ n' L � ari n h ,a x~�c ~ u~ ~r A C : � ;i 0. �o� ~ ~ E ~ ~ 71 FUR OFFICIAL 3JSE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 = FOR OFFICIAL USE ONLY ' ~ a~ , N U ro . ~ ~ ~ o J O V X O S t". t0 N.'E ~ I F~- t0 S Q Rj N ~~h~axo>, a~xx~ �~ox~ ~4 ~ u~� A~ aa~ ~ u o ^ih~ ~'"pOOO� o~�ec.`O~ sn~x in tr~ b Y' ~o~i F 4 ~ a � ~ �~co r~ ~ ~ u O V o~ ~aA' alurt Q$o ~zx ~c�xo~~,~`_ o~`r1O O ~ ~ ry ^ S z u >.Y~ ~ m x 45 S~' Q` ~ G,~ z ~ N N G xs x~~ azx z o.~ ~ u x N N'-1 3A at�J-� a c~e0p~a ~~o ~.x ~u N W ro N x a s ~ . ~ ~ u ~ W ~t Q ~a Q ~ ~ R; ~ R~ o x z a~ K x ca Q z(I) s v~ a L. ~ a N~+ ~1 N ~ x~s ~ ss F tOp'X Q =~00 ~ a N ia i~ e~ Y~ y 4, co u F ~t m c. K C. ~1-~ ~ J av s~ Y~am e V o~ a`~i n.a~ T~ ~ ul N U�~ opT~`~Fpo'o ~~ya o s~Tm N � ~1~..~ ^..L C f>, k u m x O. 0. a~.,~ C~ a0 W ~A^ Z U w w~~ ~rl ~ ~ . r ` o o ~ v~i o~~ ayi - � ~ " ~ b ~~ro s~ro T v ~-1 ~r-I a O N~ b~ ' ~o - :�x ~ ~ Q ~ U al M('~ U r0 � = Rf (Q u1 ul �rl ~I as Q QQ d-~ U.~ tT I I J O C u I C] . O pa vOG R! (0 rC3 (~fl _ ~ o 0 o Y A U o ,n - ~ ~ a1 O.-I N M y=~ _ ~ ' N lfl l0 ~O l0 l0 ~ - ~emO~f = Y 4+ F~ ~ a[ � -"aC � ~ ~ ~ T ~ a ~ ~ ~ I u ~ma ~ U �'J O ~ �rl N N -fi ~ ~ U ro N ~ ,s, ~x b �rl N N u= Y Y x O a ~ 4I N(11 N ~ c r rs. �s '0 ~ p CT R7 ~1 x T x ~ ~ U ~ Q U y~.~ O tA Q' V U ~ O tP UI �.-I �rI ' M x N rt1 N R7 - " o d x ' rG-1 ~a x b~ 0 O~~-1 U N 45= ";�_:E vA x ~'b N~u~i~~ ro u s s u~ W tG ~ ~ u s o tT ~ i~a o x T aI o k- x= ~ Q 4 � 4' l-+ `.t. SE V ~rl ~ 3-1 N�U }~1 ~U b~ CP ~ N ~ rtf N Rf ~ u mt ^ ~o p N U CU1 ~ ~ N~ 3 ~ o, ~ U o ~ a~ a ~ N a~i CL u ~ 't7 a ^ v O ~ ~ �'`r �'n~'~ 0, N A~ O ~ >C A~ LL '-i N x.' ' 0~ v y`~ ~ a~ a~ `b 6~N A ^ a ~i V~ Q/ x +s p? V t- Url ~ R7 ~ U~ tn N r~-I N S-~ W ~ = x m l~ o - ~ x ~ a " O 4-i O 'CJ ''d W R7 ~ ~ x - ~ O~ ~ ~ a x a 9 x ~ ~ ~ ?d U 0 a-? ~1 }~1 ~ U m ~ " ~ p~ c~ ,,~x ~~O T 4-~ �,-1 N O M N U O p d � U ."g. ~ ~ 'g' a a a~ N ~ N ~ ,z ~ ~ td rti 'Li U ~ Q. CJ m c~. K a . s F' N~ u1 ~ u1 ~I a N `r W G m p~ c H o z F o ~ x ~ tP I~ O d' O I 0 UI ~ y �i tL] o... - m A x ~ Y ~ m 7-+ 4~-1 N~-I (n N L] ~ r- _ i. x ~ a ~ ~ u~ o m �~1 GO O~'X 'G 'x 1~- ~ x: W aai 2� p m 'N ~ N S.-~ 0 p O 5^' O V ~p ~ ~ ~p ~~f' d~ K S' n'u^ S� a S N N 0. 0 ~ � � � � ~ L~ u ~3 C~ ~ ~ ~J 7 Q~O ~ Q(J ~ U ~fl 111 LfI ~1 ~1 U _ a~ a v ~ . A a~1 ~ ro ~ u _ H 72 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 - FOR OFFICIAL USE ONLY Kev[Continued from preceding page] 64. Number of connected storage devices 1-4, information exchange rate 10 Kbytes/s, carrier compatible with YeS EVM, capacity of 10 NIl~ytes 65. Transmission speed of 64-126 Kbytes/s, capacity of 40 Mbytes, 4 magnetic tape stores informationally compatible with YeS EVM 66. Cassette magnetic tape external storage device (WPK) 67. Capacity of 5.6 Mbits, recording speed of 4 kbits/s 68. Cassette capacity of 400 Kbytes, data transmission speed 0.5 Kbytes/s 69. Wide-format designer graphical screen console (ShGEPP2) 70. Display process~r 71. Memory block 72. Display device 73. Keyboard block 74, Permits connection of two devices, size of operating field of screen 350 X X 350 mm, number of addressable poir,ts 2,048 X 2,048, capacity of buffer storage 16 Kbytes, time of symbol formation 35 microseconds 75. A5122 graphical information to digital code converter (UPGI) 76, Console version 77. Size of operating field of plotter 850 X 600 mm, speed in digital conversion mode 4,800 points/s, speed in analog conversion mode 100 points/s 78. Systems expansion hlock (BRS) 79. Remote communications adaptor (ADS) 8~. Installation cassette 81. Output to two data transmission channels: modem-modem, modem-VT-340 display, modem-T-63 teletype, operating speed of 50-9,600 bauds 82. SM-4501 bus switch 83. Signal transmission cycle delay through PSh 500 ns, PSh load: two load units through input, 18 load units through output - g4. Analog signal input-output device (WA) 85. Maximum number of channels 1,024, contact commutator interrogation rate 200 channels per second, contactless commutator interrogation rate 600 or 2,000 channels per second 86. Digital signal input-output device (WD) 87. Dtaximum number of input-output channels 3,072, counter capacity 16 digits 88. UVD-200 high-speed input-output device 89. 48 digital irput signals, 48 digital output signals, 24 analog input signals and 2 analog output s~gnals (200 kHz) g0, CAMAC crate 91, Crate 92. Crate controller 93. Modules 94. Contains analog and digital signal input-output subsystems, initiative signal input subsystem and timing pulse and constant generator subsystem 95. SP-1-4101 BE9402 interface expander (two) 95. Increase of length b}� 15 meters, readout delay by 0.35 ms, recording delay by 0.25 ms 9~. USS-OSh12K integration matching device 98. Control block 99. Interface b.lock [Key continued on following page] 73 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFZCIAL USE ONLY _ Key [Continued from preceding page~ 100. Number of 2K devices connected to program channel 16, number of 2K devices connected to two direct access channels 16; connection to 120 devices is possible when using eight expanders 101. A71118 computer integration device (USVM) 102. Interface block 103. Pedestal 104. Floor 105. Distance between integrated computers 50 meters, data transmission speed in analog mode 40,000 bytes per second, data transmission speed in direct ac- cess mode 800,000 bytes per second~ 106. SM-4301 universal programmable dispatcher 107. SM-5410 fast Fourier transform special processor ~ 108 , kV � A 109. Internal timing frequency 5-10 MHz, size of transformable file 4,096, width of signal band 500 kHz. USO Configuration Based on Devices Having 2K Junction Output The presence of OSh interface and 2K-USS OSh/2K interface matching devices in the nomenclature of the SM-3 and SM-4 permits the use of all the nomenclature of de- vices and modules of the ASVT-M (M-400, M-6000, M-7000) and SM-1 and SM-2 having , output to the 2K interface as object communications devices. - 5.4. Operating Conditions of the Complex Complexes configured from SM EVM hardware should be operated under conditions cor- responding to GOST (State standard] 20397-74 for articles of group 3B having direct contact with the external medium. - The maximum operating conditions of the complex are ~he following: ` ` i I Maximum Variations of Factors Climatic Factors Lower Upper ~Temperature, �C +10 +35 elative humidity at +3~�C, percent " 90 tmospheric pressure, mm Hg 735 ~85 A single-phase altPrnating current industrial system (220 V, 50 + 1 ftz) is used as the main primary power supply. Smooth and intermittent variations of voltage of _ +10 + 15 percent from the nominal value are permitted. The complexes should be installed in dry heated buildings. The height of ceilings in the building is not less than 3 meters. The ceiling and walls should be fac~d with sound-absorbing materials of light tones. A whitewash coating is not permitted. 7L~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FQR OFF7CIAL USE ~NLY Louvers or blinds should be provided in the window sills. The use of fuel and flammable materials is not permitted during construction and finishing of buildings. Automatic fire signalling devices should be provided. - Lighting is fluorescent or incandescent lamps with diffusion device. Lighting is not less than 150 luxes at a height of 0.8 meter from the floor. ThE lighting of operators' positions and keyboards is 350-400 luxes. Eniergency lighting from a separate power source must be provided. An area of not less than 15 m2 is required for arrangement of the SM-3 and SM-4 complexes and not less tl:an 10 m2 is required for the auxiliary equipment. An insulated production floor which prevents accumulation of static electricity should be provided if possible. The degree of static charge capacity of the coat- ing should provide a charge leakage time of not more than 30 sec.onds. The production floor is designed for loads of not less than 300 kilograms per panel. The recommended size of the panel (nonmetal or metal) is 650 X 650 mm. The snace between the production floor and the main floor is not less than 208-250 mm in height. If a production floor cannot be provided, cable channels protected on top by wooden shields must be provided. BIBLIOGRAPHY 1. "Avtomatizirovannyye sistemy upravleniya na osnove POK" [Automated Control Sys- tems Based on POK], edited by S. N. Khrushchev, TRUDY INEUPI, No 71, 1978. 2. Boyarchenkov, P~. A. and A. N. Kabalevskiy, "The Hardware Tnterface System of the S7na11 Computer ~ystem (SM EVM)," in "Tekhnicheskiye sredstva mini-EVM" [Minicomputer F~ardware], TRUDY INEUM, No 61, 1977. 3. Brusentsov, P7. P., "Mikrokomp'yutery" [MicrocomputersJ, Moscow, Nauka, 1979. 4. Gazimov, V. M., "Vvedeniye v ASU" [Introduction to Automated Control SystemsJ, Kiev, Tekhnika, 1974. 5. Germain, Programmirovaniye na IBbi/360" [Programming on the IBM-360], trans- lated from Enq]_ish, edited by Starkman, Third Edition, Moscow, Mir, 1978. 6. lcagan, B. M. and M. P'. Kanevskiy, "Tsifrovyye vychislitel'nyye mashiny i sistemy" [Digital Computers and Systems], P4oscow, Enerqiya, 1970. 7. Mi.khalevich, S. B., B. A. Sobolev and Ye. A. Zhalnerovich, "Metodoloqicheski1~~ osnovy proyektirovaniya ASU" [Methodical Bases of Automated Control System Desiqn] , hlinsk, 1975. 8. ~Iodin, A. A. et al, "Spravochnik razrabotchika ASU" [The Automated Control System Developers Handbook], edited by N. P. Fedorenko and V. V. Ka.ribskiy, Moscow, Ekonomika, 1978. 75 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300104438-6 FOR OFFICIAL USE JNLY 9. I~torozov, A. A. and A. A. Stogniy, Problem Orientation in Automated Control Systems," UPRAVLYAYUSHCHIYE SISTF~NSY I MASHINY, No 3, 1978. 10. Naumov, B. N. and K. V. Peselev, "Malyye EVM v sfere upravleniya" [Sma1L Com- puters in the Control Sphere], Moscow, Znaniye, 1979. 11. "Printsipy raboty IBM/370" [The Operating Principles of the IBM 370], trans- lated from English, edited by L. D. Raykov, Moscow, Mir, 1978. 12. Radd, W., Programmirovaniye na yazyke assemblera i v~ychislitel'nyye sistemy IBM/360 i IBbt/370 [Programming in ?~ssembler Language and the IBM 360 and ~ IBM 370 Computer Systems], translated from English, edited by L. D. Raykov, _ Moscow, Mir, 1979. 13. Semenikhin, V. S., A. M. Larionov and V. S. Lapin, "Remote Data Processing Facilities and Networks of the Unified Computer System," in "Vychislitel'nyye sredstva v tekhnike i sistem~kh svyazi" [Computer Facilities in Engineering and Communications Systems], edited by S. D. Pashneyev, Moscow, Svyaz', 1978. 14. "Spravochnik proyektirovshchika sistem avtomatizatsii upravleniya proisvodst- vom" [The Designer's Handbook o� Automate~ Production Control Systems], Moscow, Mashinostroyeniye, 1971. 15. "Upravlyayushchiye vychisl itel'nyye mashiny v ASU tekhnologicheskim proiz- vodstvom" [Control Computers in Automated Production Process Control SystemsJ, - edited by T. Kharrisov, Vo ls 1-2, Moscow, Mir, 1975. 16. Filinov, Ye. N. and V. P. Semik, "7.'he Software of the SM-3 Universal Computer Complex," PRIBORY I SISTEMY UPRAVLENIYA, No 10, 1977. 17. Filin, A. V. and A. A. Solokhin, "Organization of Interrupt Processing in the COMNiON BUS Systems Interface of the Small Computer System," in TEKHNICHESKIYE SREDSTVA MINI-EVM, TRUDY INEUM, No 61, 1977. COPYRIGHT: Izdatel'stvo "Statistika", 1980 [lOb-6521] E521 CSO: 1863 END 76 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300100038-6
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