JPRS ID: 9510 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY

• Document Type: CREST
• Collection: JPRS
• Document Number (FOIA) /ESDN (CREST): CIA-RDP82-00850R000300070045-2
• Release Decision: RIF
• Original Classification: U
• Document Page Count: 106
• Document Creation Date: November 1, 2016
• Sequence Number: 45
• Content Type: REPORTS

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~ JPRS ~_/9510
28 January 1981
~ U SSR Re ort ~
p
- CYBERNETICS, COMPUTERS AND -
- AUTO,NIATION TECHNO~OGY
CFOUO 2/81)
FBIS FOREIGN BROADCAST INFORM~?TION SERVICE
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NOTE
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- other characteristics retained.
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COPYRIGHT LAWS AND REGUT.~ATIONS GOVERl`1ING OWDIERSHIP OF
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- JPRS L/951C
2 d ~7anuary 19 8
. -
_ USSR REPORT
CYBERNETICS, COMPUTERS AND AU~'0~1ATION TECHNOLOGY
(FOUO 2/81;
CONTENTS
HARDWARE
Construction Concept and Engineering-Economic Characteristics of Large-
Scale Integrated Memory in Prospective Unified Syst~m Computer~......... 1
Graphic Display With Matrix Gas-Ilischarge Panel 11 ~
_ Features of Special-Purpose Digital Computer Design With a Microprocessor
Set 12
" Computer Maintenance Quslity Indicator 14 ~
Problem of Interfacing Data Transmission Equipment SJith a Un~.fieci R
System Compu~~r 15
Off-Line Debugging Device for the 'Elektronika 55-11' Micr~computer...... 17 .
- SEmi-Permanent Optoelectronic Memory 20
Touch-Sensitive Aata Entry Key Pads 24 ~
i
, SOFTWARE
Languages of Realization for Systems Progra~ing. 26
_ Software Package for Integrated Modeling of Man-Machine SysCrms With
Limited Time Resource 4I
- Solving the Main Problem of Emulation 43
Progra~n Package To Organize Operation of a Multiple-Computer ~~mp;.ex of
' Small ~omputers.......
- 44
High-Level Language for Instrumentation With Built-In Microprocessors
(Microcomputers~ ~~5
- a - [II~ - USSR - 27.C S&T ~OUO]
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~
- Using a High-Level. Language for Microprogramming of Microprocessor
= Digital Devices 46
Data Bank Working Group Seminar Held 48
Abstracts From the Journal 'PROGRAMMING' 49
One Metho~ of Camplex Number Multiplication in Speci.al-Purpose ~
- ~lectronic Comput2rs 53 -
I~itational Simulation by Means of the Syst~s NIDIS and GASP-N........ 55
2~PPLICATIONS !
'Vektor-IZ' Regional Automated Syste~n fo,. Selective Distribution of `
Patent Information 56
- ~nventions Put Into Service Announced 58
CONFERENCES
~ Seminar-Schobl on Intexactive Systems 61
~ PUBI~IC.~ITIONS -
Abstracts From the Journ�1 'CONTROI, SYSTEMS A.ND MACHINES'.~~.....~...,~. 62
. Abstracts From the Journay 'AUTOI~fATION AIdD COP4'UTER TECHNOLOGY' . 7].
~ ~
Scientific Problems of Robot Engineering 76
~ Hybrid Computer Systems and Robot Simulation 82
' Environment Perception Problems 92
PERSONALITIES
Konstantin Nikolayevich Rudnev 101
.
~
- b - -
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_ UDC 681.3.29./16 ~
CONSTRUCTION CONCEPT AND ENGINEERING-ECONOMIC CHEIRACTERISTICS OF LARGE-
_ SCALE INTEGRATED MEMORY IN PROSPECTIVE UNIFIED SYSTEM COMPUTERS
Kiev UPRAVLYAYUSHCHIYE SISTEMY I MASHINY in Russian No 3, 1980 signed to
press 4 Jun 80 p~ 127-1~1
[Article by Viktor Vladimirovich Przhiyalkovskiy, candidate of technical ~
sciences (Moscow); Andrey Borisovich Akinfiyev, candidate of technical -
sciences (Moscow); and Nikolay Mikhaylovich Sharunenko, candidate of tech- -
nical sciences (Moscow); received by editor 22 Jan 80 (after revision,
2~? Mar 80) ]
(Text] ZU (memories] have largely determined and are determining the effi-
" cient use of hardware and software at all stages of d~velopment of computer -
technology, Future models of YeS computers require memories with a large
capacity, high speed, high reliability and low cost. These requirements
are currently being met with the extensive application of BIS [large-scale
- integrated circuits (LSI)] of inemory. -
Semiconductor LSI memories have already been used in models of the second -
i phase of YeS computers as bases for building processor, buffer and micro-
program memories, and the process of replacing the ferrita main memories in
these models with semiconductors has started recently. The highest indica-
tors for ferrite memories were obtained in the YeS3206 device [1], which -
has a 1M byte capacity and is mounted with power-supply sources in the -
standard rack af YeS computers.
. Memories for models YeS1022, YeS1033, YeS1035 and YpS1045 were developed in -
a short time based on microcircuits of semiconductor memory of the 565RU1
with a 4K bit capacity, and the memory for the YeS1060, based on microcir-
cuits of the 565RU3 with a 16K bit capacity. Using semiconductor circuits
for memory has made it possible to improve engineering and economic indica-
tors for memory. The cost of one bit of information in the device was
lowered three- to four-fold compared to ferrite memorie~, wnile dime~sions -
were reduced three- to eight-fold.
Since the ferrite core memory capability of storing data during accidental
power supply vari2tions has not been used in the majority of YeS computer
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applications, the expediency of replacing ferrite with semiconductor meinory
_ is obvious. Ferrite memories can be kept for those applications where data
- has to be preserved when power supplies are turned off. Parameters of main
_ memories of second-phase YeS computers and modernized first-phase models
_ are given in the table.
~ Evoiution of the YeS computer main memories, reflecting the requirement of
_ the computer and the capability of engineering the memory, is shown in
_ Fig. 1. Growth in memory of the different machines is shawn with an indi-
cation of the type of storage elements and degree of their integration.
Table
access cycle
capacity, basic ti~?e, time,
memory computer model M bytes design ns ns
YeS3206 YeS1060, YeS1045, YeS1052 1,0 (64Kx144r) rack 650 1200
YeS3262 YeS1022 0.5 (128Kx40r) frame 800 1200
YeS3263 YeS1033 1.0 (256Kx40r) " 800 1200
YeS32:i8 YeS1035 1.0 (128Kx72r) " E00 1200
YaS3267 YeS1045 1.0 (64Kx144r) " 650 read - 720
write - 840
YeS3266 YeS1060, YeS1065, YeS1052 8.0 (256Kx288r) rack 520 850
- The Series=3 computer processors, just as the Series=2, will include very
high-speed memeories that include general-purpose registers, address matrix,
address translation buffer, ultra high-speed buffer storage and micropra-
- gram or control memory. The highest speed is required of the address ma-
trix and the translation buffer. Series-3 computers with a throughput of
several millions of operations per second and a machine clock time range
of 40 to 80 ns require the use of gennral-purpose registers, address matrix
and translation buffer with an access time of no more than 10 to 15 ns.
- Since these memories need only a 1 to 2R byte capacity, they can be built
with ESL [emitter-coupled logic (ECL)] memory microcircuits with a capacity
of about 64 bits and standard access time of 5 ns.
Fig. 2 shows average computer throughput as a function of buffer and micro-
program memory speed. Parameters of Series-2 YeS computers are used t~o
show the relationship. Series-3 ultra high-spesd buffer storage is to have
_ an access time ranging from 20 to 40 ns and differ.s from Series-2 storage
by the increased information capacity reaching 64~~ bytes. In the Series-2
YeS1060 model, the 8K byte buffer storage is built with 500RU410 microcir-
cuits with a capacity of 256 bits and maximum acr_ess time of 40 ns [2].
Buffer storages for the higher Series-3 models are based on using ECL memo-
ry microcircuits with a 1024 bit capacity and access time of 10 to 15 ns.
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Fig, 1. Evolution of YeS
(1) (2) O computer main
" ~'T 6"` memories
- AK 6nr 3 luK GMi G4K6rt
~ ~ i
; Key :
; 1. M bytes
~ 2. LSI
3` ~ 3. 4K bits
~cioGs
4. VLSI, 16K bits
- %i~~i.
1" rG~"'~";`/ ' S. VLSI, 64K bits
Gr_lu',_ ~
'tr,~w ~ ' j ~ 6. ferrites
b ~~6~), w ; 7. maximum
" ~ 8. minimum
~EC1U~_ ~
~ 1
~ ~ P`~ `N ~ - ; i 9 . Series-1
i :c,o�,~ , 10. Series-2
- ~ / ~ 11. Series-3
~ EC = YeS
~ ~ .
, 1 % ~ I
L:C 1 U::U /
i
'C 1 OJ ' I
= U5 ~ j,~ ~ ,
~
. ~C~~~Z~ / ~
!7` L�C10~ ~
~ ~ I
_ O~'~.:1 m� p P M T M~ ~
~ ~ Y fi C i
~
U~1~) ~
1 Q:~ U I
~
u,~ri Er_lo'sc � ~ i
I
l~~ y I
1
~ ~
P~o- 1 n- 2 P~q-9
_ It is assumed that ECL memory microcircuits with a 4096-bit capaci~y will
not have sufficient speed for use in higher Series-3 models, b~et may be
used in lower models.
It should be noted that ECL microcircuits have high power consumption
(abou~t 0.5 to 0.9 W per ~ackage), and this does not permit obtaining maxi-
- mally possible density of packagl.ng on the boards because of difficulties
= in ensuring thermal conditions. Howev~er, maximal density of packaging is
_ needed not only t~ reduce size, but also to reduce l.ength of communication
= and increase speed. Actually, it can be expected that high-speed buffer
- storage with a capacity of 64K bytes can be placed into one standard panel
- of YeS computers when wicrocircuits with a degree of integration of 1024
- bits are used.
= Microprogram or control memories for future models must have the same
t-,igh-speed as the buffers: access time should range from 20 to 4~ ?zs,
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Fig. 2. Average computer ~
Il~x,e~wu~nn?nocrr f 1~ 2Q throughput dS 8 , ~
"3LN1, wir.onop/c _
/ func~ion of buffer _
/ and microprogram _
memory speed
a,u
- ~ciui.s
- Key: -
1. computer throughput, _
2,0 -
millions of operations
tc~oco per second _
_ ~J 2. Series-3
F, ~ ~ ~,(3)- _ ~ 3. Series-2
/ 4. access time, ns
u,lz;, j ~ciw~ ~ EC = YeS
~ ~4~
tQ.. iK
2u At, l.t~ tU 1U0
_ while the capacity of thesp memories may reach 128K bytes or more. It is .
obvious that they can be built with the~same elements having a capacity of
1024 bits, just lik.e the buffer storage, and they can be put in two panels
- of the YeS computer.
- The experience of developing and using microprogram memories in programma- -
ble microcircuits of PZU [read-only memory (ROM)J shows that the latter
are used most advantageously in control devices, for example, in magnetic -
disk storage controllers. L~ing tl~em in computer processors simplifies
operati~n, but complicates changing microprograms.
Thus, two ECL memory microcircuits are needed for the processors in higher
Series-3 YeS computer models: 1024 bits with a standard access time of
- 10 ns and 64 bit~ with a standard access time of 5 ns, The minimal nomen-
clature of the memory microcircuits for the processor makes it possible to
raise the ~uality of the products and lower the cost for producing the mo-
dels. In ~~he process, testing the microcircuits is simplified, testing -
~ost is recluced, test equipment is simplif ied, and the level of mastering -
- the production of the microcircuitF is rais ed both in connection with work-
ing out the TU [engineering specifications; and the quality of tlte micro- ~
circuits proper. Because of the small nomenclature of the memory microcir-
cuits, solving the problem on standardization of the storage TEZ's [stan-
dard exchange cards] is simplified, which in turn permits developing cheap- `
er and more efficient test equipment for them.
ECL microcircuits are the fa~test, but also the most complex in a techno-
logical sense, which affects their cost. It can be assumed with a suffi- -
_ cient degree of certainty that in the next few years, the cost per bit of
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(4~ !1 Fig. Proportionate main
C7uM~qCTb ~ V
memory cost as a
g function of degree of
~ integration of the
- 5) ~ (6) elements
0
Y V
7 I
M /
- 6'4 ~ ( EC330G, EC3307) Key :
� 1. Series-1
3,2
4K(EC3238, EC328a, EC3287) 2. Series-2
~ i,s iso � ~ 3. Series-3
�~e ieK ~ec3zas~ 4. cost
5. kopecks per bit
o,a ao 6. thousands of rubles
_ saK per M bytes
� o.~ ~0 7. FS (ferrite coreJ
= o,o ~ ssx EC = YeS
o,ozs
P*a-1 Pia - 2 P~n-3 _
(1) 2 (3)
_ information in processor memoxies will be several kopecks, and with a rela-
- [ively large information capacity of inemory (64K bytes for buffer and 128K
bytes for microprogram memory) the cost of them is becoming comgarable to
the cost of main memory built with MOP [metal-oxide-aemiconductor (MOS)j
LSI.
The evolution of main m~mories is linked to the development of MOS LSI
dynamic memory microcircuits.
In world practice, there is a steady trend of quadrupling the degree of in-
_ tegre~ion of dynamic memory microcircuits every two years, and the cost per
bit is being cut about in half during this period.
= In addition to increasing the degree of integration and loweri.ng cost, other
characteristics of microcircuits are being improved. Thus, for example, a
microcircuit with a capacity of 1K bits required several power sources,
several special control clock signals and a complex system of synchroniza-
tion; a circuit with a capacity of 4K bits has a simple system of synchroni-
zation, requires only one special control signal, has increased speed and
is assembled in a 22-lead package; although a circui~ with a capacity of
16K bits requires three power sources, it dissipates less power, is compat-~-
ible on all leads with TTL [Cransistor-transistor-logic] logic circuits,
and is assembled in a 16-lead package thanks to multiplexing of address
buses.
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Further improvement of dynamic memories is aimed at developing microcircuits
with a capacity of 64K, operating from one +SV power source, having an ac-
cess time of 100 to 150 ns, ana arranged in a 16-lead package, of which one
lead may remain free for futu:e use when circuiCs with a capacity of 256K
bits emergE~. Decreastng the number of microcircuit leads from 22 to 16 and
decreasing the package sizes makes it possible to put twice as many packages
on boards since the small dissipated power of MOS memory microcircuits does
not impose limitations on packing density. With 16K-bit microcircuits, a
- 16M-byte memory, which exhausts the possib ility of the present addr~ssing
system, can be created in a YeS computer bay. Increasing the degree of in-
tegration of inemory microcircuits to 64K and 256 K will pexmit placing a
16M-byte memory in two panels and in a half-n::~~, respectively, of a YeS
computer. ~
The cost per bit in the conversion to an arrangement for 16K-bit mi~rocir-
cuits will be 0.6 kopecks/bit, while for 64 to 256K-bit circuits a cost of
0.1 to 0.03 kopecks/bit is expected.
Figure 3 shows the trend of change in proportionate cost of main memories
as a function of storage element integration using YeS computer memories
as an example.
- If the degree of integration of dynamic MOS memory microcircuits quadruples
every two years, then this means that during the development of a computer
_ model, microcircuits may emerge with a higher degree of integration than
that at the start of the development. So that the computer is fitted with
the most advanced memory, tl:e memory can b e developed with microcircuits
- that exist at the time and then the model already developed can be modern-
ized when the next microcircuit emerges. However, this means that full-
scale development of two memories is needed, which naturally increases de-
velopment costs and requires availability of certain resources.
Another way i~ to standardize memory as much as possible, and in the f.irst
: place, to standardize memory interface, In the process, memory from a pre-
ceding model can be used in a new computer model at the stage of develop-
ment and assimilation into production and b e subsequently replaced wh~:n new
= microcircuits are available. In addition, this standardization will pro-
- mote reducing the nomenclature of test equipment (for microcircuits, TEZ's
- and devices) and will allow memory production in a specialized enterprise.
Introducing standardized devices should be preceded by a detailed economic
= and engineering analysis, since one can expect that stand~rdized devices
~ will be somewhat more complex than special ized ones and naturally more
expensive.
- A few words must be said about static.MOS memory microcircuits. These are
technologically more complex than dynamic ones. This means that the degree
- of integration of static microcircuits will always be less than that of dy-
namic circuits, and the cost per bit higher. But static microcircuits do
- have the advantage of increased speed. As the technology advances, the
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high speed of static MOS memory increases and approaches that of bipolar
memory. Thus, for example, MOS memories have been developed with a capaci-
_ ty of 1K that surpass the speed of TTL-circuit memories of the same
capacity [4J.
A definite area of application for static memories is in small-capacity
peripherals in which it is desirable to not have control circuits requiring
regeneration that dynamic memories need. Static memories are more desir-
= able in devices operating in real time since dynamic memories are inacces-
sible for reference during the regeneration process which is three to five
percent of the time.
Modern semiconductor memories for computers with high throughput are de-
vices containing thousands of inemory micro~ircuits and hundreds of electron-
ic framing elements. If specific measures are not taken to enhance reli-
ability, then the mean time between faiiures can amount to hundreds or even
dozens of hours, which is cl.early unacceptable.
= The failure rate for elements in the break-in period is especially high:
one to two orders higher than in a device that has been broken in [S].
To raise the reliability of the devices, first of all it is necess~ry to
use the Hamming code that makes it possible to correct single failure~=, or
_ malfunctions that occur, and to perform regular preventive maintPnance to
replace the microcircuits that have failed. These measures permit raising
- memory reliability by one to tr~o orders. For especially critical devices,
microcircuits have to undergo electrothermal aging prior to being installed
in a storage device. Reliability can also be raised by the manufacturer
- making a trial run of the devices for several days, introducing break-in of
_ the devices into the TU [engineering specifications]. Even after this, the
~ user will experience increased intensity of failures the first time. This
means that an increased number of storage TEZ's has to be included in the
kit of ZIP (spare parts, tools and accessori.es], and it is desirable that
the user have service equipmene to repair them.
The question on the need for service equipment is an economic and engineer-
inK one, since detection of malfunctions, diagnostics and repair can be
done during preventive maintenance on the computer. An additional increase
in reliability can be gained by increasing the amount of equipment for the
elecCronic framing elements so that a failure of an electronic framing ele-
ment does not lead to failure of several units.
_ As a general prinicple for raising reliability, it is advisable to use mi-
_ crocircuits with the least number of leads and the highest degree of inte-
- gration, Memory reliability (mean time between failures) is raised whP:~
~ the quality of development of storage TEZ's is raised, namely when there is
a small level of noise on both tihe supply and signal buses. From this as-
~ pect, the use of multilayer printed circuit boards is desirable.
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- Consid�~ring that as the degree of integration of microcircuits grows, the
proportionate cost of inem~ry will dPCline and the development of devices -
simplified, let us look at the possibili.ty of building external storage
with solid-state elements of inemory. It is evident that solid-sLate memory
elements can provide higher speed. Hawever, considering :hat the cost per
bit in contemporary VZU [external storage. units] using magnetic disks and
tapes is extremely lowy the potenr_ial area of application of solid-state
memory elements in the early stages will be limited to devices with rela-
tively small capacity.
Thus, for example, we can look at the possibility of rPplacing the YeS5064 _
fixed-head magnetic disk storage unit that has a capacity of 11M bytes for
storing an operating system. As potential replacements for this storage
unit, let us loQk at semiconductor mem~ries with random access made with
MOS units and those with serial access made with PZS [charge-coupled device]
structures, as well as storage made with magnetic bubbles (TsI~ID) and elec-
_ tron beam tubes (ELT) with a semiconductor target (6]. A comparison of
these types of storage with a magnetic disk storage unit and with each =
other has to be made on the major characteristics of external storage: -
specific information density, rate of informatic~n exchange and cost per bit
of information. _
The speed of semiconductor and electron beam storage devices is appreciably
higher than that of electromechanical ones; however, when a standard channel
is used, the criterion of speed is not paramount, since system speed is -
limieed by channel throughput. In addition, when power-dependent semicon-
- ductor memory elements are used, the problem of developing an economic
emergency power supply system has to be solved.
Information density and cost per bit of information are largely determined
by the degree of integration of the microcircuits for semiconductor main
memories and charge-coupled device [CCD] structures of storage units, the
degree of integration of microassemblies for magnetic bubble storage de-
vices and the capacity of the electron beam target. Let us l~ok at what de-
greee of integration is needed so that an 11M-byte storage unit and its
power supply could be put into a YeS computer frame and so that the cost per =
bit would be 0.1 kopeck, which corresponds to the basic characteristics of "
the fixed-head magnetic disk storage unit.
Calculation (see fig. 3) shows that to obtain the needed information density
~ and unit cost, the degree of integration of semiconductor microcircuits with _
dynamic MOS memory and of CCD microcircuits has to be 64K bits in a package.
To obtain the needed information density in magnetic bubble units, the ca-
pacity of one magnetic bubble microassembly has to be 1M bits. This is be-
: cause the microassemblies take up about four times more area on a card than
- a semiconductor microcircuit, sznce a magnetic bubble micr~assembly includes,
besides the storage chip proper, inductors to create a rotating magnetic -
field and a system of permanent magnets to create a bias field. In addition,
magnetic bubtile microassemblies need a rather large number of electronic
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framing circuits, which take up three times more space on the cards than
the magnetic bubble microassemblies [7].
: Hence it is evidenr that to attain the same information density as semicon-
ductor m~mory, the magnetic bubble microassembly has to have a degree of
integration higher by a factor o� 16 than semiconductor microcircuits. It
should be noted that world practice shows just that relationship of capa-
cities for magnetic bubble and MOS microcircuits. Thus, MOS microcircuits
with a 4K-bit capacity correspond to magnetic bubble microcircuits with a
~j 64K-bit capacity, and MOS microcircuits with a 64K-bit capacity correspond
~ to magnetic bubble microcircuits with a 256K-bit capacity. One alternative
_ solid-state external storage unit may be MOS structure storage with elec-
- tron beam access [8] . The rated capacity of an electron beam tube with a ~
50 cm length and 10 cm diameter is 4M bytes which is adequate for building _
an 11M-byte external storage unit to fit in the YeS computer fram~. This
solution seems to be feasible in an engineering sense. With this degree
of integration, the required cost of 0.1 kopeck/biL could be obtained. .
Another application cf large-capacity solid-state storage could be inter-
mediate storage needed when building archival storage systems. The speed
- of intermediate storage with a capacity of ab~ut 100M bytes, actimg as a
- buffer between the computer and the relatively slow, but lar~e-capacity,
magnetic tape storage units, largely deternines the speed of the enzire
system of archival storage. A rough estimate shows that to construct a -
100M-byte device to fit i.n a YeS computer bay and having a unit cost of
~.01 to 0.02 kopeck/biL, the capacity of semiconductor microcircuits has to
be not less than 256K bits in a package, of magnetic bubble microcircuits--
not less than 1M bits, and of electron beam tubes--not less than 4M bytes. -
Conclusions. Future models of Series-3 YeS computers should include a set
of processr~r memories with a capacity from 1 to 128K bytes ~uith access
time ranging from 10 to 40 ns; the element base will be ELS (emitter-
coupled logic? memory microcircuits with a degree of integration from 64
to 4096 bits.
The mai.n memories in the first phase of the Series-3 should have a capacity
oF up to 16M bytes with an access time of no more than 0.5 microsecond.
The element base for these memories s`~ould be microcircuits with integra-
tion of 16 to 64K bits. In some cases, it is also advisable to use magne-
Cic microferrite memories.
External storage units, used to store the operating system and traditional-
_ ly on magnetic disks, may be replaced in Series-3 machines by solid-state
integrated storage devices for enhanced speed and reliability.
9
- FOR OFFICIAL USE ONLY -
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APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2
rOR OFFICI~L USE ONLY
BIBLIOGRAPHY
1. Sharunenko, N. M., and Fateyev, A. Ye. "General-Purpose Digital Com-
puter Memory," in "Tekhnika" [Engineering], Moscow, Znaniye, 1977,
pp 27-43.
- 2. Sharunenko, N. M. "Evolution of Unified System Main Memory," in
"Vychislitel'naya tekhnika sotsialisticheskikh stran" ~Computer Tech- .
~nology of the Socialist Countries], Moscow, Statistika, 1977, 2nd ed.,
pp 21-32.
3. Hodges, D. "Semiconductor Elements of Digital Storage Devices: Pre-
sent Status and Prospects," TIIER, 1975, Vol 63, No 8, pp 54-67. -
- 4. Keypis, R. "High-Speed Static ZUPV [Random-Access MemoriesJ: Present
Status and Prospects," ELEKTRONIKA, 1979, Vol 52, No 9, pp 40-57. _
S. Madzharova, T. B. "Reliability of Large-Scale Integrated Circuits,"
~ ZARUBEZI-INAYA RADIOELEKTRONIKA, 1978, No 1, pp 143-147.
_ 6. Keypis, R. "Semiconductor Memory That Replaces Disk Storage," _
ELEKTR.ONIKA, 1979, Vol 52, No 12, pp 6-7.
7. Brayson, D.; Kl~ver, D.; and Lu, D. "Set of Large-Sca12 Integrated Cir-
- cuits for Combined Use with Magnetic Bubble Storage," ELEKTRONIKA, 1979,
Vol 52, No 9, pp 23-32. _
8. "El.ectron Beams Take Aim at 2G Byte Memory Systems," ELECTRONIC DESIGN,
1~l78, Vol 26, No 6, pp 21-22.
- COPYRIGHT: IZDATEL'STVO "NAUKOVA DUI~A" "UPRAVLYAYUSHCHIYE SISTEMY I
~ MASHINY" 1980 -
- [408-8545] -
8545 ~
_ CSO: 1863
10
FOR OFFICIAL USE ONLY
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APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2
. FOR OFFICIAI. [3SE ONLY -
UDC 621.387.3
GRAPHIC DISPLAY WITH MATRIX ~AS-DISCHARGE PANEL
Kiev UPRAVLYAYUSHCHIYE SISTEMY I MASHINY~ in Russian No 3, 1980 signed to
press 4 Jun 80 pp 66-69 -
[Article by Aleksandr Maksimovich Smolyarov, candidate of technical sci-
ences, RRTI [Ryazan' Radioengineering Institute] (Ryazan'); Vladimir
Vasil'yevich Mechetnyy, engineer, RRTI (Ryazan'); and Margarita Aleksandrov-
na Dudina, engineer, RRTI (Ryazan'); received by editor 27 Nov 78 (after
revision, 7 Jul 79)]
(Excerpt] Basic technical characteristics of the device
Input code seven bit (with sign-variable code,
one bit is signed); ~
Maximum permissible rate of
incoming information, kHz 300;
Control circuit voltage supply, V +5+5~ and +3+5%;
- Power-supply voltage, V +250 - 20% and +150 +20~;
Element base R133, K155, K141, K166, AL304 -
_ The GIP-10000 [7] DC gas-discharge panel is used as the GIP [gas-discharge
display panelJ.
The merits of this GIP are compactness, low power-supply voltage, absence
of a code-analog converter, sufficiently high precision (error +1%) and _
- brightness (not less than 100 cd/m~), and resistance to mechanical effects. -
These displays may be widely used in ASU [automated control systems], _
ASUTP [automated systems for control of industrial processes], centralized
monitoring systems, information-metering systems and as computer output .
- devices .
COPYRIGHT: IZDATEL'STVO "NAUKOVA DUI~4CA" "UPRAVLYAYUSHCHIYE SISTEMY I
MASHINY" I980
~408-8545]
8545
CSO: 1863
11
FOR OFFICIAL USE ONLY
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APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2
FOR OFFICIAL LTSE ONLY
~ UDC 681.3.48./14
FEATURES OF SPECIAL-PURPOSE DIGITAL COMPUTER DESIGN WITH A MICROPROCESSOR -
SET
Kiev UPRAVLYAYUSHCHIYE SISTEMY I MASHINY in Russian No 3, 1980 signed t~
press 4 Jun 80 pp 38-43
[Article by Yuriy Yakovlevich Berson, engineer (Leningrad~; Leonid
Veniaminovich Gol'dreyer, engineer (Leningrad); Lev Yakovlevich Lapkin,
= candi:date of technical sciences (Leningrad); Valentin Georgiyevich Nosov,
engineer (Leningrad); Nikolay Petrovich Sedov, engineer (Leni.ngrad);
Vladimir Borisovich Smolov, doctor of technical sciences, LETI [Leningrad
Electrotechnical Institute imeni V. I. U1'yanov (Lenin)) (Leningrad); and
Vladimir Tikhonovich Startsev, engineer (Leningrad); received by editor _
22 Aug 77 (af ter re~ision 3 Apr 79)]
[ExcerptsJ The largest effect from building SVM [special-purpose digital
_ computers], program compatible with the YeS computers, with BIS [large- -
scale integrated circuits] and MP [microprocessor] sets will be achieved
with series assimilation of the K583 series IS [integrated circuit] inten-
ded for realization of this system oi' instructions. Since these integrated
circuits are still in the development stage, while industry is currently =
producing microprocessors architectually incompatible with the YeS com-
puters, this work discusses the possibility and advisability of using them -
in these special-purpose digital computers.
Conclusions
~ 1. To build special-purpose digital computers with the YeS computer in-
struction set, it is advisable to use K584 IK1 microprocessors as the cen- -
- tral processor for SVM with small and medium throughput and as a channel
processor for SVM with high throughput.
2. It is possible to build an SVM with a throughput on the order of 1
million short operations/second of the format RX using an ALU [arithmetic-
logic unit] for the arithmetic unit and a microprocessor for the channel
processor.
3. To expand the possibilities of using a microprocessor as the central
processor in an SVM with high throughput, program compatible with the YeS
12
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APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2
- FOR OFFICIAI. I3SE ONLY
computers, the microprocessor must meet the following additional require- _
ments :
, --have 16 internal general-purpose registers;
~-~provide independent access to two other general-pu.rpose registers;
~ ~--have two-address operations in the system of oper.ations, performable on
operands stored in the various general-pur~ose registers;
--provide generation of attributes of overflow and zero value of the
mantissa of the result.
Of the currently known foreign microproc~zssors, these requirements are
most fully met by the Am 2901A microproc~assor produced by Advanced Micro
Devices.
= BIBLIOGRAPHY
1. Drozdov, Ye. A.; Komarnitskiy, V. A.; and Pyatibratov, A. P.
- "Elektronnyye vychislitel'nyye mashiny Yedinoy sistemy" [The Unified
System of Electronic Computers], Mo~cow, Mashinostroyeniye, 1976, 672
pages.
2. Cheglanov, L. V.; Klubkov, V. V.; Novo~hilov, A. S.; and Fiiatov, V.
N. "Special Purpose Digital Computer Made with Microprocessors with
- the YeS C~mputer Instruction Set," ELEKTRONNAYA TEKHNIKA, series 11, ~
1975, issue 2, pp 9-18.
3. Klubkov, V. V., and Madatov, A. A. "Computers with the YeS Computer
Instruction Set," ELEKTRONNAYA TEKHNIKA, series 10, 1977, issue 6,
pp 14-18.
_ 4. Khorton, Engleyd, Makgi, "Integrated Injection Logic: A Major Ad-
vance in the Technology of Bipolar Large-Scale Integrated Circuits,"
ELEKTRONIKA, 1975, Vol 48, No 3, p 24. -
_ 5. Belous, A. I.; Boldyrev, V. P.; Kaloshkin, E. P, et al. "General-
Purpose Single-Chip Four-Charge Microprocessor," ELEKTRONNAYA PROMYSH-
LENNOST', 1977, issue 5(59), pp 55-57. -
6. Rotnov, S. V.; Topolov, A. D.; Federov, Yu. T. et al. "Low-Power
Transistor-Transistor Logic Microcircuits for Building Processor Sys-
tems," ELEKTRONNAYA PROMYSHLENNOST', 1977, issue 2(56), pp 75-79.
- 7. Khasson, S. "Mikroprogrammnoye apra~leniye" [Microporgram Control],
. Moscow, Mir, 1974, 2d ed., 478 pages. -
8. "Microprocessor Data Manual," ELECTRONIC DESIGN, 1977, Vol 25, No 21,
p 170.
COPYRIGHT: IZDATEL'STVO "NAUKOVA DUMKA"."UPRA`1I,YAYUSHCHIYE SISTEMY I
MASHINY" 1980
[408-8545]
8545 -
CSO: 1863
13 -
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2

APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2
FOR OFFICIAI. USE ONLY
UDC 681.3:621.797
, COMPUTER MAINTENANCE QUALITY INDICATOR `
Kiev UPRAVLYAYUSHCHIYE SISTEMY I MASHINY in Russian No 3, 1980 signed to
press 4 Jun 80 pp 21-23
y [Article by Yuriy Artem'yevich Yershov, engineer, VNITI [All-Union Scien- _
tific Research and Industrial Design Institute of the Pipe Industry]
~ (Dnepropetrovsk); received by editor 25 Jun 79]
[Excerpt~ Table 2. Manufacturer's recommended time for preventive ~
maintenance on the YeS-1022 computer
Days computer operated in a week
Type Aours S 6 7 -
semiannual 36 72 72 72
monthly 16 160 160 160
bi~reekly 4 48 48 48 _
daily 1 235 287 340 -
- total 515 567 620
COPYRIGHT: IZDATEL'STVO "NAUKOVA DUrIIZA" "UPRAVLYAYUSHCHIYE SISTEMY I _
MASHINY" 1980
[408-8545]
8545
CSO: 1863
' 14
~
FOR OFFICIAL USE ONLY
APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2

APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2
FOR OFFICI.aL LSE ONLY
UDC 681.327.8
- PROBLEM OF INTERFACITi; DATA TRANSMtISSION EQUIPMENT WITH A UNIFIED SYSTEM -
COMPUTER
Kiev tJPRAVLYA'IUSHCHT.YE SISTEMY I MASHINY in Russian No 3, 1980 signed to
press 4 Jun 80 pp 132-135 -
[Article by Petr Matsovich Ivanov, candidate of physicomathematical sci-
ences; and engineers Vladimir Titovich Kerefov, Pavel Georgiyevich Teslya,
Igor' Ivanovich Gridyakin, and Nikolay Alekseyevich Tkhishev; all from the
- KBF VPTO [expansion unknown] "Rossel'khoztekhsistema" [system for All-
Russian Agricultural Equipment Association] (Nal'chik); rec~ived by editor -
23 Jan 79 (after revision, 29 May 79)] ~
[Excerpts] YeS [Unified System] computer hardware currently permits inter-
facing data transmission~channels with a computer input/output channel
using data transmission multiglexors (MPD-1, MPD-2, MPD-3) (2]; however,
funding limftations for acquisition of this equipment hinder their practi- -
~ cal use and in a number of cases justify developing nonstandard hardware
' performing a similar function. ,
- This work deals with the question associated with developing a single-
' address adapter to provide interface between the APD-MA [data transmission
- equipment; MA - expansion unknown] and the Ye~-1022 computer. The single-
, address adapter or interface device (US) effects coardination of the physi-
- cal parameters of signals and algorithm of operation of the computer multi- _
_ plexor channel and the joining of the data transmission equipment, and per-
forms the following functions:
--sccesses APD in accordance with address sent from the computer;
--executes commands and instructions for computer control; ~
--controls modes of operation of the APD;
--controls flow od data between the computer and the APD;
--checks characters for correctness of data sent and received;
--informs computer on status of the APD and the US itself;
--handles emergency situations automatically and subsequently restores -
operation.
The interface device was designed on the base of a standard type frame, the
K2KK6-6U3; integrated microcircuits of the 133 and 140 series were used as ~
15 -
FOR OFFICIAL i3SE ONLY
j �
~ ~
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APPR~VED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2
FOR OFFICIAI, USE ONLY
the element base. Controls and displays showing current status of the de-
vice are located on the front panel of the frame. Connectors are located
on the rear wall of the frame. The interface device connects to the compu-
ter input/output channel with two pa irs of "Nabor" connectors, similar to
standard external devices uf the Unified System (IKM-2 cables), and con~
nects to the APD with two BPP 40G1- 1T3 connectors.
COPYRIGHT: IZDATEL'STVO "NAUKOVA DUi~A" "UPRAVLYAYUSHCHIYE SISTEMY I =
MASHINY" 1980 -
~408-8545]
8545
CSO: 1863 ~
~
16
FOR OFFICIAL USE ONLY
~
APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300070045-2

APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300074445-2
I
_
FOR OFFICIAL USE ONLY
- UDC 681.326
OFF-LINE DEBUGGING DEVICE FOR THE 'ELEKTRONIKA S5-11' MICRO-
COMPUTER
Moscow PRIBORY I SISTEMY UPRAVLENIYA in Russian No 9, 1980 pp 19-20
_ (Article by V. V. Sumin, candidate oftechnical sciences, A. B. Vasil'yev and
N. M. Kalinin, engineers]
_ [Text) The very simple debugging device described in this article can be viewed
as the first practical step toward assimilation of microcomputers on a chip for
- the overwhelming majority of users. The device is an uncomplicated console for
input, monitoring and execution oic programs; thus an "Elektronika S5-11"
microcomputer outfitted with such a console becomes an off-line programmable
automation device.
- The funetional arrangement of the device was examined by the authors [1]. The
- schemata of the debugging console and the memory unit will be given later with
~ brief descriptions. Figure 1 shows the console scheme which includes the
controls for monitoring the "Elektronika 55-11" microcomputer and f4r setting it
= in the operating mode: "Work", "Inhibit G", "Dump", "Start" (KhS2 : A2, KhS 2
: A1, KhS 2: B20, KhS 2: B 23, KhS 2: B 21, KhS 2: A 22, KhS : B22);
funetional buttons (SCh, BA, Cht, ZP) and a 0-F hexadecimal keyboard with
combiner (E1-E16), connected to a digital input channel of 3 microcomputers
, (KhSl : A14, KhSI : A15, KhSl : B19, KhS : A18, KhSl : A20, KhSl : A 21, KhSl
: B22, KhSl : A22); point LEDS L1-L8 to display the information byte connected
to the digital output channel of three microcomputers (KhS2 : A14, KhS2 : B12,
KhS2 : B15, KhSl : A12, KhS2 : B14, KhS2 : A13, KhS2 : B13, KhS2 : A11).
' The diagram of the read-only memory (ftOM) in whieh the console exehange
routine is contained, is shown in Figure 2. The ROM unit contains elements
(A1-A8) for interfacing with the address (ShA) and information (ShI) busses of
the "Elektronika 55-11" microcomputers (KhS4 : B1.3, KhS4 : B14, KhS4 : A11,
, KhS4 : A10, KhS4 : B8, KhS4 : A3, KhS4 : B16, KhS4 : B17, KhS4 : A2, KhS4
: B1, KhS4 : A18, Kh54 : A20, KhS4 : B4, KhS4 : A19, KhS4 : B3, KhS4 : B7,
KhS4 : A9, KhS4 : B11, I{hS4 : A12, KhS4 : A16, KhS4 : B22, KhS4 : A17, KhS4 ~
: B19); memory access shaper (I2-I6); address decoder (D, Il); diode storage H
whicY~ t~re connected according to the console exchange routine.
The sequence of operations for the operating mode device may be described as
follows.
17
~'OR OFFICIAL USE ONI,Y
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APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-00850R000300074445-2
r
~
FOR OFFICIAL USE ONLY
1. Preparation for operation: powering up, sequential depression of buttons
, "Inhibit G", "dump", "Start", "Dump", "Start"; "Operate" light indicates the
= device is ready. -
�-7, SK..____.
o ~o ~ N 2fOx~ +SD~
- ~ ~ x . k ~ ~ ~ ~ ~ ssin~~ i . ~ 5610~1~di .
~ ~ ~ ~
~ "
I
- �~oma~~ 3an f~~ cJ~~ �/l;~t~r~' l1Al 9 ~~ax J I n,~a 510~ -
XC1:A1? A1 Q -
J 3f' Xt1~A10 XC4~613 t~ 6 ~61 XC4:G17
L4 IUAW ~ t DC
1~ 38 31 .~5 36 ~AG XCi:~l11 ~p ? e E? ~ 4~A2
- ~ 1 XC1 ~ 677 ' . XC4%6l4 4 ~ p _ , r_t4'6!
? M8 ,
/ND ME � UN13 � i s t XC4~A~4
- ,fC4~Al1 ~t
XC1:Aid U~~ C u XC ~A20
39 ~ 3n ~ o ~ B6 XC4:64
~ i ~ e 9 & 3/0 311 X~4:A1J ~ t XC4:A~9
i 1 io 9 n n 8 r~ XCt:619 ~ ~
? ~ Bd XC4~6.~
1 ' 2
) n A ~ ~ ~ n~ XC1:Al5 XC4~6e 6 nCk:67
ru e
~ s~~ ~ s g 313 1 g 315 (!lAIO S J ~ ~ . XC4;A9
- S 6 a n 3w ~ XCf:,~f4 XC9:A3 ~ ~ p XC4:~lI
6 7 ~s 6 i !lUJ 6
n � XC4:A1?
~ i6 f ~ /lAd ~ IIA~ ' A7 9~
XC9~616 M XC4AI6
�SA ~ UTAO C ~s N5 � XC4~671
300 300 300 300 300 J00 J00 300 $ M6
`C~ ~ `r XG4:61B 6 N1 8 ~ g ~ XC4;A17
- Gn, pa~a na , nr Mnpa~p. 3a~onc~Sl d N6 3x XC4~6f9
~ ~ ^ ~ ~ ^ ~ NJ ~ Al6 ~
~ ~ ~ ~ ~ ~ ~ ~ xc~:~a
~ ~ ~ ~ ~ ~ ~ ~ 39
~c ~ k ~ ~ ~ ~ Md .
Fig. 1. Debugging console. Fig. 2. Debugging memory. -
2. Input of a hexadecimal number into the information buffer (BI) (common
register R5) of the microcomputer which is accomplished by the sequential
depression of buttons 0-F (see Figure 1), starting with a high-order bit St. razr;
the low-order �byte of the BI is monitored by LEDs L1-L8.
3. Recording of the base address upon entry or read-out of information whose
initial byte address is input into the BI of the microcomputer; the contents of
the BI is transfered to the address buffer BA by pressing the BA button (common
register R6).
4. Byte entry of information into main memory of microcomputer; the
information byte is selected; the contents of the low-order byte of BI is entered
according to the BA address by pressing the ftOM button; as a result, the BA
address is automatically increased by "+1" and a new value of the BA address
is indicated; the high-ord~r byte is recorded in the memory cell first if it has
an even address; information may be input into the internal main memory
accordi~g to the addresses OOOE-OOFF.
5. Byte read-out of information from microcomptuer memory. The code of �
the information byte whose address is indicated in ~A is monitored with the
LEI by pressing the button ChT; it necessary to eqrrect it, a new byte value
18
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APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300074445-2
FOR OFFICIAL USE ONLY
is input into the BI; replacement of the byte address is executed by pressing the
= ROM button.
6. Transmission of control of the debugged program is a~complished by
pressing the button SCh; the contents of BI is recorded in the instruction
counter.
= 7. Transmission of control to the console exchange routine, executec~ by
- sequential depression of the buttons "Dump", "Start".
To realize off-line debugging device it is necessary to have the following
components: microcomputer "Elektronika S5-11" with power source connection
circuit; stabilized voltage unit +24, +5 and +1.5V (0.7, 0.5 and 1 mA,
respectively); type 155LA2, 155LA3, 155LA6, 155I~A8, 155ID3 and 561PU4 ICs;
AL307 or AL102 LEDs; triggering and switching buttons; point diodes of any type
or diode assemblies; MLT 0.125 resistors.
It should be noted that the equipment part of the device may be simplified if
- there are more convenient components available (e.g., when 561LN1 micro-
circuits are used in the interface cireuits the number of storage diodes is
- reduced by 50, and the use of the 155RYe3 component greatly simplifies the
memory unit).
The off-line debugging device proposed in the article for the "Elektronika 55-11"
_ microcomputer was realized in studies of the Volga-Vyatsk Regional Center for
Debugging and Application of Microcomputers of the family "Elektronika S5" and
has been successfully used in practice.
COPYRIGHT: Izdatel'stvo "Mashinostroyeniye". "Pribory i sistemy upravleniya",
1980.
[43-861?]
8617
CSO: 1863
19
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APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300074445-2
FOR OFFICIAL USE ONLY
- UDC 681.327.2.082.5
SEMI-P~:RMANENT OPTOELECTRONIC MEMORY
- Moscow PRIBORY I SISTEMY UPRAVLENIYA in Russian No 9~ 1980 pp 28-29
[Article by L. P. Chaykovskiy, engineer]
[Text] The first attempts at creating semipermanent computer memory with
light-pulse sensing of data were undertaken back in the early 1960s [1].
However, only the latest developments in high-speed emitters, photoelectric
sensors and fiber lightguides have made it possible to develop semipermanent
optoelectronic memories (POZU) with high operating values (2-5).
A typical aspect of the fiber-optic system of this kind of device is that it can
be used to create a meomry with an information capacity equal to the number
of emitters times the number of photoelectric sensors. In this case, the
- fiber-optic system consists of two light guide subsystems, the first of which
interfaces emission with the mask and the second tra~smits it from the mask to
the photoelectric sensors. This POZU deisgn has substantial shortcomings,
however, which diminish its values (density of information recording, speed,
overall dimensions). The most serious shortcoming is the presence of a
- discontinuity in the fiber-optic channel which predetermines increased optical
losses as compared to a continuous light guide of the same length. They are a
funetion of the magnitude of the gap between the lightguides and the solid angle
of intercept of emission passing through the information mask, which in turn
decreases with decreasing light guide diameter.
In addition to losses due to reflection upon entry into and emergence from the
lightguide, these losses may reduce the level of emission energy flux acting on
the photosensor to less than 1/10 of its initial value.
In this article a POZU system is described in which, in addition to retention of
the relationship between information capacity and the number of optronic
- components (emitter and photoreceivers), a reduction in emission energy losses
is guaranteed (Figure 1). This is achieved by structural features of the
fiber-optic system consisting of regular light guides (RS). Each of these in turn
consists of individual single fibers. The arrangement of individual fibers forming
- the input end of the RS corresponds to the arrangement configuration of the
information positions in the mask.
Light channels (SK) of the single fiber in the input end form a discontinuous line,
i.e., the part of the information mask surface corpprising a POZU word is
line-scanned. Thus each SK meets one series of 'sensed words. The light
channels on the output side of the RS are collected ~nto a packet forming the
20
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i
FOR GFFICIAL USE ONLY
matrix; while the SK entering into one of the matrix columns ab~t against one
of the photosensors of th~ receiving matrix. The information mask is arranged
in the frontal plane of the input ends of the RS. Excitation of one emitter _
_ makes it possible to sense information word by word on the same matrix of
photosensors. -
1 2
. �
OQ ~ ~ 4
V
_ OQ ? J '
Figure 1. Structural diagram of POZU: -
1) LED matrix; 2) information mask; -
3) fiber optics system; 4) photodiode
matrix.
1 7 4 , S
. _ , -L.. ~ .
. . _
.
6 7
- Figure 2. Block diagram of POZU control:
_ 1) decoder; 2) current pulse shaper;
3) LED matrix; 4) photodiode matrix;
5) wide-band amplifiers; 6) decoder X;
' 7) switching circuits.
p 3 4 S
~
~
, 0
.
.
~J
\
~ Figure 3. Structural diagram of mask generator:
1) LED matrix; 2) single fiber; 3) fiber-optics
system; 4) diaphragm; 5) photosensitive chip.
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The manufacturing technology of these RS, from which the system is later ~
assembled, is n~ more difficult than that of ordinary RS for image transmission -
and furthermore, it can be automated.
- In this lies its substantial differenc~ f~om known schemes of POZU design {6]
- where the logical positions in the information mask are connected to the
photosens~r matrix, since here we assume individual laying of lightguides.
Evidentl,y this design, with an informAtion ~a~acity of more than 103 bits (and
consequently, inclUding individual laying in the fiber-optics system) becomes
really impracticable due to the extremely great labor-intensiveness of manu-
- facture. At the same time, the fiber-optic system in this POZU design may be
- enlarged by increasing the number of base RS, which leads to increased packet
- height and increased number of SK forming a single column as well: the "tyranny
of numbers" problem is eliminated.
A polymer lightguide RS was used as the base element of the fiber-optic system; _
several of its parameters are better than those of glass lightguides; it has a
diameter of 0.1 millimeter and length of 200 millimeters. Each RS contained
100 individual SK (single fibers). The input end of the RS has an area ef 3 x
3 square millimeters, on which are arranged 100 (10 x 10) input ends of the
individual single fibers with a spacing equal to 0.3 millimeter. The input end of
each RS is located 2 millimeters from its neighbor. The fiber-optic system of
400 RS arranged in a 20 x 20 matrix has a transverse dimension of 100 x 100
square millimeters.
When a photosensitive chip 100 x 100 square millimeters is used As the
information mask, a POZU capacity of 4 x 104 bits is achieved; it is recorded
- in the foxm of individual words on the surface of the photochip. The distance
- between individual words is 2 millimeters. The presence of such intervals makes _
it possible to eliminate crosstalk between continguous sections of the photochip, _
though it also reduces effective information recording density.
GaAs lightdiodes with rated emission output of 10 mW at 100 mA (type =
AL 107-B) were used as the emitters. The control circuit, consisting of
_ decodersY excitation current pulse shapers and switches, ensured selection of one
the lightdiodes of the emittier matrix (Figure 21), whose emission was covered =
~~y i; e opposite sectio~ of the information mask which contained one word.
The matrix of photosensors consisted of 100 Si photodiodes with a sensitivity of
450 microamperes/mW, intrinsic capacity of 10 pF, dark current of less than 10
nA. Each of the 100 photosensors was loaded with 1 kohm. Parallel sensing in
' 100 chanitels makes it possible to reduce stray noise between elements of the
photosensor matrix to the minimum and obtain high reliability of informat~on
- sensing aYid speed.. '
The entire process of decoding and excitation of the transmitting matrix, _
depending on the type of lightdiode, lasts 50 to 200 nanoseconds. The total -
access time is 70 to 250 nanoseconds, which is defined by the speed of the
lightdiode. The signal tapped from the load resistor in the photodiode circuit ~
- was ~~mplified by a wideband amplifier with gain from 3 x 102 to 103.
22 -
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Because the information mask manufactured using a phototypesetting machine
can be easily replaced, the reprogramming of POZU presents no problems.
Based on the fiber-optic system of the POZU an information mask generator was
also developed whose strucfural diagram is shown in F~gure 3. Series and
_ parallel excitation of LEDs situated in the photodiode positions, where the -
_ diaphragm has an area equal to that occupied by one word in the front plane of
one input end of the RS, made it possible to expose the photochip placed behind
the di~phragm. The diaphragm was shifted to align witt~ the input end of a -
_ second RS to record the second worc~.
~ References
_ 1. Goffman, G., Dzheffreys, D. Permanent computer memory with data
sensed by light pulses, In: OpticheskRva obrabotka informatsii [Optical
- processing of information), Moscow: Mir, 1966.
2. Optical memories, RADIOELEKTRONIKA ZA RUBEZHOM 43 1971 p 18.
- 3. Osinskiy, V.I., Chaykovskiy, L.P. Principles of design of semipermanent
memories based on grid-type and fiber-optics systems. In: Vychislitel'nay~:
tekhnika v mashinostroyeniy. Vyp. 1. PJlinsk: ITK AN BSSR 1974.
4. Al'tman, L. Achievements in optoelectronics. ELEKTRONIKA 45 No 4 -
- 1972.
5. Osinskiy, V.I., Chaykovskiy, L.P. Optoelectronic semipermanent memory
with optical switching. In: Avtomatika i vychislitel'naya tekhnika. Vyp.
7. Minsk: Vysheyshaya shkola ~977.
- 6. Styuart, R.D. Optical memories. ELEKTRONIKA 39 No 4 1966.
_ ~OPYRIGHT: Izdatel'stvo "M ashinostroyeniye". "Pribory i sistemy upravleniya", -
_ 1980
(43-8617J
8617
= CSO: 1863
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UDC 681.327.12 -
TOUCH-SENSITIVE DATA ENTRY KEY PADS ~
Moscow PRIBORY I SISTEMY UPRAVLENIYA in Russian No 9, 1980 pp 31-32 -
[Article by A. I. Chebarev, V. N. Revenko, candidates of technical sciences; A.
- A. Am'_rdzhanov, D. L. Kamt~lov, E. N. Farzane, engineers; and F. Ya. Agayaev, ~
_ mechanic]
- [Text] Touch-sensitive (sensory) keypads have lately found wide aQplication in -
_ man-machine systems [1] in which information signal activation (FIS) is done by _
the operator's touching the metallic keyboard surface which has an electronic
circuit with a relay output characteristic. Analysis of existing methods of -
desig~~ of these keypads has shown that FIS realized with impact excited
- oscillation loops are the most sensitive and reliable circuits [2j. This method may
be utilized in designing keyboards. If is necessary to enter a small number of
_ functional control instructions, however, it is advantageous to use FIS circuits
- similar to those dsscrib~d in study [3]; the latter are made in the form of
individual modules.
_ The basis of the FIS whose electrical circuitry is shown in Figure 1 is a
self-excited oscillator AG in the oscillation loop, which reacts to human
_ interaction by abruptly decreasing oscillatory amplitude. The signal from the
= self-excited oscillltcr AG reaehes a threshold device PU which consists of an
emitter follower, an equalizing capacitor C and a switching circuit which
transforms the oscillation of the self-excited oscillator AG into a low-level
voltage signal without operator intervention and a high-level signal when he -
intervenes. The entire FIS circuit of the keypad module is contained in three
transistors Vl-V3 of a type K1NT251 type transistor assembly. -
The electrical_ circuit of a touch-sensitive data entry keypad TK is mounted on
~ two PCBs inserted into special grooves inside the keypad housing, which is made
of an insulating material (Figure 2). The housing base contains pin-type leads
~ to connect the keypad to the control unit. At the end of the keypad module
there is a contact surface connected to the FIS circuit which the operator
~ touches. This area is available in two ver~ions: as a metal plate or as a _
- current-conducting section applied on a transparent glass substrate. In the ~atter
: case a notch is cut in the end of the module and a replaceable template
_ indicating its functions is inserted.
The touch-sensitive keypad module developed by the Azerbaijan Institute of -
- Petroleum and Chemistry imeni M. Azizbekov has overall dimensions of
20 x 20 x 65 millimeters, which fully coincides with the dimensions of
_ electromechanical hermetic capacitor keypads usea in standard data entry
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keyboards in computers and data display devices. This structural execution of
the touch-sensitive keypad makes it possible to replace the mechanical contact
keypads with touch-sensitive ones without redesigning the consoles; this
increases the ~perating reliability and service life of the latter.
- r~ r---~ ,
I I ~ p ~ ~ lJY SB
~
sto . I j r2 ti j I ri n I
S � 0 I I ~ S !
v~ ~ s ~Ip~ _
. I
I ~
I ~ ~ ~ ~K j ~ i ~ ~ ~ -
I lK .f3 ~ I~RJ~r i ~ Q/~ ~
I ` ~
_ ~ i ~ i ~ ~ _
�---------J
~K
- Figure 1. FIS Electrical Circuit.
D) detector; C= 0.015 pF.
- v:.
r: �
. ;
, . 1~; ~;:'~~~p,,, r
.
Figure 2. External appearance of a touch-sensitive keypad.
In view of the fa~ct that this FIS circuit is a source of high-frequency noise, the
housing of the keypad module is shielded to eliminate it.
The touch-sensitive data entry keypad described here has the following eleetrical
parameters: output signal level with operator int~rvention Voutl g'~'eater than or
- equal to 4.5 V; without opprator intervention V~out less than or equal to 0.4 V;
~ output current Ilout equals 16 milliamperes at supply voltage of 5 VAC + 10
_ percent and AG self-excited oscillator frequency of about 600 kHz in a range of
operating temperatures from -10 to +60�C.
References
1. Yel'yashkvecih, S.A., Avtomaticheskoye upravleniye v televizoraith (Auto-
matic control in televisionsl, Moscow: Energiya 1975.
- 2. Chebarev, A. I., Amirdhzanov, A. A., Kamalova, D.L. Questions of analysis -
- of touch information activation. In: Problemy peredachi i preobrazovaniya
informatsii. Kiev: IK AN USSR 1977.
3. Chebarev, A.I., Revenko, V.N., Amirdhzanov, A.A., Kamalova, D.L.
Pre-CRT touch-sensitive data entry panel. PR.IBOftY I SISTEMY UPRAV-
LENIYA No 6 1979.
COPYRIGHT: Izdatel'stvo "Mashinostroyeniye", "Pribpry i sistemy upravleniya",
1980 ~
[43-8617] -
8617 25
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SOFTWARE
LANGUAGES OF REALIZATION FOR SYSTEMS PROGRAMMING
Novosibirsk Y~IZYRI REALIZATSII DLYA SISTEI~IOGO PROGRAMMIROVANIYA in Russian
. 1979 signed to press 28 Nov 79 pp 1-15, 18-24
fPreprint by I. V. Pottosin, Computer Center of the Siberian Branch of the
USSR Academy of Sciences, 130 copies, 24 pages]
[Excerpts_] _To define the sub~ecC. of ttie_ wor~k,~ one~ has to define what grop~r-
ties.�we ~hall consider determining for ~ys_Cems prcigraimning~ and what..class of
_ languages we will take~for consideration,.
= 1. Characteristics of Systems Programming. A factor in the evolution of
information science in the latter half of the sixties and in the seventies -
is the isolation of the independent course of systems programming, with _
� crystallization of the questions of its problems and methodology. Consider-
ing systems programming a key discipline in information science, Seegmeuller
[lj defined it the following way.
- ~ "Systems programming is the field concerned with the description, design,
properties, representation and functioning of specific sets of system algo-
rithms. These sets of algorithms realize the linguistic and operational
interface of a computing system under certain limitations, optimizational
and dependent on the environment."
This definition of systems programming is somewhat indistinct; hoGrever, in
our view, it can be taken as a first approximation, the refinement of which
we shall engage in in thase respects which we will consider necessary for
the needs of this work.
Let us define a number of aspects of systems progra~ing, important for
further presentation, concerning its immediate program product.
Based on this def inition, systems programming, as a rule, is a tool; its -
- products are not directly applicable to solving some problem, but are used
~ to provide a description of this solution. The link between systems pro-
gra~ing and the technology of programming is organic, and the correspond-
ing concepts have to go into the descriptive facilities of systems program-
_ ming. By virtue of instrumentality, system prograriming products have to '
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create an environment for themselves or access particular fragments direct-
ly, while the link to the environment in applications programming is indi-
rect and implicit.
Systems programming does not create isolated programs, but /program systems/ .
(spaced for emphasis]. This aspect, which is becoming more and more pro-
nounced in progra~ning in general, is all the more essential for systems
programming. The components of these program systems are quite heterogene-
Qus to satisfy the dive:se requirements of the users. Thus, for example,
a transla[or is not created for a user, but a prograffining system that in- -
cludes a translator as a basic, but not the sole part, and that contains a
number of components that meet other aspects of creating programs, different
from just an expres5ion of an algorithm in a given programming language,
namely, modifications, debugging, packaging of programs and so on. This
dictates special attention to high-leveY facilities for program interface. -
As a rule, a systems programming product either creates some program for a =
given specific machine and specific system, or realizes some execution with �
a dynamic link to an external medium, determined both by the computer in-
stallation itself and by the devices linked to it. In connection with this,
- the element of machine dependence for systems progra~ing is substantially
more important than for applications programming, the product of which, as
a rule, processes some machine-independent information (with a precision
up to the representation in the machine carriers).
It is characteristic of a systems programming product that it is used in
- some standard cycle of work on a computer which indicates the relatively
high frequency of its execution and considerably increases the requirement _
for efficiency of the product (naturally, we are talking here about an end
product, and not about experimental systems or test versions).
It is precisely systems programming that primarily deals with large pro-
gram projects (large both in the size of the program product and in the num- -
- ber of developers), for which the duration of development is important by
virtue of the variability of the collective of developers and the evolution
of the program system itself. This aspect of systems programming consider-
ably increases the requirement for documentability and understandability of
its product.
Thus, to properly define the descriptive facilities that systems programming
languages should possess, one has to consider that systems progra~ing pro-
ducts are:
- tools in some technology of problem solving;
multicomponent systems of programs;
creators of programs or realizers of execution;
elements of a standard cycle of processing cf information; and the
- results of a multiyear effort by a changing collective.
- 2. C1ass of Languages Being Considered. Programming languages may be di-
vided into three types according to their function:
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J
. Languages oriented to specification. These languages are intended primari-
ly for fixation of the problem itself, and not the algorithm of its solu- -
- tion; described in them is /what/ has to be executed rather than /how/ it
is executed. (//=underlined] Such languages are the so-called languages
of a very high level (for example, SE'~L) or languages for formulating a -
problem for specialized intellectual packages of applications programs.
Languages oriented to algorithm description. The purpose of these langu-
~ ages is fixation of an algorithm in some abstract form not associated with
~ the specif ics of realization. Examples are the widespread high-level al-
gQrithmic languages (from FORTRAN to ALGOL-68). Of course the semantics
of ex~cutic+n in these languages may be described by some abstract machine;
however, in level of concreteness, an ALGOL-machine or PASCAL-machine is
significantly different from a real computer.
Languages oriented to realization. Reflected in these languages are the
concepts and properties associated with concrete realization such that a
program in these languages already contains in an observable form the ne-
cessary details of realization. The simplest examples of these languages
are the mnemonic codes (ASSEI~LER languages); the more developed languages
of this type are the so-called high-level macttine-oriented languages
(MOYaW), which we will discuss later.
Of course it would be more precise to speak of the orientation of the
given desc�riptive facilities, and not of the orientation of the language
as a wholP, since there may be intertwined in a concrete language both
facilities oriented to specification as well as facilities oriented to
rcalizatiaa. Thu~, i~ u~?c intenrinn~lly limi:s ~imself in using th~ possi-
- bilities of the SETL language, the resulting program will diifer little
from an ALGOL program, and the designation of the number of bits or bytes
in a value, as a data type characteristic, for example, in PL/1, or use of
mnemon{~c code statements in AL'FA-6, predetermines the realization. At the
same rime, the determining set of descriptive facilities always allows us
witho~ut any great question to place a given language in one of the types
mentioned above.
On the other hand, for a certain class of problems or area of application,
we may speak of /languages of realization/ as those languages in which a -
final program product is created (in contrast to /publication languages/,
in which a description of a problem or algori~hm is fixed with subsequent
nonautomatic conversion of this description into a final program product).
Thus, it is ~e1Z known that very high level languages are used as realiza-
tion languages for experimental artifical intelligence systems; however,
more often� these languages are used as publication languages, as an inter-
mediate foz~m, ~hich is then (after debugging and fir:ishing) manually re-
written in~o some "lower" level language; ALGOL-68 is sometimes used not
as a realization language, but as a language in which there is fixed a pre-
- program description of algorithms and data (at the level of technical de- =
sign, for example); in the majority of cases for problems associated with
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_ computational mathematics~ suitable language:, for realization are the high
level algorithmic languages, since the specification of realization is
- often not so important for computational problems.
In this paper, we intend to discuss what should be the linguistic tools of
systems programming based on the current, knowledgeable systems program-
ming users. Let us note at the ouset tk~at we shall not be discussing lan-
guages of specifications t;~at may be used in some stage of development of
a program product for experiment~ with algorithms under development. Like-
wise, we shall disregard specialized languages that are used for a rela-
tively narrow class of problems of systems programming, for example, as
languages for describing certain characteristics of input languages in sys-
tems for constructing translators. Of course, these as well as other lan-
guages are useful tools; however, we shall dwell only on general-purpose
realizati~n languages for systems programming.
- We will not conceal that it seems to us that systems programming realiza-
tion languages of necessity are languages oriented to realization. An at-
tempt to take as a realization language---just as for a number of areas of
_ applications progra~ing--~a high level machine-independent language cannot
be recognized--in any cas2 for the current level of understanding of the .
problems of both languages and systems programming--as satisfactory in all
respects. The comhination of machine orientation and high level descrip-
tive facilities in realization languages is emerging as a quite successful
ans~er to current systems programming prot~lems--this thesis ~as defended
- by the author in his work ~2], A similar thesis ~z-as suhstantiated earlier
by W. Wulf in his ~tork [3].
3. Necessity of Machine Orientation and High Level. Por a long time, the
primary tools for systems programming were assemblers and macroassemblers ~
(and e~ren now they are used quite extensively for the purposes of systems
~ programming}. While providing the capability of creating eff icient pro-
grams, these machine-dependent systems essentially offered no transfer-
ability, made the process of programming itself complicated and offered
few possi.hilities for understanding the text of a program. These short-
comings stood out quite saliently vh.en compared to high level languages,
from which assemhlers differed aTiove all by the lack of a clearly visifile
program structure and poor semantics of permissifile information o5jects,
Macroassemhlers did not change the situation very much since the particular
- great compactness of the programs (compared to assemblers) made them
neither clear nor nat~ural---to the extent achieved in high level languages.
'i'he attractiveness of high level languages in these respects gave impetus
to their fieing used as systems programmin$ languages. Attempts were made
- to use even FOxTRAN and ALGOL-60, but since their utility for general pur-
poses is not very great and they are oriente3 primarily co pro~lems of com-
putational mathematics, extensions of them were used as systems programming
_ languages. The emergence of substantially more general-purpose high-level
- languages, such as PL/1 and PASCAL in particular, yielded more useful
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examples of their use as real systems programming languages (see the analy-
" sis of the poasibility of using these languages as tools for systems pro-
gramming, for example, in work ~4]). But despite the number of successful
applications of these languages for systems programming needs (what is
meant here is not their use for purposes of specification and finishing of
algorithms, but for obtaining a final program product, i.e., as realization _
languages), they did not substantially crowd assemblers and macroassemblers
in systems programming. It seems to us that as realization languages, the
- high level machine-oriented languages in which there is a rational combina-
- tion of bcth a number of the descriptive facilities of the high level gener-
, al-purpose languages and the specific possibilities of machine dependency
that characterizes assemblers and macroassemblers ha~e become their real _
competiitors. _
Let us note first of all that the concept of machine orientation does not
mean so fundamental a machine dependency and so fundamental a connection
witti the format and composition of machine instructions that there is in
assemblers. Machine orientation includes the semantic association of langu-
age concepts with such characteristics of concrete machines as the structure
and length of a machine word, the system of addressing, the availability,
methods of use and function of registers and the like. Machine orientation
of a language, therefore, does not preclude some possibilities of transfer-
ability of programs written in it, and we will later discuss the possible
methods of transferability. We shall also include in the concept of ma-
chine orientation a number of semantic links not with the machine itself,
but with the operating system--with the organization of channel operation,
syncronization and so on.
One of the determining arguments in favor of machine orientation of systems _
programming languages is the criticality of the requirement for efficiency -
on its products. For systems programming problems, not only selection of
the best algorithm is important, but also thorough realization of it, using =
all the capabilities and features of a given machine and its operating sys-
tem. As the experience of using high level machine-oriented languages in
systems progra~ing problems shows, they yield in this respect essentially
the same capabilities as assemblers (but a similar comparison of assemblers
with high level general-purpose languages, as a rule, is not favorable to
the latter). Taking the concrete features of a machine into account when
formulating algorithms by using machine-oriented languages enables the pro-
. gram originator to control the thoroughness of realization. It is important
to note that, as a rule, there is a quite clear correspondence between the
- concepts of these languages and their machine realization, while in high
level general-purpose languages, the semantics of input constructions is _
formulated in terms remote from the semantics of constructions of the
object program.
While for a number of applications areas high quality of object programs and _
good consideration of the features of realization can be achieved through
automatic optimization of programs, the methods of optimization are still
insufficiently developed for systems programming. Although the only well
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known optimizing programming system for machine-oriented systems grogram-
ming languages--for the BLISS language (5]---uses a quite developed optimiza-
tion technique, in our view it does not remove the need for clear concern
for realization, but only eases this concern somewhat. Metho3s of formal
description of machine-oriented optimization now under development based on
_ realization of BLISS may make some progress in this area. Let us note that
global optimization rather strongly distorts correspondence between input
and output constructions which may be essential for systems programming and
as a rule unimportant for applications programs. ~
It must be said that an argument for machine orientation of no little impor-
tance is the so-called "internal" machine orientation of algorithms for sys-
tems programming--they are often not only in the form of expression, but
also in producible work associated with some coacrete machine, and "know"
its characteristics and its language. Translation algorithms are like that
for example--in any case with respect to the object code generation stage.
A rather complete reflection of the various characteristics of a machine,
channels and external devices is also contained in many algorithms for
operating systems. In comparing systems programming with applications, one
may, though somewhat roighly, note their difference in the aim of applica-
tions programming being to develop a description of an algorithm for some
processing of information, and in the aim of systems programming being to
create a description of a program that has to be executed in some concrete
environment--on a specific computer, within the bounds of a specific
operating system, etc.
We will put into the concept of high level of languages the natural format
of statements not associated with the format of machine languages, and the
development of facilities of the task of control structures in the program
to adequately develop the semantics of information objects and other lin-
guistic capabilities that we will discuss later--i.e, namely those facili-
ties that provide facilitation of progra~ning and understandability of pro-
= grams, and that means--the documentability and modifiability and other re-
quirements on the program product of systems programming not being provided
- by assemblers and macroassemblers (as Wirth said: "One of the aims in de-
veloping PL-360 was to inspire the user with the capability of writing
clearly and understandably while permitting full use of the 360 system
equipment features" ~12]).
With respect to systems programming realization languages, raising the level
of the language does not lead to substantial acceleration of the process of
programming proper and does not reduce the requirement for programming skill
of the developer as occurs for applications programming since this rise is
not accompanied, as a rule, by removal from the peculiarities of realization,
form machine orientation, from concern for realization and representation
of data. High level machine-oriented languages require good programming
skills and the ability to express in their terms the realization approaches,
but for the programmer with /high/ skills, they enable making the program
clear, readable, understandable and modifiable, reducing the number of mis-
takes and facilitating debugging and verification.
.
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4, Two Generations of High Level Machine-Oriented Languages--Brief Review. -
Just as for high level algorithmic languages, for which the isolation of a
~ first (FORTRAN, ALGOL-60, COBOL, etc.) and second (PL/1, SIMULA-67, ALGOL-
68, PASCAL, etc.) generation is natural, one can pick out two generations
of languages for high level machine-oriented languages. In general, t~:e
emergence of high level machine-oriented languages sufficienCly usable for
systems programming needs dates back to the second half of the sixties.
First generation language examples were ALMO ~8], EPSILON ~10] and PL-360 -
_ [14].
In ALMO there are a number of important features of machine orientation
with overall machine independence. These features are, for example, selec-
tion of. types of storage and among them--index registers, and assignment of
sizes of values in terms associated with the size and dividing of machine
words. Some unnaturalness of constructions of ALMO (reverse Polish notation _
of expressions, for exampie) was dictated by the language being intended not
- only in particular for description of the translation process itself, but
also for an intermediate language of translation.
The semantics of statements and objects of EPSILON were consciously and
openly interpreted using a realization expression by constructions of ma-
chine language--so-called images. In part the semantics in EPSILON are
associated with types of statements and with assigned structures, but full
semantic definiteness is assigned by the image. Thus, a statement of the
form a[i]: = a[iJ + 1 -
in EPSILON is interpreted as a change per unit of value of some position of
a machine ~rord if th~s value had been earlier derived as a positive whole
number. But if this is not so, then the execution of this statement could _
be attended to only from the image compared to the replacement operator and
selection of a(i]. Values in EPSILON do not have types, i.e., interpreta-
tion of a value is fully determined by operations. Control statements in -
EPSILON are primitive and limited to conditional and unconditional jumps
(almost as in FORTRAN). Data structures are associated with the sequence
~ of machine words, divided perhaps into syllables of arbitrary length.
PL-360 had advanced facilities for control structures and quite good corres-
pondence of types of variables to formats of machine representations--pre-
cisely the features that served as the basis on which a numher of production
tools were developed for systems programming for various machines. Sust as
EPSILON, PL-360 permits easy establishment of correspondence between con-
structions of the language and their realization--thus statements for repe-
tir_ion and selction as a control variable may be only that which has been
correlated with a register; in the permitted types of values (byte, short
integer, integer, real, long real), the standard formats and types of the
IBM 360 machine language ate easily attended to. Expressions in PL-360
(just as in EPSILON) are interpreted as notation of corresponding instruc-
tions--they do not contain parenthesis hierarchy and precedence of operaCors,
to the extent that execution of the statement
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R1: = R2 + R1
(R1 and R2 are designations of registers) is interpreted as the execution
of the sequence
~ R1: = R2; R1: = R1 + R1.
PL-360 data structures are limited to linear sequence of the elements of
the format indicated.
The BLISS language (6], which emerged at the very start of the seventies,
is an example of second generation languages--it contains new, with respect
- to the preceding languages, capabilities as advanced forms of expressions
and flexible capabilities for introducing data structures. Just as in
= EPSILON, BLISS values have no types, and in values one can consider values
formed by a group in succession of the arranged positions of a machine word
(but not as a described syllable structure). Expressions (and not state-
ments) are in BLISS the basic construction of the language which coincides
with machine orientation in the sense that calculation with an expression
retaining value may be represented by remanent states of the machine regis-
ters (the adder, in particular). BLISS has advanced control statements.
An important BLISS feature is the description of the access function. Thus,
a description of the form
struct ar2[i, jJ = (.ar2 + (.i - 1)x10 + (.j - 1))
associates with the name ar2 the actions corresponding to locating the ad-
dress of the element of the array with 10 columns (the period before the
identifier means taking the value according to th~ address associated with
the identifier--in BLISS taking an address and taking a value according to
an address are syntactically different). If after this description we in-
troduce a description of the form
o~ xiloo~, yfioo~, Ziioo~;
ma ar 2 x: y: z;
which define for each of x,y,z the allocation in sequence of 100 machine
words and association with the structure (access) ar2, then the statement
x[.k, .1] - .y~.l, .k]
assigns the transfer of the value from the element with indexes 1, k of
array y to the element with indexes k, 1 of array x. Although BLISS was de-
signed for the PDP-10 and contains elements of some machine dependence
(calculation with specific length of a word, consideration of the existence
of registers and the like), these elements are not very significant--there
are versions of BLISS for the PDP-11 and the IBM series.
_ The YaRMO language [15], developed for the BESM-6, took a number of the im-
portant features of BLISS such as the expression as the basic construction
of the language, described functions of access, control facilities associ-
ated with structured programming, etc. Operating with data structures
underwene further development in YaRMO--in addition to structures with a
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describable fur~ction of access in the lan~uage there emerged notations that -
develop syllable partitioning of a machine word of the EPSILON language; in
contrast to BLISS, one may have for the same structure a different function
of access and function of notation [16]. Intermodular associations are
. described more flexibly than in BLISS. ~
In the LIS language (17J, machine orientation and machine dependence are
concealed completely. Outwardly, this language looks like a high level
language oriented to algorithm description. At the same time, there are
syntactically isolated fragments for description of realization of data re-
presentation in which different facilities of indication of machine depen-
dency are permissible. But access to data elements does not depend [18] on
the realization of their presentation.
The development of systems programming languages has still not found des- _
criptive facilities adequate for a number of practical needs--in any case,
to the same extent as development of general-purpose algorithmic languages
for the needs of applications programming. Let us discuss some properties
of realization languages important to systems programming and try to point
out these unresolved problems.
5. Data Structures and Their Realization. Flexibility of operation with
data structures is a major requirement for systems programming languages.
Of course this requirement is common with respect to modern programming
languages; however, the specific nature of systems programming lies in that
not only the wide range of information structures must be considered in them,
but also the peculiarities of their machine representation. On one hand,
there should be in the language an adequate set of types of values, and
assigning types to objects of the program unquestionably provide~ good cap-
abilities for statistical verification of semantics and f lexible understand-
ing of operational signs; on the other hand, we should, if we want to, con-
trol machine representation of values and sometimes have the capability of _
inteY~preting these machine values of variables a different way (for example,
sometimes as bit, sometimes as symbol, sometimes as integer~. As for data
structures and set of types, one of the most successful languages in this _
respect as applied to systems programming is PASCAL; the various examples
- of its application to systems programming problems indicate the sufficient '
naturalness of these external facilities. Among the successful features of
PASCAL are the capability of assigning a system of coding for objects of
the scalar describable type and of introducing notations ~ith variarits.
Assignment of interval types and describable scalar types in essence also
provides certain determination of the realization of representation of
values and arrangement of elements of notation in a machine *~rord. Further
= development of PASCAL notations in LIS led to inclusion in notation as ele-
ments of procedures of operation with components of notation.
It is also traditional in the practice of systems programming to treat one
and the same binary value as a value that may be referred to different con-
tent types and generated by various formats of a machine word. This also
- causes lack of standardization in realization languages such as EPSILON,
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BLISS and YaRMQ. In limited cases (e.g,, treatmenr. of ref erences as inte-
ger), this also occurs in LIS. The variety of formats that may be "put" ~n
one and the same value is eff ected by describable partitioning into sylla-
bles in EPSILON and YaRMO. '
~
In PASCAL, the assignment of a system of coding does not determine the bi- -
nary values of codable values of the scalar type. LIS introduces (only in
the realization part) the cap ability of explicitly assigning coding binary
values. In EPSILON, one can i~troduce not only explicit representation of
coding values, but also of classes of machine representation--so-called ~
- codes, and a set of values fo r which there is assigned either a range of -
binary values or identifying binary features in specific positions of the
machine representation. .
corstructiou of a program with detailing development even in BLISS
one has to implement not automatically, while such actions could be -
automated.
_ Along with detailing development, a popular method of providing segment- '
ability when developing comp lex programs is modular programming. It also
serves as the basis for development of. packages and complexes of programs.
- The fine analysis of the prob lems of developing modular programs, made by
Goos and Kastens (23J, showed that the majority of programming languages do _
not have convenient capabilities for expressing a modular structure and in-
termodular associations. This may be attributed to the primitiveness of
~ existing rules for localization in languages not providing the needed flex-
ibility in providing a link b etween the module and the environment. In
building both a hierarchy of modules and a family of modules, ure have to
_ have convenient facilities for snecifying an interface with sup~rmodules
, and submodules and with adjacent modules in a set; for this, one has to re-
, gulate protection and access to local and global objects (data and proce-
; dures). It must be said that many of the realization languages for systems
, programming inadequately support modular programming ~ust as liigh level al-
' gorithmic languages--in BLISS, for example, intermodular associations are
organized, just as in conv+en tional mnemonic codes, by the indication of
global and external objects. Some progress was made in languages such as
LIS where the unit of program structure consists of a data segment and a
_ program segment ~ahich allows the entire interface to be grouped in the data
segment, and YaRMO special descriptors ~24] are introduced t;o indicate as-
sociation tirith the externa~ environment and to control access to local ob-
_ jects.
In systems programming practice, dating from the appearance of macroassem- ~
blers, there arose the technological approach of the introduction of prob-
lem orientation with the help of the accumulation and use of a macrolibrary.
In one ~ray or another, there are macro facilities in systems programming
languages--at the levei of s imple macros of BLISS or the open procedures of
EPSILON~ as the basis for des cribable functions of access in XaRMO, and fi-
nally, as the basic construction of the language with free format of
- representation in SIGMA. Despite the availability of general-purpose
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macroprocessors, inclusion of macro facilities in systems programming lan-
guages remains advisable both for increasing the rate of macroprocessing
(which must not be disregarded with intensive use of macros) and for im-
proving the clearness and verifiability of results of macro substitution
(for which the macro fa~ilities must be tied to the syntactic structure of
the language, for example, as in EPSILON where macro facilities for descrip-
tion and use are similar to procedur es). Let us note that due to the de-
sire to discipline machine dependency and to combine it with facilities of
high level languages, it is natural to limit toleration of the use of con- -
_ structions of machine language or mnemonic code, customary for a number of -
systems programming languages, only to texts of macro definitions.
We have already mentioned that semantic associations with the concepts and
~ ob.jects of a concrete operating system should also be included in the con- `
cept of machine orienta~ion. Along with the desirability of this orienta-
tion, one would like to build appropriate constructions of a language by a
method rather independent of a concrete operating system. This is one of -
the most unresolved problems of systems programming languages since some
unification of the concepts of operating systems is required for this. And
this unification could be built based on an essentially efficient, flexible
and at the same time rather abstract model of an operating system, but for
now there is no such generally accepted model. The concepts of such a mo-
del have been discussed from the point of view of systems programming langu-
ages in a number of works (for example, [25] and [26]). The problem is to _
include in this model sufficiently precisely, flexibly and universally the
semantics of concepts such as, for example, processes, resources, communica-
tion, priority queues, manitors, properties of these concepts, and opera-
tions with objects of this sort.
It is rather difficult to formulate some complete set of descriptive facili-
ties for an evolving field such as systems programming. Let us mention
Chinin's work ~24] which is based on the actual experience of using and de-
veloping the YaRM~O language and which effectively expresses our current
understanding of systems programming problems. -
7. Transferability in Systems Programming. We have already noted that the
concept of machine orientation is distinct from the concept of machine de-
pendency. In principle, this makes it possible to suggest a requirement
for systems programming languages such as ensuring transfer of software from
one machine to another� Of course, a requirement for transferability is not
absolute with respect to those systems programming algorithms in which de-
finite machine dependency has been incorporated. For example, in the trans-
fer of a translator for some machine-independent language, one may speak of
the possibil ity of transferring all the translation algorithms except the
algorithm for generation (oritn the usual approach to translation), as well
as possibly some parts of the algorithm associated with a concrete operating
system, Efficiency may require changing the machine representation of daea
with the transfer.
Although fully automatic transfer of programs in machine-oriented systems _
programming languages is not always possible, nor even always desirable,
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it could nevertheless be automated under some limited conditions. An ap-
proach to automation of the transfer of programming systems, based on an
intermediate lan~uage, is offered in the ALMO system [8J. The ALMO machine-
- oriented language is a language of some abstract computer approximating a
- number of modern computers in its properties. It is assumed that there
exist programming systems written in ALMO and trans lating from input langu-
_ ages not into an object language of a concrete machine, but also into an
ALMO program. In this translation scheme, ALMO acts as an intermediate
_ language--translation occurs in two steps, first in to ALMO, and then from
ALMO into object code (existence of a translator from ALMO for a given ma-
chine is assumed). In the transfer, a new transla tor from ALMO is created
and all remaining software is transferred automatically. To make the pro-
grams being created more afficient where possible, ALMO has facilities for
assigning certain characteristics of a concrete com~uter.
The SIGMA system ~20, 21] has substantially more advanced facilities for
describing both the characteristics and the object code of a concrete com-
_ puter. According to the author [21], the languag e is a machine-oriented
. open language. The open nature derives From its s et of parameters, the fix-
ation of which determines the representation of the language oriente3 to a
concrete computer. In *_he SIGMA system, a descrip tion of a concrete compu-
ter, along with a program to be translated, is the source data; to transfer
- the output program to a new computer, one need only comp~le its description
_ accord ing to the rules of SIGMA (let us note that only input programs are
- being transferred this way, and the translating or instrumental machine
- remains the same).
Assigned in parameters concretizing a computer ar e: length of word, its
division and filling with retention of values, parameters of addressing,
and so on, as well as formats for machine represen tation of varinus lists.
The machine language proper is specified by masks and rules for filling
them w ith values of parameters of macros. Experience shows that the facili-
_ ties selected for description of a computer permit the description of an
extens ive class of machines--various machines such as the M-20, BESM-6, YeS
computer and Hewlett-Packard 2000 ;lave been described.
Great and essentially sufficient possibilities of transferability can be
obtained in machine-~oriented languages through organizational measures--by
observing certain discipline during programming. The experience of using
EPSILON, for example, indicates this. The required programming discipline
is based on the ~achine-dependent and machine-independent aspECts of con-
cepts b eing especially differentiated in EPSILON ~12J. Differentiated in
EPSILON are ~tandard f~;cilities, the semantics of which ar~ the same for
various computers, and a concrete level of linguistic �acilities definable .
for a given computer (there are different realizations of EPSILON for com-
puters of the M-20, BESM-b and Minsk-22 type--see ~11, 13~), If we ~rish to
- maintain compatibility of algorithms with different computers, we provide
beforehand for the use of machine-dependent facilities in fixed locations
of the algorithm (it is desirable to group this us a ge in procedures or ma-
cros). Recommer_dations, similar in spirit, that ma chine-dependent details
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of an algorithm should be limited to interlacing of part.