JPRS ID: 8986 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY

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~ 3~ ~ ~
RUTOMRTION TECHNOL~GY ~

28 MRRCH 1980 CFOUO 4r8~) 1 0 F 2
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~ JPRS L/8986
_ 20 Niarch 1980
~ -
~ U SSR Re ort
_ p
- CYBERNETICS, COMPUTERS AND
~ ~1UTOMATION TECHNOLOGY
CFOUO 4/80)
- FBIS FOREIGN BROADCAST INFORMATION SERVICE
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JPRS L/8986
20 March 1980
~ USSR REPORT
~
' CYBERPJETICS, COMPUTERS AND
AUTOMATION TECHNO LOGY
(FOUO 4/80)
Th~s serial publication contains article.?, abstracts of articles and news -
items from USSR scientific and technical journals on the specific subjects
reflected in the table of contents.
Photoduplications af foreign-language sources may be obtained from the
Photoduplication Service, Library of Congress, Washington, D. C. 20540.
Requests should ~rovide adequate identification both as to the source and -
the individual article(s) desired.
CONTENTS PAGE
DEVELOPMENT AND PRODUCTION OF COMPUTERS AND CONTROL EQUIPMENT....... 1
Hardware........e 1
A System of Gathering and Algorithms of 'rimary Processing
of PhotomPtric Data9 1 -
A Device for Autamatic Counting of Ob~ects on a Plane Image...... 2
A Device for Character Recognition 3
- An Adaptive Device for Data Processing 4
- Integrated Circuits for Computer Applications Discussed..,....... 5
Equipment 37
Developing Multilanguage Processors 37
~ Methods of and Experience in the Design r~f Data Processing -
_ Systems 39
- Debugging Instructions in the Input Language of the 'Pole-2' .
Programs Generator 40
Dynamic Change of Program Parameters on a Unified System
YeS-1010 Computer 40
- a- [III - USSR - 21C S&T FUUO] =
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CONTE.NTS (Coatinued) Page
Problems in Selecting the Program Structure for a Data
Retrieval System Included in a Multiple-Access System
With Modular Computer Technology 41
Library~ of Application Programs for the Solution of Scientific- ~
Technical Problems With a Disk Operating System in a Modular
_ System of Computer Technology (Second Version) (Materials on
~ Software) 42
- One Algorithm in the Software for an M-220A--BESM-6 Computer
Complex........~ 43 -
Methods of Describing Languages and Translations in Modern
Translator Desi.gr. Systems 44
'Sinkhron-2' Data Systea~. Means of Batch Processing........... 45
Automated Design and Engineering 46
Automation of Planning and the Task of Automation of Processes
and Design of Turbines 46
LCUNOMIC APPLICATIONS 47
General Treatmen'c 47
- Problems of ASU Interaction 47
Manufacturing and Processing Industries 55
Automated System rox' Technological Planning of Machining of
Blades (ASTP "Lopatka") 55
NATURAL SCIENCE RESEARCH........~ 56 ~
BiolcgY and Medicine 56
A Device for Neuran Simulation 56 -
Automatic Transformation of an Arbitrary Function to a
System of Shannon Equations 57
INFORMATION SCIENCE ..............s................................ 58
Inforination Services 58
Automated System for Formation of Small Libraries of
_ Information Sources 58
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CONTENTS (Continued) Page
THEORETICAL FOUNDATIONS 59
Ceneral Problems 59
Specialized Uniform Structures as Programmable Logical
Matrices 59
One Possible Algorithm of Optimal Load Distribution Between
Regulating Power Devices During Automatic Digital Regulation
of Exchange Power (Frequency) in a Power Grid System.......... 63
Synthesis of Method for Computing the Coordinates of the
Orientation Vector 64
Algorithms of Control of Automatic Loaders During Loading of
a Multideck Cargo Ship 65
Structure and Organization of Data for Designing the Topology
of Special-Purpose Large-Scale-Integration Systems............ 65
GENERAL INFORMATION 66 -
Conferences 66
- Integrated and Small Computer System ~quipment and Its
Application 66
Automated Design of the Logic Level in the 'Astra' Data Bank... 85
Publications 86
Abstracts from the Journal "Avtomatika i Vychislitel'Naya
Tekhnika"... 86
Abstracts from c~~e Journal "Programming" 91
Automated Processing of Hydrometeorologica2 Information........ 96
Automatic Construction of Parallel Programs. Parallelization
of Operator Flow Charts 102
Cinematographic Molds: Synthesis of the Phase Structure and
- Permissible Errors 102
Conten"ts from Issues of Voprosy Kibernetiki (Issues in
Cybernetics).......~ 103
Cyberneti.cs in Military Systems 109
~ Equipment for`Automatic Analog Computer Sca12 Chain............ 110
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CONTENTS (Continued) � Page
Excerpts on Automation and Remote Control Equipment -
From the Journal "Avtamatika I Telemekhanika" 117
Format of 'ENSDF� and Its Use in Programs Written in
'FORTRAN' 124
Logical Methods of Checking Automated Devices 125
Microprocessors and Microcomputers 126
`PITFALL' Program for Research on a Natural Language.......... 127
Principles of Organizing a Monitor for a Complex of Procedures
_ Involved in Simulation of Discrete Systems 128
- Specialized Software for Management 129 ,
Theory of Ogtimum Solutions 138 ~
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DEVELOPMENT AND PRODUCTION OF COMPUTERS AND CONTROL EQUIPMENT
Hardware
~ USSR UDC 681.51:007.5
A SYSTEM OF GATHERING AND ALGORITHMS OF PRIMARY PROCESSING OF PHOTOMETRIC
- DATA
_ Moscow INSTITUT PRIKLADNOY MATEMATIKI AKADEMII NAUK SSSR in Russian, pre- .
print No 87, 1979 34 pp
~ ,
PLATONOV, A. K. and SOKOLOV, S. M.
- [From REFERATIVNYY ZHURNAL: TEKHNICHESKAYA KIB~RNETIKA No 11, Nov 79
Abstract No 11,81.362 by G. G. Vaynshteyn] ~
[Text] Under consideration is a system of gathering photometric data which
consists of 100 photoelectric transduce~s assembled into a matrix of 1Ox10 -
elements and connected to an M-6000 small computer. Several algorithms of
primary data processing are described whicr include an algorithm of normal- -
izing the indications of photoelectric transducers with their current-illumi-
nance characteristics taken into account, an algorithm of correcting the in-
dications so ~s to account for possible faults in thz instruments, an algo-
rithm of extracting a straight brightness taper from images with a simpli-
= fied version of the Huckel operator, and an algorithm of sharpening the con-
trast by simulation of the "lateral stagnation" effect. The feasibility of
- extracting two homogeneous regions within the field of vision of the photo-
- electric matrix by the method of potentials is examined. Research effort
underwa.y is oriented toward development of a video transducer for an autono- ~
mous moving robot. Figures 25: tables 4; references 11.
[178-2415]
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CSO: 1863
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USSR UDC 681.51:007.5
A DEVICE Fc~R AUTOMATIC COUNTING OF ORJECTS ON A PLAN~ IMAGE
Moscow SBORNIK NA~JCHNYKH TRUDOV PO PROBLEMAM MIKROELEKTRONIKI [Problems in
Microelectronics, Collection of Scientific Articles] in Russian Izd-vo
_ Moskovskogo Instituta Elektronnoy Tekhniki No 39. 1978 pp 104-112
GRISHIN, M. P.
[From REFERATIVNYY ZHURNAL: TEKHNICHESKAYA KIBERNETIKA No 11, Nov 79
Abstract No 11.81.366)
[TextJ A device is described 'which makes it possible to analyze optical
images and count the number of objects w3thin the field of vision as well
as the number of internal closed regions within objects. The count depends ~
neither on the dimensions and rhe shapes of objects nor on their relative -
disposition within the field of vision. The device is realized with digi-
tal engineering components. As the transducer serves an LI-428 vidicon.
Figures 3; references 1.
[178-2415]
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CSO: 1863
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USSR UDC 681.51:007.5:681.327.12(088.8)
- A DEVICE FOR CHARACTER RECOCNITION -
- USSR Patent Class G 06 K 9/00 No 650,087 28 Feb 79 (disclosure No 2,388,895
1 Aug 76)
~ KOZLOV, L. G., GRITSYK, V. V., ZLATOGURSKIY, E. R., BOYUN, V. P. and
CHERCHYK, G. T., Institute of Cybernetics, Academy of Sciences of the
Ukrainian SSR
[From REFERATTVNYY ZHURNAL: TEKHNICHESKAYA KIBERNETIKA No 11, Nov 79
Abstract No 11.81.339 P]
_ [Text] There exists a device for character recognition which includes an
- objective, a television tube, a video amplifier, arrays of frame and line
switches, frame and line distributors, an array of triggers, a classifier
- module, a changer of coordinates, a control module, a generator of linear
voltages, an array of voltage gener3tors and a commutator. The most accu-
rate technical realization of the new concept contains a first memory mod-
ule connected through a commutator bank to a shift register and to a first
array of counters. A second memory module is connected through a shift
register to a control module. The purpos~ of this invention is to make
- the character recognition more precise and to simplify the device. The
_ purpose is achieved by including a module which classifies the spectra of '
recognizable characters and connecting it to a second array of counters as
well as to the control module. The second array of counters is connected
to the first memory module and to the control module. A third array of
counters is connected to the second memory module and to the control module. -
The spectra classifier contains a comparator connected to a register, to a _
commutator, to a counter and to a first "AND" gate, this "AND" gate being
connected to the commutator and tc? a second "AND" gate which is also con-
nected to the register and to the commutator. Figures 2; references 2.
[178-2415]
2415
- CSU: 1863
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USSR UDC 681.518:519.878
.
AN ADAPTI~~E DEVICE FOR DATA PROCESSING
USSR Patent Class G 06 F 15/20 No 650,081 28 Feb 79 (disclosure No 2,450,686
9 Feb 77)
DUBOVIK, YE. A. and SENTYURIN, V. M., Institute of Electronic Control
Machines
[From REFERATIVNYY ZHURNAL: TEKHNICHESKAYA KIBERNETIKA. No 11, Nov 79
- Abstract No 11.81.705 P]
[Text] The invention relates to the field of computer engineering and telem-
etry. The closest to it technical realization is an adaptive device for data ,
processing which includes a direct-access memory module, a control module,
two cormnutators, a recording module, a readout module, an arithmetic module,
five registers, ten "AND" gates, four counters and two decoders. The first
output of the control module is connected to the control input of ths,first _
commutator. The second output of the control module is connected throu~h
- the recording module to the fi.rst input of the direct-access memory, whose
second input is connected through the readout module to the third output of
the control module and whose first output is connected to the input of the _
first register, while the first output of the latter is connected through
the first "AND" gate to the first input of the second register. A basic de-
ficiency of this device is its limited throughput capacity. The purpo~e of -
this invention is to increase the speed. Figures 1; references 2.
(i~s-2ais)
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CSO: 1863
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INTEGRATED CIRCUITS FOR COMPUTER APPLICATIONS DISCUSSED
Moscow ANALOGOVYYE I TSIFROVYYE INTEGRAL'NYYE SKHEMY (Analog and Digital
Integrated Circuizs) in Russian 1979 signed to press 5 Apr 79, pp 136-161
[Excerpt from book by Sergey Viktorovich Yakubovskiy Nikolay Arsen'yevich
Barkanov, Boris Petrovich Kudryashov, Lev Ionovich Nissel'son, Mikhail
Nikiforovich Topeshkin and Lyubov' Petrovna Chebotareva, Izdatel'stvo
Sovetskoye Radio, 68,000 copies, 336 pages] _
[Excerpt] 3.7.4. Storage Elements Employing MNOS structures .
In all the integrated circuits discussed above, employing bipolar and MOS
[metal-oxide semic onductor] transistors, for the purpose of storing informa-
tion in a storage element the existence of a supply voltage is obligatory.
When the power is cut off information is lost. However in a number of
cases it is necessary to cut~off the power, and in addition the ability to -
store information with the power cutoff considerably reduces the mean power _
required by the storage unit.
An integrated semiconductor structure--an MNOS [metal-nitride-oxide semi-
- conductor] transistor--makes it possible to design a storage unit whi.ch re-
tains information when the power is cut off. In MNOS transistors, unlike
ordinary MOS structures, between the silicon oxide (Si02) film and the metal -
gate electrode is placed a film of silicon nitride, SigNq. The storage of
charges in the reg ion of the Si3N4-SiOL interface makes it possible to store
information when the power is cut off for several years.
The film o~ Si02 prevents the transf er of charges in the absence of voltage [
in the gate or when it is below the threshold value. This capability of a
st~rage element employing an MNOS transistor is responsible for longterm
storage of information when the power is cut off. -
Informa~ion is stored in a mer~ory element based on an MNOS structure by sup-
plying to ,the gate a certain voltage with a specific sign. When negative
voltage of a specif ic critical magnitude is supplied, at the interface of
the silicon nitride and silicon oxide films a charge originates, whose
- magnitude depends both on the amplitude and length of. the voltage pulse. _
5 `
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With this is established a state with a high threshold voltage, U .
When positive voltage of a specific critical magnitude is supplie~�,ra~ the
_ interface a charge originates which lowers the threshold value to a magni-
tude of U . The difference Up - up = ~Up is called the
interthres~io~dnzone (fig 3.50). or v or n or
.
.
30 ~ p^ ~1M
- Z~Y~n~.n~
- 2v
~
4)
~ 3 ~u;~~e '
- ~ i'~~ ~ ~ c ~s 5 ~cB
Figure 3.50. Characteristics of a Storage Element Employing an MNOS
Structure ' -
Key:
1. I, uA 4. U
2. ~~por - 12 V 5. Upor~v
3. U '
por n
When a negative voltage (U =-28 V) is supplied to the gate of an MNOS
transistor, a state is established which is character;:zed by a high thresh-
_ uld voltage of U r V= 15 V, corresponding to the "1" level, and with �
U=+28 V, a st~a~e is established with a low threshold voltage of
UZ = 3 V, corresponding to the "0" level. The existence of an inter-
t~i�res~iold zone of ~U = 12 V makes it possible confidently to distin-
- guish two states of t~i�erstorage element. For the purpose of reading out
stored information ("1" or "0 to the gate of the MNOS transistor it is
necessary to supply a readout voltage, Usch ~ satisfying the condition ,
Upor n~ Usch ~ Upor v'
Thus, if U =-(3 to 5) V is suppl.ied, then a storage element in which
a"1" (U sch_ 15 u) was entered beforehand will change to the conduction
state. ~nd~ if a"0" was entered beforehand (U = 3 V), the starage
element will not conduct. The readout signal ~�an ~i'e separated by means of
_ a not too high load resistance connected between the output of the storage
element and the ground (in a PZTJ [permanent memory] with two-coordinate
_ access), or can be determined "by the presence of current in the output
= circuit (in a PZU with word-by-word access).
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Information entered in a storage element employing an MNOS structure is
_ stored for a long time when the power is cut off, although at the beginning `
of the storage period the interthreshold zone is somewhat reduced. The
- storage properties of MNOS structures are improved in multiple repetition
of the readout-read~n cycle, which has occasioned a tendency to use them
for the purpose of creating permanent memories (PZiT's), and not memories
- with random access. Able to serve as an example of' these PZU's are series -
K519 microcircuits, representing memory matrices for 128 and 256 bits with
electrical rewriting of i.nformation (fig 3.51). Let us discuss the opera-
cion of these circuits in different modes.
_ ' r t G7IL~! � -
_ .'YFj '9`�JD/! -
; :/`pvJ4'.^/'~CQ~
/
~ ~;-a:�..
- ~y~
( `F *S Yr1
_ 1 ~ ~~i.
( J` _ I 3) `5) ~ i:,: .
2~ ~ ~ ~ i~ j -
~ . ~ :
r...:sJ:,
- ~ ,0 4)~ _ -
~ u._'_ ~
, i � .'L-_ ` .
ir . ~ � i ~
r !
= I ~ ! 6~ ` =
~ ~ r~ - ~
J ~ .
t
7~/
~ Figure 3.51. Functional Diagram of Type K519RYe1 Integrated Circuits
Key:
1. Load transistors and 4. 16 X S matrix
power switches ~ 5. Number code buses _
2. Inputs 1 to 16 6. Outputs _
3. Circuit for setting number
codes -
- When a"0" is entered (erasur.e of information), to the "power readout"
- bus (lead 47) is supplied a-9 V voltage (the voltage in the remaining ~
power buses (leads l, 2 and 48) equals zero). To a11 the inputs (Vkh~ to
- Vkh ) is supplied a+48 V voltage, and to the "number code," "inhibit
entry" (lead 36) and "select crystal "(lead 14), zero voltage. In the
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"enter ' 1"' mode, to the "power readin" (contact 1) ,"reset raadin" (con-
tact 2) and "power readout" buses are supplied voltages of -48, -48 and
-9 V, respectitiely; the voltages in the "reset readout" (contact 48) and
_ "select crystal" buses equal zero. To the inputs (Vkh to Vkh ) is fed
a-48 V voltage, and to the "number code" and "inhibit entry" buses, a
-9 V voltage. During readout, to the "power readout" and "reset readout"
buses are supplied respectively a voltage of -9 and -24 V(the voltage in
the "power rEadin" and "reset readin" buses zqua:is zero~. ~o tiie inputs of
the matrix (Vkh to Vkh1~ ) is supplied a voltage of U ~-7 V, to the
"number code" and "inhib~t readin" buses, a zero volta~eh and to the "se- -
lect crystal" bus, a-9 V.
3.7.5. Storage Elements Based on "Silicon on Sapphire" Structures ~
One of the new trends in the creation of circuit~ for diode storage units
is the employment of the technology conventionally called "silicon on
sapphire" (KNS [SOS]). The utilization of thin single-crystal films of
silicon grown on a sapphire substrate (a material having a crystal struc-
ture like that of silicon) makes it possible to produce devices with hig~
radiation resistance, which is explained by the insensitivity of the di-
electric substrate (sapphire) to radiation and the small areas of silicon
p-n junctions. The area of the p-n junction in these devices is deter-
mined by the product of the thickness of the silicon film and the length
of the junction line and equals 2�10 5 to 8�10 5 mm. This makes possible
low junction capacitance and accordingly high speed of response (to 10 9 s).
- TYie small area of the p-n junction makes it possible also to r_reate devices
by using the micropower integrated circuit variant. The data published
testifies to the feasibility of creating permanent memories with the SOS
technology with a high level of integration (of 5120 diodes on a single '
crystal) distinguished by an access time of 20 ns and dissipated power of
0.06 mW per diode. On the basis of these crystals it is possible to put
together PZU's of different capacity, e.g., for 3200 single-bit words (one
. base crystal), 384 16-bit words (two base crystals) and 2048 20-bit words
(n.ine base crysta~s). However, this trend for a number of reasons has not
_ yet received sufficient development. The series K139 microcircuits based ~
on SOS have a limited application.
3.7.6. Storage Elements Based on New Materials
Of great interest are developments of storage units based on new materials.
_ An c~xample of such a development is integrated c3rcuits employing switches '
- made of a vitreous semiconductor',~f the K524RP1 type (fig 3.52a), in the
form of a storage matrix of a permanent reprogrammable memory (PPZU), with
_ '256 bits (equivalent to this integrated circuit is a PPZU employing amor-
phous semiconductors of the C7010 type, made by the Nitron firm in the USA).
_ This circuit permits 100 rewrite cycles and ma.kes it possible to store in-
- f.ormation for 10,000 h when the power is cut off. A structural diagram
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for the rewriting o~ information is given in fig 3.52b. Znformation is
read in successively into each storage element. Here the bit bus selected
is grounded and to the selected number bus is supplled a plus readin pulse.
When a"0" is read in, the Uvkh rin ut ~~9 to 30 V. Zvkh ~ 3 Ca 7 mA ~ _
and T [p = 10 to 20 ms witenpa '~1" is read in, U = 22 V
Ivkh-i70 ~'osg~0 mA , and Ti = 3 to 10 us . When a"1" ~shread ln,~read-
out can take place only 10 Us after termination of the readin pulse. The
maximum permissible rewrite rate for a single storage element ~quals `
f = 5 Hz . The current for reading in a"0" is dr~ven by dscillator
G~Xthrough diode VDl and clipging resistor RO ~Tvkh- 11 mA). The
c~rreni lfor reading in a"1" is driven by oscillator G1 through diode
- VD2 (I k ~ 100 mA). For the purpose of achieving consistent readin of
a"~" an3h"1" a 16-fold repetition of thF readin cycle is made possible.
4,, ~
~
:d ~
46 '
11 ~ ~aRS-,
47 ~ w ' ~ 3
15 r~ ` ~ ~ S+
_ a ~d ~ ~
~ ~ ,
_ y ' ` . ' ~.r.
o . . . , ~ Pl~ ~
p . : _
o ?q ~ t
- ti 1_~l r -
1 ~ r ~ ~ - L.'~--
''J l_ ~ I
~ i~ ~ ~ ~ ~
4~~ ~ b~ ~ . -
as ~9 ~ ys 1
,c ~s ~ rv s -
Sucn7u'a~c rrc'~+~ 2 ~
_ Figure 3.52. Schematic Diagram of Type K524RP1A Integrated Circuit
(a) and Structural Diagram f-or Rewriting Information (b):
D--type K524RP1A integrated circuit, S1--switch for se-
lection of number bus, S2--switch for selection of bit
bus, PV--voltmeter
Key:
1. Bit buses 3. Rsch [readout]
2. Number buses
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~
'
~
When information is read out to the aelected number bus, a plus pulae witt?
- UeCh ~ S V is s~ipplied from oscillator G ~h through c].ipping resistor
R m 6 kSt . Reading out can be performe~ tiy a pulse of any length great-
er~~an the length of T = R ?0.0035�C (where C is the capacitance
of the matrix, equaling ~16~ p~)schThe pulse for reading in a"0" or "1,"
passing through the matrix's storage element (a diode made of a vitreous
semiconductor), changes its resistance, which makes it possible in reading =
. o~t information to producg at the output a voltage of a different magnitude, _
Uvykh [output] ~ Z Uvykh 3.S V. � -
Able to serve as another example of a storage unit based on new materials ~
is the type 307RVI int~grated circuit, representing the storage matrix of ,
a PPZU with a capacicy of eight bits, employing piezoelectric ceramics. '
A schematic diagram of a type K307RV1 integrated circuit is shown in tig
3.53. A"1" is read in by supplying to leads 3 to 6 and 9 to 12 a-250 V
pulse (Ti > 20 ms). A"0" is read in by supplying a 250 V pulse (Ti >
- > 20 ms). Leads 7(8) are hereby connected to ground. For the purpose of
reading out recorded information it is necessary with leads 7(8) gxounded -
to supply to leads 14(1) an excitation pulse of U,~o2b rexcitat~on~ ~
< 100 V or U >-50 V. The read-out signal can h9ve a po ar ty -
opgosite to the�polarity of the excitation pulse. Its magnitude is also
dgt~~'miz~ed by the magnitude of the excitation pulse with iJ b = 10 V,
U~kh =+�S~J mV . Type K307RV integrated circuits make poss~~ie the stor-.
ag~ of recorded informaeion for 15 years with the supply voltage cut off.
T'he maximum access rate is 100 kHz. ~.t the present time work is being done
to increase the capacity of the matrix t~ 256 bits.
6 r _
. 5 0----
I ;,1I
- ~ 11~ I~ L~ L R
~ ~ 8 -
~ ~ ~ r -14 ,
Figure 3.53. Schematic Diagram of K307RV1 Tntegrated Circuit ~
, 3.7.7. Major Series of Memory Unit Integrated Circuits and Their Func-
tional S~ructure
As was demonstrated above, the key element of the matrix of a memory unit =
is a storage element, as which is used most often a flip-flop. But the
10
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electrical parameters of a memory unit are not characterized only by the
parameters o~ trigger circuits. The key characteristics o~� memory unit
integrated circuits are the following: capacity, measured by the number of
binary units of in~ormation (bits) which can be stored in the memory unit;
speed of response, determined by the time for access to the memory unit*
(speed of response can be characterized in addition by the readin time and
readout time); and the power required by a single storage element (in mTrl
per bit) or the power requirement of the entire integrated circuit of the
memory unit as a whole. An important characteristic of inemory unit in-
tegrated circuits is also the degree of integration, expressed as the num-
ber of elements or equivalent gates in the package.
The development of inemory unit integrated circuits has been proceeding
along two lines: Special series of inemory units are being created, and
memory units are being developed for the purpose of expanding previously
- developed digital series. For example, in recent years the TTL [transis-
tor-transistor logic] and ESTL [electrical circuit - transistor logic]
series of integrated circuits have been expanded, whose makeup includes
OZU's [.direct-access memory units] with a capacity of 64 bits and random
access and control circuits (K155RU2 and K500RU148) and OZU's with a capa-
city of 256 bits and control circuits (K500RU410), and series of microcir-
- cuits employing CMOS [complementary MOS] transistors, whose makeup includes
OZU integrated circuits with a capacity of 256 bits and control (564RU2
_ and K176RII2).
_ A list of special series of inemory unit integrated circuits which have
found application in computers for industrial purposes, u~ed in different
sectors of the national economy, and their characteristics are given in
table 3.23. It should be emphasized that all memory unit integrated cir-
cuits developed in recent years contain, in addition to storage matrices,
control circuits (decoders, output shapers, etc.), which has made it pos-
sible significantly to reduce the number of integrated circuits used for
designing a memory unit, and at the same time to reduce its size, to sim-
_ plify installation and accordingly to improve reliability. As is obvious
from table 3.23, the majority of inemory unit circuits have been developed
_ on the basis of p-channel MOS technology, with which the unit cell of the
memory unit is of small size.
The maximum capacity of OZU's and PZU's is 16 kbits. However in,the im- -
_ mediate future must be expected the appearance of inemory unit circuits ~
with a capacity of 64 kbits. Of special interest are memory units exe-
cuted according to the MNOS technology, since they make it possible to ~
- store information with the power cut off. For the 519RYe1 and 519RYe2
circuits shown in the table this time eqtials 2000 h. Great prospects in
the area of 3.mproving the level of integration, reducing the required
power and increasing speed of response are being opened up with further
*Here is meant the time from thP instant the access signal is supplied to
the instant of termination of ti?e process of reading in or reading out in-
formation from the memory unit.
- 11 ~
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improvement of such cizcuitry and technological trends as CMOS, n-MOS and
MNO~ structures.
Table 3.23. List of Series of Memory Unit Integxated Cixcuits and Their
~ Key Parameters
- -
u~~�w i
(l''IItTIJN I~I~IN~ ~:1� yll{.'10
_ \~i ~..�Il~~~r I ~ IIttI111011.7116~k1! � ~~1~r~ T 1. l.~~t~l. 11. V~1~`PII~:! ~ '
~ T!!I1111.10 11:IfN~. I ll'.�!.'1'a N(llll� .Jif!.~CII'(00
~r..~ 1�IJ'll'~IN: I lo~.i .~n~i ~ i. .
!~~nirieuxc ~nw ai:f~~~phu :~:~i~~'rn. ~ nn.:~ r,.,trcuir nGoui;,~ir�nc n.. K~M.
,~~...1~,..~~~ 2~ 3~ ~~,~,n~~r
r~~nn.nernid in~� :lr;aer hu0n�,ca cT~it~
�G.~;ni.i iui. un~� I
5~ 6) I 7) 8)
~
~
_ .o,i~~'1 i 9!171fI1N11:1�NJKQpMTC.76 U3Y cu :~1r~(1 I ~�'y ],~t,ir~-?:! I 3.?~rr�:: c~po~l:^� /~:.Ib.l 18~i1
I.ccwa}ut yupatiuuN� p~~~(i 1::~,..:i) ,L ~u ~n=1.9 ~:i:nl I I
1. / ~ r ~~vq ~p't.�
~ ~ ~ ~r~l
- , 33~:�
;~.~".P~~ .laipuy..~naKmrn:c:lb U:f>' tn i�1UI1 I~CI '3`lea=0. ' ;rr~a il?i:i~l I ~SY?
Ic.~r.~~avN )�n{+axnrwiN I 0�~aiian I(I~~?IrI! ~ J f~r-~J.S I ch:ar:rnnu) I I
~ !14) ~
- -'};~-:.1~~! t iitl' yyi tPN:lMN ~n,.~amm~y ~ K a1~ I :t~t ~ ~~.u~ '~~�~r�u~1 - Vy
- ~ 1~ { 1: ~>.~u ,'.~N'C:IIIH A1UII li urn~ ~ ~ I I---'- ~ ~ ~
i~~. 1 ~ :.nn~vcc~u~o :nu:~1 . n�~auan u~ n,~~-~~ I ;~.I:', ~nuN :I~~12'. I I IJlen i
11 bn l) 1ii c+- -rM1
. ~ ~I~ Iqtv=cll.i~~) rfip.i::ICqqtl) ~ .
~ I 24) ,
� ~t. ~~aaeu:iN) ( ~
'.I ~ I '
� ; ~ i t~' y:n~.i~~~~p~~C T:i~u I AtC)li I r~ - ~
~',t;{'1':~1 I L7~_ r�~~r~fri ~~i.O~CI I fa~u~U.G~ I-' . ~ ~~~'.~11.~ '~n�� . 1 , ~
( 1 a ~u=U.9 I ~
~i~ ~~{~�'1 coc~c!u.ex }f':~Btl'IINA !�50!1 10:7 lar~=0.~:~ :Hillnll ; ~
4 ' �i')'~~1'~ ~ ' I fl�K:i111.'1 I ~~(1'~~ 1: I ~4 f~
_:_(I.h.1 I ' .JJ I . ~ ' _
� ~ i"'~~ U:i~' eo e~ce~awi~ )i:p~raeuN~ D5Uf1 Ir,K ?~,=,U.:�J I~;~;~ ' :ul:\.It�2 I il3~z f '
;F�..~;I'~'Jli (JH~~./MU9tCAb1U.THfId) A'1:2ddA (15:is/X1) tra-Q.:B ,,..,iw~~~~n+) I ~ _
;.;.i:; Inpu i
~ .{P.~�IrHHI~y ~
~ ~�.tt.~ ~ f~fllt I I ~
ph~l.~!::t`IIHII~ �
. Ill^H ;
. t^:~~I~:I::IiI) i .
1~>.1.~ ~ ~ r!Y cu c~~�4a~i~i y:1~hlbdClIIIA ~1017 I~.~ l. a--:n.r:~ I ~ inl`N I 7~IA.1~~ : ~ 71:9 i
1::,.:1~?'.:L ~ I p�hvna~ I!i!~'~>'l) I h~=U,95 ; _
_ " ~.i.vmH) ~
i
i' ;II'' I.'~^! O~Y _ I-FI'JI ~lri~iY,l f~a=UJ80 ~ I a9.i.:1.~ I t9:1t~ i
ti ~t~ .'It'~ I I 26\'I. ?~~ny~ I i..IJ
F~" .:'1': i J 1~::~.
' _ i
~
: ' ~Ii.l I'-�^.~{aip~~n~~�:r,vn~r.:�~ u~~c~ow~ ci~r,.itry.�~ IL'3 ~�'=5i~t :N.�I~.~ ~
.'~i i . o r~.~�.27,;pa�a~,,~p}r~:~io "sY :~am~:�: 2Ji OCpC3:lIIHiN I dl~ ~ '
~ I n~.,v~~~o- f 29
- 28) ) I i _ i
1..~f'I'~ ~1.~:ir:,Sr~n~~nn~rTrae f~.3>' co N'.9 ;118 t~ ~=5 vKC C'.I~ ~US.".11 71�,3
F:�.~x},i'll ~,:~~~.:v~< )np~n~~tiuiN, t):~o!:rI~H� It71i fnn=l~qQ a i964 i
~.C:~.a:V ucD;'~anN:b~~ Nn~lvpNa� I O.i .
~ u~it (~r.~:a0~~~no:i ~;*pc~au!:-w - ~ 31.~ !
t~�� `
" . � - � - ~
' ~
? _
[Key on following page]
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:
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Key:
1. Convention.,~ designation 19. PZU stoxage mazrix with electri-
of microcircuit ca1 reprogramtni.ng
, 2. Functfonal purpose 20. MNOS
3. Technology 21. PZU storage matrix with partial
4. Bit capacity (layout) decoding circuit and electrical
5. Cycle (readout/readin), rewriting of information
readin, address access, 22. PZU with complete address decod-
and information readout ing, output amplifiers and "in-
time, us tegrated circuit selection" con-
6. Specific power require- trol circuit
_ ment, mW/bit 23. p-channel MOS
7. Conventional designation 24. OZU with control circuits (of the
- of package dynamic type)
8. Number of elements in 25. D~namic type OZU
_ crystal 26. I L[integrated injection logic]
- 9. OZU storage matrix with 27. Storage matrix of permanent re-~ -
control circuits programmable memory unit
10. p-channel MOS 28. Vitreous semiconductor
11. Readout cycle tine 29. Rewrite f= 5 Hz
12. Readin cycle time 30. PZU storage matrix with control
13. Address access time circuits and electrical rewriting
14. Readin time of information (number of rewrite
15. OZU with control cir- cycles--104)
cuits 31. Storage time equals 2000 h
16. CMOS 32. In access "
17. Readout access time 33. In storage
18. With Ui [supply volt-
age] = 5 8
3.8. Prospects for the Development of Digital Integrated Circuits
Each of the types of digital integrated circuits discussed above (bipolar
TTL and ESTL and circuits employing MOS structures, such as p-channel,
CMOS, MNOS and`SOS) has its advantages and disadvantages, which govern
their area of application. Bipolar integrated transistors are suitable -
for the commutation of relatively high currents, because of which integra- -
ted circuits employing these transistors are distinguished by high speed
of response, whereby the stray capacitances of interconnections between
packages have little influence on the operating speed.
By means of connecting many bipolar integrated circuits, each of which is -
of moderate complexity, it is possible to create high-speed equipment com-
ponents. For the purpose of designing computers and components of discrete
automatic devices TTL circuits are now used most extensively. Ultrafast
equipment is being designed with integrated circuits of the ESTL type.
MOS transistors, because o~ their practicality, make it possible to a-
chieve considerably greater packaging density of switching circuits in
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the integrated structure than do bipolar isolated by a p-n junction or a
film of Si02. Circuits utilizing MOS transistors arranged on a single
crystal can equal whole ~unctional units. This has detexmined their ex- -
tensive application in electronic calculators, memory unita and micropro-
' cessors. ~
In turn, the steadily increasing requiremen~s ~rom the viewpoint of im-
proving sg~ed of response, reducing the required power and reducing the di-
- mensions and cost of equipment have entailed a quest for new methods making
it possible both to improve tt,e operating characteristics of MOS transis-
tors and to increase the functional packaging density of elementary switch-
ir_g rircui`ts made out of bipolar transistors. Let u~ discuss in greater
detail new technological trends in the fabrication of digital integrated
circuits.
- 3.8.1. Integrated Injection Logic
As a development of the very first switching circuit--a direct coupling
transistor logic (TLNS) circuit--in recent years has 3ppeared integrated
in3ection ;logic (abbreviated IIL or ILL). By means of circuits of the I2L
- type it has been possible to overcome the traditional disadvantages of bi-
polar int~grated circuits, i.e., their low packaging density and high dis-
sipated power per gate. In terms of packaging density IzL circuits even
surpass MOS circuits (it is possible to package more than 200 gates on an _
area of l,mm2), and in terms of levels of dissipated power are comparable
to G'MOS circuits. The high speed of response characteristic of bipolar
integrated circuits is furthermore maintained (the propagation delay time
per gate reaches 5 ns). The best known variants of base inverter circuiCs
utilizing in~ection logic of the I2L type and I2L type wtth Schottky diodes
, are shown in fig 3.54.
_ ~
Figure 3.54. Base Inverter Circuits of the z2L Type ~
The not too high dissip~ted power of I2L circuits is explained by the ab-
sence of resistors. The injection o,� carriers into the area of the trans- -
istor's base is accomp~.ished by means o~ active current generators designed -
�rom p-n-p transistors. The high speed of response with low required power
_ is explained by the insignificant stray capacitances, the absence of charge
accumulation and the very small difference in logical levels. Gates in-
cluded in the circuit can be arranged along the in~ection buses, which
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run urrl~tt~ ua~ u1vLr ~
simplifies the topology. In addition, on a single crystal it is possible _
to unite wi.thout di~~iculty both dig:,ttal I~L and analog circuits.
As can be assumed, I2L circuits with SchottYy diodes will make it poasible
to achieve even higher speed o# response (delay time of 0.1 na) without
increasing the power requirement.
3.8.2. MOS Circuits with n-Channels
The restrictions on speed of response characteristic of p-channel MOS cir-
cuits can be eliminated by means of n-channel MOS structures. The mobility
- of electrons in silicon is greater than the mobility of holes, which can
~ make possible a two-~~to.threefdld gr,eater switching.speed in MOS circuits ~
with,an n-cfiannel than in circuits with a p-channel. The latest achieve-
- ments in technology have made it possible to eliminate the d~.sadvantages
- of the firs~f n-channel ~circuits. Utilization~-of the method of ion imp~lant-
atian and ttie application in load circuits of, a structure with depleted and
not~enriched channels have made it possible~~-to lower ~he supply voltage to
5 V, which makes these circuits compatible in terms of~electrical levels
with TTL's. The use of a separate bias voltage for the substrate`has made
it possible to increase the threshold voltage, which at the original stage ;
was impermissibly low.
In tab].e 3.24 are given comparativ~e characteristics of the most well known
classes of digital integrated circuits, which demonstrate that for the pur- _
pose of designing digital equipment integrated circuits of the IzL, CMOS
and n-MOS types would most conWenient. Integrated circuits of the CMOS ~
type have already become widespread. The striving for a fundamental im- :
provement in the packaging density of bipolar integrated circuits, as well
as for an increase in the speed of response of MOS circuits began after the .
invention of microprocessors.
Tab:1e 2. Key Characteristics of Classes of Digital Integrated Circuits ;
Characteristics p-MOS n-MOS CMOS TTL ESTL I2L ~
Area required for a 5 to 7 3.7 to 5 6.25 to 12.5 to 12.5 to 2.5
single gate (10 3 18.7 37.5 31 to
~z~ 3.7
. Delay originating >100 40 to 15 to 3 to 10 0.5 to 2>5 '
in one gate, ns 100 50
_ StaCic di~sipated _ 2 to 3 0.2 to HI-~:1,t~~i/~ifi) r1P~-3N-.A ~ :~-i-I--�A. (~iiMG) (~I!A16)�IP6--.A '
P(1(- � I�-)A A-}-Pa-?:1 P,-rI--�A,Pa.(Ji/MG} A~'~i-P~--�(A/A, P~1~ ~
(,11/ ~ti16)
G->:1. rn ~ '2(A;Pa)--A
(0: - 11 �.1 ` _ , '
c~. ~ ~ - �'r I
(~Z ho~,,�nAn+ ~I
nepeet+~Kx, 7~y cnntmwc 8~
yaTanonKM ( J;~..ry,xoAN i cnct~e~i~~-e
i
9 XO) '
f(-� p. ~c:~oe� 1~~!:~penic-
i~wii nepc� nue/va- ,
� x~.~ no npemt�r+,~c '
{T) -(0; I) u~ ,
ui~a �
pB-1-E(-~~~p ~(~~IIl4 uNK.1:1~ U~'lal~~~8
- i ~n~c-� i-~ i2) ii)
creK ~7
Pe(-I- I-)1 ~
~ ~B
Conventional des~.gnations and abbreviations: --allocation pperator;
i--exclusive OR; A---OAU storage cell (working register); R and R -
operating register No a and b(a, b= 0 to 7); R--indexingaregister '
No v(v = 10 to 17); RP --result indicator regis~'er, consists of ~our
flip-tlops: R, Z, P and M; Zm --borrow, Zm ~ 1- R; M--mainline; '
MB --exchan~e o.f M with rearrangement of bytes; Xe --4-bit constant
- krom instruction word ~ield; K--second word o~ instruction; sink--region
= of inemory addressed through address indicator has been drained; *1,-gene,
ral designation of the operations (addition), -(subtraction), ~(logi-
cal multiplication), y(logical addifiion) and +[as published] ~
[Continuation and key on;following page] ~
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(non-equivalence); *2--general designation ox the operations inversion,
LL/LP (].ogica~ shi~t left/right by one bit) and TsL/Ts~ (cyclic shift
le~t/right one bit).
Key:
_ 1. OAU instruction words 9. Conditional trans~er with regard
2. Copying, setting to
3. Mixed 10. Intierrupt permission/inhibition
- 4, Unary 11. StoF'
S. B3:nary 12 . End ~if cycle
6. IAU instruction words 13. Sink "
7. Conditional transfers
8. System
Table 3.30. Structure of Improved Operating Speed MK Utilizing Series
K589 and K556 Integrated Circuits
Description Type Analog
tticroprogram control unit K589IK01 3001 Intel
Central processor element R589IK02 3002 Intel
Accelerated carry circuit K589IK03 3003 Intel
Multimode buffer register K589IR12 3212 Intel
Priority interrupt unit K589IK14 3214 Intel
Bus shaper K589AP16 3216 Intel
Bus shaper with inversian K589AP26 3226 Intel
Programmable permanent memory K556RYe4 -
Table 3.31. Key Electrical Parameters of MK Microcircuits Employing Series
589 Integrated Circuits
Parameter K589IK01 K589IK02 K589IK03 K589IR12 K589iK14 K589AP16 K589AP2
Maximum
static ~
power
require-
ment,
m~�tno~X~
~
greater
than 900 950 650 650 650 650 650
"0" out- 0.5 0,5 0.5 0.5 0.5 0.5 0.5
put sig- (outputs
- U~1~ C1 to C4)
~ 0.7 (out- 0.7
V;rynot puts B~ to
, ~ B4)
[Continued on following page]
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r~ux ur�r~tt;t~u, u5~: uNLY :
"1" out-
put sig-
n~1,
V~,'ynot~< 2.4 2.4 2.4 3.65 2,~+ 3.65 3.65 ,
- (out- ;
puts
C to
C4)
2.4 2.4
(out-
puts
B to
B4~
Length of ~
cycle, !
tts , ns >85 ?100 - - >80 - -
Pulse
length, -
_ ri , ns >30 >33 - >25 >20 - -
Time of , ,
delay in
propaga-
tion of
signal ~
_ from
input
Xi to
output
~ Yi' 16 14 - 20 15