MODEL HI-4896-1/1A MINIATURE TIME-CODE GENERATOR AND MODEL HI-4896-2 PRESENT READER JUNE 1968

• Document Type: CREST
• Collection: General CIA Records
• Document Number (FOIA) /ESDN (CREST): CIA-RDP71B00399R000300150001-0
• Release Decision: RIFPUB
• Original Classification: K
• Document Page Count: 93
• Document Creation Date: December 15, 2016
• Document Release Date: December 10, 2003
• Sequence Number: 1
• Publication Date: June 1, 1968
• Content Type: REPORT

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I FLOW CORPORATION eW?e,,'
I
MODEL HI-4896-1/1A
MINIATURE TIME-CODE GENERATOR
and
MODEL HI-4896-2
FLOW CORPORATION
Special Products Division
127 Coolidge Hill Road
Watertown, Massachusetts 02172
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TABLE OF CONTENTS
1
1.0 INTRODUCTION
1.1 Overall Description
1.2 Equipment Specification
1.2.1 Airborne Time-Code Generator
1.2.1.1 Time-Base Oscillator
1.2.1.2 Signal Outputs
1.2.1.3 Operating Controls
1.2.1.4 Output Connectors
1.2.1.5 Equipment Mechanical Specification
1.2.1.6 Environmental
1.2.2 Ground Preset Unit Specification
1.2.2.1 Operating Controls and Indicators
1.2.2.2 Output and Input Connectors
1.2.2.3 Package
1.2.2.4 Power Input
1.2.2.5 Battery-Charger Rate
1.2.2.6 Fuses
2.0 INSTALLATION
2.1 Grount Preset Unit
2.2 Airborne Time-Code Generator
2.3 Cables
3.0 OPERATION
3.1 Charge Battery
3.1.1 Connect Airborne TCG to GPU
3.1.2 Airborne Time-Code Generator
3.1.3 Keep Charger at ON
3.2 Preset Generator
3.3 Operation
3.4 Emergency Operation
4.0 MAINTENANCE
4.1 Maintenance - Airborne TCG
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TABLE OF CONTENTS
(Continued)
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4.1.1 Battery-Level Check
4.1.2 Oscillator Frequency
4.2 Preset Unit Check
4.2.1 Battery Charger Cut-Off Voltage Check
5.0 THEORY OF OPERATION - GENERAL
5.1 Airborne Time-Code Generator
5.1.1 Input Circuits
5.1.2 Input-Output Board PC-1
5.1.2.1 Power Regulator
5.1.2.2 Divider - 1 mHz to 1000 Hz
5.1.2.3 Modulator
5.1.2.4 Sine-Wave Shaper - 100 kHz
5.1.2.5 Input Filters
5.1.3 Divider-Decoder Board PC-2
5.1.3.1 Divider Flip-Flops
5.1.3.2 Code Format
5.1.3.3 Decoder X signals
5.1.3.4 Decoder Y Code Group Gates
5.1.3.5 Register Seconds Advance
5.1.4 Register Board PC-3
5.1.4.1 Register Flip-Flops
5.1.4.2 Code-Scan Gates
5.2.1 Logic Power Supply
5.2.2 Battery Charger
5.2.3 Preset Circuit Operation
5.2.4 Reader Logic
5.2.4.1 Overall Operation
5.2.4.2 Automatic Gain Control - Trigger Board A101
5.2.4.3 Code-Detector Board A102
5.2.4.4 Cycle Counter A103
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5-2
5-2
5-3
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TABLE OF CONTENTS
(Continued)
Page
5.2.4.5
Divider-Decoder Board A104
5-11
5.2.4.6
Register Boards A105, A106, A107
5-11
5.2.4.7
Display Drivers V1 to V6
APPENDIX I - BATTERY CHARACTERISTICS
5-12
Al-1
1.0
INTRODUCTION
Al -1
2.0
PRECAUTIONS
Al-1
3.0
CHARGING PRACTICES
AI-3
4.0
DISCHARGE PRACTICES
Al-3
5.0
CELL MAINTENANCE
APPENDIX II - FUNCTIONAL USE
Al-3
All-1
APPENDIX III - PARALLEL OUTPUT OPTION
AIII-1
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LIST OF FIGURES
Figure Number
1.1
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
5.25
Title
Miniature Time-Code Generator
Assembly, Ground Preset Unit
Assembly, Time-Code Generator
Logic Diagram, Ground Preset Unit
Chassis Wiring, Time-Code Generator
Waveforms, Time-Code Generator
Waveforsm, Ground Preset Unit
PC-1 Board Schematic
PC-1 Board Assembly
PC-2 Board Schematic
PC-2 Board Assembly
PC-3 Board Schematic
PC-3 Board Assembly
AGC Board Schematic - A101
AGC Board Assembly
Code-Stripper Schematic and Assembly
Penta Flip-Flop Schematic and Assembly
Divider-Decoder Schematic and Assembly
Register Schematic and Assembly
Power Supply Board Schematic
Power Supply Board Assembly
Power Supply Schematic
Component Board
Chassis, Component Layout
Outline, Time-Code Generator/Reader
Mounting Plate, Miniature TCG
Drawing Number
C4896-00001
D4896-41001
D4896-40009
R4896-71006
C4896-70002
C4896-00002
C4896-00003
D4896-70001 S 1
C4896-40002
D4896-70001 S2
C4896-40003
D4896-70001 S3
C4896-40004
D4896-70506
D4896-40506
C101-40121
C101-40409
C101-40122
CIOI-40106
C4896-71002 Si
D4896-41002
C4896-71001 S2
84896-11009
C4896-41003
C4896-01001
C4896-1101
AIII-1
AIII-2
Al 11-3
AIII-4
Generator Assembly
Generator Outline
PC-4 Schematic
PC-4 Assemb I y
D4896-40010
C4896-00004
A4896-70001 S4
D4896-30005 S3
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1
INTRODUCTION
1.0 INTRODUCTION
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The time-code generator system consists of two units: the Airborne Time-
Code Generator (TCG) and the Ground Preset Unit (GPU). The TCG is a
completely self-contained unit which generates a serial time code for per-
iods up to a day using a self-contained battery. The GPU is used to charge
the battery in the TCG, preset the time of day, and check the output code
for correct format.
1.1 Overall Description
The airborne TCG is housed in a miniature package consisting of a recharge-
able battery of six silver-zinc cells, a 1 megaHertz oscillator, and four
printed-circuit boards containing integrated circuits and discrete compon-
ents used in the power supply and modulator. The complete system operates
from a regulated +5 volts obtained from the battery.
The ground unit (GPU) is used to preset the time in hours, minutes, and sec-
onds into the TCG. The output of the TCG is read by the preset unit to in-
sure all circuits are operating properly. The internal battery of the TCG is
charged and the voltage checked by a panel meter on the GPU. Automatic
cutoff is provided for unattended charger operation.
1.2 Equipment Specification
1.2.1 Airborne Time-Code Generator
1.2.1.1 Time-Base Oscillator
Stability: I x 10-7per 24 hours after temperature stabiliza-
tion.
Frequency Change: Less than +5 x 10-6 over temperature range 0 to
60 degrees C.
1.2.1.2 Signal Outputs
a. All Outputs are short-circuit-proof to ground.
b. Time Code Format
XR3 time code modulated on a 1000 Hz carrier frequency
(20-bit code, 25 pps bit rate). Modulation ratio adjust-
able from 2:1 to 6:1. Output level is a nominal 3 volts
peak-to-peak into a 1000 ohms to ground. (J2)
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c. 100 kHz Sine Wave
Signal level 1 volt peak-to-peak into 10,000 ohms load
to ground. (J3)
1.2.1.3 Operating Controls
a. Switch, Power OFF-ON. Turns off internal battery when
equipment is not in use.
b. - Switch, OPERATE-RESET. Used to reset generator to zero
if ground preset unit is not available.
1.2.1.4 Output Connectors
a.
b.
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of code accuracy after removal of umbilical.)
100 kHz output J3 (miniature coax UG1468/U) connects
the 100 kHz sine wave to desired load.
External preset connector J1 (Deutsch DSM04-7-15S) con-
nects the generator to the GPU for charging battery and
presetting time.
Code Output J2 (Miniature coax - UG1468/U) connects
the serial time code to desired load. (Need not be con-
nected during preset; however, if connected to modulated
code input of Preset Reader, will provide a backup check
1.2.1.5 Equipment Mechanical Specification
a. Size (See Figure 1.1 for mounting dimensions)
b.
Approximately 6-1/4 x 3 x 2-7/8, including mounting base.
The unit is designed for direct mounting and no vibration
isolators are provided.
Weight
Approximately 35 ounces.
1.2.1.6 Environmental
a.
b.
Vibration
5 g's to curve B of MIL-STD-810A.
Shock
15 g's 11-millisecond duration in all three axes.
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c. Temperature and Humidity
0 to 60 degrees C at relative humidity of up to 95 per-
cent, without condensation.
d. Altitude
To 100,000 feet.
1.2.2 Ground Preset Unit Specification
1.2.2.1 Operating Controls and Indicators
a. Power Switch Si OFF-O N. Controls primary ac input
power.
b. Charger Switch S2 ON-OFF-TRICKLE. Controls opera-
tion of battery charger. Normal position during battery-
charge cycle is ON.
c. Mode Switch S3 CLEAR-SET-STOP-RUN. Allows preset
of time in airborne generator. CLEAR resets all registers
to zero. SET allows preset of hours, minutes, and seconds
into TCG, using pushbutton advance switch. STOP resets
minor counter in TCG to zero, register remains at preset
value (no output code). RUN mode is normal mode of op-
eration. The first register advance occurs one second after
unit is switched to RUN mode.
d. Time Set pushbuttons ADVANCE HOURS (S4), ADVANCE
MINUTES (S5), and ADVANCE SECONDS (S6). Depress-
ing these switches cause the time to advance in the respec-
tive registers.
e. Display Bulbs Vl to V6. The Nixie display exhibits the
register in hours, minutes, and seconds. The advance of
the register time is "on time" with the code.
f. Meter M1 shows the state of charge of the battery in the
airborne TCG. A fully-charged battery is at 9.6 volts.
1.2.2.2 Output and Input Connectors
a. J1 - Input Power MS3102A-10SL-3P.
A 115 volt, 50 to 400 Hz
B 115 volt return
C Chassis Ground
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b. J2 - Deutsch DSM04-7-15P. Connects the GPU to the
TCG. (See Dwg C-4896-70002)
c. Modulated Code J3 (BNC). Monitors the input code
from the TCG.
d. One-Pulse-Per-Second J4 (BNC). Provides method for
determining exact synchronization of generator. The
leading edge of the +4-volt pulse is "on time". The
pulse is 40 ms wide.
e. DC Code J5 (BNC). Monitors detected code.
1.2.2.3 Package
Overall dimensions are 5-1/4 inches high by 6-1/2 inches wide front
panel. (May be rack-mounted by providing extensions.) Unit extends
12 inches behind front panel. Add 2 inches for mating connector and
cable.
1.2.2.4 Power Input
The unit operates on 105 to 125 volts, 50 to 400 Hz, single-phase.
Power is less than 40 watts, depending upon battery-charger require-
ments.
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1.2.2.5 Battery-Charger Rate
The charge rate is a constant current providing a 85 percent charge
in approximately 12 hours or less. The current shuts off as the volt-
age approaches 9.6 volts across the battery. The unit may be oper-
ated while the charger is working.
1.2.2.6 Fuses
The equipment is protected by the following fuses:
Fuse Type Function
F1 1/2 Amp MDL AC primary
F2 1/4 Amp AGC +15-volt supply
F3 1/16 Amp AGC +200-volt display
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SECTION 2
INSTALLATION
2.0 INSTALLATION
2.1 Ground Preset Unit
a.
b.
The GPU may be rack-mounted in 5-1/4-inch panel height
by the addition of extension plantes on the front panel.
Optionally, the unit may be placed on the bench.
Connect the GPU to a source of ac power from 105 to 125
volts ac, 50 to 400 Hz. Avoid power lines with excessive
surges, since the unit may be damaged by line voltage in
excess of 175 volts ac for even short durations.
Connect the preset unit to the TCG by use of cable W1
which is prepared according to Section 2.3. The cable is
connected from J2 of the GPU to J1 of the TCG.
2.2 Airborne Time-Code Generator
a.
1
b.
Install the TCG in a position with base down. Other posi-
tions may result in a decrease of battery life. Caution: when 17- charging battery, airborne TCG must be mounted with mount-
i ng plate down or battery will leak with possible damage to
the circuit boards. See Figure 1.1 for mounting dimensions.
Use four each 6-32 screws to restrain unit. (Note that the
mounting plate may be removed and other more suitable
plates used, if required. Consult factory for any additional
mounting requirements.)
Airborne TCG Installation After Preset
In some applications, the generator is preset at some loca-
tion remote to the aircraft and the generator carried to the
aircraft and installed while operating. Do not operate con-
trol switch while installing. The unit must remain ON and
OPERATING during installation. After securing mounting
base, connect coax connectors to J2 and J3. The large
multi-pin connector JI is not used during normal operation.
This connector is only used on the ground to preset the gen-
erator and charge the battery.
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2.3 Cables
The TCG is connected to the GPU by a cable W1, which should not
be longer than 15 feet in length. A longer cable requires shielding.
a. Cable W1
b.
Connector P1 (TCG end) Deutsch DSM07-7-15P
Connector 62 (GPU end) Deutsch DSM07-7-15S
Connect pins indicated below with a No. 20 stranded wire
Type B20, or equal.
Connect pins 1, 2, 3, 4, 5, 6, 7, 8, 10, 13, 14, 16, 17, and
19.
Omit pins 9, 11, 12, 15, and 18.
Cable W2 (Power Cable - Preset Unit)
Connector P1 MS3106A-10SL-3S with cable clamp MS3057-4.
Connect power cord to pins as below.
Pin A 1 15-vol t ac
Pin B 115-volt ac return
Pin C Safety Ground
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OPERATION
3.0 OPERATION
3.1 Charge Battery
The TCG (Time-Code Generator) is operated only from the battery,
so for reliable operation, the battery must be charged properly to
obtain the operating time required. The following steps are to be
observed.
3.1.1 Connect Airborne Time-Code Generator to Ground Preset Unit
using cable Wl as in Section 2. Connect GPU to the power line.
Perform the following steps on the GPU.
a. Turn switch Si to ON. Nixie display lights up.
b. Place CHARGER switch S2 to ON.
c. Observe meter M1. Voltage should read between
5 and 9.6 volts, depending on state of charge.
3.1.2 Airborne Time-Code Generator
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a.
Place power switch to OFF during charge. The gen-
erator is still operable if the GPU is connected and
the charge time is minimized with this switch OFF.
b. Keep S2 in OPERATE position at alI times.
3.1.3 Keep charger at the ON position. The meter Ml should read 9.6
volts after the battery has charged. (Up to 16 hours, depending on
state of charge). At 9.6 volts, the charger will cut out. If it is de-
sired to keep unit at full charge for standby operation, charger
switch should be placed into TRICKLE. This reduces the possibility
of gassing off the water in the battery.
3.2 Preset Generator
The generator may be preset any time while it is connected to the
GPU. Observe the following steps.
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a.
b.
d.
e.
9.
Place Mode Switch S3 into CLEAR position, then move
to SET. The register display now reads all zeros.
Depress ADVANCE button until a forthcoming time is
preset into the hours, minutes, and seconds register.
Place Mode Switch S3 into STOP position as soon as
correct time is set into register.
Wait for clock time to equal register time. Turn Mode
Switch S3 to RUN the moment this time is reached. The
register will advance one second later.
Observe the operation of the display. The time will
advance normally if the unit is operating correctly.
NOTE: Several seconds may elapse before a correct
time is read after starting. This is due to the AGC in
the reader adjusting tote signal level.
Turn TCG power switch to ON. IMPORTANT.
Remove the large connector from the TCG. The unit
is now ready for operation.
3.3 Operation
The generator wi I I operate for a period up to 24 hours on one charge,
depending upon the condition of the battery and temperature of oper-
ation. The generator may be turned OFF any time during operation
to conserve the battery charge. The charge will be substantially the
same for several days or longer, depending on the condition of the
battery. After usage, turn generator OFF. If the unit is to be stored
for extended periods of time, run generator until battery is discharged
to 5 volts, then turn OFF. Battery condition may be checked at any
time by plugging in the GPU. Be sure charger switch is OFF, to check
level of battery.
3.4 Emergency Operation
The generator may be run without a GPU for preset by placing the
OPERATE-RESET switch into the RESET position and returning to
OPERATE position. The unit counts from zero time through 24 hours
and repeat. The battery must be in a charged condition for operat-
i ng.
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SECTION 4
4.0 MAINTENANCE
4.1 Maintenance - Airborne Time-Code Generator
There are two items requiring maintenance in the TCG. The battery
needs an occasional check for fluid level, and the oscillator requires
a frequency adjustment.
4.1.1 Battery-Level Check
Charge battery to full capacity. (See Section 3.1). Remove mount-
ing plate from bottom of unit by removal of the two rows of screws.
Remove the left side cover nearest the power switch. This exposes
the battery and oscillator. See Appendix I for detailed instructions
on the care of the battery.
4.1.2 Oscillator Frequency Check
WARNING: Do not reset oscillator unless source frequency has a
frequency of better than p part in 107. Observe frequency at the
100 kHz output connector. Adjust frequency by inserting a minia-
ture screwdriver into the adjustment hole on the bottom of the unit.
The mounting plate must be removed to reach this hole.
NOTE: Clockwise rotation of control decreases frequency with an
adjustment sensitivity of one part in 10-6 for each half-turn of ro-
tation.
Check operation by running unit against standard such as WWVfor
24 hours, and observe time drift. Drift should be less than 50 ms in
a normal room environment for a 24-hour period.
4.2 Preset Unit Check
4.2.1 Battery Charger Cut-Off Voltage Check
The GPU requires periodic checking to see if the meter and charging
circuit is operating correctly.
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Connect TCG as in paragraph 3.1, except remove terminal + from
battery, as per paragraph 4.1.1. Place a 1000-ohm resistor between
the red battery lead (disconnected from battery) and the return blank
lead (ground). Connect a calibrated digital voltmeter across the re-
sistor. Measure voltage. Adjust R5 in charger if voltage is not be-
tween 9.25 and 9.35 volts. Reconnect battery lead.
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The Airborne Time-Code Generator (TCG) performs the following
functions:
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a. Generates serial time-of-day code modulated on a
1000-Hz carrier.
b. Provides a 100-kHz sine-wave output.
c. Operates for 24 hours on self-contained battery.
d. Can be remotely preset and monitored by the
Ground Preset Unit (GPU).
e. Internal TCG battery is charged by GPU.
The Ground Preset Unit (GPU) performs the following functions:
a. Contains reader circuit to decode and display serial
b.
C.
d.
time code.
Has control circuits to stop and preset TCG.
Contains battery charger and meter to charge and
monitor the voltage of the internal TCG battery.
Operates from 115-volt, 50- to 400-Hz power.
5.1 Airborne Time-Code Generator
5.1.1 Input Circuits
The diagram of the chassis wiring is in Fig. 5.1. This shows the input
panel connector J1, the oscillator Y1, the battery, series regulator,
and bottom board connector. The battery voltage is reduced to +5
volts by the series regulator Q1. Panel switch S 1 removes battery
from circuit. Panel switch S2 is used as a reset of internal dividers.
The generator starts at zero time when this switch is depressed and
released. The oscillator output is a one-mHz (megaHertz) signal
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which is a square wave of 4 volts amplitude from 0 volts to +4 volts.
The battery voltage is 9.6 volts at full charge (with charger on), and
drops to approximately 6 volts when the unit becomes inoperative.
board PC-1 to the chassis and output connector wiring. The second
board PC-2 plugs into the male pin which protrudes from the compon-
ent side of this board. The input-output board PC-1 performs the fol-
lowing circuit functions:
5.1.2 Input-Output Board PC-1
The board PC-1 plugs into the connector PI mounted on the chasis.
The 19-pin connector is on one end of the board and connects this
a. Regulates battery voltage to +5 volts.
b. Divides 1-mHz signal to 1000 Hz.
c. Modulates code on 1000-Hz carrier.
d. Generates 100 kHz sine wave.
e. Provides termination and filters input
signals from GPU.
r
5.1.2.1 Power Regulator
The output of the battery is regulated by the series regulator in the
chassis. The regulator amplifier consists of Q1 and Q2, and associated
circuits on PC-1. Q1A is an emitter-follower which has an almost con-
stant output voltage driving the second zener diode CR2. The voltage
from CR2 is fed to one side of the differential amplifier Q2A and Q2B.
The base of Q2B is driven from the divider R13 and R12 which monitors
the regulator output. Transistor Q1B is an amplifier which drives the
external series regulator. Table 5.1 shows voltages at each transistor
element for this board.
5.1.2.2 Divider - 1 mHz to 1000 Hz
This divider, located on the PC-1 board, is a flip-flop divider chain
consisting of divide-by-five and divide-by-two circuits. All of the
digital circuits use a low-power R-S Master-Slave integrated-circuit-
type flip-flop. Data sheets for the items used are to be found in the
Appendix. Note that all flip-flops are externally connected (Q to
Reset gate input and7U to Set gate input) to provide the logic equiv-
alent of the J-K flip-flop.
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All logic circuit elements are powered from the +5 and ground supplies.
Output logic levels are specifically described in the product bulletin
but, generally, all signals described as a 0 logic level is between 0 and
+0.2 volts, and a 1 logic level between +4 and +5 volts. Waveforms are
very fast - in the order of 20 to 20 ns rise and fall times.
Divider waveforms are shown in Fig. 5.5. These waveforms are identical
for all dividers, and differ only in pulse rates. Shown are the flip-flop
waveforms for all the circuits.
The divider on PC-1 consists of a series of = 5 and ; 2 stages. Flip-flops
Al, A4, A2 are a 5 circuit, and A3 a binary divider stage. These divide
the 1 mHz down to a 100 kHz square wave. This square wave is fed to the
100-kHz shaper. (See Section 5.1.2.4). The 100 kHz is further divided
to 1 kHz by two successive . 10 circuits comprised of A5, A7, A6 (. 5),
A8 (-,2), A9, All, A10 (-,5), and A12 (-'2). The output of A12 is a1000-
Hz square wave.
All dividers have a common reset line on pin 5. This reset line normally
sits at +5 volts, held by R37. The reset signal, a 0, forces all flip-flops
to logic 0 output on pin 12 (Q output). The reset is present when the
unit is first preset by the GPU, or when S2 on the front panel of the
TCG is pushed to RESET.
The output of A12 (1000-Hz square wave) is fed out to the connector PI
pin 6. It is jumpered back to the board on pin 22. This jumper may be
removed during test and a 1-mc from the oscillator Y1 or external signal
from a generator fed into pin 22. These higher-speed signals allow more
rapid testing of the registers by speeding up operation of the slowerstages.
5.1.2.3 Modulator
The code output from the generator is modulated on a 1000-Hz carrier.
This modulator is found on PC-1 and consists of a sine-wave shaper, a
modulator, an amplifier, and output stage. The 1000-pps square wave
is filtered in L1, C8, C9 into a 1000-Hz sine wave. Capacitors C8 and
C9 are selected so that the zero crossing of the sine wave is in synchro-
nism with the input square wave. Transistor Q4 is a FET, and provides
a high-impedance output for the tuned circuit. The modulator is aFET
Q3. This transistor clamps a percentage of the sine wave to ground as
selected by the modulation-ratio potentiometer R19. Modulation ratio
can be set between 0 and 100 percent by use of this control. The mod-
ulated signal is fed into the differential amplifier Q5. The Q5B input
is a feedback input, and is used to reduce the output impedance. The
feedback is fed through the network R23, C13, and R22. The output
5-3
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FLOW CORPORATION
driver transistor is Q6B. The output is coupled by a capacitor C12 which
eliminates the dc offset. Levels of quiescent voltage of all transistors
may be found in Table 5.1. The output ac level is 3 volts peak-to-peak
under no load. Output impedance is under one hundred ohms, but power
limitation restricts the load resistor to greater than 1000 ohms.
5.1.2.4 Sine-Wave Shaper - 100 kHz
The 100 kHz square wave from flip-flop A3 is converted into a sine wave
by the network L2 and C15, C16. The output of this network is fed to Q7
and then coupled to the output amplifier Q8A and the driver transistor
Q8B. The output level is a 1 volt peak-to-peak, with an output imped-
ance of approximately 250 ohms.
I
5.1.2.5 Input Filters
The signals used by the preset unit (GPU) to set in a desired time-of-day
are filtered on this board PC-1 before being used by the register and di-
vider. The filter capacitors C1 through C5 are used to protect the CLEAR,
SET, ADVANCE SECONDS, ADVANCE MINUTES, and ADVANCE HOURS
lines from external noise pulses on the preset line. The pull-up resistors R1
through R5 insure a logic 1 at the input of all gates when preset unit is dis-
connected.
5.1.3 Divider-Decoder Board PC-2
The divider-decoder board is used to divide the 1000-pps signal output
from PC-1 down to 1 pps, and to generate waveforms used in the construc-
tion of the code format.
1
5.1.3.1 Divider Flip-Flops
The 1000-pps signal is divied by two 2 flip-flops A17 and A16. This is
fol lowed by _ 5 D15, D16, and D17. The output of D17 is 50 pps. This is
followed by a - 2 A12 giving 25 pps, the basic code rate. This 25 pps is
divided down to 1 pps by two -5 chains A19, A20, A21, and A22, A23,
A15.
5.1.3.2 Code Format
The function of the gates Al, A2, and A3 is to generate the basic code
elements of code zeros, code ones, and code markers. These elements
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 I FLOW CO 1 P O RARelease 004/02/09 : CIA-RDP71 B00399R000300150001-0
t
are width-coded, and are inserted into the code format at appropriate times.
The code elements have the following lengths:
Code 0
12 ms
Code 1
24 ms
Code Marker
36 ms
Code Bit Period
40 ms
(25 pps)
1
The code format may be found in the Fig. 5.5, which shows all waveforms.
Note that the trailing edge of each code element is "on time".
The code zeros (inverted) are viewed at pin 14 of the gate Al, code ones
at pin 5 of Al, and markers at pin 10 of A3.
The code ones are gated by the output of the register scan gates coming
into Al pin 10. The code ones are on Al pin 9. The output of Al pin 8
is the code ones (inverted). The zeros and gated ones are "or" gated, and
the output of A2 pin 14 is the code zeros and ones. These are gated in A2
pin 1 and 2 by the pin 10 output of A15. This removes alI moculation from
the code during the last 0.2 seconds of each second. The code marker is
gated on once each second during code element 25, forming a marker with
the trailing edge on time at the second. The combined and completed code
is found at pin 5 of A2. This code is fed to the modulator through inter-
board pin 3.
5.1.3.3 Decoder X signals
The divider A19, A20, A21 is a 5 with 25-pps input and 5-pps output.
The flip-flops have five combinations in the divide-by-five cycle. These
five combinations are decoded into a five-line output, each one for a
given period of 40 ms. Only one line is a "one" at any time. See wave-
forms, Fig. 5.5.
5.1.3.4 Decoder Y Code Group Gates
The dividers A22, A23, and A15 form a . 5 chain with 5-pps input and 1-
pps output. These five combinations are decoded into five separate sig-
nals which are observed at the outputs of the gates A7 pin 8 (Y0), A7
pin 14 (Y 1), A6 pin 8 (Y2), A6 pin 14 (Y3), and A 15 pin 12 (Y4). These
signals are used to gate out groups of code scan outputs. The group GO
is gated by YO, G1 by Y1, G2 by Y2, and G3 by Y3. These four scan-
gate groups are obtained from the register board PC-3. The outputs of
these are "or" gated, and the output of A14 pin 10 are the scan-gate
outputs which gate out the code "ones".
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 A proved For Release 2004/02/09: CIA-RDP71B00399R000300150001-0
FLOW CORPORATION
5.1.3.5 Register Seconds Advance
t
The inputs to the register board PC-3 are through A18* pin 5 and A18*
pin 8. The double inversion does not modify the 1-pps signal, except
during the preset. Normally, the inputs of A18 pin 6 and A18 pin 9
are "ones". During preset the SET line is a zero, making the output
of A18 pin 5 a one. This enables the following gate, and successive
grounding of the ADVANCE SECONDS line advances the seconds reg-
ister one second for each push of the preset switch.. Since the code
scan must take place before the new number appears in the register
display, the advance of the numbers must be done slowly to prevent
passing the desired number.
*On PC-2 board.
5.1.4 Register Board PC-3
The register board is the third board in the stacked assembly. It con-
tains the flip-flop dividers which generate the BCD (binary coded
decimal 8 - 4 - 2 - 1) time-of-day. The condition (zero or one) of
the register flip-flops are scanned once each second to generate the
new second-minute-hour time-of-day code.
1
1
5.1.4.1 Register Flip-Flops
The time is stored in the register counter flip-flops. The dividers are
weighted in a BCD 1-2-4-8 format. The seconds divider is a divide-by-
ten, followed by a divide-by-six. The waveforms are on the Waveform
Drawing Fig. 5.5. The designation of each flip-flop, such as 10S (10
seconds), indicates the time at which the flip-flop first is set, and is
also the weight of the code-bit element.
The register counts up to 23:59:59 and recycles to zero. The final
divider chain is a divide-by-twenty-four counter to provide for the
hours cycle.
t
The scan gates are used to generate the "ones" information in the out-
put code. For example, if the 10S (ten-second) flip-flop is set, the car-
responding bit in the code is a "one". In like manner, all of the 20bits
in the code are controlled. The scan gate opens the path from the flip-
flop to the "one gate" on PC-2 over the first twenty periods of the twen-
ty-five-pulse-per-second code. The scan gates are in a series sequence.
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The two-second (2S) flip-flop, for example, is scanned by the X3 signal.
The output of this gate appears on pin 6 of the interboard connectors as
G3 (Group 3). The G3 signal is gated on PC-2 at time Y3. The effect
is to open the gate to the 2S flip-flop at X3, Y3 time. The twenty gates
are opened in sequence so that the 20 flip-flops are scanned in order
from high order to low order.
5.2 Ground Preset Unit
(Dwg R 4896-71006-)
The Ground Preset Unit operates during the battery charge and time pre-
set periods. The following circuits will be discussed in detail:
a. Logic power supply.
b. Battery charger.
c. Preset circuits.
d. Reader-display logic.
e. High-voltage regulator.
In addition, the individual cards are described in detail.
5.2.1 Logic Power Supply
(Dwgs 4896-71001 and 4896-71002)
The logic power supply provides the regulated +5 volts for the operation
of digital integrated-circuit boards. I n addition, it provides an unregu-
lated +15 and -15 volts, which are used by the battery charger and AGC
boards.
1
The power transformer is provided with +5 percent taps for adjustment of
incoming voltage for marginal power operation, although the normal oper-
ating range is from 105 to 125 volts ac.
The transformer has the following specifications:
Pins
Winding
Voltage
1 (2),3(4)
Primary
115 volts, 50 to 400 Hz, +5% taps
5, 6, 7
Secondary No. 1
7.0-0-7.0 volts, 5 amperes
8, 9, 10
Secondary No. 2
12.0-0-12.0 volts, 0.2 amperes
11, 12
Secondary No. 3
160 volts, .030 amperes
All voltages are rms read across windings with an isolated meter.
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The output of secondary is full wave rectified by CR1 and CR2 with filter
capacitor C1. The output is approximately 9 volts, unregulated. Thisvolt-
age is regulated by the series pass transistor Q1 with A2 as an emitter-
follower driver.
1
1
1
1
The plus and minus 15-volt supplies are rectifed by full-wave rectifiers
on the regulator board. The output of the plus 15-volt supply is from
pin 13 on A108 and filtered by C2. This current is used to charge the
battery in the TCG. The minus 15-volt is from pin 16 of A108. This
voltage is used as a bias on the battery monitor and as a supply for the
AGC board A101.
5.2.2 Battery Charger
The battery charger is a simple resistor current-limited supply with a
shunt regulator. The basic charge current comes through a 35-ohm re-
sistor R3 for a nominal 200-ma charge current for normal CHARGE setting,
or a 330-ohm R4 for a 20-ma trickle charge. The output of the battery is
monitored by the meter and the viewing network CR4 and R5. The poten-
tiometer R5 is adjusted to turn on the shunt regulator transistor Q4 when
the voltage of the battery reaches the peak charge value of 9.3 volts.
The base of the transistor Q4 is held negative until the battery nears the
full charge voltage. At this point, the Q4 is turned on until all of the
charger current is shunted by this transistor. The Appendix contains com-
plete instructions on care and maintenance of the battery.
5.2.3 Preset Circuit Operation
The switch S3 is used in conjunction with the pushbutton switches S4, S5,
and S6 in setting a desired time into the airborne time-code generator.
The following listing shows the effect of each position of S3 on the air-
borne time-code generator.
a.
CLEAR
Register reset to 0, Divider reset to 0, no code output.
b.
SET
Divider operating, code output, register not advancing
at 1 pps, register may be advanced by pushbuttons S4,
S5, or S6.
c.
STOP
Divider reset to 0, register static at preset number, no
code out.
d.
RUN
Generator operating independently. All input circuits
open.
I
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t
Note that while in the STOP position, the code is not generated and the
reader does not function. The number last read will be in the display reg-
ister. When the unit is switched to RUN, a short time may elapse for the
reader to be synchronized to the incoming code before the correct number
appears. (AGC time response).
5.2.4 Reader Logic
The reader logic is comprised of diode-transistor integrated-circuit pack-
ages mounted on seven circuit boards. The exact specifications for each
package may be seen in the Appendix. However, as a general rule, the
logic modules operate from the +5-volt to group supply. All levels of
signals are 0 to +0.2 volts for a logic 0, and 4.0 to 5.0 for a logic 1. The
linear amplifiers on the AGC card (A101) are operated from +12 and -6
volts derived from the + and -15-volt supplies. The basic logic rules are
to be found in the logic circuit specifications, and are not repeated here.
Waveforms are presented with each circuit card description.
5.2.4.1 Overall Operation
The reader unit consists of the following logic divisions:
1
1
a. Automatic Gain Control - Trigger Board A101
(Dwg D4876-70506)
b. Code Decoder Board A102 - (Dwg 101-40121)
c. Counter (. 10) A103 - (Dwg 10 1-40409)
d. Divider-Decoder Board A104 - (Dwg 101-40122)
e. Time Register - Seconds-Minutes-Hours A105,
A106, A107 (Dwg 101-40106)
The function of the reader is to read the incoming code bit by bit, into
the display register (scan-in code). The code is generated during the
first 0.8 seconds of each second, and defines the time at the beginning
of that code frame. (See time-code format.) During the first second,
the code is read into the display one element at a time, so that at the
end of 0.8 seconds, the time at 0.0 seconds is displayed. At the start
of the next second, the time in the register is updated by one second,
so that the time display is "in phase" with the real time as generated.
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Since the updated time in the register is identical to the time coded in the
time code, the scanning in of the time into the display register does not
change the number in the display unless the incoming time bit is in error.
Errors in the generated code are observed as changes in the display during
the second after the normal advanced time.
1
1
5.2.4.2 Automatic Gain Control - Trigger Board A101
(Dwg D4876-7050-6T_
The AGC trigger board receives the incoming code and detects two points
on the wave with the level triggers. One trigger is set at the zero crossing
level, so that each cycle is reproduced as a square-wave output. The sec-
ond trigger is set to trigger on the "large cycles" of the code. The outputs
of this trigger are only present when the tops of the large cycle are present,
and only for one polarity. That is, the positive cycle top is detected and
the negative cycle top is not. The outputs of each cycle trigger (EC) and
large-cycle trigger (LC) are fed to the code-detector board. The output
signal is approximately 2 volts peak-to-peak over the AGC range.
5.2.4.3 Code-Detector Board A102
(Dwg 101-40121)
The code-detector board receives the LC trigger and EC trigger and decodes
these signals into weighted code elements in zeros, ones, or markers. The
outputs of the board are shown in Fig. 5.6. These outputs occur a millisec-
ond after the end of the code bit. Since all the code bits occur with trail-
ing edge "on time", these outputs all occur at the same relative time at a
25-pps rate. The pulse Al (pin 14 of A102) occurs for each code bitalong
with CO (pin 15 of A102) if the bit was a zero, C1 (pin 11) if the bit was a
one, or M1 (pin 12) if the bit was a one-second marker. The jumpers from
D1, D2, D4, and D8, and the complements are connected to the gates at
the inputs of the three-code element flip-flops which determine the pres-
ence of a zero, one, or marker. The large-cycle counter is composed of
the two divide-by-two counters, followed by the Dl FF, D2 FF, D4 FF,
and D8 FF, all connected as binary counters. The three-code element
flip-flops 0, 1, and M1 flip-flops are set as the large-cycle counter ar-
rives at numbers corresponding to the cross-over count between the length
of a zero, one, and marker-code element. The listing below shows the
setting of the code-element gates.
Large-Cycle Counter Function
8 Set "0" flip-flop
20 Reset "0" flip-flop - Set "1" flip-flop
32 Reset "1" flip-flop - Set Marker flip-flop
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Therefore, the reader determines that the code element is a binary zero if
the large-cycle count is between 8 and 20 (zeros are 12-ms long); a binary
"one" is between counts of 20 and 32 (ones are 24-ms long); a marker from
count of 32 up (markers are 36-ms long). These counters provide a large
tolerance for noise, and should read the code with great precision.
5.2.4.4 Cycle Counter A103
(Dwg 101-40409)
t
cycle counter is a BCD-connected, divide-by-ten counter which is
used to count each cycle. The output of this counter is used to advance
the divider-decoder board counter. The cycle counter has a 1000-pps in-
put which is the EC signal from the code trigger. The counter output isat
100 pps (every 10 ms). This counter is reset by the end of code-bit signal
every 40 ms.
5.2.4.5 Divider-Decoder Board A104
(Dwg 101-40122)
t
The divider-decoder board is used to generate a group of five x andfive Y
signals which together define any of the twenty-five code-bit periods in
the time cycle. The binary counters at the input of this board divide the
100-pps down to 25 pps, the code-bit rate. The three flip-flops in the di-
vide-by-five reduce the rate to 5 pps. The five states of these flip-flops
are decoded into the X0, X1, S2, X3, and X4 signals. The last three flip-
flops on A104 divide the 5-pps signal down to 1 pps. The states of these
flip-flops are also decoded into five Y signals, YO through Y4. The X and
Y signals are used to scan in the time-code bits into the respective flip-
flops. The combination of X and Y signals define any of the 20 code-bit
positions.
5.2.4.6 Register Boards A105, A106, A107
(Dwg 101-40106)
The three register boards each consist of a BCD-connected divide-by-sixty
counter (or divide-by-twenty-four for A107). The flip-flops which consti-
tute the storage elements in this counter each have a parallel entry gate
which allows individual set or clear of any flip-flop element in the coun-
ter chain. This parallel entry is controlled in time sequence bytheX and
Y counter which opens each series of parallel entry gates according to the
weight of the input-code bit. If the bit is a zero, the corresponding flip-
flop is cleared; if a one, the flip-flop is set. The purpose of connecting
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these flip-flops in a counter chain is to provide for advancing the count in
the register at the second so that the register display corresponds to the real
time represented by the code.
The entry into the register are the C1 or CO lines which represent the code
ones and code zeros. The C1 line becomes a logic 1 when the flip-flopcor-
responding to the code element is to be set and the CO line becomes a logic
.1 when the flip-flop is to be cleared.
5.2.4.7 Display Drivers V1 to V6
The displays and drivers are mounted behind the front panel, and display
the contents of the register. The flip-flop outputs and complements are fed
to the Nixie driver modules*. The high voltage (+200V) is fed into pins 11
of each module, and the logic return for the decoders is on pin 12, which
sits at +2 volts. The zener diode I N702, mounted behind the V1 driver, pro-
vides this bias for the Nixie driver.
*Burroughs Bipco Type 8211-P (Data Sheet in Appendix)
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Table 5.1
TRANSISTOR VOLTAGES
s
I
TRANSISTOR
ELEMENT VOLTAGE
Symbol
Type
Emitter
Base
Collector
Q1A
MD3251AF
5.0
4.4
0
Q1 B
MD3251AF
E
tt
B
E -1.0
tt
B
5.0
a
ery
a
ery
Q2A
SP8888
3.0
3.6
E -1.0
Battery
Q2 B
SP8888
3.0
3.6
+5
Q3
2N2843
0
0 V
0
Q4
2N2608
+2.5
+5.0
0
I Q5A
MD3251AF
+3.0
+2.4
+0.6
Q5B
MD3251AF
+3.0
+2.4
!! 0
Q6A
SP8888
0
+0.6
+3.0
1 Q6 B
SP8888
+2.4
+3.0
+5
Q7
2N2608
+4.5
+5.0
1 0
Q8A
SP8888
+1.5
1.8
3.5
Q813
SP8888
+3.0 V
3.5
+5.0
NOTE: All voltages measured with S2 in RESET position.
t
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1.0 INTRODUCTION
1.1 The YARDNEY SILCAD cell is a silver-cadmium cell which differs con-
siderably from the more familiar lead-acid cell and, to a certain extent,
from other alkaline cells such as nickel-cadmium, nickel-iron, etc. The
silver-cadmium cell also differs in operation and performance from the
Yardney Silvercel (silver-zinc) cell.
Silver (the positive electrode) and cadmium (the negative electrode)are
employed as the active elements, while the electrolyte isastrong solution
of postassium hydroxide (KOH). The techniques for operating the Yardney
Silcad cell are quite simple, and should be followed closely for optimum
performance.
1.1.1 We recommend that the entire instruction be read carefully before using
the Yardney Silcad cell.
2.0 PRECAUTIONS
2.1 For Handling or Accidental Exposure to Electrolyte
2.1.1 General Comments
The electrolyte (a strong solution of potassium hydroxide) is alkaline and
corrosive. It should be handled with care. If neglected, the electrolyte
will cause serious burns when it is permitted to come in contact with the
eyes or skin. Alkali-proof apron, rubber gloves and splash-proof goggles
or a face mask are recommended for personnel engaged in the filling and
servicing of Silcad cells.
1
2.1.2 Antidotes, Internal
Give large quantities of water and a weak acid solution such as vinegar,
lemon juice, or orange juice. Follow with one of the following: white-
of-egg, olive oil, starch water, mineral oil, or melted butter. Obtain
medical attention at once.
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2.1.3 Antidotes, External
2.1.3.1 Thoroughly flush the affected area (skin or eyes) with large quantities of
clean, lukewarm water. Neutralize, if possible, with a saturated solution
of boric acid. Vinegar, lemon juice, acetic acid, etc., may be used on
the skin, but should never be used for the eyes. Obtain medical atten-
tion at once.
2.1.4 Washing Glassware
The electrolyte is somewhat corrosive to glass. All beakers and syringes
should be thoroughly washed with water following their use.
2.1.5 Carbon-Dioxide Absorption
Store the electrolyte in closed alkali-resistant containers, as it absorbs
carbon dioxide from the air. Prolonged exposure to the air will impair
the properties of the electrolyte.
2.1.6 CAUTION: Do not, under any circumstances, attempt to use
any type of electrolyte other than the special
electrolyte furnished with the Yardney Silcad
cell. Other types of electrolyte will destroy it.
2.2 For Handling the Cell
2.2.1 The cell is capable of supplying unusually high currents if it is acciden-
tally shorted. A prolonged short may cause serious burns to personnel
and may destroy the cell. To avoid accidental short circuits, all tools
used in connection with the cell or within close vicinity of the cell
must be properly insulated with a double layer of electrical tape or
varnish.
1. The cell shall be kept upright under normal handling and
operating conditions.
2. When assembling a group of unsealed cells into a battery,
do not exceed the recommended maximum torque for
tightening the top terminal nuts.
3. Only the uppermost of the nuts on each of the cell's ter-
minals should be removed for assembly. The lower nut,
which rests on the cell cover, forms an integral part of
the terminal-to-cover seal; removal of the lower nut
may break this seal.
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3.0 CHARGING PRACTICES
3.1 For best results, the Hardney Silcad cell should be charged in an ambient
temperature of 70 to 90 degrees F. Charging can be accomplished byeither
the Constant-Current or Modified Constant-Potential method. While the
Constant-Current method provides the fastest means of recharging and the
best pre-performance check of expected operation, the Modified Constnat-
Potential method requires much less personal attention, and can be accom-
plished with equipment of a much less complex nature.
3.1.1 Constant-Current Charge Method
Charge the cell at the rate specified in the attached Appendix until the
cell voltage increases to the specified value. The cell voltage is to be
measured at the cell terminals, while the cell is being charged.
3.1.2 Modified Constant-Potential Charge Method
This type of charge system consists of a constant-voltage supply modified
by a current-limiting circuit or a resistor. The system should be designed
in such a manner that when the cell has reached the final (cut-off) volt-
age specified in the attached Appendix, the current flowing through the
cell will not exceed the recommended maximum; further, the initial surge
current should not exceed the recommended maximum value. As the charge
progresses, the current will gradually taper off from the initial value. Charge
the cell in this manner until the cell voltage increases to the value specified
in the Appendix. The cell voltage is to be measured at the cell terminals,
while the cell is being charged.
4.0 DISCHARGE PRACTICES
4.1 The Yardney Silcad cell is designed for low to medium rate discharges. For
optimum performance, the cell should not be discharged continuously at a
rate higher than in the maximum value specified in the attached Appendix.
5.1 A minimum of maintenance is usually required to keep the Silcad cell in
optimum operating condition. The cell vent hole and vent valve (for un-
sealed cells) should be occasionally inspected to be sure they are not
clogged.
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09: CIA-RDP71 B00399R000300150001-0
FLOW CORPORATION
FUNCTIONAL USE
Constant-Current Charge Rate 0.14 amperes
Maximum Initial Charge Rate
(Modified C.P. Charge) 0.28 amperes
Maximum Final Charge Rate
(Modified C.P. Charge) 0.01 amperes
Final (Cut-Off) Voltage 1.60 volts
Recommended Maximum Continuous
Discharge Rate 2.0 amperes
Nominal Capacity 2.0 ampere/hours
Nominal Load Voltage 1.1 volts
Final (Cut-Off) Discharge Voltage* 0.6 volts
Maximum Torque (Top Terminal Nuts -
Unsealed Cells) 6-10 In/Lbs
*NOTE: If cells are assembled into a series-connected
battery, final (cut-off) voltages should be as
follows:
Charge: 1.55 x number of cells in battery
Discharge: 0.9 x number of cells in battery
1
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
FLOW CORPORATION
1
t
Miniature time-code generators may have a parallel output option, and
are readily identified by a rectangular output connector.
Figure All-1, AIII-2, AIII-3 and AIII-4 document the changed units. A
fourth card, PC-4, is added, which provides parallel output buffers for
twenty bits of BCD time, 1 pps, and ground. Logic one is +2.4 to +5.5V,
logic zero is zero to +0.3 V. Drive capability on each line is -1.8 milli-
amperes maximum when at logic zero. Output impedance when at logic
one is about one kilohm. Outputs are short-circuit-proof to ground.
Short-circuit current is between 3 and 15 milliamperes. 1 pps has tran-
sition from high to low on time.
AIII-1
I
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 This announcement provides preliminary engineering Information on new Texas
Instruments products. Definitive specifications are now being prepared for publication.
SERIES 54L, 74L
~Oisa QI UVS!? SEMICONDUCTOR NETWORKS'
LOW-POWER TRANSISTOR-TRANSISTOR LOGIC CIRCUITS
FOR AEROSPACE COMPUTER AND CONTROL SYSTEM APPLICATIONS
description
Series 54L integrated circuits have been designed and characterized for aerospace applications where high d-c noise margin, low
power dissipation, and high reliability are important system considerations. Definitive specifications are provided for operating
characteristics over the full military temperature range of -55?C to 125?C. Series 54L devices ore available with additional high-
reliability processing as specified in General Specification for SNR, SNIT SOLID CIRCUIT Semiconductor Networks. This logic
series includes the basic gates, flip-flop elements, and storage elements needed to perform most functions of general-purpose
digital systems.
Series 74L circuits are characterized for operation over the temperature range of 0?C to 70?C.
LOW SYSTEM COST
? maximum number of circuits per package through use of 14-lead package
? alternate package configurations available
OPTIMUM CIRCUIT PERFORMANCE
? very low power dissipation - typically I mW per gate at 50% duty cycle
? relatively high speed - typical gate propagation delay time of 33 ns
? high d-c noise margin - typically one volt at 25?C
? low output impedance provides low a-c noise susceptibility
? waveform integrity over full range of loading and temperature conditions
? fan-out - 10 Series 54L loads
- 1 Series 54 load and 2 Series 54L loads
- 1 Series 54H load
? a standard Series 54 output will drive 40 Series 54L loads
Page
LOGIC DEFINITION AND SYMBOLS . . . . . . . . . .
2-3
DEFINITIVE SPECIFICATIONS . . . . . . . . . . . .
4-19
GATE PROPAGATION DELAY TIMES . . . . . . . . . .
20
FLIP-FLOP WAVEFORM DEFINITIONS . . . . . . . . . .
21
TYPICAL CHARACTERISTICS . . . . . . . . . . . . .
22-23
MECHANICAL DATA . . . . . . . . . . .
24
Texas Instruments reserves the right to make
changes at any time in order to improve de-
ign and to supply the best product possible.
I Approved
SC-10218
JULY 1967
REPLACES SC9592, MARCH 1967
TEXAS INSTRUMENTS
I N C O R P O R A T E D
SEMICONDUCTOR-COMPONENTS DIVISION
 A proved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
SERIES 4L, 74L
we
&Zia SlZ?? SEMICONDUCTOR NETWORKS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply Voltage VCC (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Input Voltage Vin (See Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating Free-Air Temperature 13snge: Series 54L . . . . . . . . . . . . . . . . . . . 55?~Cto 125?C
Series 74L . . . . . . . . . . . . . . . . . . . . 0 to 700C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -65?C to 150?C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Input signals must be zero or positive with respect to network ground terminal.
logic definition
Series 54L and 74L logic is defined in terms of standard POSITIVE LOGIC using the following definitions:
LOW VOLTAGE = LOGICAL 0
HIGH VOLTAGE = LOGICAL 1
unused gates
Inputs of unused gates should be connected to ground. This sets the gate output to logical 1 to ensure minimum power dissipation.
unused inputs
Unused inputs, including preset and clear, must be maintained at a positive voltage greater than 2.4 V but not to exceed the absolute
1
maximum rating of 5.5 V.
Some possible ways of handling unused inputs are:
a. Connect unused inputs to VCC or a supply voltage of 2.4 V to 5.5 V.
b. Connect unused inputs, except preset or clear, to a used input of the some gate if maximum fan-out of the driving output
will not be exceeded.
C. Connect unused inputs to the logical "1" output of an unused gate.
input-current requirements
Input-current requirements reflect worst-case VCC and temperature conditions. Each input of the multiple-emitter input transistor
requires that no more than -0.18 mA flow out of the input at a logical 0 voltage level; therefore, one load (N = 1) is -0.18 mA
maximum. Each input (except the SN54L71R/SN74L71R, SN54L72R/SN74L72R, and SN54L73R/SN74L73R clock inputs) requires
current into thp terminal at a logical 1 voltage level. This current is 10 pA maximum for each emitter input. See fan-out capa-
bilities (below) and typical characteristics (page 23) for flip-flop clock input current requirements. Currents into the input terminals
are specified as positive values.
fan-out capability
Fan-out (N) reflects the ability of an output to sink current from a number of Series 54L or 74L loads at a logical 0 voltage level and
to supply current at a logical 1 voltage level. Each output is capable of sinking current or supplying current to 10 Series 54L/74L
loads (N = 10), or one Series 54/74 load and two 54L/74L loads. Load currents (out of the output terminal) are specified as negative
values.
A Series 54 or 74 output is capable of sinking current or supplying current to 40 Series 54L or 74L loads (N = 40). The buffer gate
(SN5440/SN7440) is capable of driving 120 Series 54L/74L loads. The carry output (Cn+1) of the SN5480/SN7480 is capable of
driving 20 Series 54L/74 loads and the A* and B* nodes may be used to drive 12 loads.
When fanning out into SN54L71R/SN74L71R, SN54L72R/SN74L72R, or SN54L73R/SN74L73R clock inputs no load current (Iload) is
drawn at Vin(clock) = 2.4 V. Therefore, the fan-out limitation is the (sink capability of the driving output. A Series 54/74 output
will sink sufficient current to drive 44 clock inputs (88 loads), and the SN5440/SN7440 will sink sufficient current to drive 133
clock inputs (266 loads). The Series 54L/74L output is capable of driving five 54L/74L clock inputs and one additional load.
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
jr
standard line summary
SERIES 54L, 74L
I?? SEMICONDUCTOR NETWORKS
SN54LOOR
S N54L10R
S N54L20R
SN74LOOR See-20ge 4
SN74L1OR See page 5
SN74L20R See page 6
/
~~-
I
QUADRUPLE 2-INPUT
TRIPLE 3-INPUT
DUAL 4-INPUT
POSITIVE NAND GATE
POSITIVE NAND GATE
POSITIVE NAND GATE
S N54L30R
S N54L51 R
S N54L54R
S N74L30R See-E e 7
S N74L51 R See.pp e 8
S N74L54R See e 9
I I
I
I I
,
8-INPUT
DUAL 2-WIDE 3-INPUT, 2-WIDE
4-WIDE 3-2-2-3-INPUT
POSITIVE NAND GATE
2-INPUT AND-OR-INVERT GATE
AND-OR-INVERT GATE
S N54L55 R
S N54L71 R
S N54L72 R
SN74L55R See page 10
SN74L71R See page 11
SN74L72R See page 14
I I
--
--
I
R2 Preset
R3 Q
Clock
t
I
I I
J2 Preset
J3 Q
Clock 1
I
_
S1 Q
K1 Q
S3 Clear
I
K3 Clear
I I
I
L-----I
I
L------J
I
L-----.J
2-WIDE 4-INPUT
R-S MASTER-SLAVE
J-K MASTER-SLAVE
AND-OR-INVERT GATE
FLI P-FLOP
FLI P-FLOP
DUAL J-K
MASTER-SLAVE FLI P-FLOP
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 w
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
TYPES SN54L00R, SN74LOOR
QUADRUPLE 2-INPUT POSITIVE NAND GATE
schematic (each gate)
14 13 12 11 if1 O9
V
j
positive logic
t
r
t
recommended operating conditions
Supply Voltage VCC: SN54LOOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LOOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Each Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: SN54LOOR . . . . . . . . . . . . . . . . . . . . . .
S N74 LOOR . . . . . . . . . . . . . . . . . . . . . .
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
10
-55
25
125
?C
0
25
70
?C
electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
VIn(1)
Logical 1 input voltage required
at all input terminals to ensure
logical 0 level at output
VCC = MIN,
Vout(0) 0.3 V
2
V
Vln(o)
Logical 0 Input voltage required
at any input terminal to ensure
logical 1 level at output
VCC = MIN,
Vout(1) 2 2.4 V
0.7
V
Vout(1)
Logical I output voltage
load =MIN,NA
-100
Vin = 0.7 V,
2.4
V
Vout(o)
Logical 0 output voltage
VCC = MIN,
(sink = 2 mA
Vin = 2 V,
0.3
V
Iin(0)
Logical 0 level input current (each input)
VCC = MAX,
Vin = 0.3 V
-0.18
mA
Iln(l)
Logical 1 level input current (each input)
VCC = MAX,
Vin = 2.4 V
10
pA
VCC = MAX,
Vin = 5.5 V
100
pA
1os
Short-circuit output current
VCC = MAX,
Vin = 0, Vout = 0
-3 -15
mA
ICC(0)
Logical 0 level supply current (each gate)
VCC = 5 V,
vin = 5 V
0.29 0.46
mA
1CC(1)
Logical 1 level supply current (each gate)
VCC = 5 V,
Vin = 0
0.11 0.18
mA
switching characteristics, VCC - 5 V, TA - 250C, N - 10 , see figure 1
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
tpd0 Propagation delay time to logical 0 level
CI = 50 pF
31 60
ns
tpol Propagation delay time to logical I level
C1 = 50 pF
35 60
ns
t For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable device type.
4 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 t
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
TYPES SN54L10R, SN74L10R
TRIPLE 3-INPUT POSITIVE NAND GATE
schematic (each gate)
1C 3Y 3C GND 38 3A 2C
14 13 12 11 10 ( (8)
positive logic
1
recommended operating conditions
Supply Voltage VCC: SN54LIOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74L l OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Each Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: SN54L1OR . . . . . . . . . . . . . . . . . . . . . .
SN74L10R . . . . . . . . . . . . . . . . . . . . . .
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
10
-55
25
125
?C
0
25
70
electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Vin(l)
Logical 1 input voltage required
at all Input terminals to ensure
logical 0 level at output
VCC = MIN,
Vout(0) 0.3 V
2
V
Vin(0)
Logical 0 input voltage required
at any Input terminal to ensure
logical I level at output
VCC = MIN,
Vout(1) 2.4 V
0.7
V
Vout(1)
Logical I output voltage
VCC = MIN,
lload = -100 pA
Vin = 0.7 V,
2.4
V
Vout(0)
Logical 0 output voltage
VCC = MIN,
(sink = 2 mA
Vin = 2 V,
0.3
V
in(O)
Logical 0 level input current (each input)
VCC = MAX,
Vin = 0.3 V
-0. 18
mA
in(1)
Logical 1 level input current (each input)
VCC = MAX,
Vin = 2.4 V
10
pA
VCC = MAX,
Vin = 5.5 V
100
pA
IOS
Short-circuit output current
VCC = MAX,
Vin = 0, Vout = 0
-3 -15
mA
CC(0)
Logical 0 level supply current (each gate)
VCC = 5 V,
Vim = 5 V
0.29 0.46
mA
ICC(1)
Logical I level supply current (each gate)
VCC = 5 V,
Vin = 0
0.11 0.18
mA
switching characteristics, VCC - 5 V, TA - 25?C, N - 10 , see figure 1
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
tpd0 Propagation delay time to logical 0 level
C1 = 50 pF
31 60
ns
tpol Propagation delay time to ogica 1 eve
C1 = 50 pF
35 60
ns
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 A proved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
TYPES SN54L2OR, SN74L20R
DUAL 4-INPUT POSITIVE NAND GATE
schematic (each gate)
t
recommended operating conditions
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
10
-55
25
125
?C
0
25
70
?C
electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)
14 13 12 11 10 O
IA lY NC VAC NC 2A 2B
positive logic
Y = ABCD
Supply Voltage VCC: SN54L20R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74L20R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Each Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: SN54L20R . . . . . . . . . . . . . . . . . . . . . . .
S N74L20R . . . . . . . . . . . . . . . . . . . . . . .
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Vin(1)
Logical 1 Input voltage required
at all Input terminals to ensure
logical 0 level at output
VCC = MIN,
Vout(o) s 0.3 V
2
V
Vin(0)
Logical 0 Input voltage required
at any Input terminal to ensure
logical I level at output
VCC = MIN,
Vout(1) -12.4 V
0.7
V
Vout(1)
Logical 1 output voltage
i VCC = MIN
load I.LA
Vin = 0.7 V,
2.4
V
Vout(o)
Logical 0 output voltage
VCC = MIN,
]sink = 2 mA
Vin = 2 V,
0.3
V
iin(o)
Logical 0 level Input current (each input)
VCC = MAX,
Vin = 0.3 V
-0.18
mA
iin(1)
Logical 1 level input current (each input)
VCC = MAX,
Vin = 2.4 V
10
pA
VCC=MAX,
Vin=5.5V
100
pA
IOS
Short-circuit output current
VCC = MAX,
Vin = 0, Vout = 0
-3 -15
mA
ICC(0)
Logical 0 level supply current (each gate)
VCC = 5 V,
Vim = 5 V
0.29 0.46
mA
ICC(1)
Logical 1 level supply current (each gate)
VCC = 5 V,
Vin = 0
0.11 0. 18
mA
switching characteristics, VCC - 5 V, TA - 25?C, N - 10 , see figure 1
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
tpd0 Propagation delay time to logical 0 level
C1 = 50 pF
31 60
ns
tpol Propagation delay time to logical 1 eve
C1 = 50 pF
35 60
ns
t For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable device type.
6
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09: CIA-RDP71 B003f' '3N1S4 . sb SN74L3OR
8-INPUT POSITIVE NAND GATE
14 13 12 11 10 O
L
h
n
positive logic
recommended operating conditions
Supply Voltage VCC: SN54L30R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74L30R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: SN54L30R . . . . . . . . . . . . . . . . . . . . . . .
S N 74 L30R . . . . . . . . . . . . . . . . . . . . . . .
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
10
-55
25
125
?C
0
25
70
?C
electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Logical 1 input voltage required
Vin(1)
at all input terminals to ensure
VCC = MIN,
Vout(0) s 0.3 V
2
V
logical 0 level at output
Logical 0 Input voltage required
Vin(0)
at any input terminal to ensure
VCC = MIN,
Vout(1) 2 2.4 V
0.7
V
logical I level at output
Vout(1)
Logical 1 output voltage
i CC = MIN,
Vin = 0.7 V,
2.4
V
load -100 pA
Vout(0)
Logical 0 output voltage
VCC
I sink = 2 mA,
Vin = 2 V,
0.3
V
in(0)
Logical 0 level input current (each input)
VCC = MAX,
Vin = 0.3 V
-0.18
mA
(1)
Logical 1 level input current (each input)
VCC = MAX,
Vin = 2.4 V
10
.A
in
VCC = MAX,
Vin = 5.5 V
100
pA
OS
Short-circuit output current
V C = MAX,
Vin = 0, Vout 0
_3 -15
mA
CC(0)
Logical 0 level supply current
VCC = 5 V,
Vin = 5 V
0.29 0.46
mA
iCC(1)
Logical 1 level supply current
VCC = 5 V,
Vim = 0
0.11 0.18
mA
switching characteristics, VCC - 5 V, TA - 25?C, N - 10 , see figure 1
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
tpd0 Propagation delay time to logical 0 level
C1 = 50 pF
70 100
ns
tpdI Propagation delay time to logical I level
CI = 50 pF
35 60
ns
t For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable device type.
7
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
TYPES SN54L51R, SN74L51R
DUAL 2-WIDE 3-INPUT, 2-WIDE 2-INPUT AND-OR-INVERT GATE
schematic (each gate)
A
1
1
w
NOTES: 1. Component values shown are nominal.
2. Inputs C and F are available on gate 1 only.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
10
-55
25
125
C
0
25
70
?C
electrical characteristics lover recommended operating free-air temperature range unless otherwise noted)
14 13 12 11 10 0 (
positive logic
IY =(IA?ii.IC)+ (1D.1E?1F)
2Y = (2A.2B) + (2D.2E)
Supply Voltage VCC: 5N54L51R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74L51R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Each Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: 5N54L51R . . . . . . . . . . . . . . . . . . . . . .
SN74L5IR . . . . . . . . . . . . . . . . . . . . . .
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Vin(1)
Logical I input voltage required at
all input terminals of either AND
section to ensure logical 0 at output
VCC = MIN,
Vout(o) 0.3 V
2
V
Vln(0)
Logical 0 input voltage required at
one input terminal of each AND -
section to ensure logical 1 at output
VCC = MIN,
Vout(1) 2.4 V
0.7
V
Vout(1)
Logical 1 output voltage
VCC = MIN,
llood=-100pA
Vin = 0.7 V,
2.4
V
V
out(0)
Logical 0 output voltage
VCC = MIN,
(sink = 2 mA
Vin = 2 V,
0.3
V
lln(0)
Logical 0 level input current (each input)
VCC = MAX,
Vin = 0
-0.18
mA
l
(1)
Logical 1 level input current (each input)
VCC = MAX,
Vin = 2.4 V
10
pA
ln
VCCMAX,
Vin=5.5V
100
pA
1os
Short-circuit output.current
VCC = MAX
-3 -15
mA
ICC(o)
Logical 0 level supply current (each gate)
VCC = 5 V,
Vin =5 V
0.38 0.59
mA
ICC(i)
Logical 1 level supply current (each gate)
VCC = 5 V,
Vin = 0
0.22 0.36
:m JA
switching characteristics, VCC - 5 V, TA - 25?C, N - 10, see figure 1
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
tpd0 Propagation delay time to logical 0 level
CI = 50 pF
35 60
ns
tpdI Propagation delay time to logical.1 level
C1 = 50 pF
50 90
ns
t For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable device type.
8 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09: CIA-RDP71 B003?~Rp403QIQaS4QT4Q~, SN74L54R
4-WIDE 3-2-2-3 INPUT AND-OR-INVERT GATE
C B GND Y J I
14 13 12 11 10 O O
T T D O G )o
positive logic
Component values shown are nominal
recommended operating conditions
Supply Voltage VCC: SN54L54R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S N 74 L54 R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Output, N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: 5N54L54R . . . . . . . . . . . . . . . . . . . . . .
SN74L54R . . . . . . . . . . . . . . . . . . . . . .
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
10
-55
25
125
C
0
25
70
?C
electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Vin(l)
Logical I input voltage required at
all input terminals of either AND
section to ensure logical 0 at output
VCC = MIN,
Vout(0) s 0.3 V
2
V
Vin(0)
Logical 0 input voltage required at
one input terminal of each AND
section to ensure logical I at output
VCC = MIN,
Vout(1) a 2.4 V
0.7
V
Vout(1)
Logical 1 output voltage
VCC = MIN,
Iload = -100 pA
in = 0.7 V,
2.4
V
V
out(0)
Logical 0 output voltage
VCC = MIN,
kink = 2 mA
Vin = 2 V,
0.3
V
in(0)
Logical 0 level input current (each input)
VCC = MAX,
Vin = 0.3 V
-0.18
mA
Logical 1 level input current (each input)
VCC = MAX,
Vin = 2.4 V
10
pA
in(1)
VCC MAX, =
Vin = 5.5 V
100
pA
105
Short-circuit output current
VCC = MAX
-3 -15
mA
CC(0)
Logical 0 level supply current
VCC = 5 V,
Vin = 5 V
0.6 0.9
mA
ICC(l)
Logical 1 level supply current
VCC = 5 V,
Vin = 0
0.39 0.72
mA
switching characteristics, VCC ? 5 V, TA - 25?C, N ? 10 , see figure 1
PARAMETER
TEST CONDITIONSt
MIN TYP
MAX
UNIT
tpd0
Propagation delay time to logical 0 level
C1
= 50 pF
35
60
ns
tpol
Propagation delay time to logical I level
C1
= 50 pF
50
90
ns
t For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable device type.
9
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 TYPES VROk l f (52 4/02/09 : CIA-RDP71 B00399R000300150001-0
2-WIDE 4-INPUT AND -OR-INVERT GATE
14 13 11 11 10 O O8
recommended operating conditions
I
n
positive logic
Y = (ABCD) + (EFGH)
Supply Voltage VCC: SN54L55R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74L55R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: SN54L55R . . . . . . . . . . . . . . . . . . . . . .
SN74L55R . . . . . . . . . . . . . . . . . . . . . .
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
10
-55
25
125
?C
0
25
70
?C
electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Vin(1)
Logical I input voltage required
at all input terminals of either AND
section to ensure logical 0 at output
VCC = MIN,
Vout(0) 0.3 V
2
V
Vin(0)
Logical 0 input voltage required
at one input terminal of each AND
section to ensure logical 1 at output
VCC = MIN,
Vout(1) a 2.4 V
0.7
V
Vout(1)
Logical 1 output voltage
VCC = MIN,
(load-100pA
Vin = 0.7 V,
2.4
V
Vout(0)
Logical 0 output voltage
VCC
I sink = 2 MIN,
Vin = 2 V,
0.3
V
lln(0)
Logical 0 level input current (each input)
VCC = MAX,
Vin = 0
-0.18
mA
I
Logical I level input current (each input)
VCC = MAX,
Vin = 2.4 V
10
pA
in(1)
VCC=MAX,
Vin=5.5V
100
pA
lOS
Short-circuit output current
VCC = MAX
-3 -15
mA
ICC(o)
Logical 0 level supply current
VCC = 5 V,
Vin = 5 V
0.38 0.59
mA
ICC(1)
Logical 1 level supply current
VCC = 5 V,
Vin = 0
0.22 0.36
mA
switching characteristics, VCC ? 5 V, TA ? 25?C, N ? 10 , see figure 1
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
tpd0 Propagation delay time to logical 0 level
C1 = 50 pF
35 60
ns
tpdi Propagation delay time to logical 1 level
C1 = 50 pF
50 90
ns
t For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable device type.
10
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09: CIA-RDP71 BOT SO"VEM,, SN74L71R
R-S MASTER-SLAVE FLIP-FLOP
logic
TRUTH TABLE
tn
tn+l
R
S
Q
0
0
Qn
0
1
1
1
0
0
1
1
Indeterminate
description
NOTES: 1. R = R1 ? R2 ? R3
2. S=S1 ? S2 ? S3
3. to = Bit time before clock pulse.
4. to+1 = Bit time after clock pulse.
9 13 12 11 10 O9 (
positive logic
Low input to preset sets to logical 1
Low input to clear sets 0 to logical 0
Preset and clear are independent of clock
This R-S flip-flop is based on the master-slave principle. The AND
gate inputs for entry into the master section are controlled by the
clock pulse. The clock pulse also regulates the state of the coupling
transistors which connect the master and slave sections. The sequence
of operation is as follows:
1. Isolate slave from master
2. Enter information from AND gate inputs to master
3. Disable AND gate inputs
4. Transfer information from master to slave.
recommended operating conditions
Supply Voltage VCC: SN54L71R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74L71 R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: SN54L71R . . . . . . . . . . . . . . . . . . . . .
SN74L71 R . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Each Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . .
Width of Clock Pulse, tp(clock) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . .
Width of Preset Pulse, tp(preset) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . .
Width of Clear Pulse, tp(clear) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Setup Time, tsetup (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Hold Time, thold (See figure 2) . ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
-55
25
125
?C
0
25
70
?
10
200
ns
100
ns
100
ns
100
ns
20
a o
Preset Cleor
R Clock S
I Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 TYPES'rS4t 11(1, I h74 1M 02/09 : CIA-RDP71 B00399R000300150001-0
R-S MASTER-SLAVE FLIP-FLOP
I
electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Input voltage required to
Vin(1) ensure logical 1 at any
VCC = MIN
2
V
input terminal
Input voltage required to
Vin(0) ensure logical 0 at any
VCC = MIN
0.7
V
input terminal except clock
Input voltage required to
Vin(0) ensure logical Oat
VCC - MIN
0.6
V
clock input terminal
Vout(l) Logical 1 output voltage
VCC = MIN, Iload = -100 pA
2.4
V
Vout(0) Logical 0 output voltage
VCC = MIN, "ink = 2 mA
0.3
V
I Logical 0 level input current
in(0) at Rl, R2, R3, S1, S2, or S3
V = MAX, V i = 0.3 V
CC in
-0.18
mA
I Logical 0 level input current
(0)
t
t
l
l
k
V = MAX, V = 0.3 V
cc
-0.361
mA
ear, or c
m
a
prese
, c
oc
in
Logical 1 level input current
VCC = MAX, Vin,= 2.4 V
10
pA
n(1) at Rl, R2, R3, Si, S2, or S3
VCC = MAX, Vin = 5.5 V
100
I,A
Logical 1 level input current
VCC = MAX, Vi
= 2.4 V
20
pA
n
m(1) at preset or clear
VCC CC= MAVin = 5.5 V
200
?A
Logical 1 level current
l
VCC'= MAX, Vin = 2.4 V
of
pA
in(t) into the clock input
VCC = MAX, Vin = 5.5 V
200 #
pA
IOS Short-circuit output current
VCC = MAX,
-3 -15
mA
ICC Supply Current
VCC = 5 V, Vin(clock) = 0
0.76 1.3
mA
t For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable device type.
f For typical clock input current see page 23.
switching characteristics, VCC = 5 V, TA = 25?C, N = 10 (see figure 2)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
(clock
Maximum clock frequency
C1 = 50 pF
3
MHz
Propagation delay time to logical
tpd 1
1 level from clear or preset
C'1 = 50 pF
35
75
ns
to output
Propagation delay time to logical
tpd0
0 level from clear or preset
C1 = 50 pF
60
150
ns
to output
t
Propagation delay time to logical
C = 50 pF
1
10 35
75
ns
pol
1 level from clock to output
t
Propagation delay time to logical
C = 50 pF
1
10 60
150
ns
pd0
0 level from clock to output
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09: CIA-RDP71 BOO WHVIANN, SN74L71R
R-S MASTER-SLAVE FLIP-FLOP
7
0
CLOCK
0
CLOCK
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 TYPES I RAVIk/09 : CIA-RDP71 B00399R000300150001-0
J-I( MASTER-SLAVE FLIP-FLOP
TRUTH TABLE
tn
to+1
J
K
Q
0
0
Qn
0
1
0
1
0
1
1
1
Qn
NOTES: 1. J=J1'J29J3
2. K=K1eK2?K3
3. to = Bit time before clock pulse.
4. to+l = Bit time after clock pulse.
description
This J-K flip-flop is based on the master-slave principle. The AND
gate inputs for entry into the master section are controlled by the
clock pulse. The clock pulse also regulates the state of the coupling
transistors which connect the master and slave sections. The sequence
of operation is as follows:
1 . Isolate slave from master
2. Enter information from AND gate inputs to master
3. Disable AND gate inputs
4. Transfer information from master to slave.
Logical state of J and K inputs must not be allowed to change
when the clock pulse is in a high state.
recommended operating conditions
Supply Voltage VCC: SN54L72R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74L72R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: SN54L72R . . . . . . . . . . . . . . . . . . . . .
SN74L72R . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Each Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Width of Clock Pulse, tp(clock) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . .
Width of Preset Pulse, tp(preset) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . .
Width of Clear Pulse, tp(clear) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . .
Input Setup Time, tsetup (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Hold Time, thold (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14 13 12 11 10 (9 (8)
U
b 0
Preset clear
K clock d
J
I'i
positive logic
Low input to preset sets Q to logical 1
Low input to clear sets Qto logical 0
Preset and clear are independent of clock
HIGH
2
1
LOW
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
-55
25
125
?C
0
25
70
'C
10
200
ns
100
ns
100
ns
tp(c
lock)
i0
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
TYPES SN54L72R, SN54L72R
J-K MASTER-SLAVE FLIP-FLOP
1
I
electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Input voltage required to
Vin(1) ensure logical 1 at any
VCC = MIN
2
V
input terminal
Input voltage required to
Vin(0) ensure logical 0 at any
VCC = MIN
0.7
V
input terminal except clock
Input voltage required to
Vin(0) ensure logical Oat
V = MIN
cc
0.6
V
clock input terminal
Vout(l) Logical 1 output voltage
VCC = MIN, Iload = -100 pA
2.4
V
Vout(0) Logical 0 output voltage
VCC = MIN, I
k = 2 mA
i
0.3
V
s
n
I Logical 0 level input current
in(O) at J1
J2
J3
K1
K2
or K3
V CC MAX, V = 0.3 V
CC in
-0.18
mA
,
,
,
,
,
Logical 0 level input current
in(0) at preset, clear, or clock
V = MAX, V i 0.3 V
CC n=
-0.36#
mA
Logical level input current
VCC = MAX, Vi
= 2.4 V
10
pA
n(1)
n
at Jl, J2, J3, K1, K2, or K3
VCC MAX, .n = 5. V
100
Logical 1 level input current
VCC = MAX, V
= 2.4 V
20
pA
n(1)
in
at preset or clear
VCC = MAX, Vin = 5.5 V
200
NA
Logical 1 level current
VCC = MAX, Vin = 2.4 V
O t
pA
in(1)
into the clock input
VCC = MAX, Vin = 5.5 V
200
pA
IOS Short-circuit output current
VCC = MAX
-3 -15
mA
ICC Supply current
VCC = 5 V, Vin(clock) = 0
0.76 1.3
mA
For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable
device type.
For typical clock input current see page 23.
switching characteristics, VCC = 5 V, TA = 25?C, N = 10 (See figure 2)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
Unit
(clock Maximum clock frequency
C1 = 50 pF
3
MHz
Propagation delay time to logical
tpd 1 1 level from clear or preset
C1 = 50 pF
35 75
ns
to output
Propagation delay time to logical
_
tpd0 0 level from clear or preset
C1 = 50 pF
60 150
ns
to output
Propagation delay time to logical
t
ol 1 l
l f
l
k
C
= 50 pF
10 35 75
ns
p
eve
rom c
oc
to output
1
Propagation delay time to logical
t
d0 0 l
l f
l
k
C
= 50 pF
10 60 150
ns
p
eve
rom c
oc
to output
1
15
Approved For Release 2004/02/09 :CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
TYPES SN54L72R, SN54L72R
J-K MASTER-SLAVE FLIP-FLOP
t
t
116
Approved For Release 2004/02/09 :CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71BOTYPES SN54L73R, SN74L73R
DUAL J-K MASTER-SLAVE FLIP-FLOP
1
logic
TRUTH TABLE
to
to+1
J
K
Q
0
0
Qn
0
1
0
1
0
1
1
1
Qn
NOTES: 1 . to = Bit time before clock pulse.
2. to+1 = Bit time after clock pulse.
description
This J-K flip-flop is based on the master-slave prin-
ciple. Inputs to the master section are controlled by
the clock pulse. The clock pulse also regulates the
state of the coupling transistors which connect the
master and slave sections. The sequence of operation
is as follows:
1 . Isolate slave from master
2. Enter information from J and K inputs to master
3. Disable J and K inputs
4. Transfer information from master to slave.
Logical state of J and K inputs must not be allowed
to change when the clock pulse is in a high state.
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
4.75
5
5.25
V
-55
25
125
?C
0
25
70
`C
10
200
is
100
ns
100
ns
tp(cl
ock)
z0
recommended operating conditions
14 13 12 11 10 O9 OS
L Q Q Z Q
Clear Clear
J Clods K K Clock J
O O O O O ? O
Clock Clear K VCC Clock Clear J
positive logic
Low input to clear sets Q to logical 0
Clear is independent of clock
Supply Voltage VCC: SN54L73R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74L73R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA: SN54L73R . . . . . . . . . . . . . . . . . . . . .
SN74L73R . . . . . . . . . . . . . . . . . . . . .
Fan-Out From Each Output, N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Width of Clock Pulse, tp(clock) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . .
Width of Preset Pulse, tp(preset) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . .
Width of Clear Pulse, tp(clear) (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . .
Input Setup Time, tsetup (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Hold Time, thold (See figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 TYPES CIA-RDP71B00399R000300150001-0
DUAL J-K MASTER-SLAVE FLIP-FLOP
electrical characteristics (over recommended operating free-3ir temperature range unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN TYP MAX
UNIT
Input voltage required to
Vin(1) ensure logical 1 at any
VCC = MIN
2
V
input terminal
Input voltage required to
Vin(0) ensure logical 0 at any
VCC = MIN
0.7
V
input terminal except clock
Input voltage required to
Vin(0) ensure logical 0 at
VCC = MIN
0.6
V
clock input terminal
Vout(1) Logical 1 output voltage
VCC = MIN, Iload -100 pA
2.4
V
Vout(0) Logical 0 output voltage
VCC = MIN, Is ink = 2 mA
0.3
V
(0) Logical 0 level input current
in (O)
K
= 0.3 V
VCC MAX, Vin
-0.18
mA
Jor
Logical 0 level input current
l
k
t
l
0
V = MAX, V. = 0.3 V
cc
-0.361
mA
ear, or c
) a
c
oc
in(
in
Logical 1 level input current
(1)
VCC = MAX, Vin = 2.4 V
10
pA
in
at J or K
VCC = MAX, Vin = 5.5 V
100
pA
Logical 1 level input current
V CC = MAX , V i n = 2.4 V
20
pA
in(1)
at clear
VCC = MAX, Vin = 5.5 V
200
pA
Logical 1 level current
VCC = MAX, Vin = 2.4 V
of
pA
in(1) into the clock input
VCC = MAX, Vin = 5.5 V
200 #
pA
IOS Short-circuit output current
VCC = MAX
-3 -15
mA
CC Supply current (each flip-flop)
VCC = 5 V, Vin(clock) = 0
0.76 1.3
mA
t For conditions shown as MIN or MAX, use the MIN or MAX value specified under recommended operating conditions for the applicable
device type.
For typical clock input current see page 23.
switching characteristics, VCC = 5 V. TA = 25?C, N = 10 (see figure 2)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
Unit
(clock Maximum clock frequency
C1 = 50 pF
3
MHz
t Propagation delay time to logical
1 1 l
l f
l
C = 50 pF
35 75
ns
eve
rom c
ear to output
pd
1
t Propagation delay time to logical
0 l
l f
l
C = 50 pF
60 150
ns
eve
rom c
ear to output
pd0
1
t Propagation delay time to logical
l f
k
d 1 1 l
l
C = 50 PIP
10 35 75
ns
rom c
to output
p
eve
oc
1
t Propagation delay time to logical
C = 50 pF
10 60 150
ns
pd0 0 level from clock to output
1
18
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71 B TYPES OSN54L73R, SN74L73R
DUAL J-K MASTER-SLAVE FLIP-FLOP
functional block diagram (each flip-flop)
1
schematic (each flip-flop)
500 c2 1 20 k4 I ~ 56 k) 56 kQ j ~ 20 kf2 ~ 500 0
19
' Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 SERIE A prov d7or Release 2004/02/09: CIA-RDP71B00399ROO0300150001-0
?OJZI aMMIU ??SEMICONDUCTOR NETWORKS
switching characteristics
Vgen INPUT VCC
0 0 0
PULSE
GENERATO
(See Note 1)
OUTPUT
------------------
--i LOAD CIRCUIT I
1N916
[50PF - [30PF
L I -------------------JI
PULSE
GENERATOR
OUT PUT
BUFFER
(See Note 2
l
--Ij t0
2V
1.5 V I
t1
I I 3V
1/2V
l 1.5V
--------- Vin(1)
Vout(1)
- - - - - - Vout(0)
NOTES: 1. The pulse generator has the following characteristics: Vgen = 3 V, tl = to = 15 ns, f = 500 kHz, duty cycle = 50%,
Zout ~ 50 0.
2. The buffer gate is a series 54L/74L gate.
3. When testing SN54LOOR/SN74LOOR, SN54L10R/SN74L10R, SN54L20R/SN74L20R, and SN54L30R/SN74L30R the input signal
is applied to one input and all unused inputs are at VCC. When testing SN54L51 R/SN74L51R, SN54L54R/SN74L54R and
SN54L55R/SN74L55R the input signal is applied to one input of each AND section and all other inputs are at VCC.
4. C1 includes probe and jig capacitance.
Approved For Release 2004/02/09 : CIA-RDP71B00399ROO0300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
SERIES 54L, 74L
? Z ,Z V1ZI'? SEMICONDUCTOR NETWORKS
CLOCK
INPUT
J, K (See Note 1)
OR R, S INPUT
Q OR ZS
OUTPUT
Q OR Z5
OUTPUT
II
-V out( I )
1.3 V
I?- tpdo -~i
I I
-?i tpol If-
Vout(0)
Vout(1)
- - Vout(o)
PRESET AND CLEAR INPUT/OUTPUT VOLTAGE WAVEFORMS
NOTES: 1. Logical state of J and K inputs must not be allowed to change during tp(clock)?
2. Load circuit is some as shown on figure I.
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
SERIES 54L, 74L
~R 7th WZP? SEMICONDUCTOR NETWORKS
45
e 40
35
~ 30
25
20
15
10
5
00
PROPAGATION DELAY TIMES
vs
LOAD CAPACITANCE
VCC = 5 V
11110
TA=25?C
N = 1
tpol
1pd0
PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATURE
45
40
35
30
C
25
20
2
15
10
CL=50pF
tpol
VCC=5V
N=1
1
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
VCC = 5 V
N= 10
CL=50PF
I
0
30
TA - Free-Air Temperature - ?C
PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATURE
40
35
VCC=5V
N=10
CL=50pF
TA - Free-Air Temperature - ?C
tpd0 i
I Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
SERIES 54L, 74L
~OSZD .Z VZ,? SEMICONDUCTOR NETWORKS
OUTPUT VOLTAGE
INPUT VOLTAGE
OUTPUT VOLTAGE
LOAD CURRENT
OUTPUT VOLTAGE
vs
SINK CURRENT
1
VCC = 5 V
N = 10 (got. input)
VCC=5V
Vin=0.3V -
TOTAL POWER DISSIPATION
FREQUENCY
VCC=5 V
Vln(0) clock s 0.3 V
Vin(I) clock a 2.4 V
N = 10 (gate Inputs)
C150 pF
Duty cycle = 50%
TA = 25?C
N
0
C1
=0
N = 10 (p
ate in
put)
C130 p
F
3 5.0
E
4.5
0
0 4.0
? 3.5
3.0
2.5
2.0
b 1.5
1.0
0.5 0.7 1 2
f - Frequency - MHz
AVERAGE TOTAL D-C POWER DISSIPATION
FREE-AIR TEMPERATURE
V CC 5 V
Vin(0) clock = 0.3 V
Vin(1) clock = 2.4 V
PT(I) ; PT(O)
PT(avg)
-75 -50 -25 0 25 50 75
TA- Free-Air Temperature - ?C
CLOCK INPUT CURRENT
INPUT VOLTAGE
VCC=5 V
V1n=2.4V
TA
TA = 1
=25?
25?C
C
I
i
T1
0
U
-0.1
x
U -0.2
FROM
TA = 25?C
J=K=O
1H
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vin - Input Voltage - V
1 23
I Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 t
I
SERIES 541iir741J For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
aoi&zill VZilkC1WZV? SEMICONDUCTOR NETWORKS'
general
t
1
PRINTED IN U.S.A.
TEXAS INSTRUMENTS TI cannot assume any responsibility for any circuits shown
or represent that they are free from patent infringement.
SEMICONDUCTOR-COMPONENTS D VI TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
PosAplprdevelslnot: RetleasexDSION2/O9 : CIA-RDP71 BOQ081iQ?WIQQ1QIlo-Oo SUPPLY THE BEST PRODUCT POSSIBLE.
Series 54L/74L semiconductor networks are are metallic and are insulated from leads and
mounted ina glass-to-metal hermetically sealed, circuit. All Series 54L/74L networks are avail-
welded package. Package body and leads are able with formed leads, insulator attached, and/
gold-plated F-15f glass-sealing alloy. Approxi- or mounted in a Mech-Pak carrier.
mate weight is 0.1 gram. All external surfaces
Gold-plated F-15# leads require no ad-
ditional cleaning or processing when used
in soldered or welded assembly. Formed
leads are available to facilitate planar
mounting of networks on flat circuit boards.
Networks I are removed from Mech-Pak
carriers with lead lengths of 0.300 inch
(0.750 inch tip-to-tip).
An insulator, secured to the back surface of
the package, permits mounting networks on
circuit boards which have conductors passing
beneath the package. The insulator is 0.0025
inches thick and has an insulation resistance
of 10 megohms at 25?C.
mech-pak carrier
The Mech-Pak carrier facilitates handling the
network, and is compatible with automatic
equipment used for testing and assembly.
The carrier is particularly appropriate for
mechanized assembly operations and will
withstand temperatures of 125?C for in-
definite periods.
ordering instructions
Variations in mechanical configuration of
semiconductor networks are identified by
suffix numbers shown in a table at the right.
NOTES: a. All di...mi.n. in inch...
b. All d..inwl. -0.005 ....p1 n, rol.d.
lead .peeing 1el.wn . i. x0.015 a1 ..1n.,nin and x0.005
d. lead Yuen, m. n la.ol.d wi.hin 20.005 .f Il.i. 1n- P..inom
r.l.tiv, to body ....tall......
Not gpplii.abl. in M..h-P.k -i-
f. Syntboli tion d.n.1n ..i.nt.tion of pnkag..
OUTLINE DRAWING - SEMICONDUCTOR
NETWORK WELDED PACKAGE
FORMED LEADS
0.004E 0750
Typknl (NOTE C)--~I
(NOTE B )
0.7.0
NOTES: A. All dlnwmbm in ind...
E. N.1 applimbi. in M.d.-Pok Canal
C. Mwwr d f cantodin..f a.Nl& bend.
NOTES: 1. All dim-ion. ... n. nin1 in in.h., anln. otherwis..pe.ifi.d.
2. O,...ll thick..... i. 0.175 and ne.l.d height 1.0.150 each.
3. In th. pi... h.- package nnl.,Iin. i. loafed within x0.015 of th. tooling hol...enl.,Iin..
NO MECH-PAK CARRIER
MECH-PAK CARRIER
Lead Length
0.300 inch
Not Applicable
Formed Leads
No
No
Yes
Yes
No
No
Yes
Yes
Insulators
No
Yes
No
Yes
No
Yes
No
Yes
Ordering
Suffix
None
-6
-7
-1
-2
-3
-4
-5
tPatented by Texas Instruments Incorporated.
 Approved For Release 2004/02/09 : CIA-RDP71 B00399R00030SE1 -4 5 830N
a)&VV azaa WI?? SEMICONDUCTOR NETWORKSt
DIODE-TRANSISTOR-LOGIC SEMICONDUCTOR NETWORKS
IN
MOLDED PLUG-IN PACKAGES
description
Series 15 830N consists of the Series 15 830 general-purpose DTL circuits mounted within a 14-pin plastic
package and characterized for operation over the temperature range of 0?C to 75?C.
LOW SYSTEM COST
? multifunction gates offering low cost per logic function
? electrically designed specifically for monolithic integrated-circuit technology
? plug-in configuration ideal for flow-soldering techniques
I. pins on 100-mil grid spacings for industrial-type circuit-boards
PERFORMANCE
? high speed
? high d-c noise margins
? low power dissipation
? good fan-out capability
EASE OF DESIGN
I. familiar logic configuration (DTL)
? single-ended output-dot-OR logic
I f -1 f d ' fl :k:I't
t
e amt y or eslgn ex1 I 1 y
? comp e
? single power supply
i specifications, logic symbols and terminal designations
Schematic diagrams, fan-out rules, maximum ratings, and electrical characteristics for Series 15 830N net-
works are identical to those of the corresponding Series 15 830 type numbers except for maximum propa-
gation delay times. Terminal designations for the Series 15 830N networks are shown in this data sheet.
mechanical data
Series 15 830N networks are mounted on a 14-lead frame and encapsulated within a plastic compound.
The compound. will withstand soldering temperatures with no deformation, and circuit performance char-
acteristics remain stable when operated in high-humidity conditions.
I
I
1
i
I
Approved For Rel
)l.*1 I~gt?T`A&0300150001-0
SEMICONDUCTOR-COMPONENTS DIVISION
POST OFFICE BOX 5012 ? DALLAS, TEXAS 75222
 SERIES 15AWOWd For Release 2004/02/09: CIA-RDP71 B00399R000300150001-0
JTQA ZZ' aZjkg'VZV SEMICONDUCTOR NETWORKS
SN15 831N, SN15 845N,SN15 848N
MASTER-SLAVE FLIP-FLOPS
TOP VIEW
NC Cl C2 SD Q NC
L
C2 1 CD
Cl
St
S2 SD Q
1 2 3 4 5 6 1
NC CP Si S2 CD Q GND
positive logic
Low input to SD sets Q to logical 1
R-S MODE
t~
trl+t
St
S
CI
C2
Q
0
X
0
X
Qn
0
X
X
0
Qn
X
0
0
X
Qn
X
0
X
0
Qn
0
X
1
1
0
X
0
1
1
0
1
1
0
X
1
1
1
x
0
1
1
1
1
1
Indeterminate
NOTES: 1. In = bit time before clock pulse.
2. In t = bit time after clock pulse.
3. X indicates that either a logical I or a logical 0 may be
present.
4. Logical 1 is more positive than logical 0
5. For operation in the J-K mode connect S2 to 0, and C2 to 0.
SN15 850N
PULSE-TRIGGERED BINARY
TOP VIEW
VCC SD NC Q C NC NC
14 WW ? 10 n 8
A
positive logic
See asynchronous truth table
SYNCHRONOUS
PULSE INPUT
OUTPUT
S
C
PTt
PT
Q
Q
1
X
X
1
Qn
On
X
1
1
X
Qn
On
0
1
0
X
1
0
0
X
0
1
1
0
1
0
X
0
0
1
X
0
1
0
0
1
0
0
0
0
Indeterminate
DIRECT
INPUT
NOTES:
1. X indicates that either a logical I or a logical 0 may be present.
2. Logical 1 is more positive than logical 0.
3. Logical states shown for pulse inputs PTt and PT2 indicate that a transition to
that state has just occurred.
4. Truth tables reflect individual conditions at the inputs. Either direct input may be
used to inhibit its corresponding pulse input.
TEIaK4%k*~NM02/09 : CIA-RDP71B00399R000300150001-0
SEMICONDUCTOR-COMPONENTS DIVISION
POST OFFICE BOX 5012 ? DALLAS. TEXAS 75222
 1
1
I
t
Approved For Release 2004/02/09 : CIA-RDP71 B00399R000300150CHMES 15 830N
IYG1&EI iZta'uZT ? SEMICONDUCTOR NETWORKS
SN15 830N, SN15 832N (BUFFER), SN15 844N (POWER)
DUAL 4-INPUT NAND/NOR GATES
TOP VIEW
VCC 2D 2C 2X 2B 2A 2Y
14 13 12 11 10 n F8
positive logic
SN15 846N
QUADRUPLE 2-INPUT NAND/NOR GATE
VCC 4B
TOP VIEW
4A 4Y 3B
3A
3Y
14 13
11 11 10
9
8
L
T
1 1
3 4 5
6
1
lA 1B
1Y 2A 2B
2Y
GND
positive logic
Y = AB
SN15 833N
DUAL 4-INPUT EXPANDER
TOP VIEW
NC
2D
2C 2X 28 2A
NC
14
13
12 11 10 9
8
1
2
3 4 5 6
1
NC
1A
1B 1X 1C ID
GND
positive logic
X = ABCD
SN15 862N
TRIPLE 3-INPUT NAND/NOR GATE
TOP VIEW
VCC
1C lY 3C 3B
3A
3Y
4
13 12 1 10
9
8
1
2 3 4 5
6
1
lA
1B 2A 2B 2C
2Y
GND
positive logic
Y = ABC
Approved For Release 2004/02/09: CIA-RDP71
RT)M WRUMENTS
SEMICONDUCTOR-COMPONENTS DIVISION
POST OFFICE BOX 5012 ? DALLAS, TEXAS 75222
 SERIES 15 Rimed For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
jvo,L, U) azisa flt Z ??SEMICONDUCTOR NETWORKS
SN15 851N
MONOSTABLE MULTIVIBRATOR
TOP VIEW
See Note 1
VCC
NC NC NC
14
13 12 11 10 9 8
ONE
SHOT
1
2 3 4 5 6 1
0
See
1 GND
X A B
te 2
No
NOTES:
1. Refer to the schematic diagram for using pins
?, 10 , and 11 to control one-shot pulse width.
2. Input sensitivity can be decreased by adding a
capacitor from pin 0 to ground.
E Appn~aeeT F, tease 2IR4/02/09 : CIA-RDP71 B00399R000300150001-0
SEMICONDUCTOR-COMPONENTS DIVISION TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
POST OFFICE BOX 5012 . DALLAS, TEXAS 75222 IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.
 BULLETIN NO 1054$ pproved For Release 2004/02/09 : CIA-RDP71 B00399R000300150001-0
December 15, 1966
(Supersedes Bulletin No. 1054C)
1
BCD TO DECIMAL READOUT
The BIP-8211P Decoder/Driver provides decimal
readout on a standard rectangular NIXIE? Tube,
type 8422 (B-5991) from 8 wire 8-4-2-1 binary-
coded decimal inputs. Decoder circuitry which
accepts logic level separations of 2.3V to 30V is
completely solid state, and controls the selection
of the NIXIE tube numeral elements. The BIP-
8507P drives a plus/minus rectangular NIXIE
tube, type B-5992. The modules feature a socket
pack construction; i.e., socket and decoder are
an integral unit. Height and width dimensions
are those of the socket itself, permitting mini-
mum center-to-center spacing of multi-digit
displays. Refer to Bulletin 1066 for typical ap-
plications and theory of operation. Bezel assem-
blies for multi-tube displays are described in
Bulletin 1020.
DRIVER
TYPE
BIP-8211 P
BIP-8507 P
Figure 1. OUTLINE DRAWING
INPUT REQUIREMENTS (Figure 2)
INPUT SIGNAL BIP-8211P........ 4 bit (8 lines)
8-4-2-1 BCD*
BIP-8507P........ 2 lines
Logic "1" = E, volts ......... Turn "ON"
Logic "0" = E volts ?0.5V ... Turn "OFF"
BCD VOLTAGE LEVELS .......... BCD voltage levels may be any
set of two levels within limita-
tions specified under Logic
Level Separations.
INPUT CURRENT (Each input line) BIP-8211P... 1.0 ma max.
BIP-8507P... 0.5 ma max.
POWER REQUIREMENTS (Note 3)
DC Supply Voltage Note 5 .............. +200 ? 10 Vdc
DC Supply Current BIP-8211P .......... 3.7 ma nom.
BIP-8507P .......... 1.5 ma nom.
? Other modules which can accept other BCD codes such as
5-4-2-1, 2-4-21-1, 4-2-21-1, Watts, cyclic 20 Gray, etc., are also
available.(SEE BULLETIN 1108)
Bias Terminals
Using
Terminal 12
Using
Terminal 1 or 10
(Note 7)
(Note 9)
(Note 10)
Minimum Logic Level
Separation ..............................
2.3V to 30V
5.2V to 26V
E? = Logic "0" ..........................
-5.OV to -0.9V
-1.OV to +0.5V
E, = Logic "1" ..........................
+1.4V to +25V
+5.7V to +25V
MECHANICAL CHARACTERISTICS
Connector . . . . . . . . . . . . . . . . . .. 12 pin rectangular socket base Outline drawing ............... Figure 1
Receptacle ................... SK-169 (Figure 4) (Note 4) Terminal Connections .......... Table I
Mounting Diagram ............. Figure 5. Note 8 Temperature
Weight ....................... 1 oz. nom. Operating .................. -20?C to +85?C
Basing Diagram ................ Figure 3 Non-Operating ............... -50?C to +85?C
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
 s
ANODE 00-
Ra r-_--1
(zl ~ D2 ~,
(I) T o- LI v
(t ) 5 EM 2 ~TT
EDS
RI -
220,1/2W.
R2 TNRU RS -1 MEG, 1/4 W.
TERMINALS
Rg - 10, I/4 W.
BCD INPUTS
PIN 12 NOT USED EXCEPT AS NOTED IN APPLICATION BULLETIN
NUMBER IOBB FOR SPECIAL APPLICATIONS.
Figure 2a. BIP-8211 P SCHEMATIC
1
.140 - 4k-
0.005
Figure 4. RECEPTACLE SK-169 (Note 4)
1
1
SECTIONAL VIEW
FRONT MOUNTING DETAIL
SECTIONAL VIEW
REAR MOUNTING DETAIL
Figure 5. MOUNTING CONFIGURATIONS (Note 8)
NOTES
NOTE:
A polarizing pin is added
to the connector.This pin
is not internally connected
and mates with terminal 14
of receptacle SK-169.
Figure 3. BASING DIAGRAM
TERMINAL
BIP-8211P
BIP-8507P
1
Eo *
Note 1
2
BCD 8
-
3
BCD 4
-
4
BCD$
-
5
BCD i
"+" plus
6
Note 1
-
7
BCD 1
-" minus
8
BCD 2
-
9
BCD 4
10
BCD 8
E0
11
+200 Vdc
+200 Vdc
12
Table 1. TERMINAL CONNECTIONS
CODE
NUMERAL
8
4
2
1
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
1. Pin 6 on BIP-8211P and Pin 1 on BIP-8507P (NIXIE Tube Anode) are used for test purposes only.
2. NIXIE tube is not included as part of the module and must be ordered separately.
3. D.C. return for the +200V supply is normally connected to the one ED input terminal being used.
4. Receptacle SK-169 is not part of the module and must be ordered separately.
5. For B+ voltages higher than +200 Vdc, a resistor (R) must be added in series with RI (see Figures 2a and 2b) so that
the voltage at pin 11 is 200V ?1OV. For example, to operate the BIP-8211P at +300 Vdc, R is calculated by dividing the
voltage difference, 100V (300-200) by the nominal current, 3.7 ma. This gives a result of 27K (100/3.7).
6. For logic "0" more positive than logic "1"; reverse inputs and input complements.
7. All voltages given are referenced to terminal 1 or 12 (BIP-8211P) and 10 or 12 (BIP-8507P); i.e., the voltage at terminal
11 is +200V greater than at terminals 1, 10 or 12. Only one of the bias terminals is used in a given application.
8. Modules may be mounted either in front of or behind the panel (Figure 5). Front mounting should be employed only when
there is no back lighting. Rear mounting may be used whether or not back lighting is present. Following this rule will
eliminate light showing through the panel.
9. This applies to both modules.
10. This applies to terminal 1 (BIP-8211P) or terminal 10 (BIP-8507).
Burroughs Corporation /ELECTRONIC COMPONENTS DIVISION
Von PLAINFIELD. NEW JERSEY 07061
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
The information contained in this brochure does not necessarily imply a license under patents or pending applications of Burroughs Corp. or
assure a freedom from patent rights of others. No warranties of any kind are either expressed or implied by reason of this publication.
*See Notes 3, 7
Figure 2b. BIP-8507P SCHEMATIC
ED * 10
E0W, 12
(14) CONTACTS
BERYLLIUM COPPER,
SILVER PLATED TIN
DIPPED,
 v m r
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
,0074' P/ NOT USfD pO~iYG O, A 7/OH - P.Pf3#T ON[y
2 vE/G/1T' 1P.POX 3S oE.
3 MO//NT/N6 ~[ATK .PEi*fOVED *Y 4' OvfN /s UsSO
0
/~,Pi UG/?6S/U Co9#X C'ONNfcTO~P osf '6/98A COAX .2 OPL
.2T.3 UG /?L'~ U C0.4- CRASS/S CO//NFCTOR 2 0"V
ITEM PART NO. DESCRIPTION QTY. REMARKS
LIST OF MATERIAL
UNLESS OTHERWISE SPECIFIED CHK.
FRACTIONS +I /64 ENG.
DECIMALS +.005 PROD.
Approved For Release 2004/02/09 : Cl RIiMP71 B00399RO
BURRS AND SHARP
FLOW CORPORATION
205 SIXTH STREET, CAMBRIDGE, MASS.
 o - - - r
Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
54
4rsaa
S3oPs76 -
S2 /87c-4/tea P w R S~ ply .,o A /off / f/ '
Sl /D/-Qd~fa `! t~J Coq / //P F~ P L'OA/iU A-/a / Dl $,TA/,-e h
Approved For Re fs/e 04/O2/0911? GFA-R ~Y399 ?Of 3
101-40/22 /vIdEP 'DECaocl -- n A-yo4 / ",T / r c .
47 C-1896-//w7
46 C-499e-m,S
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44 391'
43 390
4e 2N358?
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38 /,x5879
37 7 SS.Ceo
36 390
39 ,JCaO-m/
33 4826-/-A5'9
32 3AG
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29 NIP
28 2372
BRAGFGr ~ PGE/yER Po T
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Bq,CKer cAAICIrr? Mnuurwy
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27 d7PS aZN-/pk3Y oNNEC7DC
26 ZLWa4-7-ISP
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PARt NO. DFSC81110N
LIST OF MATERIAL
FLOW CORPORATION
205 50GN 5mm. _G&
MASS
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Approved For Release 2004/02/09 : CIA-RDP71B00399R000300150001-0
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-.25 MAX.
(CUT AT ASSY)
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NOTE
1. IUSULATE ITEM 8 FROM ITEM 1 BY
CEMEUTn-G MYLAR TO ITEM I.
18 7055K20 SWITCH, TOGGLE SPST (SO
IT UG)468/U CONNECTOR (12,3)
21 NE0PREUE RUBBER '/a' TH .
20 11 '/4' THK
9 7065K20 SWITCH, TOGGLE DPST (S2)
I6 YS-2 BATTEPY (BTI-G)
15 MOD 1650 OSCILLATOR IMC (Y I)
14- 254-S( HEAT SIUK
13 DSM04-7.155 CONNECTOR (1
12 '(D-22S CONNECTOR (PI)
11 48%-1102 MTG. BRACKET OSCILLATOR
10 48%-4CC04- ASSY PC -3 BOARD
9 48%40703 PC-2
8 489(.40002 PC- I
7 489CI IOto P2 SPACER
C 46% I l0(PI
5 4896-1103 PANEL FPOUT SILK SCQEEAI
4 48%-1101 MODUTING PLATE
9 48% 104 C DV ER , RIc -ct
! 248%-1104;COVER., LEFT
L 148%1105, CHASSIS
rnora :vex
oECwnis :.oos
Approved For Release 2004/02/09: CIA-RDP71 B00399R00030 990
361
2 FLOW
QPL
A p.
I CUTLER HAMMER
a AMPHEAIOL
G YAPDMFY
I FLOW COQP
I WAKEFIELD FNG
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I FLOW
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FLOW
Flow
FLOW CORPORATION
205 220115 stmt. Coewocc i
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